1 /* Optimized memcpy implementation for PowerPC64.
2 Copyright (C) 2003, 2006, 2007 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, write to the Free
17 Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA
24 /* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]);
27 Memcpy handles short copies (< 32-bytes) using a binary move blocks
28 (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled
29 with the appropriate combination of byte and halfword load/stores.
30 There is minimal effort to optimize the alignment of short moves.
31 The 64-bit implementations of POWER3 and POWER4 do a reasonable job
32 of handling unligned load/stores that do not cross 32-byte boundries.
34 Longer moves (>= 32-bytes) justify the effort to get at least the
35 destination doubleword (8-byte) aligned. Further optimization is
36 posible when both source and destination are doubleword aligned.
37 Each case has a optimized unrolled loop.
39 For POWER6 unaligned loads will take a 20+ cycle hicup for any
40 L1 cache miss that crosses a 32- or 128-byte boundary. Store
41 is more forgiving and does not take a hicup until page or
42 segment boundaries. So we require doubleword alignment for
43 the source but may take a risk and only require word alignment
44 for the destination. */
47 EALIGN (BP_SYM (memcpy), 7, 0)
54 andi. 11,3,7 /* check alignement of dst. */
55 clrldi 0,0,61 /* Number of bytes until the 1st doubleword of dst. */
56 clrldi 10,4,61 /* check alignement of src. */
58 ble- cr1,.L2 /* If move < 32 bytes use short move code. */
61 srdi 9,5,3 /* Number of full double words remaining. */
65 /* Move 0-7 bytes as needed to get the destination doubleword alligned.
66 Duplicate some code to maximize fall-throught and minimize agen delays. */
95 /* Add the number of bytes until the 1st doubleword of dst to src and dst. */
99 clrldi 10,4,61 /* check alignement of src again. */
100 srdi 9,5,3 /* Number of full double words remaining. */
102 /* Copy doublewords from source to destination, assumpting the
103 destination is aligned on a doubleword boundary.
105 At this point we know there are at least 25 bytes left (32-7) to copy.
106 The next step is to determine if the source is also doubleword aligned.
107 If not branch to the unaligned move code at .L6. which uses
108 a load, shift, store strategy.
110 Otherwise source and destination are doubleword aligned, and we can
111 the optimized doubleword copy loop. */
116 srdi 12,5,7 /* Number of 128-byte blocks to move. */
117 cmpldi cr1,11,0 /* If the tail is 0 bytes */
118 bne- cr6,.L6 /* If source is not DW aligned. */
120 /* Move doublewords where destination and source are DW aligned.
121 Use a unrolled loop to copy 16 doublewords (128-bytes) per iteration.
122 If the the copy is not an exact multiple of 128 bytes, 1-15
123 doublewords are copied as needed to set up the main loop. After
124 the main loop exits there may be a tail of 1-7 bytes. These byte
125 are copied a word/halfword/byte at a time as needed to preserve
128 For POWER6 the L1 is store-through and the L2 is store-in. The
129 L2 is clocked at half CPU clock so we can store 16 bytes every
130 other cycle. POWER6 also has a load/store bypass so we can do
131 load, load, store, store every 2 cycles.
133 The following code is sensitive to cache line alignment. Do not
134 make any change with out first making sure thay don't result in
135 splitting ld/std pairs across a cache line. */
276 ble cr5,L(das_loop_e)
322 /* Check of a 1-7 byte tail, return if none. */
324 /* Return original dst pointer. */
332 /* At this point we have a tail of 0-7 bytes and we know that the
333 destiniation is double word aligned. */
361 /* Return original dst pointer. */
365 /* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31
366 bytes. Each case is handled without loops, using binary (1,2,4,8)
369 In the short (0-8 byte) case no attempt is made to force alignment
370 of either source or destination. The hardware will handle the
371 unaligned load/stores with small delays for crossing 32- 128-byte,
372 and 4096-byte boundaries. Since these short moves are unlikely to be
373 unaligned or cross these boundaries, the overhead to force
374 alignment is not justified.
376 The longer (9-31 byte) move is more likely to cross 32- or 128-byte
377 boundaries. Since only loads are sensitive to the 32-/128-byte
378 boundaries it is more important to align the source then the
379 destination. If the source is not already word aligned, we first
380 move 1-3 bytes as needed. Since we are only word aligned we don't
381 use double word load/stores to insure that all loads are aligned.
382 While the destination and stores may still be unaligned, this
383 is only an issue for page (4096 byte boundary) crossing, which
384 should be rare for these short moves. The hardware handles this
385 case automatically with a small (~20 cycle) delay. */
392 ble cr6,.LE8 /* Handle moves of 0-8 bytes. */
393 /* At least 9 bytes left. Get the source word aligned. */
398 beq L(dus_tail) /* If the source is already word aligned skip this. */
399 /* Copy 1-3 bytes to get source address word aligned. */
422 /* At least 6 bytes left and the source is word aligned. This allows
423 some speculative loads up front. */
424 /* We need to special case the fall-through because the biggest delays
425 are due to address computation not being ready in time for the
431 L(dus_tail16): /* Move 16 bytes. */
438 /* Move 8 bytes more. */
439 bf 28,L(dus_tail16p8)
445 /* Move 4 bytes more. */
446 bf 29,L(dus_tail16p4)
452 /* exactly 28 bytes. Return original dst pointer and exit. */
456 L(dus_tail16p8): /* less then 8 bytes left. */
457 beq cr1,L(dus_tailX) /* exactly 16 bytes, early exit. */
459 bf 29,L(dus_tail16p2)
460 /* Move 4 bytes more. */
466 /* exactly 20 bytes. Return original dst pointer and exit. */
470 L(dus_tail16p4): /* less then 4 bytes left. */
474 /* exactly 24 bytes. Return original dst pointer and exit. */
478 L(dus_tail16p2): /* 16 bytes moved, less then 4 bytes left. */
484 L(dus_tail8): /* Move 8 bytes. */
485 /* r6, r7 already loaded speculatively. */
492 /* Move 4 bytes more. */
499 /* exactly 12 bytes. Return original dst pointer and exit. */
503 L(dus_tail8p4): /* less then 4 bytes left. */
507 /* exactly 8 bytes. Return original dst pointer and exit. */
512 L(dus_tail4): /* Move 4 bytes. */
513 /* r6 already loaded speculatively. If we are here we know there is
514 more then 4 bytes left. So there is no need to test. */
518 L(dus_tail2): /* Move 2-3 bytes. */
527 L(dus_tail1): /* Move 1 byte. */
532 /* Return original dst pointer. */
536 /* Special case to copy 0-8 bytes. */
541 /* Exactly 8 bytes. We may cross a 32-/128-byte boundry and take a ~20
542 cycle delay. This case should be rare and any attempt to avoid this
543 would take most of 20 cycles any way. */
546 /* Return original dst pointer. */
568 /* Return original dst pointer. */
577 /* Copy doublewords where the destination is aligned but the source is
578 not. Use aligned doubleword loads from the source, shifted to realign
579 the data, to allow aligned destination stores. */
580 addi 11,9,-1 /* loop DW count is one less than total */
581 subf 5,10,12 /* Move source addr to previous full double word. */
585 srdi 8,11,2 /* calculate the 32 byte loop count */
586 ld 6,0(5) /* pre load 1st full doubleword. */
590 ld 7,8(5) /* pre load 2nd full doubleword. */
600 /* there are at least two DWs to copy */
613 blt cr6,L(du1_fini) /* if total DWs = 3, then bypass loop */
615 /* there is a third DW to copy */
624 beq cr6,L(du1_fini) /* if total DWs = 4, then bypass loop */
639 /* copy 32 bytes at a time */
666 /* calculate and store the final DW */
677 /* there are at least two DWs to copy */
690 blt cr6,L(du2_fini) /* if total DWs = 3, then bypass loop */
692 /* there is a third DW to copy */
701 beq cr6,L(du2_fini) /* if total DWs = 4, then bypass loop */
716 /* copy 32 bytes at a time */
743 /* calculate and store the final DW */
754 /* there are at least two DWs to copy */
767 blt cr6,L(du3_fini) /* if total DWs = 3, then bypass loop */
769 /* there is a third DW to copy */
778 beq cr6,L(du3_fini) /* if total DWs = 4, then bypass loop */
793 /* copy 32 bytes at a time */
820 /* calculate and store the final DW */
837 /* there are at least two DWs to copy */
850 blt cr6,L(du4_fini) /* if total DWs = 3, then bypass loop */
852 /* there is a third DW to copy */
861 beq cr6,L(du4_fini) /* if total DWs = 4, then bypass loop */
876 /* copy 32 bytes at a time */
903 /* calculate and store the final DW */
914 /* there are at least two DWs to copy */
927 blt cr6,L(du5_fini) /* if total DWs = 3, then bypass loop */
929 /* there is a third DW to copy */
938 beq cr6,L(du5_fini) /* if total DWs = 4, then bypass loop */
953 /* copy 32 bytes at a time */
980 /* calculate and store the final DW */
991 /* there are at least two DWs to copy */
1004 blt cr6,L(du6_fini) /* if total DWs = 3, then bypass loop */
1006 /* there is a third DW to copy */
1015 beq cr6,L(du6_fini) /* if total DWs = 4, then bypass loop */
1030 /* copy 32 bytes at a time */
1057 /* calculate and store the final DW */
1068 /* there are at least two DWs to copy */
1081 blt cr6,L(du7_fini) /* if total DWs = 3, then bypass loop */
1083 /* there is a third DW to copy */
1092 beq cr6,L(du7_fini) /* if total DWs = 4, then bypass loop */
1107 /* copy 32 bytes at a time */
1134 /* calculate and store the final DW */
1145 beq cr1,0f /* If the tail is 0 bytes we are done! */
1149 /* At this point we have a tail of 0-7 bytes and we know that the
1150 destiniation is double word aligned. */
1165 /* Return original dst pointer. */
1169 END_GEN_TB (BP_SYM (memcpy),TB_TOCLESS)
1170 libc_hidden_builtin_def (memcpy)