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[glibc/nacl-glibc.git] / sysdeps / powerpc / fpu / fpu_control.h
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1 /* FPU control word definitions. PowerPC version.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, write to the Free
17 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18 02111-1307 USA. */
20 #ifndef _FPU_CONTROL_H
21 #define _FPU_CONTROL_H
23 /* rounding control */
24 #define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
25 #define _FPU_RC_DOWN 0x03
26 #define _FPU_RC_UP 0x02
27 #define _FPU_RC_ZERO 0x01
29 #define _FPU_MASK_NI 0x04 /* non-ieee mode */
31 /* masking of interrupts */
32 #define _FPU_MASK_ZM 0x10 /* zero divide */
33 #define _FPU_MASK_OM 0x40 /* overflow */
34 #define _FPU_MASK_UM 0x20 /* underflow */
35 #define _FPU_MASK_XM 0x08 /* inexact */
36 #define _FPU_MASK_IM 0x80 /* invalid operation */
38 #define _FPU_RESERVED 0xffffff00 /* These bits are reserved are not changed. */
40 /* The fdlibm code requires no interrupts for exceptions. */
41 #define _FPU_DEFAULT 0x00000000 /* Default value. */
43 /* IEEE: same as above, but (some) exceptions;
44 we leave the 'inexact' exception off.
46 #define _FPU_IEEE 0x000000f0
48 /* Type of the control word. */
49 typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
51 /* Macros for accessing the hardware control word. */
52 #define _FPU_GETCW(__cw) ( { \
53 union { double d; fpu_control_t cw[2]; } \
54 tmp __attribute__ ((__aligned__(8))); \
55 __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
56 (__cw)=tmp.cw[1]; \
57 tmp.cw[1]; } )
58 #define _FPU_SETCW(__cw) { \
59 union { double d; fpu_control_t cw[2]; } \
60 tmp __attribute__ ((__aligned__(8))); \
61 tmp.cw[0] = 0xFFF80000; /* More-or-less arbitrary; this is a QNaN. */ \
62 tmp.cw[1] = __cw; \
63 __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \
66 /* Default control word set at startup. */
67 extern fpu_control_t __fpu_control;
69 #endif /* _FPU_CONTROL_H */