sysdeps/powerpc/fpu/fenv_libc.h

   1 /* Internal libc stuff for floating point environment routines.
   2    Copyright (C) 1997, 2006, 2008 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #ifndef _FENV_LIBC_H
  21 #define _FENV_LIBC_H    1
  22
  23 #include <fenv.h>
  24
  25 libm_hidden_proto (__fe_nomask_env)
  26
  27 /* The sticky bits in the FPSCR indicating exceptions have occurred.  */
  28 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
  29
  30 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
  31    pointer.  */
  32 #define fegetenv_register() \
  33         ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
  34
  35 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
  36 #define fesetenv_register(env) \
  37         ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
  38
  39 /* This very handy macro:
  40    - Sets the rounding mode to 'round to nearest';
  41    - Sets the processor into IEEE mode; and
  42    - Prevents exceptions from being raised for inexact results.
  43    These things happen to be exactly what you need for typical elementary
  44    functions.  */
  45 #define relax_fenv_state() asm ("mtfsfi 7,0")
  46
  47 /* Set/clear a particular FPSCR bit (for instance,
  48    reset_fpscr_bit(FPSCR_VE);
  49    prevents INVALID exceptions from being raised).  */
  50 #define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
  51 #define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
  52
  53 typedef union
  54 {
  55   fenv_t fenv;
  56   unsigned int l[2];
  57 } fenv_union_t;
  58
  59
  60 static inline int
  61 __fegetround (void)
  62 {
  63   int result;
  64   asm volatile ("mcrfs 7,7\n\t"
  65                 "mfcr  %0" : "=r"(result) : : "cr7");
  66   return result & 3;
  67 }
  68 #define fegetround() __fegetround()
  69
  70 static inline int
  71 __fesetround (int round)
  72 {
  73   if ((unsigned int) round < 2)
  74     {
  75        asm volatile ("mtfsb0 30");
  76        if ((unsigned int) round == 0)
  77          asm volatile ("mtfsb0 31");
  78        else
  79          asm volatile ("mtfsb1 31");
  80     }
  81   else
  82     {
  83        asm volatile ("mtfsb1 30");
  84        if ((unsigned int) round == 2)
  85          asm volatile ("mtfsb0 31");
  86        else
  87          asm volatile ("mtfsb1 31");
  88     }
  89
  90   return 0;
  91 }
  92 #define fesetround(mode) __fesetround(mode)
  93
  94 /* Definitions of all the FPSCR bit numbers */
  95 enum {
  96   FPSCR_FX = 0,    /* exception summary */
  97   FPSCR_FEX,       /* enabled exception summary */
  98   FPSCR_VX,        /* invalid operation summary */
  99   FPSCR_OX,        /* overflow */
 100   FPSCR_UX,        /* underflow */
 101   FPSCR_ZX,        /* zero divide */
 102   FPSCR_XX,        /* inexact */
 103   FPSCR_VXSNAN,    /* invalid operation for SNaN */
 104   FPSCR_VXISI,     /* invalid operation for Inf-Inf */
 105   FPSCR_VXIDI,     /* invalid operation for Inf/Inf */
 106   FPSCR_VXZDZ,     /* invalid operation for 0/0 */
 107   FPSCR_VXIMZ,     /* invalid operation for Inf*0 */
 108   FPSCR_VXVC,      /* invalid operation for invalid compare */
 109   FPSCR_FR,        /* fraction rounded [fraction was incremented by round] */
 110   FPSCR_FI,        /* fraction inexact */
 111   FPSCR_FPRF_C,    /* result class descriptor */
 112   FPSCR_FPRF_FL,   /* result less than (usually, less than 0) */
 113   FPSCR_FPRF_FG,   /* result greater than */
 114   FPSCR_FPRF_FE,   /* result equal to */
 115   FPSCR_FPRF_FU,   /* result unordered */
 116   FPSCR_20,        /* reserved */
 117   FPSCR_VXSOFT,    /* invalid operation set by software */
 118   FPSCR_VXSQRT,    /* invalid operation for square root */
 119   FPSCR_VXCVI,     /* invalid operation for invalid integer convert */
 120   FPSCR_VE,        /* invalid operation exception enable */
 121   FPSCR_OE,        /* overflow exception enable */
 122   FPSCR_UE,        /* underflow exception enable */
 123   FPSCR_ZE,        /* zero divide exception enable */
 124   FPSCR_XE,        /* inexact exception enable */
 125   FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
 126   /* the remaining two least-significant bits keep the rounding mode */
 127 };
 128
 129 /* This operation (i) sets the appropriate FPSCR bits for its
 130    parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
 131    otherwise passes its parameter through unchanged (in particular, -0
 132    and +0 stay as they were).  The `obvious' way to do this is optimised
 133    out by gcc.  */
 134 #define f_wash(x) \
 135    ({ double d; asm volatile ("fmul %0,%1,%2" \
 136                               : "=f"(d) \
 137                               : "f" (x), "f"((float)1.0)); d; })
 138 #define f_washf(x) \
 139    ({ float f; asm volatile ("fmuls %0,%1,%2" \
 140                              : "=f"(f) \
 141                              : "f" (x), "f"((float)1.0)); f; })
 142
 143 #endif /* fenv_libc.h */