2.9
[glibc/nacl-glibc.git] / nptl / sysdeps / unix / sysv / linux / sh / sh4 / lowlevellock.h
blob90be7bd8d041ab43c7eaa519daae56d5b8c44b09
1 /* 4 instruction cycles not accessing cache and TLB are needed after
2 trapa instruction to avoid an SH-4 silicon bug. */
3 #define NEED_SYSCALL_INST_PAD
4 #include_next <lowlevellock.h>