1 /* Facilities specific to the PowerPC architecture
2 Copyright (C) 2012-2014 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
19 #ifndef _SYS_PLATFORM_PPC_H
20 #define _SYS_PLATFORM_PPC_H 1
26 /* Read the Time Base Register. */
27 static inline uint64_t
28 __ppc_get_timebase (void)
30 #if __GNUC_PREREQ (4, 8)
31 return __builtin_ppc_get_timebase ();
35 /* "volatile" is necessary here, because the user expects this assembly
36 isn't moved after an optimization. */
37 __asm__
volatile ("mfspr %0, 268" : "=r" (__tb
));
39 # else /* not __powerpc64__ */
40 uint32_t __tbu
, __tbl
, __tmp
; \
41 __asm__
volatile ("0:\n\t"
47 : "=r" (__tbu
), "=r" (__tbl
), "=r" (__tmp
));
48 return (((uint64_t) __tbu
<< 32) | __tbl
);
49 # endif /* not __powerpc64__ */
53 /* The following functions provide hints about the usage of shared processor
54 resources, as defined in ISA 2.06 and newer. */
56 /* Provides a hint that performance will probably be improved if shared
57 resources dedicated to the executing processor are released for use by other
62 __asm__
volatile ("or 27,27,27");
65 /* Provides a hint that performance will probably be improved if shared
66 resources dedicated to the executing processor are released until
67 all outstanding storage accesses to caching-inhibited storage have been
72 __asm__
volatile ("or 29,29,29");
75 /* Provides a hint that performance will probably be improved if shared
76 resources dedicated to the executing processor are released until all
77 outstanding storage accesses to cacheable storage for which the data is not
78 in the cache have been completed. */
82 __asm__
volatile ("or 30,30,30");
86 /* ISA 2.05 and beyond support the Program Priority Register (PPR) to adjust
87 thread priorities based on lock acquisition, wait and release. The ISA
88 defines the use of form 'or Rx,Rx,Rx' as the way to modify the PRI field.
89 The unprivileged priorities are:
92 Rx = 6 (medium-low/normal)
93 The 'or' instruction form is a nop in previous hardware, so it is safe to
94 use unguarded. The default value is 'medium'.
98 __ppc_set_ppr_med (void)
100 __asm__
volatile ("or 2,2,2");
104 __ppc_set_ppr_med_low (void)
106 __asm__
volatile ("or 6,6,6");
110 __ppc_set_ppr_low (void)
112 __asm__
volatile ("or 1,1,1");
115 #endif /* sys/platform/ppc.h */