sysdeps/powerpc/bits/hwcap.h

   1 /* Defines for bits in AT_HWCAP and AT_HWCAP2.
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, see
  17    <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef _SYS_AUXV_H
  20 # error "Never include <bits/hwcap.h> directly; use <sys/auxv.h> instead."
  21 #endif
  22
  23 /* The bit numbers must match those in the kernel's asm/cputable.h.  */
  24
  25 /* Feature definitions in AT_HWCAP.  */
  26 #define PPC_FEATURE_32              0x80000000 /* 32-bit mode. */
  27 #define PPC_FEATURE_64              0x40000000 /* 64-bit mode. */
  28 #define PPC_FEATURE_601_INSTR       0x20000000 /* 601 chip, Old POWER ISA.  */
  29 #define PPC_FEATURE_HAS_ALTIVEC     0x10000000 /* SIMD/Vector Unit.  */
  30 #define PPC_FEATURE_HAS_FPU         0x08000000 /* Floating Point Unit.  */
  31 #define PPC_FEATURE_HAS_MMU         0x04000000 /* Memory Management Unit.  */
  32 #define PPC_FEATURE_HAS_4xxMAC      0x02000000 /* 4xx Multiply Accumulator.  */
  33 #define PPC_FEATURE_UNIFIED_CACHE   0x01000000 /* Unified I/D cache.  */
  34 #define PPC_FEATURE_HAS_SPE         0x00800000 /* Signal Processing ext.  */
  35 #define PPC_FEATURE_HAS_EFP_SINGLE  0x00400000 /* SPE Float.  */
  36 #define PPC_FEATURE_HAS_EFP_DOUBLE  0x00200000 /* SPE Double.  */
  37 #define PPC_FEATURE_NO_TB           0x00100000 /* 601/403gx have no timebase */
  38 #define PPC_FEATURE_POWER4          0x00080000 /* POWER4 ISA 2.00 */
  39 #define PPC_FEATURE_POWER5          0x00040000 /* POWER5 ISA 2.02 */
  40 #define PPC_FEATURE_POWER5_PLUS     0x00020000 /* POWER5+ ISA 2.03 */
  41 #define PPC_FEATURE_CELL_BE         0x00010000 /* CELL Broadband Engine */
  42 #define PPC_FEATURE_BOOKE           0x00008000 /* ISA Category Embedded */
  43 #define PPC_FEATURE_SMT             0x00004000 /* Simultaneous
  44                                                   Multi-Threading */
  45 #define PPC_FEATURE_ICACHE_SNOOP    0x00002000
  46 #define PPC_FEATURE_ARCH_2_05       0x00001000 /* ISA 2.05 */
  47 #define PPC_FEATURE_PA6T            0x00000800 /* PA Semi 6T Core */
  48 #define PPC_FEATURE_HAS_DFP         0x00000400 /* Decimal FP Unit */
  49 #define PPC_FEATURE_POWER6_EXT      0x00000200 /* P6 + mffgpr/mftgpr */
  50 #define PPC_FEATURE_ARCH_2_06       0x00000100 /* ISA 2.06 */
  51 #define PPC_FEATURE_HAS_VSX         0x00000080 /* P7 Vector Extension.  */
  52 #define PPC_FEATURE_PSERIES_PERFMON_COMPAT  0x00000040
  53 #define PPC_FEATURE_TRUE_LE         0x00000002
  54 #define PPC_FEATURE_PPC_LE          0x00000001
  55
  56 /* Feature definitions in AT_HWCAP2.  */
  57 #define PPC_FEATURE2_ARCH_2_07     0x80000000 /* ISA 2.07 */
  58 #define PPC_FEATURE2_HAS_HTM       0x40000000 /* Hardware Transactional
  59                                                  Memory */
  60 #define PPC_FEATURE2_HAS_DSCR      0x20000000 /* Data Stream Control
  61                                                  Register */
  62 #define PPC_FEATURE2_HAS_EBB       0x10000000 /* Event Base Branching */
  63 #define PPC_FEATURE2_HAS_ISEL      0x08000000 /* Integer Select */
  64 #define PPC_FEATURE2_HAS_TAR       0x04000000 /* Target Address Register */