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[glibc.git] / ports / sysdeps / mips / sys / ucontext.h
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1 /* Copyright (C) 1998-2014 Free Software Foundation, Inc.
2 This file is part of the GNU C Library.
4 The GNU C Library is free software; you can redistribute it and/or
5 modify it under the terms of the GNU Lesser General Public
6 License as published by the Free Software Foundation; either
7 version 2.1 of the License, or (at your option) any later version.
9 The GNU C Library is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 Lesser General Public License for more details.
14 You should have received a copy of the GNU Lesser General Public
15 License along with the GNU C Library. If not, see
16 <http://www.gnu.org/licenses/>. */
18 /* System V/mips ABI compliant context switching support. */
20 #ifndef _SYS_UCONTEXT_H
21 #define _SYS_UCONTEXT_H 1
23 #include <features.h>
24 #include <sgidefs.h>
25 #include <signal.h>
27 /* Type for general register. */
28 #if _MIPS_SIM == _ABIO32
29 typedef __uint32_t greg_t;
30 #else
31 typedef __uint64_t greg_t;
32 #endif
34 /* Number of general registers. */
35 #define NGREG 36
37 /* Container for all general registers. */
38 typedef greg_t gregset_t[NGREG];
40 /* Number of each register is the `gregset_t' array. */
41 enum
43 CTX_R0 = 0,
44 #define CTX_R0 CTX_R0
45 CTX_AT = 1,
46 #define CTX_AT CTX_AT
47 CTX_V0 = 2,
48 #define CTX_V0 CTX_V0
49 CTX_V1 = 3,
50 #define CTX_V1 CTX_V1
51 CTX_A0 = 4,
52 #define CTX_A0 CTX_A0
53 CTX_A1 = 5,
54 #define CTX_A1 CTX_A1
55 CTX_A2 = 6,
56 #define CTX_A2 CTX_A2
57 CTX_A3 = 7,
58 #define CTX_A3 CTX_A3
59 CTX_T0 = 8,
60 #define CTX_T0 CTX_T0
61 CTX_T1 = 9,
62 #define CTX_T1 CTX_T1
63 CTX_T2 = 10,
64 #define CTX_T2 CTX_T2
65 CTX_T3 = 11,
66 #define CTX_T3 CTX_T3
67 CTX_T4 = 12,
68 #define CTX_T4 CTX_T4
69 CTX_T5 = 13,
70 #define CTX_T5 CTX_T5
71 CTX_T6 = 14,
72 #define CTX_T6 CTX_T6
73 CTX_T7 = 15,
74 #define CTX_T7 CTX_T7
75 CTX_S0 = 16,
76 #define CTX_S0 CTX_S0
77 CTX_S1 = 17,
78 #define CTX_S1 CTX_S1
79 CTX_S2 = 18,
80 #define CTX_S2 CTX_S2
81 CTX_S3 = 19,
82 #define CTX_S3 CTX_S3
83 CTX_S4 = 20,
84 #define CTX_S4 CTX_S4
85 CTX_S5 = 21,
86 #define CTX_S5 CTX_S5
87 CTX_S6 = 22,
88 #define CTX_S6 CTX_S6
89 CTX_S7 = 23,
90 #define CTX_S7 CTX_S7
91 CTX_T8 = 24,
92 #define CTX_T8 CTX_T8
93 CTX_T9 = 25,
94 #define CTX_T9 CTX_T9
95 CTX_K0 = 26,
96 #define CTX_K0 CTX_K0
97 CTX_K1 = 27,
98 #define CTX_K1 CTX_K1
99 CTX_GP = 28,
100 #define CTX_GP CTX_GP
101 CTX_SP = 29,
102 #define CTX_SP CTX_SP
103 CTX_S8 = 30,
104 #define CTX_S8 CTX_S8
105 CTX_RA = 31,
106 #define CTX_RA CTX_RA
107 CTX_MDLO = 32,
108 #define CTX_MDLO CTX_MDLO
109 CTX_MDHI = 33,
110 #define CTX_MDHI CTX_MDHI
111 CTX_CAUSE = 34,
112 #define CTX_CAUSE CTX_CAUSE
113 CTX_EPC = 35,
114 #define CTX_EPC CTX_EPC
117 /* Structure to describe FPU registers. */
118 typedef struct fpregset
120 union
122 #if _MIPS_SIM == _ABIO32
123 double fp_dregs[16];
124 float fp_fregs[32];
125 unsigned int fp_regs[32];
126 #else
127 double fp_dregs[32];
128 /* float fp_fregs[32]; */
129 __uint64_t fp_regs[32];
130 #endif
131 } fp_r;
132 unsigned int fp_csr;
133 unsigned int fp_pad;
134 } fpregset_t;
136 /* Context to describe whole processor state. */
137 typedef struct
139 gregset_t gpregs;
140 fpregset_t fpregs;
141 } mcontext_t;
143 /* Userlevel context. */
144 typedef struct ucontext
146 #if _MIPS_SIM == _ABIO32
147 unsigned long int uc_flags;
148 #else
149 __uint64_t uc_flags;
150 #endif
151 struct ucontext *uc_link;
152 __sigset_t uc_sigmask;
153 stack_t uc_stack;
154 mcontext_t uc_mcontext;
155 int uc_filler[48];
156 } ucontext_t;
158 #endif /* sys/ucontext.h */