sysdeps/unix/sysv/linux/alpha/ioperm.c

   1 /* Copyright (C) 1992-2015 Free Software Foundation, Inc.
   2    This file is part of the GNU C Library.
   3    Contributed by David Mosberger.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library.  If not, see
  17    <http://www.gnu.org/licenses/>.  */
  18
  19 /* I/O access is restricted to ISA port space (ports 0..65535).
  20    Modern devices hopefully are sane enough not to put any performance
  21    critical registers in i/o space.
  22
  23    On the first call to ioperm, the entire (E)ISA port space is mapped
  24    into the virtual address space at address io.base.  mprotect calls
  25    are then used to enable/disable access to ports.  Per page, there
  26    are PAGE_SIZE>>IO_SHIFT I/O ports (e.g., 256 ports on a Low Cost Alpha
  27    based system using 8KB pages).
  28
  29    Keep in mind that this code should be able to run in a 32bit address
  30    space.  It is therefore unreasonable to expect mmap'ing the entire
  31    sparse address space would work (e.g., the Low Cost Alpha chip has an
  32    I/O address space that's 512MB large!).  */
  33
  34 /* Make sure the ldbu/stb asms below are not expaneded to macros.  */
  35 #ifndef __alpha_bwx__
  36 asm(".arch ev56");
  37 #endif
  38
  39 #include <errno.h>
  40 #include <fcntl.h>
  41 #include <stdio.h>
  42 #include <ctype.h>
  43 #include <stdlib.h>
  44 #include <string.h>
  45 #include <unistd.h>
  46
  47 #include <sys/types.h>
  48 #include <sys/mman.h>
  49 #include <sys/io.h>
  50
  51 #include <sysdep.h>
  52 #include <sys/syscall.h>
  53
  54 #define PATH_ALPHA_SYSTYPE      "/etc/alpha_systype"
  55 #define PATH_CPUINFO            "/proc/cpuinfo"
  56
  57 #define MAX_PORT        0x10000
  58 #define vip             volatile int *
  59 #define vuip            volatile unsigned int *
  60 #define vusp            volatile unsigned short *
  61 #define vucp            volatile unsigned char *
  62
  63 #define JENSEN_IO_BASE          (0x300000000UL)
  64 #define JENSEN_SPARSE_MEM       (0x200000000UL)
  65
  66 /* With respect to the I/O architecture, APECS and LCA are identical,
  67    so the following defines apply to LCA as well.  */
  68 #define APECS_IO_BASE           (0x1c0000000UL)
  69 #define APECS_SPARSE_MEM        (0x200000000UL)
  70 #define APECS_DENSE_MEM         (0x300000000UL)
  71
  72 /* The same holds for CIA and PYXIS, except for PYXIS we prefer BWX.  */
  73 #define CIA_IO_BASE             (0x8580000000UL)
  74 #define CIA_SPARSE_MEM          (0x8000000000UL)
  75 #define CIA_DENSE_MEM           (0x8600000000UL)
  76
  77 #define PYXIS_IO_BASE           (0x8900000000UL)
  78 #define PYXIS_DENSE_MEM         (0x8800000000UL)
  79
  80 /* SABLE is EV4, GAMMA is EV5 */
  81 #define T2_IO_BASE              (0x3a0000000UL)
  82 #define T2_SPARSE_MEM           (0x200000000UL)
  83 #define T2_DENSE_MEM            (0x3c0000000UL)
  84
  85 #define GAMMA_IO_BASE           (0x83a0000000UL)
  86 #define GAMMA_SPARSE_MEM        (0x8200000000UL)
  87 #define GAMMA_DENSE_MEM         (0x83c0000000UL)
  88
  89 /* NOTE: these are hardwired to PCI bus 0 addresses!!! */
  90 #define MCPCIA_IO_BASE          (0xf980000000UL)
  91 #define MCPCIA_SPARSE_MEM       (0xf800000000UL)
  92 #define MCPCIA_DENSE_MEM        (0xf900000000UL)
  93
  94 /* Tsunami and Irongate use the same offsets, at least for hose 0.  */
  95 #define TSUNAMI_IO_BASE         (0x801fc000000UL)
  96 #define TSUNAMI_DENSE_MEM       (0x80000000000UL)
  97
  98 /* Polaris has SPARSE space, but we prefer to use only DENSE
  99    because of some idiosyncracies in actually using SPARSE.  */
 100 #define POLARIS_IO_BASE         (0xf9fc000000UL)
 101 #define POLARIS_DENSE_MEM       (0xf900000000UL)
 102
 103 typedef enum {
 104   IOSYS_UNKNOWN, IOSYS_JENSEN, IOSYS_APECS, IOSYS_CIA, IOSYS_PYXIS, IOSYS_T2,
 105   IOSYS_TSUNAMI, IOSYS_MCPCIA, IOSYS_GAMMA, IOSYS_POLARIS,
 106   IOSYS_CPUDEP, IOSYS_PCIDEP
 107 } iosys_t;
 108
 109 typedef enum {
 110   IOSWIZZLE_JENSEN, IOSWIZZLE_SPARSE, IOSWIZZLE_DENSE
 111 } ioswizzle_t;
 112
 113 static struct io_system {
 114   unsigned long int bus_memory_base;
 115   unsigned long int sparse_bus_mem_base;
 116   unsigned long int bus_io_base;
 117 } io_system[] = { /* NOTE! must match iosys_t enumeration */
 118 /* UNKNOWN */   {0, 0, 0},
 119 /* JENSEN */    {0, JENSEN_SPARSE_MEM, JENSEN_IO_BASE},
 120 /* APECS */     {APECS_DENSE_MEM, APECS_SPARSE_MEM, APECS_IO_BASE},
 121 /* CIA */       {CIA_DENSE_MEM, CIA_SPARSE_MEM, CIA_IO_BASE},
 122 /* PYXIS */     {PYXIS_DENSE_MEM, 0, PYXIS_IO_BASE},
 123 /* T2 */        {T2_DENSE_MEM, T2_SPARSE_MEM, T2_IO_BASE},
 124 /* TSUNAMI */   {TSUNAMI_DENSE_MEM, 0, TSUNAMI_IO_BASE},
 125 /* MCPCIA */    {MCPCIA_DENSE_MEM, MCPCIA_SPARSE_MEM, MCPCIA_IO_BASE},
 126 /* GAMMA */     {GAMMA_DENSE_MEM, GAMMA_SPARSE_MEM, GAMMA_IO_BASE},
 127 /* POLARIS */   {POLARIS_DENSE_MEM, 0, POLARIS_IO_BASE},
 128 /* CPUDEP */    {0, 0, 0}, /* for platforms dependent on CPU type */
 129 /* PCIDEP */    {0, 0, 0}, /* for platforms dependent on core logic */
 130 };
 131
 132 static struct platform {
 133   const char       *name;
 134   iosys_t           io_sys;
 135 } platform[] = {
 136   {"Alcor",     IOSYS_CIA},
 137   {"Avanti",    IOSYS_APECS},
 138   {"Cabriolet", IOSYS_APECS},
 139   {"EB164",     IOSYS_PCIDEP},
 140   {"EB64+",     IOSYS_APECS},
 141   {"EB66",      IOSYS_APECS},
 142   {"EB66P",     IOSYS_APECS},
 143   {"Jensen",    IOSYS_JENSEN},
 144   {"Miata",     IOSYS_PYXIS},
 145   {"Mikasa",    IOSYS_CPUDEP},
 146   {"Nautilus",  IOSYS_TSUNAMI},
 147   {"Noname",    IOSYS_APECS},
 148   {"Noritake",  IOSYS_CPUDEP},
 149   {"Rawhide",   IOSYS_MCPCIA},
 150   {"Ruffian",   IOSYS_PYXIS},
 151   {"Sable",     IOSYS_CPUDEP},
 152   {"Takara",    IOSYS_CIA},
 153   {"Tsunami",   IOSYS_TSUNAMI},
 154   {"XL",        IOSYS_APECS},
 155 };
 156
 157 struct ioswtch {
 158   void          (*sethae)(unsigned long int addr);
 159   void          (*outb)(unsigned char b, unsigned long int port);
 160   void          (*outw)(unsigned short b, unsigned long int port);
 161   void          (*outl)(unsigned int b, unsigned long int port);
 162   unsigned int  (*inb)(unsigned long int port);
 163   unsigned int  (*inw)(unsigned long int port);
 164   unsigned int  (*inl)(unsigned long int port);
 165 };
 166
 167 static struct {
 168   unsigned long int hae_cache;
 169   unsigned long int     base;
 170   struct ioswtch *      swp;
 171   unsigned long int     bus_memory_base;
 172   unsigned long int     sparse_bus_memory_base;
 173   unsigned long int     io_base;
 174   ioswizzle_t           swiz;
 175 } io;
 176
 177 static inline void
 178 stb_mb(unsigned char val, unsigned long addr)
 179 {
 180   __asm__("stb %1,%0; mb" : "=m"(*(vucp)addr) : "r"(val));
 181 }
 182
 183 static inline void
 184 stw_mb(unsigned short val, unsigned long addr)
 185 {
 186   __asm__("stw %1,%0; mb" : "=m"(*(vusp)addr) : "r"(val));
 187 }
 188
 189 static inline void
 190 stl_mb(unsigned int val, unsigned long addr)
 191 {
 192   __asm__("stl %1,%0; mb" : "=m"(*(vip)addr) : "r"(val));
 193 }
 194
 195 /* No need to examine error -- sethae never fails.  */
 196 static inline void
 197 __sethae(unsigned long value)
 198 {
 199   register unsigned long r16 __asm__("$16") = value;
 200   register unsigned long r0 __asm__("$0") = __NR_sethae;
 201   __asm__ __volatile__ ("callsys"
 202                         : "=r"(r0)
 203                         : "0"(r0), "r" (r16)
 204                         : inline_syscall_clobbers, "$19");
 205 }
 206
 207 extern long __pciconfig_iobase(enum __pciconfig_iobase_which __which,
 208                                unsigned long int __bus,
 209                                unsigned long int __dfn);
 210
 211 static inline unsigned long int
 212 port_to_cpu_addr (unsigned long int port, ioswizzle_t ioswiz, int size)
 213 {
 214   if (ioswiz == IOSWIZZLE_SPARSE)
 215     return io.base + (port << 5) + ((size - 1) << 3);
 216   else if (ioswiz == IOSWIZZLE_DENSE)
 217     return port + io.base;
 218   else
 219     return io.base + (port << 7) + ((size - 1) << 5);
 220 }
 221
 222 static inline __attribute__((always_inline)) void
 223 inline_sethae (unsigned long int addr, ioswizzle_t ioswiz)
 224 {
 225   if (ioswiz == IOSWIZZLE_SPARSE)
 226     {
 227       unsigned long int msb;
 228
 229       /* no need to set hae if msb is 0: */
 230       msb = addr & 0xf8000000;
 231       if (msb && msb != io.hae_cache)
 232         {
 233           io.hae_cache = msb;
 234           __sethae (msb);
 235         }
 236     }
 237   else if (ioswiz == IOSWIZZLE_JENSEN)
 238     {
 239       /* HAE on the Jensen is bits 31:25 shifted right.  */
 240       addr >>= 25;
 241       if (addr != io.hae_cache)
 242         {
 243           io.hae_cache = addr;
 244           __sethae (addr);
 245         }
 246     }
 247 }
 248
 249 static inline void
 250 inline_outb (unsigned char b, unsigned long int port, ioswizzle_t ioswiz)
 251 {
 252   unsigned int w;
 253   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
 254
 255   asm ("insbl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
 256   stl_mb(w, addr);
 257 }
 258
 259
 260 static inline void
 261 inline_outw (unsigned short int b, unsigned long int port, ioswizzle_t ioswiz)
 262 {
 263   unsigned long w;
 264   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
 265
 266   asm ("inswl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
 267   stl_mb(w, addr);
 268 }
 269
 270
 271 static inline void
 272 inline_outl (unsigned int b, unsigned long int port, ioswizzle_t ioswiz)
 273 {
 274   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
 275
 276   stl_mb(b, addr);
 277 }
 278
 279
 280 static inline unsigned int
 281 inline_inb (unsigned long int port, ioswizzle_t ioswiz)
 282 {
 283   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
 284   int result;
 285
 286   result = *(vip) addr;
 287   result >>= (port & 3) * 8;
 288   return 0xffUL & result;
 289 }
 290
 291
 292 static inline unsigned int
 293 inline_inw (unsigned long int port, ioswizzle_t ioswiz)
 294 {
 295   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
 296   int result;
 297
 298   result = *(vip) addr;
 299   result >>= (port & 3) * 8;
 300   return 0xffffUL & result;
 301 }
 302
 303
 304 static inline unsigned int
 305 inline_inl (unsigned long int port, ioswizzle_t ioswiz)
 306 {
 307   unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
 308
 309   return *(vuip) addr;
 310 }
 311
 312 /*
 313  * Now define the inline functions for CPUs supporting byte/word insns,
 314  * and whose core logic supports I/O space accesses utilizing them.
 315  *
 316  * These routines could be used by MIATA, for example, because it has
 317  * and EV56 plus PYXIS, but it currently uses SPARSE anyway. This is
 318  * also true of RX164 which used POLARIS, but we will choose to use
 319  * these routines in that case instead of SPARSE.
 320  *
 321  * These routines are necessary for TSUNAMI/TYPHOON based platforms,
 322  * which will have (at least) EV6.
 323  */
 324
 325 static inline unsigned long int
 326 dense_port_to_cpu_addr (unsigned long int port)
 327 {
 328   return port + io.base;
 329 }
 330
 331 static inline void
 332 inline_bwx_outb (unsigned char b, unsigned long int port)
 333 {
 334   unsigned long int addr = dense_port_to_cpu_addr (port);
 335   stb_mb (b, addr);
 336 }
 337
 338 static inline void
 339 inline_bwx_outw (unsigned short int b, unsigned long int port)
 340 {
 341   unsigned long int addr = dense_port_to_cpu_addr (port);
 342   stw_mb (b, addr);
 343 }
 344
 345 static inline void
 346 inline_bwx_outl (unsigned int b, unsigned long int port)
 347 {
 348   unsigned long int addr = dense_port_to_cpu_addr (port);
 349   stl_mb (b, addr);
 350 }
 351
 352 static inline unsigned int
 353 inline_bwx_inb (unsigned long int port)
 354 {
 355   unsigned long int addr = dense_port_to_cpu_addr (port);
 356   unsigned char r;
 357
 358   __asm__ ("ldbu %0,%1" : "=r"(r) : "m"(*(vucp)addr));
 359   return r;
 360 }
 361
 362 static inline unsigned int
 363 inline_bwx_inw (unsigned long int port)
 364 {
 365   unsigned long int addr = dense_port_to_cpu_addr (port);
 366   unsigned short r;
 367
 368   __asm__ ("ldwu %0,%1" : "=r"(r) : "m"(*(vusp)addr));
 369   return r;
 370 }
 371
 372 static inline unsigned int
 373 inline_bwx_inl (unsigned long int port)
 374 {
 375   unsigned long int addr = dense_port_to_cpu_addr (port);
 376
 377   return *(vuip) addr;
 378 }
 379
 380 /* macros to define routines with appropriate names and functions */
 381
 382 /* these do either SPARSE or JENSEN swizzle */
 383
 384 #define DCL_SETHAE(name, ioswiz)                        \
 385 static void                                             \
 386 name##_sethae (unsigned long int addr)                  \
 387 {                                                       \
 388   inline_sethae (addr, IOSWIZZLE_##ioswiz);             \
 389 }
 390
 391 #define DCL_OUT(name, func, type, ioswiz)               \
 392 static void                                             \
 393 name##_##func (unsigned type b, unsigned long int addr) \
 394 {                                                       \
 395   inline_##func (b, addr, IOSWIZZLE_##ioswiz);          \
 396 }
 397
 398 #define DCL_IN(name, func, ioswiz)                      \
 399 static unsigned int                                     \
 400 name##_##func (unsigned long int addr)                  \
 401 {                                                       \
 402   return inline_##func (addr, IOSWIZZLE_##ioswiz);      \
 403 }
 404
 405 /* these do DENSE, so no swizzle is needed */
 406
 407 #define DCL_OUT_BWX(name, func, type)                   \
 408 static void                                             \
 409 name##_##func (unsigned type b, unsigned long int addr) \
 410 {                                                       \
 411   inline_bwx_##func (b, addr);                          \
 412 }
 413
 414 #define DCL_IN_BWX(name, func)                          \
 415 static unsigned int                                     \
 416 name##_##func (unsigned long int addr)                  \
 417 {                                                       \
 418   return inline_bwx_##func (addr);                      \
 419 }
 420
 421 /* now declare/define the necessary routines */
 422
 423 DCL_SETHAE(jensen, JENSEN)
 424 DCL_OUT(jensen, outb, char,  JENSEN)
 425 DCL_OUT(jensen, outw, short int, JENSEN)
 426 DCL_OUT(jensen, outl, int,   JENSEN)
 427 DCL_IN(jensen, inb, JENSEN)
 428 DCL_IN(jensen, inw, JENSEN)
 429 DCL_IN(jensen, inl, JENSEN)
 430
 431 DCL_SETHAE(sparse, SPARSE)
 432 DCL_OUT(sparse, outb, char,  SPARSE)
 433 DCL_OUT(sparse, outw, short int, SPARSE)
 434 DCL_OUT(sparse, outl, int,   SPARSE)
 435 DCL_IN(sparse, inb, SPARSE)
 436 DCL_IN(sparse, inw, SPARSE)
 437 DCL_IN(sparse, inl, SPARSE)
 438
 439 DCL_SETHAE(dense, DENSE)
 440 DCL_OUT_BWX(dense, outb, char)
 441 DCL_OUT_BWX(dense, outw, short int)
 442 DCL_OUT_BWX(dense, outl, int)
 443 DCL_IN_BWX(dense, inb)
 444 DCL_IN_BWX(dense, inw)
 445 DCL_IN_BWX(dense, inl)
 446
 447 /* define the "swizzle" switch */
 448 static struct ioswtch ioswtch[] = {
 449   {
 450     jensen_sethae,
 451     jensen_outb, jensen_outw, jensen_outl,
 452     jensen_inb, jensen_inw, jensen_inl
 453   },
 454   {
 455     sparse_sethae,
 456     sparse_outb, sparse_outw, sparse_outl,
 457     sparse_inb, sparse_inw, sparse_inl
 458   },
 459   {
 460     dense_sethae,
 461     dense_outb, dense_outw, dense_outl,
 462     dense_inb, dense_inw, dense_inl
 463   }
 464 };
 465
 466 #undef DEBUG_IOPERM
 467
 468 /* Routine to process the /proc/cpuinfo information into the fields
 469    that are required for correctly determining the platform parameters.  */
 470
 471 struct cpuinfo_data
 472 {
 473   char systype[256];            /* system type field */
 474   char sysvari[256];            /* system variation field */
 475   char cpumodel[256];           /* cpu model field */
 476 };
 477
 478 static inline int
 479 process_cpuinfo(struct cpuinfo_data *data)
 480 {
 481   int got_type, got_vari, got_model;
 482   char dummy[256];
 483   FILE * fp;
 484   int n;
 485
 486   data->systype[0] = 0;
 487   data->sysvari[0] = 0;
 488   data->cpumodel[0] = 0;
 489
 490   /* If there's an /etc/alpha_systype link, we're intending to override
 491      whatever's in /proc/cpuinfo.  */
 492   n = __readlink (PATH_ALPHA_SYSTYPE, data->systype, 256 - 1);
 493   if (n > 0)
 494     {
 495       data->systype[n] = '\0';
 496       return 1;
 497     }
 498
 499   fp = fopen (PATH_CPUINFO, "rce");
 500   if (!fp)
 501     return 0;
 502
 503   got_type = got_vari = got_model = 0;
 504
 505   while (1)
 506     {
 507       if (fgets_unlocked (dummy, 256, fp) == NULL)
 508         break;
 509       if (!got_type &&
 510           sscanf (dummy, "system type : %256[^\n]\n", data->systype) == 1)
 511         got_type = 1;
 512       if (!got_vari &&
 513           sscanf (dummy, "system variation : %256[^\n]\n", data->sysvari) == 1)
 514         got_vari = 1;
 515       if (!got_model &&
 516           sscanf (dummy, "cpu model : %256[^\n]\n", data->cpumodel) == 1)
 517         got_model = 1;
 518     }
 519
 520   fclose (fp);
 521
 522 #ifdef DEBUG_IOPERM
 523   fprintf(stderr, "system type: `%s'\n", data->systype);
 524   fprintf(stderr, "system vari: `%s'\n", data->sysvari);
 525   fprintf(stderr, "cpu model: `%s'\n", data->cpumodel);
 526 #endif
 527
 528   return got_type + got_vari + got_model;
 529 }
 530
 531
 532 /*
 533  * Initialize I/O system.
 534  */
 535 static int
 536 init_iosys (void)
 537 {
 538   long addr;
 539   int i, olderrno = errno;
 540   struct cpuinfo_data data;
 541
 542   /* First try the pciconfig_iobase syscall added to 2.2.15 and 2.3.99.  */
 543
 544 #ifdef __NR_pciconfig_iobase
 545   addr = __pciconfig_iobase (IOBASE_DENSE_MEM, 0, 0);
 546   if (addr != -1)
 547     {
 548       ioswizzle_t io_swiz;
 549
 550       if (addr == 0)
 551         {
 552           /* Only Jensen doesn't have dense mem space.  */
 553           io.sparse_bus_memory_base
 554             = io_system[IOSYS_JENSEN].sparse_bus_mem_base;
 555           io.io_base = io_system[IOSYS_JENSEN].bus_io_base;
 556           io_swiz = IOSWIZZLE_JENSEN;
 557         }
 558       else
 559         {
 560           io.bus_memory_base = addr;
 561
 562           addr = __pciconfig_iobase (IOBASE_DENSE_IO, 0, 0);
 563           if (addr != 0)
 564             {
 565               /* The X server uses _bus_base_sparse == 0 to know that
 566                  BWX access are supported to dense mem space.  This is
 567                  true of every system that supports dense io space, so
 568                  never fill in io.sparse_bus_memory_base in this case.  */
 569               io_swiz = IOSWIZZLE_DENSE;
 570               io.io_base = addr;
 571             }
 572           else
 573             {
 574               io.sparse_bus_memory_base
 575                 = __pciconfig_iobase (IOBASE_SPARSE_MEM, 0, 0);
 576               io.io_base = __pciconfig_iobase (IOBASE_SPARSE_IO, 0, 0);
 577               io_swiz = IOSWIZZLE_SPARSE;
 578             }
 579         }
 580
 581       io.swiz = io_swiz;
 582       io.swp = &ioswtch[io_swiz];
 583
 584       return 0;
 585     }
 586 #endif
 587
 588   /* Second, collect the contents of /etc/alpha_systype or /proc/cpuinfo.  */
 589
 590   if (process_cpuinfo(&data) == 0)
 591     {
 592       /* This can happen if the format of /proc/cpuinfo changes.  */
 593       fprintf (stderr,
 594                "ioperm.init_iosys: Unable to determine system type.\n"
 595                "\t(May need " PATH_ALPHA_SYSTYPE " symlink?)\n");
 596       __set_errno (ENODEV);
 597       return -1;
 598     }
 599
 600   /* Translate systype name into i/o system.  */
 601   for (i = 0; i < sizeof (platform) / sizeof (platform[0]); ++i)
 602     {
 603       if (strcmp (platform[i].name, data.systype) == 0)
 604         {
 605           iosys_t io_sys = platform[i].io_sys;
 606
 607           /* Some platforms can have either EV4 or EV5 CPUs.  */
 608           if (io_sys == IOSYS_CPUDEP)
 609             {
 610               /* SABLE or MIKASA or NORITAKE so far.  */
 611               if (strcmp (platform[i].name, "Sable") == 0)
 612                 {
 613                   if (strncmp (data.cpumodel, "EV4", 3) == 0)
 614                     io_sys = IOSYS_T2;
 615                   else if (strncmp (data.cpumodel, "EV5", 3) == 0)
 616                     io_sys = IOSYS_GAMMA;
 617                 }
 618               else
 619                 {
 620                   /* This covers MIKASA/NORITAKE.  */
 621                   if (strncmp (data.cpumodel, "EV4", 3) == 0)
 622                     io_sys = IOSYS_APECS;
 623                   else if (strncmp (data.cpumodel, "EV5", 3) == 0)
 624                     io_sys = IOSYS_CIA;
 625                 }
 626               if (io_sys == IOSYS_CPUDEP)
 627                 {
 628                   /* This can happen if the format of /proc/cpuinfo changes.*/
 629                   fprintf (stderr, "ioperm.init_iosys: Unable to determine"
 630                            " CPU model.\n");
 631                   __set_errno (ENODEV);
 632                   return -1;
 633                 }
 634             }
 635           /* Some platforms can have different core logic chipsets */
 636           if (io_sys == IOSYS_PCIDEP)
 637             {
 638               /* EB164 so far */
 639               if (strcmp (data.systype, "EB164") == 0)
 640                 {
 641                   if (strncmp (data.sysvari, "RX164", 5) == 0)
 642                     io_sys = IOSYS_POLARIS;
 643                   else if (strncmp (data.sysvari, "LX164", 5) == 0
 644                            || strncmp (data.sysvari, "SX164", 5) == 0)
 645                     io_sys = IOSYS_PYXIS;
 646                   else
 647                     io_sys = IOSYS_CIA;
 648                 }
 649               if (io_sys == IOSYS_PCIDEP)
 650                 {
 651                   /* This can happen if the format of /proc/cpuinfo changes.*/
 652                   fprintf (stderr, "ioperm.init_iosys: Unable to determine"
 653                            " core logic chipset.\n");
 654                   __set_errno (ENODEV);
 655                   return -1;
 656                 }
 657             }
 658           io.bus_memory_base = io_system[io_sys].bus_memory_base;
 659           io.sparse_bus_memory_base = io_system[io_sys].sparse_bus_mem_base;
 660           io.io_base = io_system[io_sys].bus_io_base;
 661
 662           if (io_sys == IOSYS_JENSEN)
 663             io.swiz = IOSWIZZLE_JENSEN;
 664           else if (io_sys == IOSYS_TSUNAMI
 665                    || io_sys == IOSYS_POLARIS
 666                    || io_sys == IOSYS_PYXIS)
 667             io.swiz = IOSWIZZLE_DENSE;
 668           else
 669             io.swiz = IOSWIZZLE_SPARSE;
 670           io.swp = &ioswtch[io.swiz];
 671
 672           __set_errno (olderrno);
 673           return 0;
 674         }
 675     }
 676
 677   __set_errno (ENODEV);
 678   fprintf(stderr, "ioperm.init_iosys: Platform not recognized.\n"
 679           "\t(May need " PATH_ALPHA_SYSTYPE " symlink?)\n");
 680   return -1;
 681 }
 682
 683
 684 int
 685 _ioperm (unsigned long int from, unsigned long int num, int turn_on)
 686 {
 687   unsigned long int addr, len, pagesize = __getpagesize();
 688   int prot;
 689
 690   if (!io.swp && init_iosys() < 0)
 691     {
 692 #ifdef DEBUG_IOPERM
 693       fprintf(stderr, "ioperm: init_iosys() failed (%m)\n");
 694 #endif
 695       return -1;
 696     }
 697
 698   /* This test isn't as silly as it may look like; consider overflows! */
 699   if (from >= MAX_PORT || from + num > MAX_PORT)
 700     {
 701       __set_errno (EINVAL);
 702 #ifdef DEBUG_IOPERM
 703       fprintf(stderr, "ioperm: from/num out of range\n");
 704 #endif
 705       return -1;
 706     }
 707
 708 #ifdef DEBUG_IOPERM
 709   fprintf(stderr, "ioperm: turn_on %d io.base %ld\n", turn_on, io.base);
 710 #endif
 711
 712   if (turn_on)
 713     {
 714       if (!io.base)
 715         {
 716           int fd;
 717
 718           io.hae_cache = 0;
 719           if (io.swiz != IOSWIZZLE_DENSE)
 720             {
 721               /* Synchronize with hw.  */
 722               __sethae (0);
 723             }
 724
 725           fd = __open ("/dev/mem", O_RDWR);
 726           if (fd < 0)
 727             {
 728 #ifdef DEBUG_IOPERM
 729               fprintf(stderr, "ioperm: /dev/mem open failed (%m)\n");
 730 #endif
 731               return -1;
 732             }
 733
 734           addr = port_to_cpu_addr (0, io.swiz, 1);
 735           len = port_to_cpu_addr (MAX_PORT, io.swiz, 1) - addr;
 736           io.base =
 737             (unsigned long int) __mmap (0, len, PROT_NONE, MAP_SHARED,
 738                                         fd, io.io_base);
 739           __close (fd);
 740 #ifdef DEBUG_IOPERM
 741           fprintf(stderr, "ioperm: mmap of len 0x%lx  returned 0x%lx\n",
 742                   len, io.base);
 743 #endif
 744           if ((long) io.base == -1)
 745             return -1;
 746         }
 747       prot = PROT_READ | PROT_WRITE;
 748     }
 749   else
 750     {
 751       if (!io.base)
 752         return 0;       /* never was turned on... */
 753
 754       /* turnoff access to relevant pages: */
 755       prot = PROT_NONE;
 756     }
 757   addr = port_to_cpu_addr (from, io.swiz, 1);
 758   addr &= ~(pagesize - 1);
 759   len = port_to_cpu_addr (from + num, io.swiz, 1) - addr;
 760   return __mprotect ((void *) addr, len, prot);
 761 }
 762
 763
 764 int
 765 _iopl (int level)
 766 {
 767   switch (level)
 768     {
 769     case 0:
 770       return 0;
 771
 772     case 1: case 2: case 3:
 773       return _ioperm (0, MAX_PORT, 1);
 774
 775     default:
 776       __set_errno (EINVAL);
 777       return -1;
 778     }
 779 }
 780
 781
 782 void
 783 _sethae (unsigned long int addr)
 784 {
 785   if (!io.swp && init_iosys () < 0)
 786     return;
 787
 788   io.swp->sethae (addr);
 789 }
 790
 791
 792 void
 793 _outb (unsigned char b, unsigned long int port)
 794 {
 795   if (port >= MAX_PORT)
 796     return;
 797
 798   io.swp->outb (b, port);
 799 }
 800
 801
 802 void
 803 _outw (unsigned short b, unsigned long int port)
 804 {
 805   if (port >= MAX_PORT)
 806     return;
 807
 808   io.swp->outw (b, port);
 809 }
 810
 811
 812 void
 813 _outl (unsigned int b, unsigned long int port)
 814 {
 815   if (port >= MAX_PORT)
 816     return;
 817
 818   io.swp->outl (b, port);
 819 }
 820
 821
 822 unsigned int
 823 _inb (unsigned long int port)
 824 {
 825   return io.swp->inb (port);
 826 }
 827
 828
 829 unsigned int
 830 _inw (unsigned long int port)
 831 {
 832   return io.swp->inw (port);
 833 }
 834
 835
 836 unsigned int
 837 _inl (unsigned long int port)
 838 {
 839   return io.swp->inl (port);
 840 }
 841
 842
 843 unsigned long int
 844 _bus_base(void)
 845 {
 846   if (!io.swp && init_iosys () < 0)
 847     return -1;
 848   return io.bus_memory_base;
 849 }
 850
 851 unsigned long int
 852 _bus_base_sparse(void)
 853 {
 854   if (!io.swp && init_iosys () < 0)
 855     return -1;
 856   return io.sparse_bus_memory_base;
 857 }
 858
 859 int
 860 _hae_shift(void)
 861 {
 862   if (!io.swp && init_iosys () < 0)
 863     return -1;
 864   if (io.swiz == IOSWIZZLE_JENSEN)
 865     return 7;
 866   if (io.swiz == IOSWIZZLE_SPARSE)
 867     return 5;
 868   return 0;
 869 }
 870
 871 weak_alias (_sethae, sethae);
 872 weak_alias (_ioperm, ioperm);
 873 weak_alias (_iopl, iopl);
 874 weak_alias (_inb, inb);
 875 weak_alias (_inw, inw);
 876 weak_alias (_inl, inl);
 877 weak_alias (_outb, outb);
 878 weak_alias (_outw, outw);
 879 weak_alias (_outl, outl);
 880 weak_alias (_bus_base, bus_base);
 881 weak_alias (_bus_base_sparse, bus_base_sparse);
 882 weak_alias (_hae_shift, hae_shift);