sysdeps/powerpc/fpu/fenv_libc.h

   1 /* Internal libc stuff for floating point environment routines.
   2    Copyright (C) 1997-2015 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, see
  17    <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef _FENV_LIBC_H
  20 #define _FENV_LIBC_H    1
  21
  22 #include <fenv.h>
  23 #include <ldsodefs.h>
  24 #include <sysdep.h>
  25
  26 extern const fenv_t *__fe_nomask_env_priv (void);
  27
  28 extern const fenv_t *__fe_mask_env (void) attribute_hidden;
  29
  30 /* The sticky bits in the FPSCR indicating exceptions have occurred.  */
  31 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
  32
  33 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
  34    pointer.  */
  35 #define fegetenv_register() \
  36         ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
  37
  38 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
  39 #define fesetenv_register(env) \
  40         do { \
  41           double d = (env); \
  42           if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
  43             asm volatile (".machine push; " \
  44                           ".machine \"power6\"; " \
  45                           "mtfsf 0xff,%0,1,0; " \
  46                           ".machine pop" : : "f" (d)); \
  47           else \
  48             asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
  49         } while(0)
  50
  51 /* This very handy macro:
  52    - Sets the rounding mode to 'round to nearest';
  53    - Sets the processor into IEEE mode; and
  54    - Prevents exceptions from being raised for inexact results.
  55    These things happen to be exactly what you need for typical elementary
  56    functions.  */
  57 #define relax_fenv_state() \
  58         do { \
  59            if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
  60              asm (".machine push; .machine \"power6\"; " \
  61                   "mtfsfi 7,0,1; .machine pop"); \
  62            asm ("mtfsfi 7,0"); \
  63         } while(0)
  64
  65 /* Set/clear a particular FPSCR bit (for instance,
  66    reset_fpscr_bit(FPSCR_VE);
  67    prevents INVALID exceptions from being raised).  */
  68 #define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
  69 #define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
  70
  71 typedef union
  72 {
  73   fenv_t fenv;
  74   unsigned long long l;
  75 } fenv_union_t;
  76
  77
  78 static inline int
  79 __fesetround (int round)
  80 {
  81   if ((unsigned int) round < 2)
  82     {
  83        asm volatile ("mtfsb0 30");
  84        if ((unsigned int) round == 0)
  85          asm volatile ("mtfsb0 31");
  86        else
  87          asm volatile ("mtfsb1 31");
  88     }
  89   else
  90     {
  91        asm volatile ("mtfsb1 30");
  92        if ((unsigned int) round == 2)
  93          asm volatile ("mtfsb0 31");
  94        else
  95          asm volatile ("mtfsb1 31");
  96     }
  97
  98   return 0;
  99 }
 100
 101 /* Definitions of all the FPSCR bit numbers */
 102 enum {
 103   FPSCR_FX = 0,    /* exception summary */
 104   FPSCR_FEX,       /* enabled exception summary */
 105   FPSCR_VX,        /* invalid operation summary */
 106   FPSCR_OX,        /* overflow */
 107   FPSCR_UX,        /* underflow */
 108   FPSCR_ZX,        /* zero divide */
 109   FPSCR_XX,        /* inexact */
 110   FPSCR_VXSNAN,    /* invalid operation for sNaN */
 111   FPSCR_VXISI,     /* invalid operation for Inf-Inf */
 112   FPSCR_VXIDI,     /* invalid operation for Inf/Inf */
 113   FPSCR_VXZDZ,     /* invalid operation for 0/0 */
 114   FPSCR_VXIMZ,     /* invalid operation for Inf*0 */
 115   FPSCR_VXVC,      /* invalid operation for invalid compare */
 116   FPSCR_FR,        /* fraction rounded [fraction was incremented by round] */
 117   FPSCR_FI,        /* fraction inexact */
 118   FPSCR_FPRF_C,    /* result class descriptor */
 119   FPSCR_FPRF_FL,   /* result less than (usually, less than 0) */
 120   FPSCR_FPRF_FG,   /* result greater than */
 121   FPSCR_FPRF_FE,   /* result equal to */
 122   FPSCR_FPRF_FU,   /* result unordered */
 123   FPSCR_20,        /* reserved */
 124   FPSCR_VXSOFT,    /* invalid operation set by software */
 125   FPSCR_VXSQRT,    /* invalid operation for square root */
 126   FPSCR_VXCVI,     /* invalid operation for invalid integer convert */
 127   FPSCR_VE,        /* invalid operation exception enable */
 128   FPSCR_OE,        /* overflow exception enable */
 129   FPSCR_UE,        /* underflow exception enable */
 130   FPSCR_ZE,        /* zero divide exception enable */
 131   FPSCR_XE,        /* inexact exception enable */
 132 #ifdef _ARCH_PWR6
 133   FPSCR_29,        /* Reserved in ISA 2.05  */
 134 #else
 135   FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
 136 #endif /* _ARCH_PWR6 */
 137   /* the remaining two least-significant bits keep the rounding mode */
 138 };
 139
 140 static inline int
 141 fenv_reg_to_exceptions (unsigned long long l)
 142 {
 143   int result = 0;
 144   if (l & (1 << (31 - FPSCR_XE)))
 145     result |= FE_INEXACT;
 146   if (l & (1 << (31 - FPSCR_ZE)))
 147     result |= FE_DIVBYZERO;
 148   if (l & (1 << (31 - FPSCR_UE)))
 149     result |= FE_UNDERFLOW;
 150   if (l & (1 << (31 - FPSCR_OE)))
 151     result |= FE_OVERFLOW;
 152   if (l & (1 << (31 - FPSCR_VE)))
 153     result |= FE_INVALID;
 154   return result;
 155 }
 156
 157 #ifdef _ARCH_PWR6
 158   /* Not supported in ISA 2.05.  Provided for source compat only.  */
 159 # define FPSCR_NI 29
 160 #endif /* _ARCH_PWR6 */
 161
 162 /* This operation (i) sets the appropriate FPSCR bits for its
 163    parameter, (ii) converts sNaN to the corresponding qNaN, and (iii)
 164    otherwise passes its parameter through unchanged (in particular, -0
 165    and +0 stay as they were).  The `obvious' way to do this is optimised
 166    out by gcc.  */
 167 #define f_wash(x) \
 168    ({ double d; asm volatile ("fmul %0,%1,%2" \
 169                               : "=f"(d) \
 170                               : "f" (x), "f"((float)1.0)); d; })
 171 #define f_washf(x) \
 172    ({ float f; asm volatile ("fmuls %0,%1,%2" \
 173                              : "=f"(f) \
 174                              : "f" (x), "f"((float)1.0)); f; })
 175
 176 #endif /* fenv_libc.h */