sysdeps/unix/sysv/linux/x86_64/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static const struct intel_02_cache_info
  30 {
  31   unsigned int idx;
  32   int name;
  33   long int size;
  34   long int assoc;
  35   long int linesize;
  36 } intel_02_known[] =
  37   {
  38     { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
  39     { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
  40     { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
  41     { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
  42     { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
  43     { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
  44     { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
  45     { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
  46     { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
  47     { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
  48     { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
  49     { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
  50     { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
  51     { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
  52     { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
  53     { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
  54     { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
  55     { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
  56     { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
  57     { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  58     { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
  59     { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
  60     { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
  61     { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  62     { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
  63     { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
  64     { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
  65     { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
  66     { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
  67     { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
  68     { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  69   };
  70 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
  71
  72
  73 static int
  74 intel_02_known_compare (const void *p1, const void *p2)
  75 {
  76   const struct intel_02_cache_info *i1;
  77   const struct intel_02_cache_info *i2;
  78
  79   i1 = (const struct intel_02_cache_info *) p1;
  80   i2 = (const struct intel_02_cache_info *) p2;
  81
  82   if (i1->idx == i2->idx)
  83     return 0;
  84
  85   return i1->idx < i2->idx ? -1 : 1;
  86 }
  87
  88
  89 static long int
  90 intel_check_word (int name, unsigned int value, bool *has_level_2,
  91                   bool *no_level_2_or_3)
  92 {
  93   if ((value & 0x80000000) != 0)
  94     /* The register value is reserved.  */
  95     return 0;
  96
  97   /* Fold the name.  The _SC_ constants are always in the order SIZE,
  98      ASSOC, LINESIZE.  */
  99   int folded_name = (_SC_LEVEL1_ICACHE_SIZE
 100                      + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
 101
 102   while (value != 0)
 103     {
 104       unsigned int byte = value & 0xff;
 105
 106       if (byte == 0x40)
 107         {
 108           *no_level_2_or_3 = true;
 109
 110           if (folded_name == _SC_LEVEL3_CACHE_SIZE)
 111             /* No need to look further.  */
 112             break;
 113         }
 114       else
 115         {
 116           struct intel_02_cache_info *found;
 117           struct intel_02_cache_info search;
 118
 119           search.idx = byte;
 120           found = bsearch (&search, intel_02_known, nintel_02_known,
 121                            sizeof (intel_02_known[0]), intel_02_known_compare);
 122           if (found != NULL)
 123             {
 124               if (found->name == folded_name)
 125                 {
 126                   unsigned int offset = name - folded_name;
 127
 128                   if (offset == 0)
 129                     /* Cache size.  */
 130                     return found->size;
 131                   if (offset == 1)
 132                     return found->assoc;
 133
 134                   assert (offset == 2);
 135                   return found->linesize;
 136                 }
 137
 138               if (found->name == _SC_LEVEL2_CACHE_SIZE)
 139                 *has_level_2 = true;
 140             }
 141         }
 142
 143       /* Next byte for the next round.  */
 144       value >>= 8;
 145     }
 146
 147   /* Nothing found.  */
 148   return 0;
 149 }
 150
 151
 152 static long int
 153 handle_intel (int name, unsigned int maxidx)
 154 {
 155   assert (maxidx >= 2);
 156
 157   /* OK, we can use the CPUID instruction to get all info about the
 158      caches.  */
 159   unsigned int cnt = 0;
 160   unsigned int max = 1;
 161   long int result = 0;
 162   bool no_level_2_or_3 = false;
 163   bool has_level_2 = false;
 164   while (cnt++ < max)
 165     {
 166       unsigned int eax;
 167       unsigned int ebx;
 168       unsigned int ecx;
 169       unsigned int edx;
 170       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 171                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 172                     : "0" (2));
 173
 174       /* The low byte of EAX in the first round contain the number of
 175          rounds we have to make.  At least one, the one we are already
 176          doing.  */
 177       if (cnt == 1)
 178         {
 179           max = eax & 0xff;
 180           eax &= 0xffffff00;
 181         }
 182
 183       /* Process the individual registers' value.  */
 184       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 185       if (result != 0)
 186         return result;
 187
 188       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 189       if (result != 0)
 190         return result;
 191
 192       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 193       if (result != 0)
 194         return result;
 195
 196       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 197       if (result != 0)
 198         return result;
 199     }
 200
 201   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 202       && no_level_2_or_3)
 203     return -1;
 204
 205   return 0;
 206 }
 207
 208
 209 static long int
 210 handle_amd (int name)
 211 {
 212   unsigned int eax;
 213   unsigned int ebx;
 214   unsigned int ecx;
 215   unsigned int edx;
 216   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 217                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 218                 : "0" (0x80000000));
 219
 220   if (name >= _SC_LEVEL3_CACHE_SIZE)
 221     return 0;
 222
 223   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 224   if (eax < fn)
 225     return 0;
 226
 227   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 228                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 229                 : "0" (fn));
 230
 231   if (name < _SC_LEVEL1_DCACHE_SIZE)
 232     {
 233       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 234       ecx = edx;
 235     }
 236
 237   switch (name)
 238     {
 239     case _SC_LEVEL1_DCACHE_SIZE:
 240       return (ecx >> 14) & 0x3fc00;
 241     case _SC_LEVEL1_DCACHE_ASSOC:
 242       ecx >>= 16;
 243       if ((ecx & 0xff) == 0xff)
 244         /* Fully associative.  */
 245         return (ecx << 2) & 0x3fc00;
 246       return ecx & 0xff;
 247     case _SC_LEVEL1_DCACHE_LINESIZE:
 248       return ecx & 0xff;
 249     case _SC_LEVEL2_CACHE_SIZE:
 250       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 251     case _SC_LEVEL2_CACHE_ASSOC:
 252       ecx >>= 12;
 253       switch (ecx & 0xf)
 254         {
 255         case 0:
 256         case 1:
 257         case 2:
 258         case 4:
 259           return ecx & 0xf;
 260         case 6:
 261           return 8;
 262         case 8:
 263           return 16;
 264         case 0xf:
 265           return (ecx << 6) & 0x3fffc00;
 266         default:
 267           return 0;
 268         }
 269     case _SC_LEVEL2_CACHE_LINESIZE:
 270       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 271     default:
 272       assert (! "cannot happen");
 273     }
 274   return -1;
 275 }
 276
 277
 278 /* Get the value of the system variable NAME.  */
 279 long int
 280 __sysconf (int name)
 281 {
 282   if (name == _SC_CPUTIME || name == _SC_THREAD_CPUTIME)
 283     {
 284       /* XXX Test whether TSC is usable.  */
 285       return 200112L;
 286     }
 287
 288   /* We only handle the cache information here (for now).  */
 289   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 290     return linux_sysconf (name);
 291
 292   /* Find out what brand of processor.  */
 293   unsigned int eax;
 294   unsigned int ebx;
 295   unsigned int ecx;
 296   unsigned int edx;
 297   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 298                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 299                 : "0" (0));
 300
 301   /* This spells out "GenuineIntel".  */
 302   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 303     return handle_intel (name, eax);
 304
 305   /* This spells out "AuthenticAMD".  */
 306   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 307     return handle_amd (name);
 308
 309   // XXX Fill in more vendors.
 310
 311   /* CPU not known, we have no information.  */
 312   return 0;
 313 }
 314
 315 /* Now the generic Linux version.  */
 316 #undef __sysconf
 317 #define __sysconf static linux_sysconf
 318 #include "../sysconf.c"