sysdeps/unix/sysv/linux/i386/sysconf.c

   1 /* Get file-specific information about a file.  Linux version.
   2    Copyright (C) 2003, 2004 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #include <assert.h>
  21 #include <stdbool.h>
  22 #include <stdlib.h>
  23 #include <unistd.h>
  24 #include <hp-timing.h>
  25
  26 static long int linux_sysconf (int name);
  27
  28
  29 static long int
  30 handle_i486 (int name)
  31 {
  32   /* The processor only has a unified level 1 cache of 8k.  */
  33   switch (name)
  34     {
  35     case _SC_LEVEL1_ICACHE_SIZE:
  36     case _SC_LEVEL1_DCACHE_SIZE:
  37       return 8 * 1024;
  38
  39     case _SC_LEVEL1_ICACHE_ASSOC:
  40     case _SC_LEVEL1_DCACHE_ASSOC:
  41       // XXX Anybody know this?
  42       return 0;
  43
  44     case _SC_LEVEL1_ICACHE_LINESIZE:
  45     case _SC_LEVEL1_DCACHE_LINESIZE:
  46       // XXX Anybody know for sure?
  47       return 16;
  48
  49     case _SC_LEVEL2_CACHE_SIZE:
  50     case _SC_LEVEL2_CACHE_ASSOC:
  51     case _SC_LEVEL2_CACHE_LINESIZE:
  52     case _SC_LEVEL3_CACHE_SIZE:
  53     case _SC_LEVEL3_CACHE_ASSOC:
  54     case _SC_LEVEL3_CACHE_LINESIZE:
  55     case _SC_LEVEL4_CACHE_SIZE:
  56     case _SC_LEVEL4_CACHE_ASSOC:
  57       /* Not available.  */
  58       break;
  59
  60     default:
  61       assert (! "cannot happen");
  62     }
  63
  64   return -1;
  65 }
  66
  67
  68 static const struct intel_02_cache_info
  69 {
  70   unsigned int idx;
  71   int name;
  72   long int size;
  73   long int assoc;
  74   long int linesize;
  75 } intel_02_known[] =
  76   {
  77     { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
  78     { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
  79     { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
  80     { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
  81     { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
  82     { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
  83     { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
  84     { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
  85     { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
  86     { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
  87     { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
  88     { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
  89     { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
  90     { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
  91     { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
  92     { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
  93     { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
  94     { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
  95     { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
  96     { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
  97     { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
  98     { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
  99     { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
 100     { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 101     { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
 102     { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
 103     { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
 104     { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
 105     { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
 106     { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
 107     { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
 108   };
 109 #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
 110
 111
 112 static int
 113 intel_02_known_compare (const void *p1, const void *p2)
 114 {
 115   const struct intel_02_cache_info *i1;
 116   const struct intel_02_cache_info *i2;
 117
 118   i1 = (const struct intel_02_cache_info *) p1;
 119   i2 = (const struct intel_02_cache_info *) p2;
 120
 121   if (i1->idx == i2->idx)
 122     return 0;
 123
 124   return i1->idx < i2->idx ? -1 : 1;
 125 }
 126
 127
 128 static long int
 129 intel_check_word (int name, unsigned int value, bool *has_level_2,
 130                   bool *no_level_2_or_3)
 131 {
 132   if ((value & 0x80000000) != 0)
 133     /* The register value is reserved.  */
 134     return 0;
 135
 136   /* Fold the name.  The _SC_ constants are always in the order SIZE,
 137      ASSOC, LINESIZE.  */
 138   int folded_name = (_SC_LEVEL1_ICACHE_SIZE
 139                      + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
 140
 141   while (value != 0)
 142     {
 143       unsigned int byte = value & 0xff;
 144
 145       if (byte == 0x40)
 146         {
 147           *no_level_2_or_3 = true;
 148
 149           if (folded_name == _SC_LEVEL3_CACHE_SIZE)
 150             /* No need to look further.  */
 151             break;
 152         }
 153       else
 154         {
 155           struct intel_02_cache_info *found;
 156           struct intel_02_cache_info search;
 157
 158           search.idx = byte;
 159           found = bsearch (&search, intel_02_known, nintel_02_known,
 160                            sizeof (intel_02_known[0]), intel_02_known_compare);
 161           if (found != NULL)
 162             {
 163               if (found->name == folded_name)
 164                 {
 165                   unsigned int offset = name - folded_name;
 166
 167                   if (offset == 0)
 168                     /* Cache size.  */
 169                     return found->size;
 170                   if (offset == 1)
 171                     return found->assoc;
 172
 173                   assert (offset == 2);
 174                   return found->linesize;
 175                 }
 176
 177               if (found->name == _SC_LEVEL2_CACHE_SIZE)
 178                 *has_level_2 = true;
 179             }
 180         }
 181
 182       /* Next byte for the next round.  */
 183       value >>= 8;
 184     }
 185
 186   /* Nothing found.  */
 187   return 0;
 188 }
 189
 190
 191 static long int
 192 handle_intel (int name, unsigned int maxidx)
 193 {
 194   if (maxidx < 2)
 195     {
 196       // XXX Do such processors exist?  When we know we can fill in some
 197       // values.
 198       return 0;
 199     }
 200
 201   /* OK, we can use the CPUID instruction to get all info about the
 202      caches.  */
 203   unsigned int cnt = 0;
 204   unsigned int max = 1;
 205   long int result = 0;
 206   bool no_level_2_or_3 = false;
 207   bool has_level_2 = false;
 208   while (cnt++ < max)
 209     {
 210       unsigned int eax;
 211       unsigned int ebx;
 212       unsigned int ecx;
 213       unsigned int edx;
 214       asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 215                     : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 216                     : "0" (2));
 217
 218       /* The low byte of EAX in the first round contain the number of
 219          rounds we have to make.  At least one, the one we are already
 220          doing.  */
 221       if (cnt == 1)
 222         {
 223           max = eax & 0xff;
 224           eax &= 0xffffff00;
 225         }
 226
 227       /* Process the individual registers' value.  */
 228       result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
 229       if (result != 0)
 230         return result;
 231
 232       result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
 233       if (result != 0)
 234         return result;
 235
 236       result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
 237       if (result != 0)
 238         return result;
 239
 240       result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
 241       if (result != 0)
 242         return result;
 243     }
 244
 245   if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
 246       && no_level_2_or_3)
 247     return -1;
 248
 249   return 0;
 250 }
 251
 252
 253 static long int
 254 handle_amd (int name)
 255 {
 256   unsigned int eax;
 257   unsigned int ebx;
 258   unsigned int ecx;
 259   unsigned int edx;
 260   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 261                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 262                 : "0" (0x80000000));
 263
 264   if (name >= _SC_LEVEL3_CACHE_SIZE)
 265     return 0;
 266
 267   unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
 268   if (eax < fn)
 269     return 0;
 270
 271   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 272                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 273                 : "0" (fn));
 274
 275   if (name < _SC_LEVEL1_DCACHE_SIZE)
 276     {
 277       name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
 278       ecx = edx;
 279     }
 280
 281   switch (name)
 282     {
 283     case _SC_LEVEL1_DCACHE_SIZE:
 284       return (ecx >> 14) & 0x3fc00;
 285     case _SC_LEVEL1_DCACHE_ASSOC:
 286       ecx >>= 16;
 287       if ((ecx & 0xff) == 0xff)
 288         /* Fully associative.  */
 289         return (ecx << 2) & 0x3fc00;
 290       return ecx & 0xff;
 291     case _SC_LEVEL1_DCACHE_LINESIZE:
 292       return ecx & 0xff;
 293     case _SC_LEVEL2_CACHE_SIZE:
 294       return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
 295     case _SC_LEVEL2_CACHE_ASSOC:
 296       ecx >>= 12;
 297       switch (ecx & 0xf)
 298         {
 299         case 0:
 300         case 1:
 301         case 2:
 302         case 4:
 303           return ecx & 0xf;
 304         case 6:
 305           return 8;
 306         case 8:
 307           return 16;
 308         case 0xf:
 309           return (ecx << 6) & 0x3fffc00;
 310         default:
 311           return 0;
 312         }
 313     case _SC_LEVEL2_CACHE_LINESIZE:
 314       return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
 315     default:
 316       assert (! "cannot happen");
 317     }
 318   return -1;
 319 }
 320
 321
 322 static int
 323 i386_i486_test (void)
 324 {
 325   int eflags;
 326   int ac;
 327   asm volatile ("pushfl;\n\t"
 328                 "popl %0;\n\t"
 329                 "movl $0x240000, %1;\n\t"
 330                 "xorl %0, %1;\n\t"
 331                 "pushl %1;\n\t"
 332                 "popfl;\n\t"
 333                 "pushfl;\n\t"
 334                 "popl %1;\n\t"
 335                 "xorl %0, %1;\n\t"
 336                 "pushl %0;\n\t"
 337                 "popfl"
 338                 : "=r" (eflags), "=r" (ac));
 339
 340   return ac;
 341 }
 342
 343
 344 /* Get the value of the system variable NAME.  */
 345 long int
 346 __sysconf (int name)
 347 {
 348   if (name == _SC_CPUTIME || name == _SC_THREAD_CPUTIME)
 349     {
 350 #if HP_TIMING_AVAIL
 351       // XXX We can add  here test for machines which cannot support a
 352       // XXX usable TSC.
 353       return 200112L;
 354 #else
 355       return -1;
 356 #endif
 357     }
 358
 359   /* All the remainder, except the cache information, is handled in
 360      the generic code.  */
 361   if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
 362     return linux_sysconf (name);
 363
 364   /* Recognize i386 and compatible.  These don't have any cache on
 365      board.  */
 366   int ac = i386_i486_test ();
 367
 368   if (ac == 0)
 369     /* This is an i386.  */
 370     // XXX Is this true for all brands?
 371     return -1;
 372
 373   /* Detect i486, the last Intel processor without CPUID.  */
 374   if ((ac & (1 << 21)) == 0)
 375     {
 376       /* No CPUID.  */
 377       // XXX Fill in info about other brands.  For now only Intel.
 378       return handle_i486 (name);
 379     }
 380
 381   /* Find out what brand of processor.  */
 382   unsigned int eax;
 383   unsigned int ebx;
 384   unsigned int ecx;
 385   unsigned int edx;
 386   asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
 387                 : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
 388                 : "0" (0));
 389
 390   /* This spells out "GenuineIntel".  */
 391   if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
 392     return handle_intel (name, eax);
 393
 394   /* This spells out "AuthenticAMD".  */
 395   if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
 396     return handle_amd (name);
 397
 398   // XXX Fill in more vendors.
 399
 400   /* CPU not known, we have no information.  */
 401   return 0;
 402 }
 403
 404 /* Now the generic Linux version.  */
 405 #undef __sysconf
 406 #define __sysconf static linux_sysconf
 407 #include "../sysconf.c"