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Sun Dec 17 15:56:35 1995 Miles Bader <miles@gnu.ai.mit.edu>
[glibc.git] / stdlib / longlong.h
blobe52bf32dbac4a05cceb705bbd68f5c3a6eedf7c6
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2
3 Copyright (C) 1991, 1992, 1993, 1994 Free Software Foundation, Inc.
4
5 This file is free software; you can redistribute it and/or modify
6 it under the terms of the GNU Library General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or (at your
8 option) any later version.
9
10 This file is distributed in the hope that it will be useful, but
11 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public
13 License for more details.
14
15 You should have received a copy of the GNU Library General Public License
16 along with this file; see the file COPYING.LIB. If not, write to
17 the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
18
19 /* You have to define the following before including this file:
20
21 UWtype -- An unsigned type, default type for operations (typically a "word")
22 UHWtype -- An unsigned type, at least half the size of UWtype.
23 UDWtype -- An unsigned type, at least twice as large a UWtype
24 W_TYPE_SIZE -- size in bits of UWtype
25
26 SItype, USItype -- Signed and unsigned 32 bit types.
27 DItype, UDItype -- Signed and unsigned 64 bit types.
28
29 On a 32 bit machine UWtype should typically be USItype;
30 on a 64 bit machine, UWtype should typically be UDItype.
31 */
32
33 #define __BITS4 (W_TYPE_SIZE / 4)
34 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
35 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
36 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
37
38 /* Define auxiliary asm macros.
39
40 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
41 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
42 word product in HIGH_PROD and LOW_PROD.
43
44 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
45 UDWtype product. This is just a variant of umul_ppmm.
46
47 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
48 denominator) divides a UDWtype, composed by the UWtype integers
49 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
50 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
51 than DENOMINATOR for correct operation. If, in addition, the most
52 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
53 UDIV_NEEDS_NORMALIZATION is defined to 1.
54
55 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
56 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
57 is rounded towards 0.
58
59 5) count_leading_zeros(count, x) counts the number of zero-bits from the
60 msb to the first non-zero bit in the UWtype X. This is the number of
61 steps X needs to be shifted left to set the msb. Undefined for X == 0,
62 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
63
64 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
65 from the least significant end.
66
67 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
68 high_addend_2, low_addend_2) adds two UWtype integers, composed by
69 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
70 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
71 (i.e. carry out) is not stored anywhere, and is lost.
72
73 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
74 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
75 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
76 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
77 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
78 and is lost.
79
80 If any of these macros are left undefined for a particular CPU,
81 C macros are used. */
82
83 /* The CPUs come in alphabetical order below.
84
85 Please add support for more CPUs here, or improve the current support
86 for the CPUs below! */
87
88 #if defined (__GNUC__) && !defined (NO_ASM)
89
90 /* We sometimes need to clobber "cc" with gcc2, but that would not be
91 understood by gcc1. Use cpp to avoid major code duplication. */
92 #if __GNUC__ < 2
93 #define __CLOBBER_CC
94 #define __AND_CLOBBER_CC
95 #else /* __GNUC__ >= 2 */
96 #define __CLOBBER_CC : "cc"
97 #define __AND_CLOBBER_CC , "cc"
98 #endif /* __GNUC__ < 2 */
99
100 #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
101 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
102 __asm__ ("add %1,%4,%5
103 addc %0,%2,%3" \
104 : "=r" ((USItype)(sh)), \
105 "=&r" ((USItype)(sl)) \
106 : "%r" ((USItype)(ah)), \
107 "rI" ((USItype)(bh)), \
108 "%r" ((USItype)(al)), \
109 "rI" ((USItype)(bl)))
110 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
111 __asm__ ("sub %1,%4,%5
112 subc %0,%2,%3" \
113 : "=r" ((USItype)(sh)), \
114 "=&r" ((USItype)(sl)) \
115 : "r" ((USItype)(ah)), \
116 "rI" ((USItype)(bh)), \
117 "r" ((USItype)(al)), \
118 "rI" ((USItype)(bl)))
119 #define umul_ppmm(xh, xl, m0, m1) \
120 do { \
121 USItype __m0 = (m0), __m1 = (m1); \
122 __asm__ ("multiplu %0,%1,%2" \
123 : "=r" ((USItype)(xl)) \
124 : "r" (__m0), \
125 "r" (__m1)); \
126 __asm__ ("multmu %0,%1,%2" \
127 : "=r" ((USItype)(xh)) \
128 : "r" (__m0), \
129 "r" (__m1)); \
130 } while (0)
131 #define udiv_qrnnd(q, r, n1, n0, d) \
132 __asm__ ("dividu %0,%3,%4" \
133 : "=r" ((USItype)(q)), \
134 "=q" ((USItype)(r)) \
135 : "1" ((USItype)(n1)), \
136 "r" ((USItype)(n0)), \
137 "r" ((USItype)(d)))
138 #define count_leading_zeros(count, x) \
139 __asm__ ("clz %0,%1" \
140 : "=r" ((USItype)(count)) \
141 : "r" ((USItype)(x)))
142 #define COUNT_LEADING_ZEROS_0 32
143 #endif /* __a29k__ */
144
145 #if defined (__alpha__) && W_TYPE_SIZE == 64
146 #define umul_ppmm(ph, pl, m0, m1) \
147 do { \
148 UDItype __m0 = (m0), __m1 = (m1); \
149 __asm__ ("umulh %r1,%2,%0" \
150 : "=r" ((UDItype) ph) \
151 : "%rJ" (__m0), \
152 "rI" (__m1)); \
153 (pl) = __m0 * __m1; \
154 } while (0)
155 #define UMUL_TIME 46
156 #ifndef LONGLONG_STANDALONE
157 #define udiv_qrnnd(q, r, n1, n0, d) \
158 do { UDItype __r; \
159 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
160 (r) = __r; \
161 } while (0)
162 extern UDItype __udiv_qrnnd ();
163 #define UDIV_TIME 220
164 #endif /* LONGLONG_STANDALONE */
165 #endif /* __alpha__ */
166
167 #if defined (__arm__) && W_TYPE_SIZE == 32
168 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
169 __asm__ ("adds %1, %4, %5
170 adc %0, %2, %3" \
171 : "=r" ((USItype)(sh)), \
172 "=&r" ((USItype)(sl)) \
173 : "%r" ((USItype)(ah)), \
174 "rI" ((USItype)(bh)), \
175 "%r" ((USItype)(al)), \
176 "rI" ((USItype)(bl)))
177 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
178 __asm__ ("subs %1, %4, %5
179 sbc %0, %2, %3" \
180 : "=r" ((USItype)(sh)), \
181 "=&r" ((USItype)(sl)) \
182 : "r" ((USItype)(ah)), \
183 "rI" ((USItype)(bh)), \
184 "r" ((USItype)(al)), \
185 "rI" ((USItype)(bl)))
186 #define umul_ppmm(xh, xl, a, b) \
187 __asm__ ("%@ Inlined umul_ppmm
188 mov %|r0, %2, lsr #16
189 mov %|r2, %3, lsr #16
190 bic %|r1, %2, %|r0, lsl #16
191 bic %|r2, %3, %|r2, lsl #16
192 mul %1, %|r1, %|r2
193 mul %|r2, %|r0, %|r2
194 mul %|r1, %0, %|r1
195 mul %0, %|r0, %0
196 adds %|r1, %|r2, %|r1
197 addcs %0, %0, #65536
198 adds %1, %1, %|r1, lsl #16
199 adc %0, %0, %|r1, lsr #16" \
200 : "=&r" ((USItype)(xh)), \
201 "=r" ((USItype)(xl)) \
202 : "r" ((USItype)(a)), \
203 "r" ((USItype)(b)) \
204 : "r0", "r1", "r2")
205 #define UMUL_TIME 20
206 #define UDIV_TIME 100
207 #endif /* __arm__ */
208
209 #if defined (__clipper__) && W_TYPE_SIZE == 32
210 #define umul_ppmm(w1, w0, u, v) \
211 ({union {UDItype __ll; \
212 struct {USItype __l, __h;} __i; \
213 } __xx; \
214 __asm__ ("mulwux %2,%0" \
215 : "=r" (__xx.__ll) \
216 : "%0" ((USItype)(u)), \
217 "r" ((USItype)(v))); \
218 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
219 #define smul_ppmm(w1, w0, u, v) \
220 ({union {DItype __ll; \
221 struct {SItype __l, __h;} __i; \
222 } __xx; \
223 __asm__ ("mulwx %2,%0" \
224 : "=r" (__xx.__ll) \
225 : "%0" ((SItype)(u)), \
226 "r" ((SItype)(v))); \
227 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
228 #define __umulsidi3(u, v) \
229 ({UDItype __w; \
230 __asm__ ("mulwux %2,%0" \
231 : "=r" (__w) \
232 : "%0" ((USItype)(u)), \
233 "r" ((USItype)(v))); \
234 __w; })
235 #endif /* __clipper__ */
236
237 #if defined (__gmicro__) && W_TYPE_SIZE == 32
238 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
239 __asm__ ("add.w %5,%1
240 addx %3,%0" \
241 : "=g" ((USItype)(sh)), \
242 "=&g" ((USItype)(sl)) \
243 : "%0" ((USItype)(ah)), \
244 "g" ((USItype)(bh)), \
245 "%1" ((USItype)(al)), \
246 "g" ((USItype)(bl)))
247 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
248 __asm__ ("sub.w %5,%1
249 subx %3,%0" \
250 : "=g" ((USItype)(sh)), \
251 "=&g" ((USItype)(sl)) \
252 : "0" ((USItype)(ah)), \
253 "g" ((USItype)(bh)), \
254 "1" ((USItype)(al)), \
255 "g" ((USItype)(bl)))
256 #define umul_ppmm(ph, pl, m0, m1) \
257 __asm__ ("mulx %3,%0,%1" \
258 : "=g" ((USItype)(ph)), \
259 "=r" ((USItype)(pl)) \
260 : "%0" ((USItype)(m0)), \
261 "g" ((USItype)(m1)))
262 #define udiv_qrnnd(q, r, nh, nl, d) \
263 __asm__ ("divx %4,%0,%1" \
264 : "=g" ((USItype)(q)), \
265 "=r" ((USItype)(r)) \
266 : "1" ((USItype)(nh)), \
267 "0" ((USItype)(nl)), \
268 "g" ((USItype)(d)))
269 #define count_leading_zeros(count, x) \
270 __asm__ ("bsch/1 %1,%0" \
271 : "=g" (count) \
272 : "g" ((USItype)(x)), \
273 "0" ((USItype)0))
274 #endif
275
276 #if defined (__hppa) && W_TYPE_SIZE == 32
277 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
278 __asm__ ("add %4,%5,%1
279 addc %2,%3,%0" \
280 : "=r" ((USItype)(sh)), \
281 "=&r" ((USItype)(sl)) \
282 : "%rM" ((USItype)(ah)), \
283 "rM" ((USItype)(bh)), \
284 "%rM" ((USItype)(al)), \
285 "rM" ((USItype)(bl)))
286 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
287 __asm__ ("sub %4,%5,%1
288 subb %2,%3,%0" \
289 : "=r" ((USItype)(sh)), \
290 "=&r" ((USItype)(sl)) \
291 : "rM" ((USItype)(ah)), \
292 "rM" ((USItype)(bh)), \
293 "rM" ((USItype)(al)), \
294 "rM" ((USItype)(bl)))
295 #if defined (_PA_RISC1_1)
296 #define umul_ppmm(wh, wl, u, v) \
297 do { \
298 union {UDItype __ll; \
299 struct {USItype __h, __l;} __i; \
300 } __xx; \
301 __asm__ ("xmpyu %1,%2,%0" \
302 : "=*f" (__xx.__ll) \
303 : "*f" ((USItype)(u)), \
304 "*f" ((USItype)(v))); \
305 (wh) = __xx.__i.__h; \
306 (wl) = __xx.__i.__l; \
307 } while (0)
308 #define UMUL_TIME 8
309 #define UDIV_TIME 60
310 #else
311 #define UMUL_TIME 40
312 #define UDIV_TIME 80
313 #endif
314 #ifndef LONGLONG_STANDALONE
315 #define udiv_qrnnd(q, r, n1, n0, d) \
316 do { USItype __r; \
317 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
318 (r) = __r; \
319 } while (0)
320 extern USItype __udiv_qrnnd ();
321 #endif /* LONGLONG_STANDALONE */
322 #define count_leading_zeros(count, x) \
323 do { \
324 USItype __tmp; \
325 __asm__ ( \
326 "ldi 1,%0
327 extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
328 extru,tr %1,15,16,%1 ; No. Shift down, skip add.
329 ldo 16(%0),%0 ; Yes. Perform add.
330 extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
331 extru,tr %1,23,8,%1 ; No. Shift down, skip add.
332 ldo 8(%0),%0 ; Yes. Perform add.
333 extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
334 extru,tr %1,27,4,%1 ; No. Shift down, skip add.
335 ldo 4(%0),%0 ; Yes. Perform add.
336 extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
337 extru,tr %1,29,2,%1 ; No. Shift down, skip add.
338 ldo 2(%0),%0 ; Yes. Perform add.
339 extru %1,30,1,%1 ; Extract bit 1.
340 sub %0,%1,%0 ; Subtract it.
341 " : "=r" (count), "=r" (__tmp) : "1" (x)); \
342 } while (0)
343 #endif /* hppa */
344
345 #if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32
346 #define umul_ppmm(xh, xl, m0, m1) \
347 do { \
348 union {UDItype __ll; \
349 struct {USItype __h, __l;} __i; \
350 } __xx; \
351 USItype __m0 = (m0), __m1 = (m1); \
352 __asm__ ("mr %0,%3" \
353 : "=r" (__xx.__i.__h), \
354 "=r" (__xx.__i.__l) \
355 : "%1" (__m0), \
356 "r" (__m1)); \
357 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
358 (xh) += ((((SItype) __m0 >> 31) & __m1) \
359 + (((SItype) __m1 >> 31) & __m0)); \
360 } while (0)
361 #define smul_ppmm(xh, xl, m0, m1) \
362 do { \
363 union {DItype __ll; \
364 struct {USItype __h, __l;} __i; \
365 } __xx; \
366 __asm__ ("mr %0,%3" \
367 : "=r" (__xx.__i.__h), \
368 "=r" (__xx.__i.__l) \
369 : "%1" (m0), \
370 "r" (m1)); \
371 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
372 } while (0)
373 #define sdiv_qrnnd(q, r, n1, n0, d) \
374 do { \
375 union {DItype __ll; \
376 struct {USItype __h, __l;} __i; \
377 } __xx; \
378 __xx.__i.__h = n1; __xx.__i.__l = n0; \
379 __asm__ ("dr %0,%2" \
380 : "=r" (__xx.__ll) \
381 : "0" (__xx.__ll), "r" (d)); \
382 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
383 } while (0)
384 #endif
385
386 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
387 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
388 __asm__ ("addl %5,%1
389 adcl %3,%0" \
390 : "=r" ((USItype)(sh)), \
391 "=&r" ((USItype)(sl)) \
392 : "%0" ((USItype)(ah)), \
393 "g" ((USItype)(bh)), \
394 "%1" ((USItype)(al)), \
395 "g" ((USItype)(bl)))
396 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
397 __asm__ ("subl %5,%1
398 sbbl %3,%0" \
399 : "=r" ((USItype)(sh)), \
400 "=&r" ((USItype)(sl)) \
401 : "0" ((USItype)(ah)), \
402 "g" ((USItype)(bh)), \
403 "1" ((USItype)(al)), \
404 "g" ((USItype)(bl)))
405 #define umul_ppmm(w1, w0, u, v) \
406 __asm__ ("mull %3" \
407 : "=a" ((USItype)(w0)), \
408 "=d" ((USItype)(w1)) \
409 : "%0" ((USItype)(u)), \
410 "rm" ((USItype)(v)))
411 #define udiv_qrnnd(q, r, n1, n0, d) \
412 __asm__ ("divl %4" \
413 : "=a" ((USItype)(q)), \
414 "=d" ((USItype)(r)) \
415 : "0" ((USItype)(n0)), \
416 "1" ((USItype)(n1)), \
417 "rm" ((USItype)(d)))
418 #define count_leading_zeros(count, x) \
419 do { \
420 USItype __cbtmp; \
421 __asm__ ("bsrl %1,%0" \
422 : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
423 (count) = __cbtmp ^ 31; \
424 } while (0)
425 #define count_trailing_zeros(count, x) \
426 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
427 #ifndef UMUL_TIME
428 #define UMUL_TIME 40
429 #endif
430 #ifndef UDIV_TIME
431 #define UDIV_TIME 40
432 #endif
433 #endif /* 80x86 */
434
435 #if defined (__i860__) && W_TYPE_SIZE == 32
436 #define rshift_rhlc(r,h,l,c) \
437 __asm__ ("shr %3,r0,r0\;shrd %1,%2,%0" \
438 "=r" (r) : "r" (h), "r" (l), "rn" (c))
439 #endif /* i860 */
440
441 #if defined (__i960__) && W_TYPE_SIZE == 32
442 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
443 __asm__ ("cmpo 1,0\;addc %5,%4,%1\;addc %3,%2,%0" \
444 : "=r" ((USItype)(sh)), \
445 "=&r" ((USItype)(sl)) \
446 : "%dI" ((USItype)(ah)), \
447 "dI" ((USItype)(bh)), \
448 "%dI" ((USItype)(al)), \
449 "dI" ((USItype)(bl)))
450 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
451 __asm__ ("cmpo 0,0\;subc %5,%4,%1\;subc %3,%2,%0" \
452 : "=r" ((USItype)(sh)), \
453 "=&r" ((USItype)(sl)) \
454 : "dI" ((USItype)(ah)), \
455 "dI" ((USItype)(bh)), \
456 "dI" ((USItype)(al)), \
457 "dI" ((USItype)(bl)))
458 #define umul_ppmm(w1, w0, u, v) \
459 ({union {UDItype __ll; \
460 struct {USItype __l, __h;} __i; \
461 } __xx; \
462 __asm__ ("emul %2,%1,%0" \
463 : "=d" (__xx.__ll) \
464 : "%dI" ((USItype)(u)), \
465 "dI" ((USItype)(v))); \
466 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
467 #define __umulsidi3(u, v) \
468 ({UDItype __w; \
469 __asm__ ("emul %2,%1,%0" \
470 : "=d" (__w) \
471 : "%dI" ((USItype)(u)), \
472 "dI" ((USItype)(v))); \
473 __w; })
474 #define udiv_qrnnd(q, r, nh, nl, d) \
475 do { \
476 union {UDItype __ll; \
477 struct {USItype __l, __h;} __i; \
478 } __nn; \
479 __nn.__i.__h = (nh); __nn.__i.__l = (nl); \
480 __asm__ ("ediv %d,%n,%0" \
481 : "=d" (__rq.__ll) \
482 : "dI" (__nn.__ll), \
483 "dI" ((USItype)(d))); \
484 (r) = __rq.__i.__l; (q) = __rq.__i.__h; \
485 } while (0)
486 #define count_leading_zeros(count, x) \
487 do { \
488 USItype __cbtmp; \
489 __asm__ ("scanbit %1,%0" \
490 : "=r" (__cbtmp) \
491 : "r" ((USItype)(x))); \
492 (count) = __cbtmp ^ 31; \
493 } while (0)
494 #define COUNT_LEADING_ZEROS_0 (-32) /* sic */
495 #if defined (__i960mx) /* what is the proper symbol to test??? */
496 #define rshift_rhlc(r,h,l,c) \
497 do { \
498 union {UDItype __ll; \
499 struct {USItype __l, __h;} __i; \
500 } __nn; \
501 __nn.__i.__h = (h); __nn.__i.__l = (l); \
502 __asm__ ("shre %2,%1,%0" \
503 : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \
504 }
505 #endif /* i960mx */
506 #endif /* i960 */
507
508 #if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
509 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
510 __asm__ ("add%.l %5,%1
511 addx%.l %3,%0" \
512 : "=d" ((USItype)(sh)), \
513 "=&d" ((USItype)(sl)) \
514 : "%0" ((USItype)(ah)), \
515 "d" ((USItype)(bh)), \
516 "%1" ((USItype)(al)), \
517 "g" ((USItype)(bl)))
518 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
519 __asm__ ("sub%.l %5,%1
520 subx%.l %3,%0" \
521 : "=d" ((USItype)(sh)), \
522 "=&d" ((USItype)(sl)) \
523 : "0" ((USItype)(ah)), \
524 "d" ((USItype)(bh)), \
525 "1" ((USItype)(al)), \
526 "g" ((USItype)(bl)))
527 #if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020))
528 #define umul_ppmm(w1, w0, u, v) \
529 __asm__ ("mulu%.l %3,%1:%0" \
530 : "=d" ((USItype)(w0)), \
531 "=d" ((USItype)(w1)) \
532 : "%0" ((USItype)(u)), \
533 "dmi" ((USItype)(v)))
534 #define UMUL_TIME 45
535 #define udiv_qrnnd(q, r, n1, n0, d) \
536 __asm__ ("divu%.l %4,%1:%0" \
537 : "=d" ((USItype)(q)), \
538 "=d" ((USItype)(r)) \
539 : "0" ((USItype)(n0)), \
540 "1" ((USItype)(n1)), \
541 "dmi" ((USItype)(d)))
542 #define UDIV_TIME 90
543 #define sdiv_qrnnd(q, r, n1, n0, d) \
544 __asm__ ("divs%.l %4,%1:%0" \
545 : "=d" ((USItype)(q)), \
546 "=d" ((USItype)(r)) \
547 : "0" ((USItype)(n0)), \
548 "1" ((USItype)(n1)), \
549 "dmi" ((USItype)(d)))
550 #define count_leading_zeros(count, x) \
551 __asm__ ("bfffo %1{%b2:%b2},%0" \
552 : "=d" ((USItype)(count)) \
553 : "od" ((USItype)(x)), "n" (0))
554 #define COUNT_LEADING_ZEROS_0 32
555 #else /* not mc68020 */
556 #define umul_ppmm(xh, xl, a, b) \
557 do { USItype __umul_tmp1, __umul_tmp2; \
558 __asm__ ("| Inlined umul_ppmm
559 move%.l %5,%3
560 move%.l %2,%0
561 move%.w %3,%1
562 swap %3
563 swap %0
564 mulu %2,%1
565 mulu %3,%0
566 mulu %2,%3
567 swap %2
568 mulu %5,%2
569 add%.l %3,%2
570 jcc 1f
571 add%.l %#0x10000,%0
572 1: move%.l %2,%3
573 clr%.w %2
574 swap %2
575 swap %3
576 clr%.w %3
577 add%.l %3,%1
578 addx%.l %2,%0
579 | End inlined umul_ppmm" \
580 : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
581 "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
582 : "%2" ((USItype)(a)), "d" ((USItype)(b))); \
583 } while (0)
584 #define UMUL_TIME 100
585 #define UDIV_TIME 400
586 #endif /* not mc68020 */
587 #endif /* mc68000 */
588
589 #if defined (__m88000__) && W_TYPE_SIZE == 32
590 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
591 __asm__ ("addu.co %1,%r4,%r5
592 addu.ci %0,%r2,%r3" \
593 : "=r" ((USItype)(sh)), \
594 "=&r" ((USItype)(sl)) \
595 : "%rJ" ((USItype)(ah)), \
596 "rJ" ((USItype)(bh)), \
597 "%rJ" ((USItype)(al)), \
598 "rJ" ((USItype)(bl)))
599 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
600 __asm__ ("subu.co %1,%r4,%r5
601 subu.ci %0,%r2,%r3" \
602 : "=r" ((USItype)(sh)), \
603 "=&r" ((USItype)(sl)) \
604 : "rJ" ((USItype)(ah)), \
605 "rJ" ((USItype)(bh)), \
606 "rJ" ((USItype)(al)), \
607 "rJ" ((USItype)(bl)))
608 #define count_leading_zeros(count, x) \
609 do { \
610 USItype __cbtmp; \
611 __asm__ ("ff1 %0,%1" \
612 : "=r" (__cbtmp) \
613 : "r" ((USItype)(x))); \
614 (count) = __cbtmp ^ 31; \
615 } while (0)
616 #define COUNT_LEADING_ZEROS_0 63 /* sic */
617 #if defined (__m88110__)
618 #define umul_ppmm(wh, wl, u, v) \
619 do { \
620 union {UDItype __ll; \
621 struct {USItype __h, __l;} __i; \
622 } __xx; \
623 __asm__ ("mulu.d %0,%1,%2" \
624 : "=r" (__xx.__ll) \
625 : "r" ((USItype)(u)), \
626 "r" ((USItype)(v))); \
627 (wh) = __xx.__i.__h; \
628 (wl) = __xx.__i.__l; \
629 } while (0)
630 #define udiv_qrnnd(q, r, n1, n0, d) \
631 ({union {UDItype __ll; \
632 struct {USItype __h, __l;} __i; \
633 } __xx; \
634 USItype __q; \
635 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
636 __asm__ ("divu.d %0,%1,%2" \
637 : "=r" (__q) \
638 : "r" (__xx.__ll), \
639 "r" ((USItype)(d))); \
640 (r) = (n0) - __q * (d); (q) = __q; })
641 #define UMUL_TIME 5
642 #define UDIV_TIME 25
643 #else
644 #define UMUL_TIME 17
645 #define UDIV_TIME 150
646 #endif /* __m88110__ */
647 #endif /* __m88000__ */
648
649 #if defined (__mips__) && W_TYPE_SIZE == 32
650 #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
651 #define umul_ppmm(w1, w0, u, v) \
652 __asm__ ("multu %2,%3" \
653 : "=l" ((USItype)(w0)), \
654 "=h" ((USItype)(w1)) \
655 : "d" ((USItype)(u)), \
656 "d" ((USItype)(v)))
657 #else
658 #define umul_ppmm(w1, w0, u, v) \
659 __asm__ ("multu %2,%3
660 mflo %0
661 mfhi %1" \
662 : "=d" ((USItype)(w0)), \
663 "=d" ((USItype)(w1)) \
664 : "d" ((USItype)(u)), \
665 "d" ((USItype)(v)))
666 #endif
667 #define UMUL_TIME 10
668 #define UDIV_TIME 100
669 #endif /* __mips__ */
670
671 #if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64
672 #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
673 #define umul_ppmm(w1, w0, u, v) \
674 __asm__ ("dmultu %2,%3" \
675 : "=l" ((UDItype)(w0)), \
676 "=h" ((UDItype)(w1)) \
677 : "d" ((UDItype)(u)), \
678 "d" ((UDItype)(v)))
679 #else
680 #define umul_ppmm(w1, w0, u, v) \
681 __asm__ ("dmultu %2,%3
682 mflo %0
683 mfhi %1" \
684 : "=d" ((UDItype)(w0)), \
685 "=d" ((UDItype)(w1)) \
686 : "d" ((UDItype)(u)), \
687 "d" ((UDItype)(v)))
688 #endif
689 #define UMUL_TIME 20
690 #define UDIV_TIME 140
691 #endif /* __mips__ */
692
693 #if defined (__ns32000__) && W_TYPE_SIZE == 32
694 #define umul_ppmm(w1, w0, u, v) \
695 ({union {UDItype __ll; \
696 struct {USItype __l, __h;} __i; \
697 } __xx; \
698 __asm__ ("meid %2,%0" \
699 : "=g" (__xx.__ll) \
700 : "%0" ((USItype)(u)), \
701 "g" ((USItype)(v))); \
702 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
703 #define __umulsidi3(u, v) \
704 ({UDItype __w; \
705 __asm__ ("meid %2,%0" \
706 : "=g" (__w) \
707 : "%0" ((USItype)(u)), \
708 "g" ((USItype)(v))); \
709 __w; })
710 #define udiv_qrnnd(q, r, n1, n0, d) \
711 ({union {UDItype __ll; \
712 struct {USItype __l, __h;} __i; \
713 } __xx; \
714 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
715 __asm__ ("deid %2,%0" \
716 : "=g" (__xx.__ll) \
717 : "0" (__xx.__ll), \
718 "g" ((USItype)(d))); \
719 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
720 #define count_trailing_zeros(count,x) \
721 do {
722 __asm__ ("ffsd %2,%0" \
723 : "=r" ((USItype) (count)) \
724 : "0" ((USItype) 0), \
725 "r" ((USItype) (x))); \
726 } while (0)
727 #endif /* __ns32000__ */
728
729 #if (defined (_ARCH_PPC) || defined (_IBMR2)) && W_TYPE_SIZE == 32
730 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
731 do { \
732 if (__builtin_constant_p (bh) && (bh) == 0) \
733 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
734 : "=r" ((USItype)(sh)), \
735 "=&r" ((USItype)(sl)) \
736 : "%r" ((USItype)(ah)), \
737 "%r" ((USItype)(al)), \
738 "rI" ((USItype)(bl))); \
739 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
740 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
741 : "=r" ((USItype)(sh)), \
742 "=&r" ((USItype)(sl)) \
743 : "%r" ((USItype)(ah)), \
744 "%r" ((USItype)(al)), \
745 "rI" ((USItype)(bl))); \
746 else \
747 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
748 : "=r" ((USItype)(sh)), \
749 "=&r" ((USItype)(sl)) \
750 : "%r" ((USItype)(ah)), \
751 "r" ((USItype)(bh)), \
752 "%r" ((USItype)(al)), \
753 "rI" ((USItype)(bl))); \
754 } while (0)
755 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
756 do { \
757 if (__builtin_constant_p (ah) && (ah) == 0) \
758 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
759 : "=r" ((USItype)(sh)), \
760 "=&r" ((USItype)(sl)) \
761 : "r" ((USItype)(bh)), \
762 "rI" ((USItype)(al)), \
763 "r" ((USItype)(bl))); \
764 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
765 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
766 : "=r" ((USItype)(sh)), \
767 "=&r" ((USItype)(sl)) \
768 : "r" ((USItype)(bh)), \
769 "rI" ((USItype)(al)), \
770 "r" ((USItype)(bl))); \
771 else if (__builtin_constant_p (bh) && (bh) == 0) \
772 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
773 : "=r" ((USItype)(sh)), \
774 "=&r" ((USItype)(sl)) \
775 : "r" ((USItype)(ah)), \
776 "rI" ((USItype)(al)), \
777 "r" ((USItype)(bl))); \
778 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
779 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
780 : "=r" ((USItype)(sh)), \
781 "=&r" ((USItype)(sl)) \
782 : "r" ((USItype)(ah)), \
783 "rI" ((USItype)(al)), \
784 "r" ((USItype)(bl))); \
785 else \
786 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
787 : "=r" ((USItype)(sh)), \
788 "=&r" ((USItype)(sl)) \
789 : "r" ((USItype)(ah)), \
790 "r" ((USItype)(bh)), \
791 "rI" ((USItype)(al)), \
792 "r" ((USItype)(bl))); \
793 } while (0)
794 #define count_leading_zeros(count, x) \
795 __asm__ ("{cntlz|cntlzw} %0,%1" \
796 : "=r" ((USItype)(count)) \
797 : "r" ((USItype)(x)))
798 #define COUNT_LEADING_ZEROS_0 32
799 #if defined (_ARCH_PPC)
800 #define umul_ppmm(ph, pl, m0, m1) \
801 do { \
802 USItype __m0 = (m0), __m1 = (m1); \
803 __asm__ ("mulhwu %0,%1,%2" \
804 : "=r" ((USItype) ph) \
805 : "%r" (__m0), \
806 "r" (__m1)); \
807 (pl) = __m0 * __m1; \
808 } while (0)
809 #define UMUL_TIME 15
810 #define smul_ppmm(ph, pl, m0, m1) \
811 do { \
812 SItype __m0 = (m0), __m1 = (m1); \
813 __asm__ ("mulhw %0,%1,%2" \
814 : "=r" ((SItype) ph) \
815 : "%r" (__m0), \
816 "r" (__m1)); \
817 (pl) = __m0 * __m1; \
818 } while (0)
819 #define SMUL_TIME 14
820 #define UDIV_TIME 120
821 #else
822 #define umul_ppmm(xh, xl, m0, m1) \
823 do { \
824 USItype __m0 = (m0), __m1 = (m1); \
825 __asm__ ("mul %0,%2,%3" \
826 : "=r" ((USItype)(xh)), \
827 "=q" ((USItype)(xl)) \
828 : "r" (__m0), \
829 "r" (__m1)); \
830 (xh) += ((((SItype) __m0 >> 31) & __m1) \
831 + (((SItype) __m1 >> 31) & __m0)); \
832 } while (0)
833 #define UMUL_TIME 8
834 #define smul_ppmm(xh, xl, m0, m1) \
835 __asm__ ("mul %0,%2,%3" \
836 : "=r" ((SItype)(xh)), \
837 "=q" ((SItype)(xl)) \
838 : "r" (m0), \
839 "r" (m1))
840 #define SMUL_TIME 4
841 #define sdiv_qrnnd(q, r, nh, nl, d) \
842 __asm__ ("div %0,%2,%4" \
843 : "=r" ((SItype)(q)), "=q" ((SItype)(r)) \
844 : "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d)))
845 #define UDIV_TIME 100
846 #endif
847 #endif /* Power architecture variants. */
848
849 #if defined (__pyr__) && W_TYPE_SIZE == 32
850 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
851 __asm__ ("addw %5,%1
852 addwc %3,%0" \
853 : "=r" ((USItype)(sh)), \
854 "=&r" ((USItype)(sl)) \
855 : "%0" ((USItype)(ah)), \
856 "g" ((USItype)(bh)), \
857 "%1" ((USItype)(al)), \
858 "g" ((USItype)(bl)))
859 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
860 __asm__ ("subw %5,%1
861 subwb %3,%0" \
862 : "=r" ((USItype)(sh)), \
863 "=&r" ((USItype)(sl)) \
864 : "0" ((USItype)(ah)), \
865 "g" ((USItype)(bh)), \
866 "1" ((USItype)(al)), \
867 "g" ((USItype)(bl)))
868 /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
869 #define umul_ppmm(w1, w0, u, v) \
870 ({union {UDItype __ll; \
871 struct {USItype __h, __l;} __i; \
872 } __xx; \
873 __asm__ ("movw %1,%R0
874 uemul %2,%0" \
875 : "=&r" (__xx.__ll) \
876 : "g" ((USItype) (u)), \
877 "g" ((USItype)(v))); \
878 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
879 #endif /* __pyr__ */
880
881 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
882 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
883 __asm__ ("a %1,%5
884 ae %0,%3" \
885 : "=r" ((USItype)(sh)), \
886 "=&r" ((USItype)(sl)) \
887 : "%0" ((USItype)(ah)), \
888 "r" ((USItype)(bh)), \
889 "%1" ((USItype)(al)), \
890 "r" ((USItype)(bl)))
891 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
892 __asm__ ("s %1,%5
893 se %0,%3" \
894 : "=r" ((USItype)(sh)), \
895 "=&r" ((USItype)(sl)) \
896 : "0" ((USItype)(ah)), \
897 "r" ((USItype)(bh)), \
898 "1" ((USItype)(al)), \
899 "r" ((USItype)(bl)))
900 #define umul_ppmm(ph, pl, m0, m1) \
901 do { \
902 USItype __m0 = (m0), __m1 = (m1); \
903 __asm__ ( \
904 "s r2,r2
905 mts r10,%2
906 m r2,%3
907 m r2,%3
908 m r2,%3
909 m r2,%3
910 m r2,%3
911 m r2,%3
912 m r2,%3
913 m r2,%3
914 m r2,%3
915 m r2,%3
916 m r2,%3
917 m r2,%3
918 m r2,%3
919 m r2,%3
920 m r2,%3
921 m r2,%3
922 cas %0,r2,r0
923 mfs r10,%1" \
924 : "=r" ((USItype)(ph)), \
925 "=r" ((USItype)(pl)) \
926 : "%r" (__m0), \
927 "r" (__m1) \
928 : "r2"); \
929 (ph) += ((((SItype) __m0 >> 31) & __m1) \
930 + (((SItype) __m1 >> 31) & __m0)); \
931 } while (0)
932 #define UMUL_TIME 20
933 #define UDIV_TIME 200
934 #define count_leading_zeros(count, x) \
935 do { \
936 if ((x) >= 0x10000) \
937 __asm__ ("clz %0,%1" \
938 : "=r" ((USItype)(count)) \
939 : "r" ((USItype)(x) >> 16)); \
940 else \
941 { \
942 __asm__ ("clz %0,%1" \
943 : "=r" ((USItype)(count)) \
944 : "r" ((USItype)(x))); \
945 (count) += 16; \
946 } \
947 } while (0)
948 #endif /* RT/ROMP */
949
950 #if defined (__sh2__) && W_TYPE_SIZE == 32
951 #define umul_ppmm(w1, w0, u, v) \
952 __asm__ ( \
953 "dmulu.l %2,%3
954 sts macl,%1
955 sts mach,%0" \
956 : "=r" ((USItype)(w1)), \
957 "=r" ((USItype)(w0)) \
958 : "r" ((USItype)(u)), \
959 "r" ((USItype)(v)) \
960 : "macl", "mach")
961 #define UMUL_TIME 5
962 #endif
963
964 #if defined (__sparc__) && W_TYPE_SIZE == 32
965 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
966 __asm__ ("addcc %r4,%5,%1
967 addx %r2,%3,%0" \
968 : "=r" ((USItype)(sh)), \
969 "=&r" ((USItype)(sl)) \
970 : "%rJ" ((USItype)(ah)), \
971 "rI" ((USItype)(bh)), \
972 "%rJ" ((USItype)(al)), \
973 "rI" ((USItype)(bl)) \
974 __CLOBBER_CC)
975 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
976 __asm__ ("subcc %r4,%5,%1
977 subx %r2,%3,%0" \
978 : "=r" ((USItype)(sh)), \
979 "=&r" ((USItype)(sl)) \
980 : "rJ" ((USItype)(ah)), \
981 "rI" ((USItype)(bh)), \
982 "rJ" ((USItype)(al)), \
983 "rI" ((USItype)(bl)) \
984 __CLOBBER_CC)
985 #if defined (__sparc_v8__)
986 /* Don't match immediate range because, 1) it is not often useful,
987 2) the 'I' flag thinks of the range as a 13 bit signed interval,
988 while we want to match a 13 bit interval, sign extended to 32 bits,
989 but INTERPRETED AS UNSIGNED. */
990 #define umul_ppmm(w1, w0, u, v) \
991 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
992 : "=r" ((USItype)(w1)), \
993 "=r" ((USItype)(w0)) \
994 : "r" ((USItype)(u)), \
995 "r" ((USItype)(v)))
996 #define UMUL_TIME 5
997 #ifndef SUPERSPARC /* SuperSPARC's udiv only handles 53 bit dividends */
998 #define udiv_qrnnd(q, r, n1, n0, d) \
999 do { \
1000 USItype __q; \
1001 __asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
1002 : "=r" ((USItype)(__q)) \
1003 : "r" ((USItype)(n1)), \
1004 "r" ((USItype)(n0)), \
1005 "r" ((USItype)(d))); \
1006 (r) = (n0) - __q * (d); \
1007 (q) = __q; \
1008 } while (0)
1009 #define UDIV_TIME 25
1010 #endif /* SUPERSPARC */
1011 #else /* ! __sparc_v8__ */
1012 #if defined (__sparclite__)
1013 /* This has hardware multiply but not divide. It also has two additional
1014 instructions scan (ffs from high bit) and divscc. */
1015 #define umul_ppmm(w1, w0, u, v) \
1016 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1017 : "=r" ((USItype)(w1)), \
1018 "=r" ((USItype)(w0)) \
1019 : "r" ((USItype)(u)), \
1020 "r" ((USItype)(v)))
1021 #define UMUL_TIME 5
1022 #define udiv_qrnnd(q, r, n1, n0, d) \
1023 __asm__ ("! Inlined udiv_qrnnd
1024 wr %%g0,%2,%%y ! Not a delayed write for sparclite
1025 tst %%g0
1026 divscc %3,%4,%%g1
1027 divscc %%g1,%4,%%g1
1028 divscc %%g1,%4,%%g1
1029 divscc %%g1,%4,%%g1
1030 divscc %%g1,%4,%%g1
1031 divscc %%g1,%4,%%g1
1032 divscc %%g1,%4,%%g1
1033 divscc %%g1,%4,%%g1
1034 divscc %%g1,%4,%%g1
1035 divscc %%g1,%4,%%g1
1036 divscc %%g1,%4,%%g1
1037 divscc %%g1,%4,%%g1
1038 divscc %%g1,%4,%%g1
1039 divscc %%g1,%4,%%g1
1040 divscc %%g1,%4,%%g1
1041 divscc %%g1,%4,%%g1
1042 divscc %%g1,%4,%%g1
1043 divscc %%g1,%4,%%g1
1044 divscc %%g1,%4,%%g1
1045 divscc %%g1,%4,%%g1
1046 divscc %%g1,%4,%%g1
1047 divscc %%g1,%4,%%g1
1048 divscc %%g1,%4,%%g1
1049 divscc %%g1,%4,%%g1
1050 divscc %%g1,%4,%%g1
1051 divscc %%g1,%4,%%g1
1052 divscc %%g1,%4,%%g1
1053 divscc %%g1,%4,%%g1
1054 divscc %%g1,%4,%%g1
1055 divscc %%g1,%4,%%g1
1056 divscc %%g1,%4,%%g1
1057 divscc %%g1,%4,%0
1058 rd %%y,%1
1059 bl,a 1f
1060 add %1,%4,%1
1061 1: ! End of inline udiv_qrnnd" \
1062 : "=r" ((USItype)(q)), \
1063 "=r" ((USItype)(r)) \
1064 : "r" ((USItype)(n1)), \
1065 "r" ((USItype)(n0)), \
1066 "rI" ((USItype)(d)) \
1067 : "%g1" __AND_CLOBBER_CC)
1068 #define UDIV_TIME 37
1069 #define count_leading_zeros(count, x) \
1070 __asm__ ("scan %1,0,%0" \
1071 : "=r" ((USItype)(x)) \
1072 : "r" ((USItype)(count)))
1073 #endif /* __sparclite__ */
1074 #endif /* __sparc_v8__ */
1075 /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
1076 #ifndef umul_ppmm
1077 #define umul_ppmm(w1, w0, u, v) \
1078 __asm__ ("! Inlined umul_ppmm
1079 wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
1080 sra %3,31,%%g2 ! Don't move this insn
1081 and %2,%%g2,%%g2 ! Don't move this insn
1082 andcc %%g0,0,%%g1 ! Don't move this insn
1083 mulscc %%g1,%3,%%g1
1084 mulscc %%g1,%3,%%g1
1085 mulscc %%g1,%3,%%g1
1086 mulscc %%g1,%3,%%g1
1087 mulscc %%g1,%3,%%g1
1088 mulscc %%g1,%3,%%g1
1089 mulscc %%g1,%3,%%g1
1090 mulscc %%g1,%3,%%g1
1091 mulscc %%g1,%3,%%g1
1092 mulscc %%g1,%3,%%g1
1093 mulscc %%g1,%3,%%g1
1094 mulscc %%g1,%3,%%g1
1095 mulscc %%g1,%3,%%g1
1096 mulscc %%g1,%3,%%g1
1097 mulscc %%g1,%3,%%g1
1098 mulscc %%g1,%3,%%g1
1099 mulscc %%g1,%3,%%g1
1100 mulscc %%g1,%3,%%g1
1101 mulscc %%g1,%3,%%g1
1102 mulscc %%g1,%3,%%g1
1103 mulscc %%g1,%3,%%g1
1104 mulscc %%g1,%3,%%g1
1105 mulscc %%g1,%3,%%g1
1106 mulscc %%g1,%3,%%g1
1107 mulscc %%g1,%3,%%g1
1108 mulscc %%g1,%3,%%g1
1109 mulscc %%g1,%3,%%g1
1110 mulscc %%g1,%3,%%g1
1111 mulscc %%g1,%3,%%g1
1112 mulscc %%g1,%3,%%g1
1113 mulscc %%g1,%3,%%g1
1114 mulscc %%g1,%3,%%g1
1115 mulscc %%g1,0,%%g1
1116 add %%g1,%%g2,%0
1117 rd %%y,%1" \
1118 : "=r" ((USItype)(w1)), \
1119 "=r" ((USItype)(w0)) \
1120 : "%rI" ((USItype)(u)), \
1121 "r" ((USItype)(v)) \
1122 : "%g1", "%g2" __AND_CLOBBER_CC)
1123 #define UMUL_TIME 39 /* 39 instructions */
1124 #endif
1125 #ifndef udiv_qrnnd
1126 #ifndef LONGLONG_STANDALONE
1127 #define udiv_qrnnd(q, r, n1, n0, d) \
1128 do { USItype __r; \
1129 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
1130 (r) = __r; \
1131 } while (0)
1132 extern USItype __udiv_qrnnd ();
1133 #define UDIV_TIME 140
1134 #endif /* LONGLONG_STANDALONE */
1135 #endif /* udiv_qrnnd */
1136 #endif /* __sparc__ */
1137
1138 #if defined (__vax__) && W_TYPE_SIZE == 32
1139 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1140 __asm__ ("addl2 %5,%1
1141 adwc %3,%0" \
1142 : "=g" ((USItype)(sh)), \
1143 "=&g" ((USItype)(sl)) \
1144 : "%0" ((USItype)(ah)), \
1145 "g" ((USItype)(bh)), \
1146 "%1" ((USItype)(al)), \
1147 "g" ((USItype)(bl)))
1148 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1149 __asm__ ("subl2 %5,%1
1150 sbwc %3,%0" \
1151 : "=g" ((USItype)(sh)), \
1152 "=&g" ((USItype)(sl)) \
1153 : "0" ((USItype)(ah)), \
1154 "g" ((USItype)(bh)), \
1155 "1" ((USItype)(al)), \
1156 "g" ((USItype)(bl)))
1157 #define umul_ppmm(xh, xl, m0, m1) \
1158 do { \
1159 union {UDItype __ll; \
1160 struct {USItype __l, __h;} __i; \
1161 } __xx; \
1162 USItype __m0 = (m0), __m1 = (m1); \
1163 __asm__ ("emul %1,%2,$0,%0" \
1164 : "=g" (__xx.__ll) \
1165 : "g" (__m0), \
1166 "g" (__m1)); \
1167 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1168 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1169 + (((SItype) __m1 >> 31) & __m0)); \
1170 } while (0)
1171 #define sdiv_qrnnd(q, r, n1, n0, d) \
1172 do { \
1173 union {DItype __ll; \
1174 struct {SItype __l, __h;} __i; \
1175 } __xx; \
1176 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1177 __asm__ ("ediv %3,%2,%0,%1" \
1178 : "=g" (q), "=g" (r) \
1179 : "g" (__xx.ll), "g" (d)); \
1180 } while (0)
1181 #endif /* __vax__ */
1182
1183 #if defined (__z8000__) && W_TYPE_SIZE == 16
1184 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1185 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1186 : "=r" ((unsigned int)(sh)), \
1187 "=&r" ((unsigned int)(sl)) \
1188 : "%0" ((unsigned int)(ah)), \
1189 "r" ((unsigned int)(bh)), \
1190 "%1" ((unsigned int)(al)), \
1191 "rQR" ((unsigned int)(bl)))
1192 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1193 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1194 : "=r" ((unsigned int)(sh)), \
1195 "=&r" ((unsigned int)(sl)) \
1196 : "0" ((unsigned int)(ah)), \
1197 "r" ((unsigned int)(bh)), \
1198 "1" ((unsigned int)(al)), \
1199 "rQR" ((unsigned int)(bl)))
1200 #define umul_ppmm(xh, xl, m0, m1) \
1201 do { \
1202 union {long int __ll; \
1203 struct {unsigned int __h, __l;} __i; \
1204 } __xx; \
1205 unsigned int __m0 = (m0), __m1 = (m1); \
1206 __asm__ ("mult %S0,%H3" \
1207 : "=r" (__xx.__i.__h), \
1208 "=r" (__xx.__i.__l) \
1209 : "%1" (__m0), \
1210 "rQR" (__m1)); \
1211 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1212 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1213 + (((signed int) __m1 >> 15) & __m0)); \
1214 } while (0)
1215 #endif /* __z8000__ */
1216
1217 #endif /* __GNUC__ */
1218
1219
1220 #if !defined (umul_ppmm) && defined (__umulsidi3)
1221 #define umul_ppmm(ph, pl, m0, m1) \
1222 { \
1223 UDWtype __ll = __umulsidi3 (m0, m1); \
1224 ph = (UWtype) (__ll >> W_TYPE_SIZE); \
1225 pl = (UWtype) __ll; \
1226 }
1227 #endif
1228
1229 #if !defined (__umulsidi3)
1230 #define __umulsidi3(u, v) \
1231 ({UWtype __hi, __lo; \
1232 umul_ppmm (__hi, __lo, u, v); \
1233 ((UDWtype) __hi << W_TYPE_SIZE) | __lo; })
1234 #endif
1235
1236 /* If this machine has no inline assembler, use C macros. */
1237
1238 #if !defined (add_ssaaaa)
1239 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1240 do { \
1241 UWtype __x; \
1242 __x = (al) + (bl); \
1243 (sh) = (ah) + (bh) + (__x < (al)); \
1244 (sl) = __x; \
1245 } while (0)
1246 #endif
1247
1248 #if !defined (sub_ddmmss)
1249 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1250 do { \
1251 UWtype __x; \
1252 __x = (al) - (bl); \
1253 (sh) = (ah) - (bh) - (__x > (al)); \
1254 (sl) = __x; \
1255 } while (0)
1256 #endif
1257
1258 #if !defined (umul_ppmm)
1259 #define umul_ppmm(w1, w0, u, v) \
1260 do { \
1261 UWtype __x0, __x1, __x2, __x3; \
1262 UHWtype __ul, __vl, __uh, __vh; \
1263 UWtype __u = (u), __v = (v); \
1264 \
1265 __ul = __ll_lowpart (__u); \
1266 __uh = __ll_highpart (__u); \
1267 __vl = __ll_lowpart (__v); \
1268 __vh = __ll_highpart (__v); \
1269 \
1270 __x0 = (UWtype) __ul * __vl; \
1271 __x1 = (UWtype) __ul * __vh; \
1272 __x2 = (UWtype) __uh * __vl; \
1273 __x3 = (UWtype) __uh * __vh; \
1274 \
1275 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1276 __x1 += __x2; /* but this indeed can */ \
1277 if (__x1 < __x2) /* did we get it? */ \
1278 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1279 \
1280 (w1) = __x3 + __ll_highpart (__x1); \
1281 (w0) = (__ll_lowpart (__x1) << W_TYPE_SIZE/2) + __ll_lowpart (__x0);\
1282 } while (0)
1283 #endif
1284
1285 #if !defined (umul_ppmm)
1286 #define smul_ppmm(w1, w0, u, v) \
1287 do { \
1288 UWtype __w1; \
1289 UWtype __m0 = (u), __m1 = (v); \
1290 umul_ppmm (__w1, w0, __m0, __m1); \
1291 (w1) = __w1 - (-(__m0 >> (W_TYPE_SIZE - 1)) & __m1) \
1292 - (-(__m1 >> (W_TYPE_SIZE - 1)) & __m0); \
1293 } while (0)
1294 #endif
1295
1296 /* Define this unconditionally, so it can be used for debugging. */
1297 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1298 do { \
1299 UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
1300 __d1 = __ll_highpart (d); \
1301 __d0 = __ll_lowpart (d); \
1302 \
1303 __r1 = (n1) % __d1; \
1304 __q1 = (n1) / __d1; \
1305 __m = (UWtype) __q1 * __d0; \
1306 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1307 if (__r1 < __m) \
1308 { \
1309 __q1--, __r1 += (d); \
1310 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1311 if (__r1 < __m) \
1312 __q1--, __r1 += (d); \
1313 } \
1314 __r1 -= __m; \
1315 \
1316 __r0 = __r1 % __d1; \
1317 __q0 = __r1 / __d1; \
1318 __m = (UWtype) __q0 * __d0; \
1319 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1320 if (__r0 < __m) \
1321 { \
1322 __q0--, __r0 += (d); \
1323 if (__r0 >= (d)) \
1324 if (__r0 < __m) \
1325 __q0--, __r0 += (d); \
1326 } \
1327 __r0 -= __m; \
1328 \
1329 (q) = (UWtype) __q1 * __ll_B | __q0; \
1330 (r) = __r0; \
1331 } while (0)
1332
1333 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1334 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1335 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1336 #define udiv_qrnnd(q, r, nh, nl, d) \
1337 do { \
1338 UWtype __r; \
1339 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1340 (r) = __r; \
1341 } while (0)
1342 #endif
1343
1344 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1345 #if !defined (udiv_qrnnd)
1346 #define UDIV_NEEDS_NORMALIZATION 1
1347 #define udiv_qrnnd __udiv_qrnnd_c
1348 #endif
1349
1350 #if !defined (count_leading_zeros)
1351 extern
1352 #ifdef __STDC__
1353 const
1354 #endif
1355 unsigned char __clz_tab[];
1356 #define count_leading_zeros(count, x) \
1357 do { \
1358 UWtype __xr = (x); \
1359 UWtype __a; \
1360 \
1361 if (W_TYPE_SIZE <= 32) \
1362 { \
1363 __a = __xr < ((UWtype) 1 << 2*__BITS4) \
1364 ? (__xr < ((UWtype) 1 << __BITS4) ? 0 : __BITS4) \
1365 : (__xr < ((UWtype) 1 << 3*__BITS4) ? 2*__BITS4 : 3*__BITS4);\
1366 } \
1367 else \
1368 { \
1369 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1370 if (((__xr >> __a) & 0xff) != 0) \
1371 break; \
1372 } \
1373 \
1374 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1375 } while (0)
1376 /* This version gives a well-defined value for zero. */
1377 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1378 #endif
1379
1380 #if !defined (count_trailing_zeros)
1381 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1382 defined in asm, but if it is not, the C version above is good enough. */
1383 #define count_trailing_zeros(count, x) \
1384 do { \
1385 UWtype __ctz_x = (x); \
1386 UWtype __ctz_c; \
1387 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1388 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1389 } while (0)
1390 #endif
1391
1392 #ifndef UDIV_NEEDS_NORMALIZATION
1393 #define UDIV_NEEDS_NORMALIZATION 0
1394 #endif
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