Test for stack alignment.
[glibc.git] / sysdeps / mips / sys / ucontext.h
blobfe378e94cd6696c6d6369a5a0eecb7d07177d82b
1 /* Copyright (C) 1998, 1999, 2002, 2003, 2004 Free Software Foundation, Inc.
2 This file is part of the GNU C Library.
4 The GNU C Library is free software; you can redistribute it and/or
5 modify it under the terms of the GNU Lesser General Public
6 License as published by the Free Software Foundation; either
7 version 2.1 of the License, or (at your option) any later version.
9 The GNU C Library is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 Lesser General Public License for more details.
14 You should have received a copy of the GNU Lesser General Public
15 License along with the GNU C Library; if not, write to the Free
16 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
17 02111-1307 USA. */
19 /* System V/mips ABI compliant context switching support. */
21 #ifndef _SYS_UCONTEXT_H
22 #define _SYS_UCONTEXT_H 1
24 #include <features.h>
25 #include <sgidefs.h>
26 #include <signal.h>
28 /* Type for general register. */
29 #if _MIPS_SIM == _ABIO32
30 typedef __uint32_t greg_t;
31 #else
32 typedef __uint64_t greg_t;
33 #endif
35 /* Number of general registers. */
36 #define NGREG 36
38 /* Container for all general registers. */
39 typedef greg_t gregset_t[NGREG];
41 /* Number of each register is the `gregset_t' array. */
42 enum
44 CTX_R0 = 0,
45 #define CTX_R0 CTX_R0
46 CTX_AT = 1,
47 #define CTX_AT CTX_AT
48 CTX_V0 = 2,
49 #define CTX_V0 CTX_V0
50 CTX_V1 = 3,
51 #define CTX_V1 CTX_V1
52 CTX_A0 = 4,
53 #define CTX_A0 CTX_A0
54 CTX_A1 = 5,
55 #define CTX_A1 CTX_A1
56 CTX_A2 = 6,
57 #define CTX_A2 CTX_A2
58 CTX_A3 = 7,
59 #define CTX_A3 CTX_A3
60 CTX_T0 = 8,
61 #define CTX_T0 CTX_T0
62 CTX_T1 = 9,
63 #define CTX_T1 CTX_T1
64 CTX_T2 = 10,
65 #define CTX_T2 CTX_T2
66 CTX_T3 = 11,
67 #define CTX_T3 CTX_T3
68 CTX_T4 = 12,
69 #define CTX_T4 CTX_T4
70 CTX_T5 = 13,
71 #define CTX_T5 CTX_T5
72 CTX_T6 = 14,
73 #define CTX_T6 CTX_T6
74 CTX_T7 = 15,
75 #define CTX_T7 CTX_T7
76 CTX_S0 = 16,
77 #define CTX_S0 CTX_S0
78 CTX_S1 = 17,
79 #define CTX_S1 CTX_S1
80 CTX_S2 = 18,
81 #define CTX_S2 CTX_S2
82 CTX_S3 = 19,
83 #define CTX_S3 CTX_S3
84 CTX_S4 = 20,
85 #define CTX_S4 CTX_S4
86 CTX_S5 = 21,
87 #define CTX_S5 CTX_S5
88 CTX_S6 = 22,
89 #define CTX_S6 CTX_S6
90 CTX_S7 = 23,
91 #define CTX_S7 CTX_S7
92 CTX_T8 = 24,
93 #define CTX_T8 CTX_T8
94 CTX_T9 = 25,
95 #define CTX_T9 CTX_T9
96 CTX_K0 = 26,
97 #define CTX_K0 CTX_K0
98 CTX_K1 = 27,
99 #define CTX_K1 CTX_K1
100 CTX_GP = 28,
101 #define CTX_GP CTX_GP
102 CTX_SP = 29,
103 #define CTX_SP CTX_SP
104 CTX_S8 = 30,
105 #define CTX_S8 CTX_S8
106 CTX_RA = 31,
107 #define CTX_RA CTX_RA
108 CTX_MDLO = 32,
109 #define CTX_MDLO CTX_MDLO
110 CTX_MDHI = 33,
111 #define CTX_MDHI CTX_MDHI
112 CTX_CAUSE = 34,
113 #define CTX_CAUSE CTX_CAUSE
114 CTX_EPC = 35,
115 #define CTX_EPC CTX_EPC
118 /* Structure to describe FPU registers. */
119 typedef struct fpregset
121 union
123 #if _MIPS_SIM == _ABIO32
124 double fp_dregs[16];
125 float fp_fregs[32];
126 unsigned int fp_regs[32];
127 #else
128 double fp_dregs[32];
129 /* float fp_fregs[32]; */
130 __uint64_t fp_regs[32];
131 #endif
132 } fp_r;
133 unsigned int fp_csr;
134 unsigned int fp_pad;
135 } fpregset_t;
137 /* Context to describe whole processor state. */
138 typedef struct
140 gregset_t gpregs;
141 fpregset_t fpregs;
142 } mcontext_t;
144 /* Userlevel context. */
145 typedef struct ucontext
147 #if _MIPS_SIM == _ABIO32
148 unsigned long int uc_flags;
149 #else
150 __uint64_t uc_flags;
151 #endif
152 struct ucontext *uc_link;
153 __sigset_t uc_sigmask;
154 stack_t uc_stack;
155 mcontext_t uc_mcontext;
156 int uc_filler[48];
157 } ucontext_t;
159 #endif /* sys/ucontext.h */