sysdeps/standalone/i960/i960ca.h

   1 /* Copyright (C) 1994, 1996 Free Software Foundation, Inc.
   2    This file is part of the GNU C Library.
   3    Contributed by Joel Sherrill (jsherril@redstone-emh2.army.mil),
   4    On-Line Applications Research Corporation.
   5
   6    The GNU C Library is free software; you can redistribute it and/or
   7    modify it under the terms of the GNU Library General Public License as
   8    published by the Free Software Foundation; either version 2 of the
   9    License, or (at your option) any later version.
  10
  11    The GNU C Library is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    Library General Public License for more details.
  15
  16    You should have received a copy of the GNU Library General Public
  17    License along with the GNU C Library; see the file COPYING.LIB.  If not,
  18    write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19    Boston, MA 02111-1307, USA.  */
  20
  21 /* i960ca.h
  22  *
  23  *  This file contains macros which are used to access i80960CA
  24  *  registers which are not addressable by C.  The functions
  25  *  in this file should be useful to the developer of target
  26  *  specific code.
  27  */
  28
  29 #ifndef i960ca_h__
  30 #define i960ca_h__
  31
  32 typedef unsigned char   unsigned8;
  33 typedef unsigned short  unsigned16;
  34 typedef unsigned int    unsigned32;
  35
  36 /*
  37  *  Intel i80960CA Processor Control Block
  38  */
  39
  40 struct i80960ca_prcb {
  41   unsigned32          *fault_tbl;     /* fault table base address     */
  42   struct i80960ca_ctltbl
  43                       *control_tbl;   /* control table base address   */
  44   unsigned32           initial_ac;    /* AC register initial value    */
  45   unsigned32           fault_config;  /* fault configuration word     */
  46   void                *intr_tbl;      /* interrupt table base address */
  47   void                *sys_proc_tbl;  /* system procedure table       */
  48                                       /*   base address               */
  49   unsigned32           reserved;      /* reserved                     */
  50   unsigned32          *intr_stack;    /* interrupt stack pointer      */
  51   unsigned32           ins_cache_cfg; /* instruction cache            */
  52                                       /*   configuration word         */
  53   unsigned32           reg_cache_cfg; /* register cache               */
  54                                       /*   configuration word         */
  55 };
  56
  57 /*
  58  *  Intel i80960CA Control Table
  59  */
  60
  61 struct i80960ca_ctltbl {
  62                             /* Control Group 0 */
  63   unsigned32       ipb0;              /* IP breakpoint 0 */
  64   unsigned32       ipb1;              /* IP breakpoint 1 */
  65   unsigned32       dab0;              /* data address breakpoint 0 */
  66   unsigned32       dab1;              /* data address breakpoint 1 */
  67                             /* Control Group 1 */
  68   unsigned32       imap0;             /* interrupt map 0 */
  69   unsigned32       imap1;             /* interrupt map 1 */
  70   unsigned32       imap2;             /* interrupt map 2 */
  71   unsigned32       icon;              /* interrupt control */
  72                             /* Control Group 2 */
  73   unsigned32       mcon0;             /* memory region 0 configuration */
  74   unsigned32       mcon1;             /* memory region 1 configuration */
  75   unsigned32       mcon2;             /* memory region 2 configuration */
  76   unsigned32       mcon3;             /* memory region 3 configuration */
  77                             /* Control Group 3 */
  78   unsigned32       mcon4;             /* memory region 4 configuration */
  79   unsigned32       mcon5;             /* memory region 5 configuration */
  80   unsigned32       mcon6;             /* memory region 6 configuration */
  81   unsigned32       mcon7;             /* memory region 7 configuration */
  82                             /* Control Group 4 */
  83   unsigned32       mcon8;             /* memory region 8 configuration */
  84   unsigned32       mcon9;             /* memory region 9 configuration */
  85   unsigned32       mcon10;            /* memory region 10 configuration */
  86   unsigned32       mcon11;            /* memory region 11 configuration */
  87                             /* Control Group 5 */
  88   unsigned32       mcon12;            /* memory region 12 configuration */
  89   unsigned32       mcon13;            /* memory region 13 configuration */
  90   unsigned32       mcon14;            /* memory region 14 configuration */
  91   unsigned32       mcon15;            /* memory region 15 configuration */
  92                             /* Control Group 6 */
  93   unsigned32       bpcon;             /* breakpoint control */
  94   unsigned32       tc;                /* trace control */
  95   unsigned32       bcon;              /* bus configuration control */
  96   unsigned32       reserved;          /* reserved */
  97 };
  98
  99 #define disable_intr( oldlevel ) \
 100   { (oldlevel) = 0x1f0000; \
 101     asm volatile ( "modpc   0,%1,%1" \
 102                        : "=d" ((oldlevel)) \
 103                        : "0"  ((oldlevel)) ); \
 104   }
 105
 106 #define enable_intr( oldlevel ) \
 107   { unsigned32 _mask = 0x1f0000; \
 108     asm volatile ( "modpc   0,%0,%1" \
 109                        : "=d" (_mask), "=d" ((oldlevel)) \
 110                        : "0"  (_mask), "1"  ((oldlevel)) ); \
 111   }
 112
 113 #define flash_intr( oldlevel ) \
 114   { unsigned32 _mask = 0x1f0000; \
 115     asm volatile ( "modpc   0,%0,%1 ; \
 116                     mov     %0,%1 ; \
 117                     modpc   0,%0,%1"  \
 118                        : "=d" (_mask), "=d" ((oldlevel)) \
 119                        : "0"  (_mask), "1"  ((oldlevel)) ); \
 120   }
 121
 122 #define atomic_modify( mask, addr, prev ) \
 123  { register unsigned32  _mask = (mask); \
 124    register unsigned32 *_addr = (unsigned32 *)(addr); \
 125    asm volatile( "atmod  %0,%1,%1" \
 126                   : "=d" (_addr), "=d" (_mask) \
 127                   : "0"  (_addr), "1"  (_mask) ); \
 128    (prev) = _mask; \
 129  }
 130
 131 #define delay( microseconds ) \
 132   { register unsigned32 _delay=(microseconds); \
 133     register unsigned32 _tmp; \
 134     asm volatile( "delay0: \
 135                      remo      3,31,%0 ; \
 136                      cmpo      0,%0 ; \
 137                      subo      1,%1,%1 ; \
 138                      cmpobne.t 0,%1,delay0 " \
 139                   : "=d" (_tmp), "=d" (_delay) \
 140                   : "0"  (_tmp), "1"  (_delay) ); \
 141   }
 142
 143 #define enable_tracing() \
 144  { register unsigned32 _pc = 0x1; \
 145    asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
 146  }
 147
 148 #define unmask_intr( xint ) \
 149  { register unsigned32 _mask= (1<<(xint)); \
 150    asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
 151  }
 152
 153 #define mask_intr( xint ) \
 154  { register unsigned32 _mask= (1<<(xint)); \
 155    asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
 156  }
 157
 158 #define clear_intr( xint ) \
 159  { register unsigned32 _xint=(xint); \
 160    asm volatile( "loop_til_cleared:
 161                     clrbit %0,sf0,sf0 ; \
 162                     bbs    %0,sf0,loop_til_cleared" \
 163                   : "=d" (_xint) : "0" (_xint) ); \
 164  }
 165
 166 #define reload_ctl_group( group ) \
 167  { register int _cmd = ((group)|0x400) ; \
 168    asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
 169  }
 170
 171 #define cause_intr( intr ) \
 172  { register int _intr = (intr); \
 173    asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
 174  }
 175
 176 #define soft_reset( prcb ) \
 177  { register struct i80960ca_prcb *_prcb = (prcb); \
 178    register unsigned32         *_next=0; \
 179    register unsigned32          _cmd  = 0x30000; \
 180    asm volatile( "lda    next,%1; \
 181                   sysctl %0,%1,%2; \
 182             next: mov    g0,g0" \
 183                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
 184                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
 185  }
 186
 187 static inline unsigned32 pend_intrs()
 188 { register unsigned32 _intr=0;
 189   asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
 190   return ( _intr );
 191 }
 192
 193 static inline unsigned32 mask_intrs()
 194 { register unsigned32 _intr=0;
 195   asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
 196   return( _intr );
 197 }
 198
 199 static inline unsigned32 get_fp()
 200 { register unsigned32 _fp=0;
 201   asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
 202   return ( _fp );
 203 }
 204
 205 #endif
 206 /* end of include file */