1 /* Internal libc stuff for floating point environment routines.
2 Copyright (C) 1997, 2006, 2008, 2009 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
20 #define _FENV_LIBC_H 1
26 libm_hidden_proto (__fe_nomask_env
)
28 /* The sticky bits in the FPSCR indicating exceptions have occurred. */
29 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
31 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
33 #define fegetenv_register() \
34 ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
36 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
37 #define fesetenv_register(env) \
40 if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
41 asm volatile (".machine push; " \
42 ".machine \"power6\"; " \
43 "mtfsf 0xff,%0,1,0; " \
44 ".machine pop" : : "f" (d)); \
46 asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
49 /* This very handy macro:
50 - Sets the rounding mode to 'round to nearest';
51 - Sets the processor into IEEE mode; and
52 - Prevents exceptions from being raised for inexact results.
53 These things happen to be exactly what you need for typical elementary
55 #define relax_fenv_state() \
57 if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
58 asm (".machine push; .machine \"power6\"; " \
59 "mtfsfi 7,0,1; .machine pop"); \
63 /* Set/clear a particular FPSCR bit (for instance,
64 reset_fpscr_bit(FPSCR_VE);
65 prevents INVALID exceptions from being raised). */
66 #define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
67 #define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
80 asm volatile ("mcrfs 7,7\n\t"
81 "mfcr %0" : "=r"(result
) : : "cr7");
84 #define fegetround() __fegetround()
87 __fesetround (int round
)
89 if ((unsigned int) round
< 2)
91 asm volatile ("mtfsb0 30");
92 if ((unsigned int) round
== 0)
93 asm volatile ("mtfsb0 31");
95 asm volatile ("mtfsb1 31");
99 asm volatile ("mtfsb1 30");
100 if ((unsigned int) round
== 2)
101 asm volatile ("mtfsb0 31");
103 asm volatile ("mtfsb1 31");
108 #define fesetround(mode) __fesetround(mode)
110 /* Definitions of all the FPSCR bit numbers */
112 FPSCR_FX
= 0, /* exception summary */
113 FPSCR_FEX
, /* enabled exception summary */
114 FPSCR_VX
, /* invalid operation summary */
115 FPSCR_OX
, /* overflow */
116 FPSCR_UX
, /* underflow */
117 FPSCR_ZX
, /* zero divide */
118 FPSCR_XX
, /* inexact */
119 FPSCR_VXSNAN
, /* invalid operation for SNaN */
120 FPSCR_VXISI
, /* invalid operation for Inf-Inf */
121 FPSCR_VXIDI
, /* invalid operation for Inf/Inf */
122 FPSCR_VXZDZ
, /* invalid operation for 0/0 */
123 FPSCR_VXIMZ
, /* invalid operation for Inf*0 */
124 FPSCR_VXVC
, /* invalid operation for invalid compare */
125 FPSCR_FR
, /* fraction rounded [fraction was incremented by round] */
126 FPSCR_FI
, /* fraction inexact */
127 FPSCR_FPRF_C
, /* result class descriptor */
128 FPSCR_FPRF_FL
, /* result less than (usually, less than 0) */
129 FPSCR_FPRF_FG
, /* result greater than */
130 FPSCR_FPRF_FE
, /* result equal to */
131 FPSCR_FPRF_FU
, /* result unordered */
132 FPSCR_20
, /* reserved */
133 FPSCR_VXSOFT
, /* invalid operation set by software */
134 FPSCR_VXSQRT
, /* invalid operation for square root */
135 FPSCR_VXCVI
, /* invalid operation for invalid integer convert */
136 FPSCR_VE
, /* invalid operation exception enable */
137 FPSCR_OE
, /* overflow exception enable */
138 FPSCR_UE
, /* underflow exception enable */
139 FPSCR_ZE
, /* zero divide exception enable */
140 FPSCR_XE
, /* inexact exception enable */
142 FPSCR_29
, /* Reserved in ISA 2.05 */
144 FPSCR_NI
/* non-IEEE mode (typically, no denormalised numbers) */
145 #endif /* _ARCH_PWR6 */
146 /* the remaining two least-significant bits keep the rounding mode */
150 /* Not supported in ISA 2.05. Provided for source compat only. */
152 #endif /* _ARCH_PWR6 */
154 /* This operation (i) sets the appropriate FPSCR bits for its
155 parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
156 otherwise passes its parameter through unchanged (in particular, -0
157 and +0 stay as they were). The `obvious' way to do this is optimised
160 ({ double d; asm volatile ("fmul %0,%1,%2" \
162 : "f" (x), "f"((float)1.0)); d; })
164 ({ float f; asm volatile ("fmuls %0,%1,%2" \
166 : "f" (x), "f"((float)1.0)); f; })
168 #endif /* fenv_libc.h */