sysdeps/alpha/fpu/bits/fenv.h

   1 /* Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
   2    This file is part of the GNU C Library.
   3
   4    The GNU C Library is free software; you can redistribute it and/or
   5    modify it under the terms of the GNU Library General Public License as
   6    published by the Free Software Foundation; either version 2 of the
   7    License, or (at your option) any later version.
   8
   9    The GNU C Library is distributed in the hope that it will be useful,
  10    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12    Library General Public License for more details.
  13
  14    You should have received a copy of the GNU Library General Public
  15    License along with the GNU C Library; see the file COPYING.LIB.  If not,
  16    write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  17    Boston, MA 02111-1307, USA.  */
  18
  19 #ifndef _FENV_H
  20 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
  21 #endif
  22
  23
  24 /* Define the bits representing the exception.
  25
  26    Note that these are the bit positions as defined by the OSF/1
  27    ieee_{get,set}_control_word interface and not by the hardware fpcr.
  28
  29    See the Alpha Architecture Handbook section 4.7.7.3 for details,
  30    but in summary, trap shadows mean the hardware register can acquire
  31    extra exception bits so for proper IEEE support the tracking has to
  32    be done in software -- in this case with kernel support.
  33
  34    As to why the system call interface isn't in the same format as
  35    the hardware register, only those crazy folks at DEC can tell you.  */
  36
  37 enum
  38   {
  39     FE_INEXACT =        1UL << 21,
  40 #define FE_INEXACT      FE_INEXACT
  41
  42     FE_UNDERFLOW =      1UL << 20,
  43 #define FE_UNDERFLOW    FE_UNDERFLOW
  44
  45     FE_OVERFLOW =       1UL << 19,
  46 #define FE_OVERFLOW     FE_OVERFLOW
  47
  48     FE_DIVBYZERO =      1UL << 18,
  49 #define FE_DIVBYZERO    FE_DIVBYZERO
  50
  51     FE_INVALID =        1UL << 17,
  52 #define FE_INVALID      FE_INVALID
  53
  54     FE_ALL_EXCEPT =
  55         (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
  56 #define FE_ALL_EXCEPT   FE_ALL_EXCEPT
  57   };
  58
  59
  60 /* Alpha chips support all four defined rouding modes.
  61
  62    Note that code must be compiled to use dynamic rounding (/d) instructions
  63    to see these changes.  For gcc this is -mfp-rounding-mode=d; for DEC cc
  64    this is -fprm d.  The default for both is static rounding to nearest.
  65
  66    These are shifted down 58 bits from the hardware fpcr because the
  67    functions are declared to take integers.  */
  68
  69 enum
  70   {
  71     FE_TOWARDZERO =     0,
  72 #define FE_TOWARDZERO   FE_TOWARDZERO
  73
  74     FE_DOWNWARD =       1,
  75 #define FE_DOWNWARD     FE_DOWNWARD
  76
  77     FE_TONEAREST =      2,
  78 #define FE_TONEAREST    FE_TONEAREST
  79
  80     FE_UPWARD =         3,
  81 #define FE_UPWARD       FE_UPWARD
  82   };
  83
  84
  85 /* Type representing exception flags.  */
  86 typedef unsigned long int fexcept_t;
  87
  88 /* Type representing floating-point environment.  */
  89 typedef unsigned long int fenv_t;
  90
  91 /* If the default argument is used we use this value.  Note that due to
  92    architecture-specified page mappings, no user-space pointer will ever
  93    have its two high bits set.  Co-opt one.  */
  94 #define FE_DFL_ENV      ((fenv_t *) 0x8800000000000000UL)
  95
  96 #ifdef __USE_GNU
  97 /* Floating-point environment where none of the exceptions are masked.  */
  98 # define FE_NOMASK_ENV  ((fenv_t *) 0x880000000000003eUL)
  99 #endif
 100
 101 /* The system calls to talk to the kernel's FP code.  */
 102 extern unsigned long int __ieee_get_fp_control __P ((void));
 103 extern void __ieee_set_fp_control __P ((unsigned long int __value));