sysdeps/standalone/i960/i960ca.h

   1 /* Copyright (C) 1994 Free Software Foundation, Inc.
   2    Contributed by Joel Sherrill (jsherril@redstone-emh2.army.mil),
   3      On-Line Applications Research Corporation.
   4
   5 This file is part of the GNU C Library.
   6
   7 The GNU C Library is free software; you can redistribute it and/or
   8 modify it under the terms of the GNU Library General Public License as
   9 published by the Free Software Foundation; either version 2 of the
  10 License, or (at your option) any later version.
  11
  12 The GNU C Library is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 Library General Public License for more details.
  16
  17 You should have received a copy of the GNU Library General Public
  18 License along with the GNU C Library; see the file COPYING.LIB.  If
  19 not, write to the Free Software Foundation, Inc., 675 Mass Ave,
  20 Cambridge, MA 02139, USA.  */
  21
  22 /* i960ca.h
  23  *
  24  *  This file contains macros which are used to access i80960CA
  25  *  registers which are not addressable by C.  The functions
  26  *  in this file sould be useful to the developer of target
  27  *  specific code.
  28  */
  29
  30 #ifndef i960ca_h__
  31 #define i960ca_h__
  32
  33 typedef unsigned char   unsigned8;
  34 typedef unsigned short  unsigned16;
  35 typedef unsigned int    unsigned32;
  36
  37 /*
  38  *  Intel i80960CA Processor Control Block
  39  */
  40
  41 struct i80960ca_prcb {
  42   unsigned32          *fault_tbl;     /* fault table base address     */
  43   struct i80960ca_ctltbl
  44                       *control_tbl;   /* control table base address   */
  45   unsigned32           initial_ac;    /* AC register initial value    */
  46   unsigned32           fault_config;  /* fault configuration word     */
  47   void                *intr_tbl;      /* interrupt table base address */
  48   void                *sys_proc_tbl;  /* system procedure table       */
  49                                       /*   base address               */
  50   unsigned32           reserved;      /* reserved                     */
  51   unsigned32          *intr_stack;    /* interrupt stack pointer      */
  52   unsigned32           ins_cache_cfg; /* instruction cache            */
  53                                       /*   configuration word         */
  54   unsigned32           reg_cache_cfg; /* register cache               */
  55                                       /*   configuration word         */
  56 };
  57
  58 /*
  59  *  Intel i80960CA Control Table
  60  */
  61
  62 struct i80960ca_ctltbl {
  63                             /* Control Group 0 */
  64   unsigned32       ipb0;              /* IP breakpoint 0 */
  65   unsigned32       ipb1;              /* IP breakpoint 1 */
  66   unsigned32       dab0;              /* data address breakpoint 0 */
  67   unsigned32       dab1;              /* data address breakpoint 1 */
  68                             /* Control Group 1 */
  69   unsigned32       imap0;             /* interrupt map 0 */
  70   unsigned32       imap1;             /* interrupt map 1 */
  71   unsigned32       imap2;             /* interrupt map 2 */
  72   unsigned32       icon;              /* interrupt control */
  73                             /* Control Group 2 */
  74   unsigned32       mcon0;             /* memory region 0 configuration */
  75   unsigned32       mcon1;             /* memory region 1 configuration */
  76   unsigned32       mcon2;             /* memory region 2 configuration */
  77   unsigned32       mcon3;             /* memory region 3 configuration */
  78                             /* Control Group 3 */
  79   unsigned32       mcon4;             /* memory region 4 configuration */
  80   unsigned32       mcon5;             /* memory region 5 configuration */
  81   unsigned32       mcon6;             /* memory region 6 configuration */
  82   unsigned32       mcon7;             /* memory region 7 configuration */
  83                             /* Control Group 4 */
  84   unsigned32       mcon8;             /* memory region 8 configuration */
  85   unsigned32       mcon9;             /* memory region 9 configuration */
  86   unsigned32       mcon10;            /* memory region 10 configuration */
  87   unsigned32       mcon11;            /* memory region 11 configuration */
  88                             /* Control Group 5 */
  89   unsigned32       mcon12;            /* memory region 12 configuration */
  90   unsigned32       mcon13;            /* memory region 13 configuration */
  91   unsigned32       mcon14;            /* memory region 14 configuration */
  92   unsigned32       mcon15;            /* memory region 15 configuration */
  93                             /* Control Group 6 */
  94   unsigned32       bpcon;             /* breakpoint control */
  95   unsigned32       tc;                /* trace control */
  96   unsigned32       bcon;              /* bus configuration control */
  97   unsigned32       reserved;          /* reserved */
  98 };
  99
 100 #define disable_intr( oldlevel ) \
 101   { (oldlevel) = 0x1f0000; \
 102     asm volatile ( "modpc   0,%1,%1" \
 103                        : "=d" ((oldlevel)) \
 104                        : "0"  ((oldlevel)) ); \
 105   }
 106
 107 #define enable_intr( oldlevel ) \
 108   { unsigned32 _mask = 0x1f0000; \
 109     asm volatile ( "modpc   0,%0,%1" \
 110                        : "=d" (_mask), "=d" ((oldlevel)) \
 111                        : "0"  (_mask), "1"  ((oldlevel)) ); \
 112   }
 113
 114 #define flash_intr( oldlevel ) \
 115   { unsigned32 _mask = 0x1f0000; \
 116     asm volatile ( "modpc   0,%0,%1 ; \
 117                     mov     %0,%1 ; \
 118                     modpc   0,%0,%1"  \
 119                        : "=d" (_mask), "=d" ((oldlevel)) \
 120                        : "0"  (_mask), "1"  ((oldlevel)) ); \
 121   }
 122
 123 #define atomic_modify( mask, addr, prev ) \
 124  { register unsigned32  _mask = (mask); \
 125    register unsigned32 *_addr = (unsigned32 *)(addr); \
 126    asm volatile( "atmod  %0,%1,%1" \
 127                   : "=d" (_addr), "=d" (_mask) \
 128                   : "0"  (_addr), "1"  (_mask) ); \
 129    (prev) = _mask; \
 130  }
 131
 132 #define delay( microseconds ) \
 133   { register unsigned32 _delay=(microseconds); \
 134     register unsigned32 _tmp; \
 135     asm volatile( "delay0: \
 136                      remo      3,31,%0 ; \
 137                      cmpo      0,%0 ; \
 138                      subo      1,%1,%1 ; \
 139                      cmpobne.t 0,%1,delay0 " \
 140                   : "=d" (_tmp), "=d" (_delay) \
 141                   : "0"  (_tmp), "1"  (_delay) ); \
 142   }
 143
 144 #define enable_tracing() \
 145  { register unsigned32 _pc = 0x1; \
 146    asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
 147  }
 148
 149 #define unmask_intr( xint ) \
 150  { register unsigned32 _mask= (1<<(xint)); \
 151    asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
 152  }
 153
 154 #define mask_intr( xint ) \
 155  { register unsigned32 _mask= (1<<(xint)); \
 156    asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
 157  }
 158
 159 #define clear_intr( xint ) \
 160  { register unsigned32 _xint=(xint); \
 161    asm volatile( "loop_til_cleared:
 162                     clrbit %0,sf0,sf0 ; \
 163                     bbs    %0,sf0,loop_til_cleared" \
 164                   : "=d" (_xint) : "0" (_xint) ); \
 165  }
 166
 167 #define reload_ctl_group( group ) \
 168  { register int _cmd = ((group)|0x400) ; \
 169    asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
 170  }
 171
 172 #define cause_intr( intr ) \
 173  { register int _intr = (intr); \
 174    asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
 175  }
 176
 177 #define soft_reset( prcb ) \
 178  { register struct i80960ca_prcb *_prcb = (prcb); \
 179    register unsigned32         *_next=0; \
 180    register unsigned32          _cmd  = 0x30000; \
 181    asm volatile( "lda    next,%1; \
 182                   sysctl %0,%1,%2; \
 183             next: mov    g0,g0" \
 184                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
 185                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
 186  }
 187
 188 static inline unsigned32 pend_intrs()
 189 { register unsigned32 _intr=0;
 190   asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
 191   return ( _intr );
 192 }
 193
 194 static inline unsigned32 mask_intrs()
 195 { register unsigned32 _intr=0;
 196   asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
 197   return( _intr );
 198 }
 199
 200 static inline unsigned32 get_fp()
 201 { register unsigned32 _fp=0;
 202   asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
 203   return ( _fp );
 204 }
 205
 206 #endif
 207 /* end of include file */