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[gdb.git] / include / opcode / mips.h
blob6ddc9d0ef785d571b1b0cdfcf26fb9004b43ee13
1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2008
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
7
8 This file is part of GDB, GAS, and the GNU binutils.
9
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version
13 1, or (at your option) any later version.
14
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
23
24 #ifndef _MIPS_H_
25 #define _MIPS_H_
26
27 /* These are bit masks and shift counts to use to access the various
28 fields of an instruction. To retrieve the X field of an
29 instruction, use the expression
30 (i >> OP_SH_X) & OP_MASK_X
31 To set the same field (to j), use
32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
33
34 Make sure you use fields that are appropriate for the instruction,
35 of course.
36
37 The 'i' format uses OP, RS, RT and IMMEDIATE.
38
39 The 'j' format uses OP and TARGET.
40
41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
42
43 The 'b' format uses OP, RS, RT and DELTA.
44
45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
46
47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
48
49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
50 breakpoint instruction are not defined; Kane says the breakpoint
51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
52 only use ten bits). An optional two-operand form of break/sdbbp
53 allows the lower ten bits to be set too, and MIPS32 and later
54 architectures allow 20 bits to be set with a signal operand
55 (using CODE20).
56
57 The syscall instruction uses CODE20.
58
59 The general coprocessor instructions use COPZ. */
60
61 #define OP_MASK_OP 0x3f
62 #define OP_SH_OP 26
63 #define OP_MASK_RS 0x1f
64 #define OP_SH_RS 21
65 #define OP_MASK_FR 0x1f
66 #define OP_SH_FR 21
67 #define OP_MASK_FMT 0x1f
68 #define OP_SH_FMT 21
69 #define OP_MASK_BCC 0x7
70 #define OP_SH_BCC 18
71 #define OP_MASK_CODE 0x3ff
72 #define OP_SH_CODE 16
73 #define OP_MASK_CODE2 0x3ff
74 #define OP_SH_CODE2 6
75 #define OP_MASK_RT 0x1f
76 #define OP_SH_RT 16
77 #define OP_MASK_FT 0x1f
78 #define OP_SH_FT 16
79 #define OP_MASK_CACHE 0x1f
80 #define OP_SH_CACHE 16
81 #define OP_MASK_RD 0x1f
82 #define OP_SH_RD 11
83 #define OP_MASK_FS 0x1f
84 #define OP_SH_FS 11
85 #define OP_MASK_PREFX 0x1f
86 #define OP_SH_PREFX 11
87 #define OP_MASK_CCC 0x7
88 #define OP_SH_CCC 8
89 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
90 #define OP_SH_CODE20 6
91 #define OP_MASK_SHAMT 0x1f
92 #define OP_SH_SHAMT 6
93 #define OP_MASK_FD 0x1f
94 #define OP_SH_FD 6
95 #define OP_MASK_TARGET 0x3ffffff
96 #define OP_SH_TARGET 0
97 #define OP_MASK_COPZ 0x1ffffff
98 #define OP_SH_COPZ 0
99 #define OP_MASK_IMMEDIATE 0xffff
100 #define OP_SH_IMMEDIATE 0
101 #define OP_MASK_DELTA 0xffff
102 #define OP_SH_DELTA 0
103 #define OP_MASK_FUNCT 0x3f
104 #define OP_SH_FUNCT 0
105 #define OP_MASK_SPEC 0x3f
106 #define OP_SH_SPEC 0
107 #define OP_SH_LOCC 8 /* FP condition code. */
108 #define OP_SH_HICC 18 /* FP condition code. */
109 #define OP_MASK_CC 0x7
110 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
111 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
112 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
113 #define OP_MASK_COP1SPEC 0xf
114 #define OP_MASK_COP1SCLR 0x4
115 #define OP_MASK_COP1CMP 0x3
116 #define OP_SH_COP1CMP 4
117 #define OP_SH_FORMAT 21 /* FP short format field. */
118 #define OP_MASK_FORMAT 0x7
119 #define OP_SH_TRUE 16
120 #define OP_MASK_TRUE 0x1
121 #define OP_SH_GE 17
122 #define OP_MASK_GE 0x01
123 #define OP_SH_UNSIGNED 16
124 #define OP_MASK_UNSIGNED 0x1
125 #define OP_SH_HINT 16
126 #define OP_MASK_HINT 0x1f
127 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
128 #define OP_MASK_MMI 0x3f
129 #define OP_SH_MMISUB 6
130 #define OP_MASK_MMISUB 0x1f
131 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
132 #define OP_SH_PERFREG 1
133 #define OP_SH_SEL 0 /* Coprocessor select field. */
134 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
135 #define OP_SH_CODE19 6 /* 19 bit wait code. */
136 #define OP_MASK_CODE19 0x7ffff
137 #define OP_SH_ALN 21
138 #define OP_MASK_ALN 0x7
139 #define OP_SH_VSEL 21
140 #define OP_MASK_VSEL 0x1f
141 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
142 but 0x8-0xf don't select bytes. */
143 #define OP_SH_VECBYTE 22
144 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
145 #define OP_SH_VECALIGN 21
146 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
147 #define OP_SH_INSMSB 11
148 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
149 #define OP_SH_EXTMSBD 11
150
151 /* MIPS DSP ASE */
152 #define OP_SH_DSPACC 11
153 #define OP_MASK_DSPACC 0x3
154 #define OP_SH_DSPACC_S 21
155 #define OP_MASK_DSPACC_S 0x3
156 #define OP_SH_DSPSFT 20
157 #define OP_MASK_DSPSFT 0x3f
158 #define OP_SH_DSPSFT_7 19
159 #define OP_MASK_DSPSFT_7 0x7f
160 #define OP_SH_SA3 21
161 #define OP_MASK_SA3 0x7
162 #define OP_SH_SA4 21
163 #define OP_MASK_SA4 0xf
164 #define OP_SH_IMM8 16
165 #define OP_MASK_IMM8 0xff
166 #define OP_SH_IMM10 16
167 #define OP_MASK_IMM10 0x3ff
168 #define OP_SH_WRDSP 11
169 #define OP_MASK_WRDSP 0x3f
170 #define OP_SH_RDDSP 16
171 #define OP_MASK_RDDSP 0x3f
172 #define OP_SH_BP 11
173 #define OP_MASK_BP 0x3
174
175 /* MIPS MT ASE */
176 #define OP_SH_MT_U 5
177 #define OP_MASK_MT_U 0x1
178 #define OP_SH_MT_H 4
179 #define OP_MASK_MT_H 0x1
180 #define OP_SH_MTACC_T 18
181 #define OP_MASK_MTACC_T 0x3
182 #define OP_SH_MTACC_D 13
183 #define OP_MASK_MTACC_D 0x3
184
185 #define OP_OP_COP0 0x10
186 #define OP_OP_COP1 0x11
187 #define OP_OP_COP2 0x12
188 #define OP_OP_COP3 0x13
189 #define OP_OP_LWC1 0x31
190 #define OP_OP_LWC2 0x32
191 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
192 #define OP_OP_LDC1 0x35
193 #define OP_OP_LDC2 0x36
194 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
195 #define OP_OP_SWC1 0x39
196 #define OP_OP_SWC2 0x3a
197 #define OP_OP_SWC3 0x3b
198 #define OP_OP_SDC1 0x3d
199 #define OP_OP_SDC2 0x3e
200 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
201
202 /* Values in the 'VSEL' field. */
203 #define MDMX_FMTSEL_IMM_QH 0x1d
204 #define MDMX_FMTSEL_IMM_OB 0x1e
205 #define MDMX_FMTSEL_VEC_QH 0x15
206 #define MDMX_FMTSEL_VEC_OB 0x16
207
208 /* UDI */
209 #define OP_SH_UDI1 6
210 #define OP_MASK_UDI1 0x1f
211 #define OP_SH_UDI2 6
212 #define OP_MASK_UDI2 0x3ff
213 #define OP_SH_UDI3 6
214 #define OP_MASK_UDI3 0x7fff
215 #define OP_SH_UDI4 6
216 #define OP_MASK_UDI4 0xfffff
217
218 /* This structure holds information for a particular instruction. */
219
220 struct mips_opcode
221 {
222 /* The name of the instruction. */
223 const char *name;
224 /* A string describing the arguments for this instruction. */
225 const char *args;
226 /* The basic opcode for the instruction. When assembling, this
227 opcode is modified by the arguments to produce the actual opcode
228 that is used. If pinfo is INSN_MACRO, then this is 0. */
229 unsigned long match;
230 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
231 relevant portions of the opcode when disassembling. If the
232 actual opcode anded with the match field equals the opcode field,
233 then we have found the correct instruction. If pinfo is
234 INSN_MACRO, then this field is the macro identifier. */
235 unsigned long mask;
236 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
237 of bits describing the instruction, notably any relevant hazard
238 information. */
239 unsigned long pinfo;
240 /* A collection of additional bits describing the instruction. */
241 unsigned long pinfo2;
242 /* A collection of bits describing the instruction sets of which this
243 instruction or macro is a member. */
244 unsigned long membership;
245 };
246
247 /* These are the characters which may appear in the args field of an
248 instruction. They appear in the order in which the fields appear
249 when the instruction is used. Commas and parentheses in the args
250 string are ignored when assembling, and written into the output
251 when disassembling.
252
253 Each of these characters corresponds to a mask field defined above.
254
255 "<" 5 bit shift amount (OP_*_SHAMT)
256 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
257 "a" 26 bit target address (OP_*_TARGET)
258 "b" 5 bit base register (OP_*_RS)
259 "c" 10 bit breakpoint code (OP_*_CODE)
260 "d" 5 bit destination register specifier (OP_*_RD)
261 "h" 5 bit prefx hint (OP_*_PREFX)
262 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
263 "j" 16 bit signed immediate (OP_*_DELTA)
264 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
265 Also used for immediate operands in vr5400 vector insns.
266 "o" 16 bit signed offset (OP_*_DELTA)
267 "p" 16 bit PC relative branch target address (OP_*_DELTA)
268 "q" 10 bit extra breakpoint code (OP_*_CODE2)
269 "r" 5 bit same register used as both source and target (OP_*_RS)
270 "s" 5 bit source register specifier (OP_*_RS)
271 "t" 5 bit target register (OP_*_RT)
272 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
273 "v" 5 bit same register used as both source and destination (OP_*_RS)
274 "w" 5 bit same register used as both target and destination (OP_*_RT)
275 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
276 (used by clo and clz)
277 "C" 25 bit coprocessor function code (OP_*_COPZ)
278 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
279 "J" 19 bit wait function code (OP_*_CODE19)
280 "x" accept and ignore register name
281 "z" must be zero register
282 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
283 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
284 LSB (OP_*_SHAMT).
285 Enforces: 0 <= pos < 32.
286 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
287 Requires that "+A" or "+E" occur first to set position.
288 Enforces: 0 < (pos+size) <= 32.
289 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
290 Requires that "+A" or "+E" occur first to set position.
291 Enforces: 0 < (pos+size) <= 32.
292 (Also used by "dext" w/ different limits, but limits for
293 that are checked by the M_DEXT macro.)
294 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
295 Enforces: 32 <= pos < 64.
296 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
297 Requires that "+A" or "+E" occur first to set position.
298 Enforces: 32 < (pos+size) <= 64.
299 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
300 Requires that "+A" or "+E" occur first to set position.
301 Enforces: 32 < (pos+size) <= 64.
302 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
303 Requires that "+A" or "+E" occur first to set position.
304 Enforces: 32 < (pos+size) <= 64.
305
306 Floating point instructions:
307 "D" 5 bit destination register (OP_*_FD)
308 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
309 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
310 "S" 5 bit fs source 1 register (OP_*_FS)
311 "T" 5 bit ft source 2 register (OP_*_FT)
312 "R" 5 bit fr source 3 register (OP_*_FR)
313 "V" 5 bit same register used as floating source and destination (OP_*_FS)
314 "W" 5 bit same register used as floating target and destination (OP_*_FT)
315
316 Coprocessor instructions:
317 "E" 5 bit target register (OP_*_RT)
318 "G" 5 bit destination register (OP_*_RD)
319 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
320 "P" 5 bit performance-monitor register (OP_*_PERFREG)
321 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
322 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
323 see also "k" above
324 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
325 for pretty-printing in disassembly only.
326
327 Macro instructions:
328 "A" General 32 bit expression
329 "I" 32 bit immediate (value placed in imm_expr).
330 "+I" 32 bit immediate (value placed in imm2_expr).
331 "F" 64 bit floating point constant in .rdata
332 "L" 64 bit floating point constant in .lit8
333 "f" 32 bit floating point constant
334 "l" 32 bit floating point constant in .lit4
335
336 MDMX instruction operands (note that while these use the FP register
337 fields, they accept both $fN and $vN names for the registers):
338 "O" MDMX alignment offset (OP_*_ALN)
339 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
340 "X" MDMX destination register (OP_*_FD)
341 "Y" MDMX source register (OP_*_FS)
342 "Z" MDMX source register (OP_*_FT)
343
344 DSP ASE usage:
345 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
346 "3" 3 bit unsigned immediate (OP_*_SA3)
347 "4" 4 bit unsigned immediate (OP_*_SA4)
348 "5" 8 bit unsigned immediate (OP_*_IMM8)
349 "6" 5 bit unsigned immediate (OP_*_RS)
350 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
351 "8" 6 bit unsigned immediate (OP_*_WRDSP)
352 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
353 "0" 6 bit signed immediate (OP_*_DSPSFT)
354 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
355 "'" 6 bit unsigned immediate (OP_*_RDDSP)
356 "@" 10 bit signed immediate (OP_*_IMM10)
357
358 MT ASE usage:
359 "!" 1 bit usermode flag (OP_*_MT_U)
360 "$" 1 bit load high flag (OP_*_MT_H)
361 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
362 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
363 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
364 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
365 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
366
367 UDI immediates:
368 "+1" UDI immediate bits 6-10
369 "+2" UDI immediate bits 6-15
370 "+3" UDI immediate bits 6-20
371 "+4" UDI immediate bits 6-25
372
373 Other:
374 "()" parens surrounding optional value
375 "," separates operands
376 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
377 "+" Start of extension sequence.
378
379 Characters used so far, for quick reference when adding more:
380 "234567890"
381 "%[]<>(),+:'@!$*&"
382 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
383 "abcdefghijklopqrstuvwxz"
384
385 Extension character sequences used so far ("+" followed by the
386 following), for quick reference when adding more:
387 "1234"
388 "ABCDEFGHIT"
389 "t"
390 */
391
392 /* These are the bits which may be set in the pinfo field of an
393 instructions, if it is not equal to INSN_MACRO. */
394
395 /* Modifies the general purpose register in OP_*_RD. */
396 #define INSN_WRITE_GPR_D 0x00000001
397 /* Modifies the general purpose register in OP_*_RT. */
398 #define INSN_WRITE_GPR_T 0x00000002
399 /* Modifies general purpose register 31. */
400 #define INSN_WRITE_GPR_31 0x00000004
401 /* Modifies the floating point register in OP_*_FD. */
402 #define INSN_WRITE_FPR_D 0x00000008
403 /* Modifies the floating point register in OP_*_FS. */
404 #define INSN_WRITE_FPR_S 0x00000010
405 /* Modifies the floating point register in OP_*_FT. */
406 #define INSN_WRITE_FPR_T 0x00000020
407 /* Reads the general purpose register in OP_*_RS. */
408 #define INSN_READ_GPR_S 0x00000040
409 /* Reads the general purpose register in OP_*_RT. */
410 #define INSN_READ_GPR_T 0x00000080
411 /* Reads the floating point register in OP_*_FS. */
412 #define INSN_READ_FPR_S 0x00000100
413 /* Reads the floating point register in OP_*_FT. */
414 #define INSN_READ_FPR_T 0x00000200
415 /* Reads the floating point register in OP_*_FR. */
416 #define INSN_READ_FPR_R 0x00000400
417 /* Modifies coprocessor condition code. */
418 #define INSN_WRITE_COND_CODE 0x00000800
419 /* Reads coprocessor condition code. */
420 #define INSN_READ_COND_CODE 0x00001000
421 /* TLB operation. */
422 #define INSN_TLB 0x00002000
423 /* Reads coprocessor register other than floating point register. */
424 #define INSN_COP 0x00004000
425 /* Instruction loads value from memory, requiring delay. */
426 #define INSN_LOAD_MEMORY_DELAY 0x00008000
427 /* Instruction loads value from coprocessor, requiring delay. */
428 #define INSN_LOAD_COPROC_DELAY 0x00010000
429 /* Instruction has unconditional branch delay slot. */
430 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
431 /* Instruction has conditional branch delay slot. */
432 #define INSN_COND_BRANCH_DELAY 0x00040000
433 /* Conditional branch likely: if branch not taken, insn nullified. */
434 #define INSN_COND_BRANCH_LIKELY 0x00080000
435 /* Moves to coprocessor register, requiring delay. */
436 #define INSN_COPROC_MOVE_DELAY 0x00100000
437 /* Loads coprocessor register from memory, requiring delay. */
438 #define INSN_COPROC_MEMORY_DELAY 0x00200000
439 /* Reads the HI register. */
440 #define INSN_READ_HI 0x00400000
441 /* Reads the LO register. */
442 #define INSN_READ_LO 0x00800000
443 /* Modifies the HI register. */
444 #define INSN_WRITE_HI 0x01000000
445 /* Modifies the LO register. */
446 #define INSN_WRITE_LO 0x02000000
447 /* Takes a trap (easier to keep out of delay slot). */
448 #define INSN_TRAP 0x04000000
449 /* Instruction stores value into memory. */
450 #define INSN_STORE_MEMORY 0x08000000
451 /* Instruction uses single precision floating point. */
452 #define FP_S 0x10000000
453 /* Instruction uses double precision floating point. */
454 #define FP_D 0x20000000
455 /* Instruction is part of the tx39's integer multiply family. */
456 #define INSN_MULT 0x40000000
457 /* Instruction synchronize shared memory. */
458 #define INSN_SYNC 0x80000000
459
460 /* These are the bits which may be set in the pinfo2 field of an
461 instruction. */
462
463 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
464 #define INSN2_ALIAS 0x00000001
465 /* Instruction reads MDMX accumulator. */
466 #define INSN2_READ_MDMX_ACC 0x00000002
467 /* Instruction writes MDMX accumulator. */
468 #define INSN2_WRITE_MDMX_ACC 0x00000004
469
470 /* Instruction is actually a macro. It should be ignored by the
471 disassembler, and requires special treatment by the assembler. */
472 #define INSN_MACRO 0xffffffff
473
474 /* Masks used to mark instructions to indicate which MIPS ISA level
475 they were introduced in. INSN_ISA_MASK masks an enumeration that
476 specifies the base ISA level(s). The remainder of a 32-bit
477 word constructed using these macros is a bitmask of the remaining
478 INSN_* values below. */
479
480 #define INSN_ISA_MASK 0x0000000ful
481
482 /* We cannot start at zero due to ISA_UNKNOWN below. */
483 #define INSN_ISA1 1
484 #define INSN_ISA2 2
485 #define INSN_ISA3 3
486 #define INSN_ISA4 4
487 #define INSN_ISA5 5
488 #define INSN_ISA32 6
489 #define INSN_ISA32R2 7
490 #define INSN_ISA64 8
491 #define INSN_ISA64R2 9
492 /* Below this point the INSN_* values correspond to combinations of ISAs.
493 They are only for use in the opcodes table to indicate membership of
494 a combination of ISAs that cannot be expressed using the usual inclusion
495 ordering on the above INSN_* values. */
496 #define INSN_ISA3_32 10
497 #define INSN_ISA3_32R2 11
498 #define INSN_ISA4_32 12
499 #define INSN_ISA4_32R2 13
500 #define INSN_ISA5_32R2 14
501
502 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
503 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
504 this table describes whether at least one of the ISAs described by X
505 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
506 a particular core and X as the ISA level(s) at which a certain instruction
507 is defined.) The ISA(s) described by X is/are implemented by Y iff
508 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
509 is non-zero. */
510 static const unsigned int mips_isa_table[] =
511 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
512
513 /* Masks used for Chip specific instructions. */
514 #define INSN_CHIP_MASK 0xc3ff0800
515
516 /* Cavium Networks Octeon instructions. */
517 #define INSN_OCTEON 0x00000800
518
519 /* Masks used for MIPS-defined ASEs. */
520 #define INSN_ASE_MASK 0x3c00f000
521
522 /* DSP ASE */
523 #define INSN_DSP 0x00001000
524 #define INSN_DSP64 0x00002000
525 /* MIPS 16 ASE */
526 #define INSN_MIPS16 0x00004000
527 /* MIPS-3D ASE */
528 #define INSN_MIPS3D 0x00008000
529
530 /* MIPS R4650 instruction. */
531 #define INSN_4650 0x00010000
532 /* LSI R4010 instruction. */
533 #define INSN_4010 0x00020000
534 /* NEC VR4100 instruction. */
535 #define INSN_4100 0x00040000
536 /* Toshiba R3900 instruction. */
537 #define INSN_3900 0x00080000
538 /* MIPS R10000 instruction. */
539 #define INSN_10000 0x00100000
540 /* Broadcom SB-1 instruction. */
541 #define INSN_SB1 0x00200000
542 /* NEC VR4111/VR4181 instruction. */
543 #define INSN_4111 0x00400000
544 /* NEC VR4120 instruction. */
545 #define INSN_4120 0x00800000
546 /* NEC VR5400 instruction. */
547 #define INSN_5400 0x01000000
548 /* NEC VR5500 instruction. */
549 #define INSN_5500 0x02000000
550
551 /* MDMX ASE */
552 #define INSN_MDMX 0x04000000
553 /* MT ASE */
554 #define INSN_MT 0x08000000
555 /* SmartMIPS ASE */
556 #define INSN_SMARTMIPS 0x10000000
557 /* DSP R2 ASE */
558 #define INSN_DSPR2 0x20000000
559 /* ST Microelectronics Loongson 2E. */
560 #define INSN_LOONGSON_2E 0x40000000
561 /* ST Microelectronics Loongson 2F. */
562 #define INSN_LOONGSON_2F 0x80000000
563
564 /* MIPS ISA defines, use instead of hardcoding ISA level. */
565
566 #define ISA_UNKNOWN 0 /* Gas internal use. */
567 #define ISA_MIPS1 INSN_ISA1
568 #define ISA_MIPS2 INSN_ISA2
569 #define ISA_MIPS3 INSN_ISA3
570 #define ISA_MIPS4 INSN_ISA4
571 #define ISA_MIPS5 INSN_ISA5
572
573 #define ISA_MIPS32 INSN_ISA32
574 #define ISA_MIPS64 INSN_ISA64
575
576 #define ISA_MIPS32R2 INSN_ISA32R2
577 #define ISA_MIPS64R2 INSN_ISA64R2
578
579
580 /* CPU defines, use instead of hardcoding processor number. Keep this
581 in sync with bfd/archures.c in order for machine selection to work. */
582 #define CPU_UNKNOWN 0 /* Gas internal use. */
583 #define CPU_R3000 3000
584 #define CPU_R3900 3900
585 #define CPU_R4000 4000
586 #define CPU_R4010 4010
587 #define CPU_VR4100 4100
588 #define CPU_R4111 4111
589 #define CPU_VR4120 4120
590 #define CPU_R4300 4300
591 #define CPU_R4400 4400
592 #define CPU_R4600 4600
593 #define CPU_R4650 4650
594 #define CPU_R5000 5000
595 #define CPU_VR5400 5400
596 #define CPU_VR5500 5500
597 #define CPU_R6000 6000
598 #define CPU_RM7000 7000
599 #define CPU_R8000 8000
600 #define CPU_RM9000 9000
601 #define CPU_R10000 10000
602 #define CPU_R12000 12000
603 #define CPU_MIPS16 16
604 #define CPU_MIPS32 32
605 #define CPU_MIPS32R2 33
606 #define CPU_MIPS5 5
607 #define CPU_MIPS64 64
608 #define CPU_MIPS64R2 65
609 #define CPU_SB1 12310201 /* octal 'SB', 01. */
610 #define CPU_LOONGSON_2E 3001
611 #define CPU_LOONGSON_2F 3002
612 #define CPU_OCTEON 6501
613
614 /* Test for membership in an ISA including chip specific ISAs. INSN
615 is pointer to an element of the opcode table; ISA is the specified
616 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
617 test, or zero if no CPU specific ISA test is desired. */
618
619 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
620 (((isa & INSN_ISA_MASK) != 0 \
621 && ((insn)->membership & INSN_ISA_MASK) != 0 \
622 && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
623 (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
624 || ((isa & ~INSN_ISA_MASK) \
625 & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
626 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
627 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
628 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
629 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
630 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
631 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
632 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
633 && ((insn)->membership & INSN_10000) != 0) \
634 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
635 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
636 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
637 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
638 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
639 || (cpu == CPU_LOONGSON_2E \
640 && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
641 || (cpu == CPU_LOONGSON_2F \
642 && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
643 || (cpu == CPU_OCTEON \
644 && ((insn)->membership & INSN_OCTEON) != 0) \
645 || 0) /* Please keep this term for easier source merging. */
646
647 /* This is a list of macro expanded instructions.
648
649 _I appended means immediate
650 _A appended means address
651 _AB appended means address with base register
652 _D appended means 64 bit floating point constant
653 _S appended means 32 bit floating point constant. */
654
655 enum
656 {
657 M_ABS,
658 M_ADD_I,
659 M_ADDU_I,
660 M_AND_I,
661 M_BALIGN,
662 M_BEQ,
663 M_BEQ_I,
664 M_BEQL_I,
665 M_BGE,
666 M_BGEL,
667 M_BGE_I,
668 M_BGEL_I,
669 M_BGEU,
670 M_BGEUL,
671 M_BGEU_I,
672 M_BGEUL_I,
673 M_BGT,
674 M_BGTL,
675 M_BGT_I,
676 M_BGTL_I,
677 M_BGTU,
678 M_BGTUL,
679 M_BGTU_I,
680 M_BGTUL_I,
681 M_BLE,
682 M_BLEL,
683 M_BLE_I,
684 M_BLEL_I,
685 M_BLEU,
686 M_BLEUL,
687 M_BLEU_I,
688 M_BLEUL_I,
689 M_BLT,
690 M_BLTL,
691 M_BLT_I,
692 M_BLTL_I,
693 M_BLTU,
694 M_BLTUL,
695 M_BLTU_I,
696 M_BLTUL_I,
697 M_BNE,
698 M_BNE_I,
699 M_BNEL_I,
700 M_CACHE_AB,
701 M_DABS,
702 M_DADD_I,
703 M_DADDU_I,
704 M_DDIV_3,
705 M_DDIV_3I,
706 M_DDIVU_3,
707 M_DDIVU_3I,
708 M_DEXT,
709 M_DINS,
710 M_DIV_3,
711 M_DIV_3I,
712 M_DIVU_3,
713 M_DIVU_3I,
714 M_DLA_AB,
715 M_DLCA_AB,
716 M_DLI,
717 M_DMUL,
718 M_DMUL_I,
719 M_DMULO,
720 M_DMULO_I,
721 M_DMULOU,
722 M_DMULOU_I,
723 M_DREM_3,
724 M_DREM_3I,
725 M_DREMU_3,
726 M_DREMU_3I,
727 M_DSUB_I,
728 M_DSUBU_I,
729 M_DSUBU_I_2,
730 M_J_A,
731 M_JAL_1,
732 M_JAL_2,
733 M_JAL_A,
734 M_L_DOB,
735 M_L_DAB,
736 M_LA_AB,
737 M_LB_A,
738 M_LB_AB,
739 M_LBU_A,
740 M_LBU_AB,
741 M_LCA_AB,
742 M_LD_A,
743 M_LD_OB,
744 M_LD_AB,
745 M_LDC1_AB,
746 M_LDC2_AB,
747 M_LDC3_AB,
748 M_LDL_AB,
749 M_LDR_AB,
750 M_LH_A,
751 M_LH_AB,
752 M_LHU_A,
753 M_LHU_AB,
754 M_LI,
755 M_LI_D,
756 M_LI_DD,
757 M_LI_S,
758 M_LI_SS,
759 M_LL_AB,
760 M_LLD_AB,
761 M_LS_A,
762 M_LW_A,
763 M_LW_AB,
764 M_LWC0_A,
765 M_LWC0_AB,
766 M_LWC1_A,
767 M_LWC1_AB,
768 M_LWC2_A,
769 M_LWC2_AB,
770 M_LWC3_A,
771 M_LWC3_AB,
772 M_LWL_A,
773 M_LWL_AB,
774 M_LWR_A,
775 M_LWR_AB,
776 M_LWU_AB,
777 M_MOVE,
778 M_MUL,
779 M_MUL_I,
780 M_MULO,
781 M_MULO_I,
782 M_MULOU,
783 M_MULOU_I,
784 M_NOR_I,
785 M_OR_I,
786 M_REM_3,
787 M_REM_3I,
788 M_REMU_3,
789 M_REMU_3I,
790 M_DROL,
791 M_ROL,
792 M_DROL_I,
793 M_ROL_I,
794 M_DROR,
795 M_ROR,
796 M_DROR_I,
797 M_ROR_I,
798 M_S_DA,
799 M_S_DOB,
800 M_S_DAB,
801 M_S_S,
802 M_SC_AB,
803 M_SCD_AB,
804 M_SD_A,
805 M_SD_OB,
806 M_SD_AB,
807 M_SDC1_AB,
808 M_SDC2_AB,
809 M_SDC3_AB,
810 M_SDL_AB,
811 M_SDR_AB,
812 M_SEQ,
813 M_SEQ_I,
814 M_SGE,
815 M_SGE_I,
816 M_SGEU,
817 M_SGEU_I,
818 M_SGT,
819 M_SGT_I,
820 M_SGTU,
821 M_SGTU_I,
822 M_SLE,
823 M_SLE_I,
824 M_SLEU,
825 M_SLEU_I,
826 M_SLT_I,
827 M_SLTU_I,
828 M_SNE,
829 M_SNE_I,
830 M_SB_A,
831 M_SB_AB,
832 M_SH_A,
833 M_SH_AB,
834 M_SW_A,
835 M_SW_AB,
836 M_SWC0_A,
837 M_SWC0_AB,
838 M_SWC1_A,
839 M_SWC1_AB,
840 M_SWC2_A,
841 M_SWC2_AB,
842 M_SWC3_A,
843 M_SWC3_AB,
844 M_SWL_A,
845 M_SWL_AB,
846 M_SWR_A,
847 M_SWR_AB,
848 M_SUB_I,
849 M_SUBU_I,
850 M_SUBU_I_2,
851 M_TEQ_I,
852 M_TGE_I,
853 M_TGEU_I,
854 M_TLT_I,
855 M_TLTU_I,
856 M_TNE_I,
857 M_TRUNCWD,
858 M_TRUNCWS,
859 M_ULD,
860 M_ULD_A,
861 M_ULH,
862 M_ULH_A,
863 M_ULHU,
864 M_ULHU_A,
865 M_ULW,
866 M_ULW_A,
867 M_USH,
868 M_USH_A,
869 M_USW,
870 M_USW_A,
871 M_USD,
872 M_USD_A,
873 M_XOR_I,
874 M_COP0,
875 M_COP1,
876 M_COP2,
877 M_COP3,
878 M_NUM_MACROS
879 };
880
881
882 /* The order of overloaded instructions matters. Label arguments and
883 register arguments look the same. Instructions that can have either
884 for arguments must apear in the correct order in this table for the
885 assembler to pick the right one. In other words, entries with
886 immediate operands must apear after the same instruction with
887 registers.
888
889 Many instructions are short hand for other instructions (i.e., The
890 jal <register> instruction is short for jalr <register>). */
891
892 extern const struct mips_opcode mips_builtin_opcodes[];
893 extern const int bfd_mips_num_builtin_opcodes;
894 extern struct mips_opcode *mips_opcodes;
895 extern int bfd_mips_num_opcodes;
896 #define NUMOPCODES bfd_mips_num_opcodes
897
898 \f
899 /* The rest of this file adds definitions for the mips16 TinyRISC
900 processor. */
901
902 /* These are the bitmasks and shift counts used for the different
903 fields in the instruction formats. Other than OP, no masks are
904 provided for the fixed portions of an instruction, since they are
905 not needed.
906
907 The I format uses IMM11.
908
909 The RI format uses RX and IMM8.
910
911 The RR format uses RX, and RY.
912
913 The RRI format uses RX, RY, and IMM5.
914
915 The RRR format uses RX, RY, and RZ.
916
917 The RRI_A format uses RX, RY, and IMM4.
918
919 The SHIFT format uses RX, RY, and SHAMT.
920
921 The I8 format uses IMM8.
922
923 The I8_MOVR32 format uses RY and REGR32.
924
925 The IR_MOV32R format uses REG32R and MOV32Z.
926
927 The I64 format uses IMM8.
928
929 The RI64 format uses RY and IMM5.
930 */
931
932 #define MIPS16OP_MASK_OP 0x1f
933 #define MIPS16OP_SH_OP 11
934 #define MIPS16OP_MASK_IMM11 0x7ff
935 #define MIPS16OP_SH_IMM11 0
936 #define MIPS16OP_MASK_RX 0x7
937 #define MIPS16OP_SH_RX 8
938 #define MIPS16OP_MASK_IMM8 0xff
939 #define MIPS16OP_SH_IMM8 0
940 #define MIPS16OP_MASK_RY 0x7
941 #define MIPS16OP_SH_RY 5
942 #define MIPS16OP_MASK_IMM5 0x1f
943 #define MIPS16OP_SH_IMM5 0
944 #define MIPS16OP_MASK_RZ 0x7
945 #define MIPS16OP_SH_RZ 2
946 #define MIPS16OP_MASK_IMM4 0xf
947 #define MIPS16OP_SH_IMM4 0
948 #define MIPS16OP_MASK_REGR32 0x1f
949 #define MIPS16OP_SH_REGR32 0
950 #define MIPS16OP_MASK_REG32R 0x1f
951 #define MIPS16OP_SH_REG32R 3
952 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
953 #define MIPS16OP_MASK_MOVE32Z 0x7
954 #define MIPS16OP_SH_MOVE32Z 0
955 #define MIPS16OP_MASK_IMM6 0x3f
956 #define MIPS16OP_SH_IMM6 5
957
958 /* These are the characters which may appears in the args field of an
959 instruction. They appear in the order in which the fields appear
960 when the instruction is used. Commas and parentheses in the args
961 string are ignored when assembling, and written into the output
962 when disassembling.
963
964 "y" 3 bit register (MIPS16OP_*_RY)
965 "x" 3 bit register (MIPS16OP_*_RX)
966 "z" 3 bit register (MIPS16OP_*_RZ)
967 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
968 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
969 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
970 "0" zero register ($0)
971 "S" stack pointer ($sp or $29)
972 "P" program counter
973 "R" return address register ($ra or $31)
974 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
975 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
976 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
977 "a" 26 bit jump address
978 "e" 11 bit extension value
979 "l" register list for entry instruction
980 "L" register list for exit instruction
981
982 The remaining codes may be extended. Except as otherwise noted,
983 the full extended operand is a 16 bit signed value.
984 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
985 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
986 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
987 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
988 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
989 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
990 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
991 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
992 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
993 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
994 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
995 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
996 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
997 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
998 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
999 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1000 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1001 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1002 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1003 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1004 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1005 "m" 7 bit register list for save instruction (18 bit extended)
1006 "M" 7 bit register list for restore instruction (18 bit extended)
1007 */
1008
1009 /* Save/restore encoding for the args field when all 4 registers are
1010 either saved as arguments or saved/restored as statics. */
1011 #define MIPS16_ALL_ARGS 0xe
1012 #define MIPS16_ALL_STATICS 0xb
1013
1014 /* For the mips16, we use the same opcode table format and a few of
1015 the same flags. However, most of the flags are different. */
1016
1017 /* Modifies the register in MIPS16OP_*_RX. */
1018 #define MIPS16_INSN_WRITE_X 0x00000001
1019 /* Modifies the register in MIPS16OP_*_RY. */
1020 #define MIPS16_INSN_WRITE_Y 0x00000002
1021 /* Modifies the register in MIPS16OP_*_RZ. */
1022 #define MIPS16_INSN_WRITE_Z 0x00000004
1023 /* Modifies the T ($24) register. */
1024 #define MIPS16_INSN_WRITE_T 0x00000008
1025 /* Modifies the SP ($29) register. */
1026 #define MIPS16_INSN_WRITE_SP 0x00000010
1027 /* Modifies the RA ($31) register. */
1028 #define MIPS16_INSN_WRITE_31 0x00000020
1029 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1030 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1031 /* Reads the register in MIPS16OP_*_RX. */
1032 #define MIPS16_INSN_READ_X 0x00000080
1033 /* Reads the register in MIPS16OP_*_RY. */
1034 #define MIPS16_INSN_READ_Y 0x00000100
1035 /* Reads the register in MIPS16OP_*_MOVE32Z. */
1036 #define MIPS16_INSN_READ_Z 0x00000200
1037 /* Reads the T ($24) register. */
1038 #define MIPS16_INSN_READ_T 0x00000400
1039 /* Reads the SP ($29) register. */
1040 #define MIPS16_INSN_READ_SP 0x00000800
1041 /* Reads the RA ($31) register. */
1042 #define MIPS16_INSN_READ_31 0x00001000
1043 /* Reads the program counter. */
1044 #define MIPS16_INSN_READ_PC 0x00002000
1045 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
1046 #define MIPS16_INSN_READ_GPR_X 0x00004000
1047 /* Is a branch insn. */
1048 #define MIPS16_INSN_BRANCH 0x00010000
1049
1050 /* The following flags have the same value for the mips16 opcode
1051 table:
1052 INSN_UNCOND_BRANCH_DELAY
1053 INSN_COND_BRANCH_DELAY
1054 INSN_COND_BRANCH_LIKELY (never used)
1055 INSN_READ_HI
1056 INSN_READ_LO
1057 INSN_WRITE_HI
1058 INSN_WRITE_LO
1059 INSN_TRAP
1060 INSN_ISA3
1061 */
1062
1063 extern const struct mips_opcode mips16_opcodes[];
1064 extern const int bfd_mips16_num_opcodes;
1065
1066 #endif /* _MIPS_H_ */
GDB/KDevelop