1 ;;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2014 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara <mac@verilog.com>
6 ;; Wilson Snyder <wsnyder@wsnyder.org>
7 ;; http://www.verilog.com
8 ;; http://www.veripool.org
10 ;; Keywords: languages
12 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
13 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
14 ;; filed in the Emacs bug reporting system against this file, a copy
15 ;; of the bug report be sent to the maintainer's email address.
17 ;; This code supports Emacs 21.1 and later
18 ;; And XEmacs 21.1 and later
19 ;; Please do not make changes that break Emacs 21. Thanks!
23 ;; This file is part of GNU Emacs.
25 ;; GNU Emacs is free software: you can redistribute it and/or modify
26 ;; it under the terms of the GNU General Public License as published by
27 ;; the Free Software Foundation, either version 3 of the License, or
28 ;; (at your option) any later version.
30 ;; GNU Emacs is distributed in the hope that it will be useful,
31 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
32 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 ;; GNU General Public License for more details.
35 ;; You should have received a copy of the GNU General Public License
36 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
43 ;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
44 ;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
45 ;; mode, you may get more info by pressing C-h m. You may also get online
46 ;; help describing various functions by: C-h f <Name of function you want
49 ;; KNOWN BUGS / BUG REPORTS
50 ;; =======================
52 ;; SystemVerilog is a rapidly evolving language, and hence this mode is
53 ;; under continuous development. Please report any issues to the issue
56 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result we will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ; ;; Enable syntax highlighting of **all** languages
96 ; (global-font-lock-mode t)
98 ; ;; User customization for Verilog mode
99 ; (setq verilog-indent-level 3
100 ; verilog-indent-level-module 3
101 ; verilog-indent-level-declaration 3
102 ; verilog-indent-level-behavioral 3
103 ; verilog-indent-level-directive 1
104 ; verilog-case-indent 2
105 ; verilog-auto-newline t
106 ; verilog-auto-indent-on-newline t
107 ; verilog-tab-always-indent t
108 ; verilog-auto-endcomments t
109 ; verilog-minimum-comment-distance 40
110 ; verilog-indent-begin-after-if t
111 ; verilog-auto-lineup 'declarations
112 ; verilog-highlight-p1800-keywords nil
113 ; verilog-linter "my_lint_shell_command"
120 ;; See commit history at http://www.veripool.org/verilog-mode.html
121 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version
"2013-11-05-78e66ba-vpo"
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-emacs t
129 "If non-nil, this version of Verilog mode was released with Emacs itself.")
131 (defun verilog-version ()
132 "Inform caller of the version of this file."
134 (message "Using verilog-mode version %s" verilog-mode-version
))
136 ;; Insure we have certain packages, and deal with it if we don't
137 ;; Be sure to note which Emacs flavor and version added each feature.
139 ;; Provide stuff if we are XEmacs
140 (when (featurep 'xemacs
)
145 (require 'regexp-opt
)
147 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
154 (defmacro when
(cond &rest body
)
155 (list 'if cond
(cons 'progn body
))))
158 (if (fboundp 'unless
)
160 (defmacro unless
(cond &rest body
)
161 (cons 'if
(cons cond
(cons nil body
)))))
164 (if (fboundp 'store-match-data
)
166 (defmacro store-match-data
(&rest _args
) nil
))
169 (if (fboundp 'char-before
)
171 (defmacro char-before
(&rest _body
)
172 (char-after (1- (point)))))
177 (defsubst point-at-bol
(&optional N
)
178 (save-excursion (beginning-of-line N
) (point))))
183 (defsubst point-at-eol
(&optional N
)
184 (save-excursion (end-of-line N
) (point))))
190 (if (fboundp 'match-string-no-properties
)
192 (defsubst match-string-no-properties
(num &optional string
)
193 "Return string of text matched by last search, without text properties.
194 NUM specifies which parenthesized expression in the last regexp.
195 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
196 Zero means the entire text matched by the whole regexp or whole string.
197 STRING should be given if the last search was by `string-match' on STRING."
198 (if (match-beginning num
)
202 (match-beginning num
) (match-end num
))))
203 (set-text-properties 0 (length result
) nil result
)
205 (buffer-substring-no-properties (match-beginning num
)
210 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
211 nil
;; We've got what we needed
212 ;; We have the old custom-library, hack around it!
213 (defmacro defgroup
(&rest _args
) nil
)
214 (defmacro customize
(&rest _args
)
216 "Sorry, Customize is not available with this version of Emacs"))
217 (defmacro defcustom
(var value doc
&rest _args
)
218 `(defvar ,var
,value
,doc
))
220 (if (fboundp 'defface
)
222 (defmacro defface
(var values doc
&rest _args
)
226 (if (and (featurep 'custom
) (fboundp 'customize-group
))
227 nil
;; We've got what we needed
228 ;; We have an intermediate custom-library, hack around it!
229 (defmacro customize-group
(var &rest _args
)
233 (unless (boundp 'inhibit-point-motion-hooks
)
234 (defvar inhibit-point-motion-hooks nil
))
235 (unless (boundp 'deactivate-mark
)
236 (defvar deactivate-mark nil
))
239 ;; OK, do this stuff if we are NOT XEmacs:
240 (unless (featurep 'xemacs
)
241 (unless (fboundp 'region-active-p
)
242 (defmacro region-active-p
()
243 `(and transient-mark-mode mark-active
))))
246 ;; Provide a regular expression optimization routine, using regexp-opt
247 ;; if provided by the user's elisp libraries
249 ;; The below were disabled when GNU Emacs 22 was released;
250 ;; perhaps some still need to be there to support Emacs 21.
251 (if (featurep 'xemacs
)
252 (if (fboundp 'regexp-opt
)
253 ;; regexp-opt is defined, does it take 3 or 2 arguments?
254 (if (fboundp 'function-max-args
)
255 (let ((args (function-max-args `regexp-opt
)))
257 ((eq args
3) ;; It takes 3
258 (condition-case nil
; Hide this defun from emacses
259 ;with just a two input regexp
260 (defun verilog-regexp-opt (a b
)
261 "Deal with differing number of required arguments for `regexp-opt'.
262 Call `regexp-opt' on A and B."
266 ((eq args
2) ;; It takes 2
267 (defun verilog-regexp-opt (a b
)
268 "Call `regexp-opt' on A and B."
272 ;; We can't tell; assume it takes 2
273 (defun verilog-regexp-opt (a b
)
274 "Call `regexp-opt' on A and B."
277 ;; There is no regexp-opt, provide our own
278 (defun verilog-regexp-opt (strings &optional paren _shy
)
279 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
280 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
283 (defalias 'verilog-regexp-opt
'regexp-opt
)))
286 ;; Both xemacs and emacs
288 (require 'diff
) ;; diff-command and diff-switches
291 (require 'compile
) ;; compilation-error-regexp-alist-alist
294 (unless (fboundp 'buffer-chars-modified-tick
) ;; Emacs 22 added
295 (defmacro buffer-chars-modified-tick
() (buffer-modified-tick)))
297 ;; Added in Emacs 24.1
299 (unless (fboundp 'prog-mode
)
300 (define-derived-mode prog-mode fundamental-mode
"Prog"))
304 (defun verilog-regexp-words (a)
305 "Call 'regexp-opt' with word delimiters for the words A."
306 (concat "\\<" (verilog-regexp-opt a t
) "\\>")))
307 (defun verilog-regexp-words (a)
308 "Call 'regexp-opt' with word delimiters for the words A."
309 ;; The FAQ references this function, so user LISP sometimes calls it
310 (concat "\\<" (verilog-regexp-opt a t
) "\\>"))
312 (defun verilog-easy-menu-filter (menu)
313 "Filter `easy-menu-define' MENU to support new features."
314 (cond ((not (featurep 'xemacs
))
315 menu
) ;; GNU Emacs - passthru
316 ;; XEmacs doesn't support :help. Strip it.
317 ;; Recursively filter the a submenu
319 (mapcar 'verilog-easy-menu-filter menu
))
320 ;; Look for [:help "blah"] and remove
322 (let ((i 0) (out []))
323 (while (< i
(length menu
))
324 (if (equal `:help
(aref menu i
))
326 (setq out
(vconcat out
(vector (aref menu i
)))
329 (t menu
))) ;; Default - ok
330 ;;(verilog-easy-menu-filter
331 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
332 ;; "----" ["MB" nil :help "Help MB"]))
334 (defun verilog-define-abbrev (table name expansion
&optional hook
)
335 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
336 Provides SYSTEM-FLAG in newer Emacs."
338 (define-abbrev table name expansion hook
0 t
)
340 (define-abbrev table name expansion hook
))))
342 (defun verilog-customize ()
343 "Customize variables and other settings used by Verilog-Mode."
345 (customize-group 'verilog-mode
))
347 (defun verilog-font-customize ()
348 "Customize fonts used by Verilog-Mode."
350 (if (fboundp 'customize-apropos
)
351 (customize-apropos "font-lock-*" 'faces
)))
353 (defun verilog-booleanp (value)
354 "Return t if VALUE is boolean.
355 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
356 This function may be removed when Emacs 21 is no longer supported."
357 (or (equal value t
) (equal value nil
)))
359 (defun verilog-insert-last-command-event ()
360 "Insert the `last-command-event'."
361 (insert (if (featurep 'xemacs
)
362 ;; XEmacs 21.5 doesn't like last-command-event
364 ;; And GNU Emacs 22 has obsoleted last-command-char
365 last-command-event
)))
367 (defvar verilog-no-change-functions nil
368 "True if `after-change-functions' is disabled.
369 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
371 (defvar verilog-in-hooks nil
372 "True when within a `verilog-run-hooks' block.")
374 (defmacro verilog-run-hooks
(&rest hooks
)
375 "Run each hook in HOOKS using `run-hooks'.
376 Set `verilog-in-hooks' during this time, to assist AUTO caches."
377 `(let ((verilog-in-hooks t
))
378 (run-hooks ,@hooks
)))
380 (defun verilog-syntax-ppss (&optional pos
)
381 (when verilog-no-change-functions
383 (verilog-scan-cache-flush)
384 ;; else don't let the AUTO code itself get away with flushing the cache,
385 ;; as that'll make things very slow
387 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
388 (verilog-point-text))))
389 (if (fboundp 'syntax-ppss
)
391 (parse-partial-sexp (point-min) (or pos
(point)))))
393 (defgroup verilog-mode nil
394 "Major mode for Verilog source code."
398 ; (defgroup verilog-mode-fonts nil
399 ; "Facilitates easy customization fonts used in Verilog source text"
400 ; :link '(customize-apropos "font-lock-*" 'faces)
401 ; :group 'verilog-mode)
403 (defgroup verilog-mode-indent nil
404 "Customize indentation and highlighting of Verilog source text."
405 :group
'verilog-mode
)
407 (defgroup verilog-mode-actions nil
408 "Customize actions on Verilog source text."
409 :group
'verilog-mode
)
411 (defgroup verilog-mode-auto nil
412 "Customize AUTO actions when expanding Verilog source text."
413 :group
'verilog-mode
)
415 (defvar verilog-debug nil
416 "Non-nil means enable debug messages for `verilog-mode' internals.")
418 (defvar verilog-warn-fatal nil
419 "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
421 (defcustom verilog-linter
422 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
423 "Unix program and arguments to call to run a lint checker on Verilog source.
424 Depending on the `verilog-set-compile-command', this may be invoked when
425 you type \\[compile]. When the compile completes, \\[next-error] will take
426 you to the next lint error."
428 :group
'verilog-mode-actions
)
429 ;; We don't mark it safe, as it's used as a shell command
431 (defcustom verilog-coverage
432 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
433 "Program and arguments to use to annotate for coverage Verilog source.
434 Depending on the `verilog-set-compile-command', this may be invoked when
435 you type \\[compile]. When the compile completes, \\[next-error] will take
436 you to the next lint error."
438 :group
'verilog-mode-actions
)
439 ;; We don't mark it safe, as it's used as a shell command
441 (defcustom verilog-simulator
442 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
443 "Program and arguments to use to interpret Verilog source.
444 Depending on the `verilog-set-compile-command', this may be invoked when
445 you type \\[compile]. When the compile completes, \\[next-error] will take
446 you to the next lint error."
448 :group
'verilog-mode-actions
)
449 ;; We don't mark it safe, as it's used as a shell command
451 (defcustom verilog-compiler
452 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
453 "Program and arguments to use to compile Verilog source.
454 Depending on the `verilog-set-compile-command', this may be invoked when
455 you type \\[compile]. When the compile completes, \\[next-error] will take
456 you to the next lint error."
458 :group
'verilog-mode-actions
)
459 ;; We don't mark it safe, as it's used as a shell command
461 (defcustom verilog-preprocessor
462 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
463 "vppreproc __FLAGS__ __FILE__"
464 "Program and arguments to use to preprocess Verilog source.
465 This is invoked with `verilog-preprocess', and depending on the
466 `verilog-set-compile-command', may also be invoked when you type
467 \\[compile]. When the compile completes, \\[next-error] will
468 take you to the next lint error."
470 :group
'verilog-mode-actions
)
471 ;; We don't mark it safe, as it's used as a shell command
473 (defvar verilog-preprocess-history nil
474 "History for `verilog-preprocess'.")
476 (defvar verilog-tool
'verilog-linter
477 "Which tool to use for building compiler-command.
478 Either nil, `verilog-linter, `verilog-compiler,
479 `verilog-coverage, `verilog-preprocessor, or `verilog-simulator.
480 Alternatively use the \"Choose Compilation Action\" menu. See
481 `verilog-set-compile-command' for more information.")
483 (defcustom verilog-highlight-translate-off nil
484 "Non-nil means background-highlight code excluded from translation.
485 That is, all code between \"// synopsys translate_off\" and
486 \"// synopsys translate_on\" is highlighted using a different background color
487 \(face `verilog-font-lock-translate-off-face').
489 Note: This will slow down on-the-fly fontification (and thus editing).
491 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
492 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
494 :group
'verilog-mode-indent
)
495 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
496 (put 'verilog-highlight-translate-off
'safe-local-variable
'verilog-booleanp
)
498 (defcustom verilog-auto-lineup
'declarations
499 "Type of statements to lineup across multiple lines.
500 If 'all' is selected, then all line ups described below are done.
502 If 'declarations', then just declarations are lined up with any
503 preceding declarations, taking into account widths and the like,
504 so or example the code:
511 If 'assignment', then assignments are lined up with any preceding
512 assignments, so for example the code
513 a_long_variable <= b + c;
516 a_long_variable <= b + c;
519 In order to speed up editing, large blocks of statements are lined up
520 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
521 are lineup only when \\[verilog-pretty-declarations] is typed."
523 :type
'(radio (const :tag
"Line up Assignments and Declarations" all
)
524 (const :tag
"Line up Assignment statements" assignments
)
525 (const :tag
"Line up Declarations" declarations
)
526 (function :tag
"Other"))
527 :group
'verilog-mode-indent
)
528 (put 'verilog-auto-lineup
'safe-local-variable
529 '(lambda (x) (memq x
'(nil all assignments declarations
))))
531 (defcustom verilog-indent-level
3
532 "Indentation of Verilog statements with respect to containing block."
533 :group
'verilog-mode-indent
535 (put 'verilog-indent-level
'safe-local-variable
'integerp
)
537 (defcustom verilog-indent-level-module
3
538 "Indentation of Module level Verilog statements (eg always, initial).
539 Set to 0 to get initial and always statements lined up on the left side of
541 :group
'verilog-mode-indent
543 (put 'verilog-indent-level-module
'safe-local-variable
'integerp
)
545 (defcustom verilog-indent-level-declaration
3
546 "Indentation of declarations with respect to containing block.
547 Set to 0 to get them list right under containing block."
548 :group
'verilog-mode-indent
550 (put 'verilog-indent-level-declaration
'safe-local-variable
'integerp
)
552 (defcustom verilog-indent-declaration-macros nil
553 "How to treat macro expansions in a declaration.
558 If non nil, treat as:
562 :group
'verilog-mode-indent
564 (put 'verilog-indent-declaration-macros
'safe-local-variable
'verilog-booleanp
)
566 (defcustom verilog-indent-lists t
567 "How to treat indenting items in a list.
568 If t (the default), indent as:
569 always @( posedge a or
573 always @( posedge a or
575 :group
'verilog-mode-indent
577 (put 'verilog-indent-lists
'safe-local-variable
'verilog-booleanp
)
579 (defcustom verilog-indent-level-behavioral
3
580 "Absolute indentation of first begin in a task or function block.
581 Set to 0 to get such code to start at the left side of the screen."
582 :group
'verilog-mode-indent
584 (put 'verilog-indent-level-behavioral
'safe-local-variable
'integerp
)
586 (defcustom verilog-indent-level-directive
1
587 "Indentation to add to each level of `ifdef declarations.
588 Set to 0 to have all directives start at the left side of the screen."
589 :group
'verilog-mode-indent
591 (put 'verilog-indent-level-directive
'safe-local-variable
'integerp
)
593 (defcustom verilog-cexp-indent
2
594 "Indentation of Verilog statements split across lines."
595 :group
'verilog-mode-indent
597 (put 'verilog-cexp-indent
'safe-local-variable
'integerp
)
599 (defcustom verilog-case-indent
2
600 "Indentation for case statements."
601 :group
'verilog-mode-indent
603 (put 'verilog-case-indent
'safe-local-variable
'integerp
)
605 (defcustom verilog-auto-newline t
606 "Non-nil means automatically newline after semicolons."
607 :group
'verilog-mode-indent
609 (put 'verilog-auto-newline
'safe-local-variable
'verilog-booleanp
)
611 (defcustom verilog-auto-indent-on-newline t
612 "Non-nil means automatically indent line after newline."
613 :group
'verilog-mode-indent
615 (put 'verilog-auto-indent-on-newline
'safe-local-variable
'verilog-booleanp
)
617 (defcustom verilog-tab-always-indent t
618 "Non-nil means TAB should always re-indent the current line.
619 A nil value means TAB will only reindent when at the beginning of the line."
620 :group
'verilog-mode-indent
622 (put 'verilog-tab-always-indent
'safe-local-variable
'verilog-booleanp
)
624 (defcustom verilog-tab-to-comment nil
625 "Non-nil means TAB moves to the right hand column in preparation for a comment."
626 :group
'verilog-mode-actions
628 (put 'verilog-tab-to-comment
'safe-local-variable
'verilog-booleanp
)
630 (defcustom verilog-indent-begin-after-if t
631 "Non-nil means indent begin statements following if, else, while, etc.
632 Otherwise, line them up."
633 :group
'verilog-mode-indent
635 (put 'verilog-indent-begin-after-if
'safe-local-variable
'verilog-booleanp
)
637 (defcustom verilog-align-ifelse nil
638 "Non-nil means align `else' under matching `if'.
639 Otherwise else is lined up with first character on line holding matching if."
640 :group
'verilog-mode-indent
642 (put 'verilog-align-ifelse
'safe-local-variable
'verilog-booleanp
)
644 (defcustom verilog-minimum-comment-distance
10
645 "Minimum distance (in lines) between begin and end required before a comment.
646 Setting this variable to zero results in every end acquiring a comment; the
647 default avoids too many redundant comments in tight quarters."
648 :group
'verilog-mode-indent
650 (put 'verilog-minimum-comment-distance
'safe-local-variable
'integerp
)
652 (defcustom verilog-highlight-p1800-keywords nil
653 "Non-nil means highlight words newly reserved by IEEE-1800.
654 These will appear in `verilog-font-lock-p1800-face' in order to gently
655 suggest changing where these words are used as variables to something else.
656 A nil value means highlight these words as appropriate for the SystemVerilog
657 IEEE-1800 standard. Note that changing this will require restarting Emacs
658 to see the effect as font color choices are cached by Emacs."
659 :group
'verilog-mode-indent
661 (put 'verilog-highlight-p1800-keywords
'safe-local-variable
'verilog-booleanp
)
663 (defcustom verilog-highlight-grouping-keywords nil
664 "Non-nil means highlight grouping keywords more dramatically.
665 If false, these words are in the `font-lock-type-face'; if True then they are in
666 `verilog-font-lock-ams-face'. Some find that special highlighting on these
667 grouping constructs allow the structure of the code to be understood at a glance."
668 :group
'verilog-mode-indent
670 (put 'verilog-highlight-grouping-keywords
'safe-local-variable
'verilog-booleanp
)
672 (defcustom verilog-highlight-modules nil
673 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
674 When true, mousing over module names will allow jumping to the
675 module definition. If false, this is not supported. Setting
676 this is experimental, and may lead to bad performance."
677 :group
'verilog-mode-indent
679 (put 'verilog-highlight-modules
'safe-local-variable
'verilog-booleanp
)
681 (defcustom verilog-highlight-includes t
682 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
683 When true, mousing over include file names will allow jumping to the
684 file referenced. If false, this is not supported."
685 :group
'verilog-mode-indent
687 (put 'verilog-highlight-includes
'safe-local-variable
'verilog-booleanp
)
689 (defcustom verilog-auto-declare-nettype nil
690 "Non-nil specifies the data type to use with `verilog-auto-input' etc.
691 Set this to \"wire\" if the Verilog code uses \"`default_nettype
692 none\". Note using `default_nettype none isn't recommended practice; this
693 mode is experimental."
694 :version
"24.1" ;; rev670
695 :group
'verilog-mode-actions
697 (put 'verilog-auto-declare-nettype
'safe-local-variable
`stringp
)
699 (defcustom verilog-auto-wire-type nil
700 "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
701 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
702 :version
"24.1" ;; rev673
703 :group
'verilog-mode-actions
705 (put 'verilog-auto-wire-type
'safe-local-variable
`stringp
)
707 (defcustom verilog-auto-endcomments t
708 "Non-nil means insert a comment /* ... */ after 'end's.
709 The name of the function or case will be set between the braces."
710 :group
'verilog-mode-actions
712 (put 'verilog-auto-endcomments
'safe-local-variable
'verilog-booleanp
)
714 (defcustom verilog-auto-delete-trailing-whitespace nil
715 "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
716 :version
"24.1" ;; rev703
717 :group
'verilog-mode-actions
719 (put 'verilog-auto-delete-trailing-whitespace
'safe-local-variable
'verilog-booleanp
)
721 (defcustom verilog-auto-ignore-concat nil
722 "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
723 This will exclude signals referenced as pin connections in {...}
724 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
725 for backward compatibility only and not set in new designs; it
726 may be removed in future versions."
727 :group
'verilog-mode-actions
729 (put 'verilog-auto-ignore-concat
'safe-local-variable
'verilog-booleanp
)
731 (defcustom verilog-auto-read-includes nil
732 "Non-nil means to automatically read includes before AUTOs.
733 This will do a `verilog-read-defines' and `verilog-read-includes' before
734 each AUTO expansion. This makes it easier to embed defines and includes,
735 but can result in very slow reading times if there are many or large
737 :group
'verilog-mode-actions
739 (put 'verilog-auto-read-includes
'safe-local-variable
'verilog-booleanp
)
741 (defcustom verilog-auto-save-policy nil
742 "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
743 A value of `force' will always do a \\[verilog-auto] automatically if
744 needed on every save. A value of `detect' will do \\[verilog-auto]
745 automatically when it thinks necessary. A value of `ask' will query the
746 user when it thinks updating is needed.
748 You should not rely on the 'ask or 'detect policies, they are safeguards
749 only. They do not detect when AUTOINSTs need to be updated because a
750 sub-module's port list has changed."
751 :group
'verilog-mode-actions
752 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
754 (defcustom verilog-auto-star-expand t
755 "Non-nil means to expand SystemVerilog .* instance ports.
756 They will be expanded in the same way as if there was an AUTOINST in the
757 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
758 :group
'verilog-mode-actions
760 (put 'verilog-auto-star-expand
'safe-local-variable
'verilog-booleanp
)
762 (defcustom verilog-auto-star-save nil
763 "Non-nil means save to disk SystemVerilog .* instance expansions.
764 A nil value indicates direct connections will be removed before saving.
765 Only meaningful to those created due to `verilog-auto-star-expand' being set.
767 Instead of setting this, you may want to use /*AUTOINST*/, which will
769 :group
'verilog-mode-actions
771 (put 'verilog-auto-star-save
'safe-local-variable
'verilog-booleanp
)
773 (defvar verilog-auto-update-tick nil
774 "Modification tick at which autos were last performed.")
776 (defvar verilog-auto-last-file-locals nil
777 "Text from file-local-variables during last evaluation.")
779 (defvar verilog-diff-function
'verilog-diff-report
780 "Function to run when `verilog-diff-auto' detects differences.
781 Function takes three arguments, the original buffer, the
782 difference buffer, and the point in original buffer with the
787 (defvar verilog-error-regexp-added nil
)
789 (defvar verilog-error-regexp-emacs-alist
792 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
794 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
796 ".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
798 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
800 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
803 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
804 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
806 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
808 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
810 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
812 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
814 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
816 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
818 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
820 "List of regexps for Verilog compilers.
821 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
823 (defvar verilog-error-regexp-xemacs-alist
824 ;; Emacs form is '((v-tool "re" 1 2) ...)
825 ;; XEmacs form is '(verilog ("re" 1 2) ...)
826 ;; So we can just map from Emacs to XEmacs
827 (cons 'verilog
(mapcar 'cdr verilog-error-regexp-emacs-alist
))
828 "List of regexps for Verilog compilers.
829 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
831 (defvar verilog-error-font-lock-keywords
834 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
835 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
837 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t
)
838 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t
)
839 ;; verilog-IES (nc-verilog)
840 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
841 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t
)
842 ;; verilog-surefire-1
843 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
844 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
845 ;; verilog-surefire-2
846 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
847 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
850 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
851 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
853 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
854 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
856 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
857 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
859 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
860 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
862 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
863 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
865 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
866 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
868 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
869 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
871 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t
)
872 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t
)
874 "Keywords to also highlight in Verilog *compilation* buffers.
875 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
877 (defcustom verilog-library-flags
'("")
878 "List of standard Verilog arguments to use for /*AUTOINST*/.
879 These arguments are used to find files for `verilog-auto', and match
880 the flags accepted by a standard Verilog-XL simulator.
882 -f filename Reads more `verilog-library-flags' from the filename.
883 +incdir+dir Adds the directory to `verilog-library-directories'.
884 -Idir Adds the directory to `verilog-library-directories'.
885 -y dir Adds the directory to `verilog-library-directories'.
886 +libext+.v Adds the extensions to `verilog-library-extensions'.
887 -v filename Adds the filename to `verilog-library-files'.
889 filename Adds the filename to `verilog-library-files'.
890 This is not recommended, -v is a better choice.
892 You might want these defined in each file; put at the *END* of your file
896 // verilog-library-flags:(\"-y dir -y otherdir\")
899 Verilog-mode attempts to detect changes to this local variable, but they
900 are only insured to be correct when the file is first visited. Thus if you
901 have problems, use \\[find-alternate-file] RET to have these take effect.
903 See also the variables mentioned above."
904 :group
'verilog-mode-auto
905 :type
'(repeat string
))
906 (put 'verilog-library-flags
'safe-local-variable
'listp
)
908 (defcustom verilog-library-directories
'(".")
909 "List of directories when looking for files for /*AUTOINST*/.
910 The directory may be relative to the current file, or absolute.
911 Environment variables are also expanded in the directory names.
912 Having at least the current directory is a good idea.
914 You might want these defined in each file; put at the *END* of your file
918 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
921 Verilog-mode attempts to detect changes to this local variable, but they
922 are only insured to be correct when the file is first visited. Thus if you
923 have problems, use \\[find-alternate-file] RET to have these take effect.
925 See also `verilog-library-flags', `verilog-library-files'
926 and `verilog-library-extensions'."
927 :group
'verilog-mode-auto
928 :type
'(repeat file
))
929 (put 'verilog-library-directories
'safe-local-variable
'listp
)
931 (defcustom verilog-library-files
'()
932 "List of files to search for modules.
933 AUTOINST will use this when it needs to resolve a module name.
934 This is a complete path, usually to a technology file with many standard
937 You might want these defined in each file; put at the *END* of your file
941 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
944 Verilog-mode attempts to detect changes to this local variable, but they
945 are only insured to be correct when the file is first visited. Thus if you
946 have problems, use \\[find-alternate-file] RET to have these take effect.
948 See also `verilog-library-flags', `verilog-library-directories'."
949 :group
'verilog-mode-auto
950 :type
'(repeat directory
))
951 (put 'verilog-library-files
'safe-local-variable
'listp
)
953 (defcustom verilog-library-extensions
'(".v" ".sv")
954 "List of extensions to use when looking for files for /*AUTOINST*/.
955 See also `verilog-library-flags', `verilog-library-directories'."
956 :type
'(repeat string
)
957 :group
'verilog-mode-auto
)
958 (put 'verilog-library-extensions
'safe-local-variable
'listp
)
960 (defcustom verilog-active-low-regexp nil
961 "If true, treat signals matching this regexp as active low.
962 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
963 you will probably also need `verilog-auto-reset-widths' set."
964 :group
'verilog-mode-auto
965 :type
'(choice (const nil
) regexp
))
966 (put 'verilog-active-low-regexp
'safe-local-variable
'stringp
)
968 (defcustom verilog-auto-sense-include-inputs nil
969 "Non-nil means AUTOSENSE should include all inputs.
970 If nil, only inputs that are NOT output signals in the same block are
972 :group
'verilog-mode-auto
974 (put 'verilog-auto-sense-include-inputs
'safe-local-variable
'verilog-booleanp
)
976 (defcustom verilog-auto-sense-defines-constant nil
977 "Non-nil means AUTOSENSE should assume all defines represent constants.
978 When true, the defines will not be included in sensitivity lists. To
979 maintain compatibility with other sites, this should be set at the bottom
980 of each Verilog file that requires it, rather than being set globally."
981 :group
'verilog-mode-auto
983 (put 'verilog-auto-sense-defines-constant
'safe-local-variable
'verilog-booleanp
)
985 (defcustom verilog-auto-reset-blocking-in-non t
986 "Non-nil means AUTORESET will reset blocking statements.
987 When true, AUTORESET will reset in blocking statements those
988 signals which were assigned with blocking assignments (=) even in
989 a block with non-blocking assignments (<=).
991 If nil, all blocking assigned signals are ignored when any
992 non-blocking assignment is in the AUTORESET block. This allows
993 blocking assignments to be used for temporary values and not have
994 those temporaries reset. See example in `verilog-auto-reset'."
995 :version
"24.1" ;; rev718
997 :group
'verilog-mode-auto
)
998 (put 'verilog-auto-reset-blocking-in-non
'safe-local-variable
'verilog-booleanp
)
1000 (defcustom verilog-auto-reset-widths t
1001 "True means AUTORESET should determine the width of signals.
1002 This is then used to set the width of the zero (32'h0 for example). This
1003 is required by some lint tools that aren't smart enough to ignore widths of
1004 the constant zero. This may result in ugly code when parameters determine
1005 the MSB or LSB of a signal inside an AUTORESET.
1007 If nil, AUTORESET uses \"0\" as the constant.
1009 If 'unbased', AUTORESET used the unbased unsized literal \"'0\"
1010 as the constant. This setting is strongly recommended for
1011 SystemVerilog designs."
1013 :group
'verilog-mode-auto
)
1014 (put 'verilog-auto-reset-widths
'safe-local-variable
1015 '(lambda (x) (memq x
'(nil t unbased
))))
1017 (defcustom verilog-assignment-delay
""
1018 "Text used for delays in delayed assignments. Add a trailing space if set."
1019 :group
'verilog-mode-auto
1021 (put 'verilog-assignment-delay
'safe-local-variable
'stringp
)
1023 (defcustom verilog-auto-arg-sort nil
1024 "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
1025 Declaration order is advantageous with order based instantiations
1026 and is the default for backward compatibility. Sorted order
1027 reduces changes when declarations are moved around in a file, and
1028 it's bad practice to rely on order based instantiations anyhow.
1030 See also `verilog-auto-inst-sort'."
1031 :group
'verilog-mode-auto
1033 (put 'verilog-auto-arg-sort
'safe-local-variable
'verilog-booleanp
)
1035 (defcustom verilog-auto-inst-dot-name nil
1036 "Non-nil means when creating ports with AUTOINST, use .name syntax.
1037 This will use \".port\" instead of \".port(port)\" when possible.
1038 This is only legal in SystemVerilog files, and will confuse older
1039 simulators. Setting `verilog-auto-inst-vector' to nil may also
1040 be desirable to increase how often .name will be used."
1041 :group
'verilog-mode-auto
1043 (put 'verilog-auto-inst-dot-name
'safe-local-variable
'verilog-booleanp
)
1045 (defcustom verilog-auto-inst-param-value nil
1046 "Non-nil means AUTOINST will replace parameters with the parameter value.
1047 If nil, leave parameters as symbolic names.
1049 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1050 listed as such there (as when the default value is acceptable), it will not
1051 be replaced, and will remain symbolic.
1053 For example, imagine a submodule uses parameters to declare the size of its
1054 inputs. This is then used by an upper module:
1056 module InstModule (o,i);
1058 input [WIDTH-1:0] i;
1068 Note even though PARAM=10, the AUTOINST has left the parameter as a
1069 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1078 :group
'verilog-mode-auto
1080 (put 'verilog-auto-inst-param-value
'safe-local-variable
'verilog-booleanp
)
1082 (defcustom verilog-auto-inst-sort nil
1083 "Non-nil means AUTOINST signals will be sorted, not in declaration order.
1084 Also affects AUTOINSTPARAM. Declaration order is the default for
1085 backward compatibility, and as some teams prefer signals that are
1086 declared together to remain together. Sorted order reduces
1087 changes when declarations are moved around in a file.
1089 See also `verilog-auto-arg-sort'."
1090 :version
"24.1" ;; rev688
1091 :group
'verilog-mode-auto
1093 (put 'verilog-auto-inst-sort
'safe-local-variable
'verilog-booleanp
)
1095 (defcustom verilog-auto-inst-vector t
1096 "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
1097 If nil, skip the subscript when it matches the entire bus as declared in
1098 the module (AUTOWIRE signals always are subscripted, you must manually
1099 declare the wire to have the subscripts removed.) Setting this to nil may
1100 speed up some simulators, but is less general and harder to read, so avoid."
1101 :group
'verilog-mode-auto
1103 (put 'verilog-auto-inst-vector
'safe-local-variable
'verilog-booleanp
)
1105 (defcustom verilog-auto-inst-template-numbers nil
1106 "If true, when creating templated ports with AUTOINST, add a comment.
1108 If t, the comment will add the line number of the template that
1109 was used for that port declaration. This setting is suggested
1110 only for debugging use, as regular use may cause a large numbers
1113 If 'lhs', the comment will show the left hand side of the
1114 AUTO_TEMPLATE rule that is matched. This is less precise than
1115 numbering (t) when multiple rules have the same pin name, but
1116 won't merge conflict."
1117 :group
'verilog-mode-auto
1118 :type
'(choice (const nil
) (const t
) (const lhs
)))
1119 (put 'verilog-auto-inst-template-numbers
'safe-local-variable
1120 '(lambda (x) (memq x
'(nil t lhs
))))
1122 (defcustom verilog-auto-inst-column
40
1123 "Indent-to column number for net name part of AUTOINST created pin."
1124 :group
'verilog-mode-indent
1126 (put 'verilog-auto-inst-column
'safe-local-variable
'integerp
)
1128 (defcustom verilog-auto-inst-interfaced-ports nil
1129 "Non-nil means include interfaced ports in AUTOINST expansions."
1130 :version
"24.3" ;; rev773, default change rev815
1131 :group
'verilog-mode-auto
1133 (put 'verilog-auto-inst-interfaced-ports
'safe-local-variable
'verilog-booleanp
)
1135 (defcustom verilog-auto-input-ignore-regexp nil
1136 "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
1137 See the \\[verilog-faq] for examples on using this."
1138 :group
'verilog-mode-auto
1139 :type
'(choice (const nil
) regexp
))
1140 (put 'verilog-auto-input-ignore-regexp
'safe-local-variable
'stringp
)
1142 (defcustom verilog-auto-inout-ignore-regexp nil
1143 "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
1144 See the \\[verilog-faq] for examples on using this."
1145 :group
'verilog-mode-auto
1146 :type
'(choice (const nil
) regexp
))
1147 (put 'verilog-auto-inout-ignore-regexp
'safe-local-variable
'stringp
)
1149 (defcustom verilog-auto-output-ignore-regexp nil
1150 "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
1151 See the \\[verilog-faq] for examples on using this."
1152 :group
'verilog-mode-auto
1153 :type
'(choice (const nil
) regexp
))
1154 (put 'verilog-auto-output-ignore-regexp
'safe-local-variable
'stringp
)
1156 (defcustom verilog-auto-template-warn-unused nil
1157 "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
1158 This feature is not supported before Emacs 21.1 or XEmacs 21.4."
1159 :version
"24.3" ;;rev787
1160 :group
'verilog-mode-auto
1162 (put 'verilog-auto-template-warn-unused
'safe-local-variable
'verilog-booleanp
)
1164 (defcustom verilog-auto-tieoff-declaration
"wire"
1165 "Data type used for the declaration for AUTOTIEOFF.
1166 If \"wire\" then create a wire, if \"assign\" create an
1167 assignment, else the data type for variable creation."
1168 :version
"24.1" ;; rev713
1169 :group
'verilog-mode-auto
1171 (put 'verilog-auto-tieoff-declaration
'safe-local-variable
'stringp
)
1173 (defcustom verilog-auto-tieoff-ignore-regexp nil
1174 "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
1175 See the \\[verilog-faq] for examples on using this."
1176 :group
'verilog-mode-auto
1177 :type
'(choice (const nil
) regexp
))
1178 (put 'verilog-auto-tieoff-ignore-regexp
'safe-local-variable
'stringp
)
1180 (defcustom verilog-auto-unused-ignore-regexp nil
1181 "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
1182 See the \\[verilog-faq] for examples on using this."
1183 :group
'verilog-mode-auto
1184 :type
'(choice (const nil
) regexp
))
1185 (put 'verilog-auto-unused-ignore-regexp
'safe-local-variable
'stringp
)
1187 (defcustom verilog-case-fold t
1188 "Non-nil means `verilog-mode' regexps should ignore case.
1189 This variable is t for backward compatibility; nil is suggested."
1191 :group
'verilog-mode
1193 (put 'verilog-case-fold
'safe-local-variable
'verilog-booleanp
)
1195 (defcustom verilog-typedef-regexp nil
1196 "If non-nil, regular expression that matches Verilog-2001 typedef names.
1197 For example, \"_t$\" matches typedefs named with _t, as in the C language.
1198 See also `verilog-case-fold'."
1199 :group
'verilog-mode-auto
1200 :type
'(choice (const nil
) regexp
))
1201 (put 'verilog-typedef-regexp
'safe-local-variable
'stringp
)
1203 (defcustom verilog-mode-hook
'verilog-set-compile-command
1204 "Hook run after Verilog mode is loaded."
1206 :group
'verilog-mode
)
1208 (defcustom verilog-auto-hook nil
1209 "Hook run after `verilog-mode' updates AUTOs."
1210 :group
'verilog-mode-auto
1213 (defcustom verilog-before-auto-hook nil
1214 "Hook run before `verilog-mode' updates AUTOs."
1215 :group
'verilog-mode-auto
1218 (defcustom verilog-delete-auto-hook nil
1219 "Hook run after `verilog-mode' deletes AUTOs."
1220 :group
'verilog-mode-auto
1223 (defcustom verilog-before-delete-auto-hook nil
1224 "Hook run before `verilog-mode' deletes AUTOs."
1225 :group
'verilog-mode-auto
1228 (defcustom verilog-getopt-flags-hook nil
1229 "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1230 :group
'verilog-mode-auto
1233 (defcustom verilog-before-getopt-flags-hook nil
1234 "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1235 :group
'verilog-mode-auto
1238 (defcustom verilog-before-save-font-hook nil
1239 "Hook run before `verilog-save-font-mods' removes highlighting."
1240 :version
"24.3" ;;rev735
1241 :group
'verilog-mode-auto
1244 (defcustom verilog-after-save-font-hook nil
1245 "Hook run after `verilog-save-font-mods' restores highlighting."
1246 :version
"24.3" ;;rev735
1247 :group
'verilog-mode-auto
1250 (defvar verilog-imenu-generic-expression
1251 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1252 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1253 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1256 ;; provide a verilog-header function.
1257 ;; Customization variables:
1259 (defvar verilog-date-scientific-format nil
1260 "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1261 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1262 format (e.g. 09/17/1997) is not supported.")
1264 (defvar verilog-company nil
1265 "Default name of Company for Verilog header.
1266 If set will become buffer local.")
1267 (make-variable-buffer-local 'verilog-company
)
1269 (defvar verilog-project nil
1270 "Default name of Project for Verilog header.
1271 If set will become buffer local.")
1272 (make-variable-buffer-local 'verilog-project
)
1274 (defvar verilog-mode-map
1275 (let ((map (make-sparse-keymap)))
1276 (define-key map
";" 'electric-verilog-semi
)
1277 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
1278 (define-key map
":" 'electric-verilog-colon
)
1279 ;;(define-key map "=" 'electric-verilog-equal)
1280 (define-key map
"\`" 'electric-verilog-tick
)
1281 (define-key map
"\t" 'electric-verilog-tab
)
1282 (define-key map
"\r" 'electric-verilog-terminate-line
)
1283 ;; backspace/delete key bindings
1284 (define-key map
[backspace] 'backward-delete-char-untabify)
1285 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1286 (define-key map [delete] 'delete-char)
1287 (define-key map [(meta delete)] 'kill-word))
1288 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1289 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1290 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1291 (define-key map "\M-\t" 'verilog-complete-word)
1292 (define-key map "\M-?" 'verilog-show-completions)
1293 ;; Note \C-c and letter are reserved for users
1294 (define-key map "\C-c\`" 'verilog-lint-off)
1295 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1296 (define-key map "\C-c\?" 'verilog-diff-auto)
1297 (define-key map "\C-c\C-r" 'verilog-label-be)
1298 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1299 (define-key map "\C-c=" 'verilog-pretty-expr)
1300 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1301 (define-key map "\M-*" 'verilog-star-comment)
1302 (define-key map "\C-c\C-c" 'verilog-comment-region)
1303 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1304 (when (featurep 'xemacs)
1305 (define-key map [(meta control h)] 'verilog-mark-defun)
1306 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1307 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1308 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1309 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1310 (define-key map "\C-c\C-a" 'verilog-auto)
1311 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1312 (define-key map "\C-c\C-p" 'verilog-preprocess)
1313 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1314 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1315 (define-key map "\C-c\C-h" 'verilog-header)
1317 "Keymap used in Verilog mode.")
1321 verilog-menu verilog-mode-map "Menu for Verilog mode"
1322 (verilog-easy-menu-filter
1324 ("Choose Compilation Action"
1327 (setq verilog-tool nil)
1328 (verilog-set-compile-command))
1330 :selected (equal verilog-tool nil)
1331 :help "When invoking compilation, use compile-command"]
1334 (setq verilog-tool 'verilog-linter)
1335 (verilog-set-compile-command))
1337 :selected (equal verilog-tool `verilog-linter)
1338 :help "When invoking compilation, use lint checker"]
1341 (setq verilog-tool 'verilog-coverage)
1342 (verilog-set-compile-command))
1344 :selected (equal verilog-tool `verilog-coverage)
1345 :help "When invoking compilation, annotate for coverage"]
1348 (setq verilog-tool 'verilog-simulator)
1349 (verilog-set-compile-command))
1351 :selected (equal verilog-tool `verilog-simulator)
1352 :help "When invoking compilation, interpret Verilog source"]
1355 (setq verilog-tool 'verilog-compiler)
1356 (verilog-set-compile-command))
1358 :selected (equal verilog-tool `verilog-compiler)
1359 :help "When invoking compilation, compile Verilog source"]
1362 (setq verilog-tool 'verilog-preprocessor)
1363 (verilog-set-compile-command))
1365 :selected (equal verilog-tool `verilog-preprocessor)
1366 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1369 ["Beginning of function" verilog-beg-of-defun
1371 :help "Move backward to the beginning of the current function or procedure"]
1372 ["End of function" verilog-end-of-defun
1374 :help "Move forward to the end of the current function or procedure"]
1375 ["Mark function" verilog-mark-defun
1377 :help "Mark the current Verilog function or procedure"]
1378 ["Goto function/module" verilog-goto-defun
1379 :help "Move to specified Verilog module/task/function"]
1380 ["Move to beginning of block" electric-verilog-backward-sexp
1381 :help "Move backward over one balanced expression"]
1382 ["Move to end of block" electric-verilog-forward-sexp
1383 :help "Move forward over one balanced expression"]
1386 ["Comment Region" verilog-comment-region
1387 :help "Put marked area into a comment"]
1388 ["UnComment Region" verilog-uncomment-region
1389 :help "Uncomment an area commented with Comment Region"]
1390 ["Multi-line comment insert" verilog-star-comment
1391 :help "Insert Verilog /* */ comment at point"]
1392 ["Lint error to comment" verilog-lint-off
1393 :help "Convert a Verilog linter warning line into a disable statement"]
1397 :help "Perform compilation-action (above) on the current buffer"]
1398 ["AUTO, Save, Compile" verilog-auto-save-compile
1399 :help "Recompute AUTOs, save buffer, and compile"]
1400 ["Next Compile Error" next-error
1401 :help "Visit next compilation error message and corresponding source code"]
1402 ["Ignore Lint Warning at point" verilog-lint-off
1403 :help "Convert a Verilog linter warning line into a disable statement"]
1405 ["Line up declarations around point" verilog-pretty-declarations
1406 :help "Line up declarations around point"]
1407 ["Line up equations around point" verilog-pretty-expr
1408 :help "Line up expressions around point"]
1409 ["Redo/insert comments on every end" verilog-label-be
1410 :help "Label matching begin ... end statements"]
1411 ["Expand [x:y] vector line" verilog-expand-vector
1412 :help "Take a signal vector on the current line and expand it to multiple lines"]
1413 ["Insert begin-end block" verilog-insert-block
1414 :help "Insert begin ... end"]
1415 ["Complete word" verilog-complete-word
1416 :help "Complete word at point"]
1418 ["Recompute AUTOs" verilog-auto
1419 :help "Expand AUTO meta-comment statements"]
1420 ["Kill AUTOs" verilog-delete-auto
1421 :help "Remove AUTO expansions"]
1422 ["Diff AUTOs" verilog-diff-auto
1423 :help "Show differences in AUTO expansions"]
1424 ["Inject AUTOs" verilog-inject-auto
1425 :help "Inject AUTOs into legacy non-AUTO buffer"]
1427 ["AUTO General" (describe-function 'verilog-auto)
1428 :help "Help introduction on AUTOs"]
1429 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1430 :help "Help on verilog-library-flags"]
1431 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1432 :help "Help on verilog-library-directories"]
1433 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1434 :help "Help on verilog-library-files"]
1435 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1436 :help "Help on verilog-library-extensions"]
1437 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1438 :help "Help on reading `defines"]
1439 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1440 :help "Help on parsing `includes"]
1441 ["AUTOARG" (describe-function 'verilog-auto-arg)
1442 :help "Help on AUTOARG - declaring module port list"]
1443 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1444 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1445 ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
1446 :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
1447 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1448 :help "Help on AUTOINOUT - adding inouts from cells"]
1449 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1450 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1451 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1452 :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
1453 ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
1454 :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
1455 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1456 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1457 ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
1458 :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
1459 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1460 :help "Help on AUTOINPUT - adding inputs from cells"]
1461 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1462 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1463 ["AUTOINST" (describe-function 'verilog-auto-inst)
1464 :help "Help on AUTOINST - adding pins for cells"]
1465 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1466 :help "Help on expanding Verilog-2001 .* pins"]
1467 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1468 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1469 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1470 :help "Help on AUTOLOGIC - declaring logic signals"]
1471 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1472 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1473 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1474 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1475 ["AUTOREG" (describe-function 'verilog-auto-reg)
1476 :help "Help on AUTOREG - declaring registers for non-wires"]
1477 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1478 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1479 ["AUTORESET" (describe-function 'verilog-auto-reset)
1480 :help "Help on AUTORESET - resetting always blocks"]
1481 ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
1482 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1483 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1484 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1485 ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
1486 :help "Help on AUTOUNDEF - undefine all local defines"]
1487 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1488 :help "Help on AUTOUNUSED - terminating unused inputs"]
1489 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1490 :help "Help on AUTOWIRE - declaring wires for cells"]
1493 ["Submit bug report" verilog-submit-bug-report
1494 :help "Submit via mail a bug report on verilog-mode.el"]
1495 ["Version and FAQ" verilog-faq
1496 :help "Show the current version, and where to get the FAQ etc"]
1497 ["Customize Verilog Mode..." verilog-customize
1498 :help "Customize variables and other settings used by Verilog-Mode"]
1499 ["Customize Verilog Fonts & Colors" verilog-font-customize
1500 :help "Customize fonts used by Verilog-Mode."])))
1503 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1504 (verilog-easy-menu-filter
1506 ["Header" verilog-sk-header
1507 :help "Insert a header block at the top of file"]
1508 ["Comment" verilog-sk-comment
1509 :help "Insert a comment block"]
1511 ["Module" verilog-sk-module
1512 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1513 ["OVM Class" verilog-sk-ovm-class
1514 :help "Insert an OVM class block"]
1515 ["UVM Object" verilog-sk-uvm-object
1516 :help "Insert an UVM object block"]
1517 ["UVM Component" verilog-sk-uvm-component
1518 :help "Insert an UVM component block"]
1519 ["Primitive" verilog-sk-primitive
1520 :help "Insert a primitive .. (.. );.. endprimitive block"]
1522 ["Input" verilog-sk-input
1523 :help "Insert an input declaration"]
1524 ["Output" verilog-sk-output
1525 :help "Insert an output declaration"]
1526 ["Inout" verilog-sk-inout
1527 :help "Insert an inout declaration"]
1528 ["Wire" verilog-sk-wire
1529 :help "Insert a wire declaration"]
1530 ["Reg" verilog-sk-reg
1531 :help "Insert a register declaration"]
1532 ["Define thing under point as a register" verilog-sk-define-signal
1533 :help "Define signal under point as a register at the top of the module"]
1535 ["Initial" verilog-sk-initial
1536 :help "Insert an initial begin .. end block"]
1537 ["Always" verilog-sk-always
1538 :help "Insert an always @(AS) begin .. end block"]
1539 ["Function" verilog-sk-function
1540 :help "Insert a function .. begin .. end endfunction block"]
1541 ["Task" verilog-sk-task
1542 :help "Insert a task .. begin .. end endtask block"]
1543 ["Specify" verilog-sk-specify
1544 :help "Insert a specify .. endspecify block"]
1545 ["Generate" verilog-sk-generate
1546 :help "Insert a generate .. endgenerate block"]
1548 ["Begin" verilog-sk-begin
1549 :help "Insert a begin .. end block"]
1551 :help "Insert an if (..) begin .. end block"]
1552 ["(if) else" verilog-sk-else-if
1553 :help "Insert an else if (..) begin .. end block"]
1554 ["For" verilog-sk-for
1555 :help "Insert a for (...) begin .. end block"]
1556 ["While" verilog-sk-while
1557 :help "Insert a while (...) begin .. end block"]
1558 ["Fork" verilog-sk-fork
1559 :help "Insert a fork begin .. end .. join block"]
1560 ["Repeat" verilog-sk-repeat
1561 :help "Insert a repeat (..) begin .. end block"]
1562 ["Case" verilog-sk-case
1563 :help "Insert a case block, prompting for details"]
1564 ["Casex" verilog-sk-casex
1565 :help "Insert a casex (...) item: begin.. end endcase block"]
1566 ["Casez" verilog-sk-casez
1567 :help "Insert a casez (...) item: begin.. end endcase block"])))
1569 (defvar verilog-mode-abbrev-table nil
1570 "Abbrev table in use in Verilog-mode buffers.")
1572 (define-abbrev-table 'verilog-mode-abbrev-table ())
1573 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1574 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1575 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1576 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1577 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1578 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1579 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1580 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1581 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1582 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1583 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1584 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1585 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1586 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1587 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1588 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1589 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1590 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1591 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1592 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1593 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1594 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1595 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1596 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1597 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1603 (defsubst verilog-within-string ()
1604 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1606 (defsubst verilog-string-match-fold (regexp string &optional start)
1607 "Like `string-match', but use `verilog-case-fold'.
1608 Return index of start of first match for REGEXP in STRING, or nil.
1609 Matching ignores case if `verilog-case-fold' is non-nil.
1610 If third arg START is non-nil, start search at that index in STRING."
1611 (let ((case-fold-search verilog-case-fold))
1612 (string-match regexp string start)))
1614 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1615 "Replace occurrences of FROM-STRING with TO-STRING.
1616 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1617 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1618 will break, as the o's continuously replace. xa -> x works ok though."
1619 ;; Hopefully soon to an Emacs built-in
1620 ;; Also note \ in the replacement prevent multiple replacements; IE
1621 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1622 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1624 (while (string-match from-string string start)
1625 (setq string (replace-match to-string fixedcase literal string)
1626 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1629 (defsubst verilog-string-remove-spaces (string)
1630 "Remove spaces surrounding STRING."
1632 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1633 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1636 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1637 ; checkdoc-params: (REGEXP BOUND NOERROR)
1638 "Like `re-search-forward', but skips over match in comments or strings."
1639 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1641 (re-search-forward REGEXP BOUND NOERROR)
1642 (setq mdata (match-data))
1643 (and (verilog-skip-forward-comment-or-string)
1645 (setq mdata '(nil nil))
1649 (store-match-data mdata)
1652 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1653 ; checkdoc-params: (REGEXP BOUND NOERROR)
1654 "Like `re-search-backward', but skips over match in comments or strings."
1655 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1657 (re-search-backward REGEXP BOUND NOERROR)
1658 (setq mdata (match-data))
1659 (and (verilog-skip-backward-comment-or-string)
1661 (setq mdata '(nil nil))
1665 (store-match-data mdata)
1668 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1669 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1670 but trashes match data and is faster for REGEXP that doesn't match often.
1671 This uses `verilog-scan' and text properties to ignore comments,
1672 so there may be a large up front penalty for the first search."
1674 (while (and (not pt)
1675 (re-search-forward regexp bound noerror))
1676 (if (verilog-inside-comment-or-string-p)
1677 (re-search-forward "[/\"\n]" nil t) ;; Only way a comment or quote can end
1678 (setq pt (match-end 0))))
1681 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1682 ; checkdoc-params: (REGEXP BOUND NOERROR)
1683 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1684 but trashes match data and is faster for REGEXP that doesn't match often.
1685 This uses `verilog-scan' and text properties to ignore comments,
1686 so there may be a large up front penalty for the first search."
1688 (while (and (not pt)
1689 (re-search-backward regexp bound noerror))
1690 (if (verilog-inside-comment-or-string-p)
1691 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
1692 (setq pt (match-beginning 0))))
1695 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1696 "Like `re-search-forward', but first search for SUBSTR constant.
1697 Then searched for the normal REGEXP (which contains SUBSTR), with given
1698 BOUND and NOERROR. The REGEXP must fit within a single line.
1699 This speeds up complicated regexp matches."
1700 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1701 ;; thus require matches to be on one line, and use beginning-of-line.
1703 (while (and (not done)
1704 (search-forward substr bound noerror))
1707 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1708 (unless (and (<= (match-beginning 0) (point))
1709 (>= (match-end 0) (point)))
1711 (when done (goto-char done))
1713 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1715 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1716 "Like `re-search-backward', but first search for SUBSTR constant.
1717 Then searched for the normal REGEXP (which contains SUBSTR), with given
1718 BOUND and NOERROR. The REGEXP must fit within a single line.
1719 This speeds up complicated regexp matches."
1720 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1721 ;; thus require matches to be on one line, and use beginning-of-line.
1723 (while (and (not done)
1724 (search-backward substr bound noerror))
1727 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1728 (unless (and (<= (match-beginning 0) (point))
1729 (>= (match-end 0) (point)))
1731 (when done (goto-char done))
1733 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1735 (defun verilog-delete-trailing-whitespace ()
1736 "Delete trailing spaces or tabs, but not newlines nor linefeeds.
1737 Also add missing final newline.
1739 To call this from the command line, see \\[verilog-batch-diff-auto].
1741 To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
1742 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1744 (goto-char (point-min))
1745 (while (re-search-forward "[ \t]+$" nil t) ;; Not syntactic WS as no formfeed
1746 (replace-match "" nil nil))
1747 (goto-char (point-max))
1748 (unless (bolp) (insert "\n"))))
1750 (defvar compile-command)
1752 ;; compilation program
1753 (defun verilog-set-compile-command ()
1754 "Function to compute shell command to compile Verilog.
1756 This reads `verilog-tool' and sets `compile-command'. This specifies the
1757 program that executes when you type \\[compile] or
1758 \\[verilog-auto-save-compile].
1760 By default `verilog-tool' uses a Makefile if one exists in the
1761 current directory. If not, it is set to the `verilog-linter',
1762 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1763 or `verilog-simulator' variables, as selected with the Verilog ->
1764 \"Choose Compilation Action\" menu.
1766 You should set `verilog-tool' or the other variables to the path and
1767 arguments for your Verilog simulator. For example:
1770 \"(cd /tmp; surecov %s)\".
1772 In the former case, the path to the current buffer is concat'ed to the
1773 value of `verilog-tool'; in the later, the path to the current buffer is
1774 substituted for the %s.
1776 Where __FLAGS__ appears in the string `verilog-current-flags'
1777 will be substituted.
1779 Where __FILE__ appears in the string, the variable
1780 `buffer-file-name' of the current buffer, without the directory
1781 portion, will be substituted."
1784 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1785 (file-exists-p "Makefile"))
1786 (set (make-local-variable 'compile-command) "make "))
1788 (set (make-local-variable 'compile-command)
1790 (if (string-match "%s" (eval verilog-tool))
1791 (format (eval verilog-tool) (or buffer-file-name ""))
1792 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1794 (verilog-modify-compile-command))
1796 (defun verilog-expand-command (command)
1797 "Replace meta-information in COMMAND and return it.
1798 Where __FLAGS__ appears in the string `verilog-current-flags'
1799 will be substituted. Where __FILE__ appears in the string, the
1800 current buffer's file-name, without the directory portion, will
1802 (setq command (verilog-string-replace-matches
1803 ;; Note \\b only works if under verilog syntax table
1804 "\\b__FLAGS__\\b" (verilog-current-flags)
1806 (setq command (verilog-string-replace-matches
1807 "\\b__FILE__\\b" (file-name-nondirectory
1808 (or (buffer-file-name) ""))
1812 (defun verilog-modify-compile-command ()
1813 "Update `compile-command' using `verilog-expand-command'."
1815 (stringp compile-command)
1816 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1817 (set (make-local-variable 'compile-command)
1818 (verilog-expand-command compile-command))))
1820 (if (featurep 'xemacs)
1821 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1822 (defun verilog-error-regexp-add-xemacs ()
1823 "Teach XEmacs about verilog errors.
1824 Called by `compilation-mode-hook'. This allows \\[next-error] to
1827 (if (boundp 'compilation-error-regexp-systems-alist)
1829 (not (equal compilation-error-regexp-systems-list 'all))
1830 (not (member compilation-error-regexp-systems-list 'verilog)))
1831 (push 'verilog compilation-error-regexp-systems-list)))
1832 (if (boundp 'compilation-error-regexp-alist-alist)
1833 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1834 (setcdr compilation-error-regexp-alist-alist
1835 (cons verilog-error-regexp-xemacs-alist
1836 (cdr compilation-error-regexp-alist-alist)))))
1837 (if (boundp 'compilation-font-lock-keywords)
1839 (set (make-local-variable 'compilation-font-lock-keywords)
1840 verilog-error-font-lock-keywords)
1841 (font-lock-set-defaults)))
1842 ;; Need to re-run compilation-error-regexp builder
1843 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1844 (compilation-build-compilation-error-regexp-alist))
1847 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1848 (defun verilog-error-regexp-add-emacs ()
1849 "Tell Emacs compile that we are Verilog.
1850 Called by `compilation-mode-hook'. This allows \\[next-error] to
1853 (if (boundp 'compilation-error-regexp-alist-alist)
1855 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1858 (push (car item) compilation-error-regexp-alist)
1859 (push item compilation-error-regexp-alist-alist)
1861 verilog-error-regexp-emacs-alist)))))
1863 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1864 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1866 (defconst verilog-directive-re
1868 (verilog-regexp-words
1870 "`case" "`default" "`define" "`else" "`elsif" "`endfor" "`endif"
1871 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1872 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1873 "`time_scale" "`undef" "`while" ))))
1875 (defconst verilog-directive-re-1
1876 (concat "[ \t]*" verilog-directive-re))
1878 (defconst verilog-directive-begin
1879 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1881 (defconst verilog-directive-middle
1882 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1884 (defconst verilog-directive-end
1885 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1887 (defconst verilog-ovm-begin-re
1891 "`ovm_component_utils_begin"
1892 "`ovm_component_param_utils_begin"
1893 "`ovm_field_utils_begin"
1894 "`ovm_object_utils_begin"
1895 "`ovm_object_param_utils_begin"
1896 "`ovm_sequence_utils_begin"
1897 "`ovm_sequencer_utils_begin"
1900 (defconst verilog-ovm-end-re
1904 "`ovm_component_utils_end"
1905 "`ovm_field_utils_end"
1906 "`ovm_object_utils_end"
1907 "`ovm_sequence_utils_end"
1908 "`ovm_sequencer_utils_end"
1911 (defconst verilog-uvm-begin-re
1915 "`uvm_component_utils_begin"
1916 "`uvm_component_param_utils_begin"
1917 "`uvm_field_utils_begin"
1918 "`uvm_object_utils_begin"
1919 "`uvm_object_param_utils_begin"
1920 "`uvm_sequence_utils_begin"
1921 "`uvm_sequencer_utils_begin"
1924 (defconst verilog-uvm-end-re
1928 "`uvm_component_utils_end"
1929 "`uvm_field_utils_end"
1930 "`uvm_object_utils_end"
1931 "`uvm_sequence_utils_end"
1932 "`uvm_sequencer_utils_end"
1935 (defconst verilog-vmm-begin-re
1939 "`vmm_data_member_begin"
1940 "`vmm_env_member_begin"
1941 "`vmm_scenario_member_begin"
1942 "`vmm_subenv_member_begin"
1943 "`vmm_xactor_member_begin"
1946 (defconst verilog-vmm-end-re
1950 "`vmm_data_member_end"
1951 "`vmm_env_member_end"
1952 "`vmm_scenario_member_end"
1953 "`vmm_subenv_member_end"
1954 "`vmm_xactor_member_end"
1957 (defconst verilog-vmm-statement-re
1961 ;; "`vmm_xactor_member_enum_array"
1962 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
1963 ;; "`vmm_xactor_member_scalar_array"
1964 ;; "`vmm_xactor_member_scalar"
1967 (defconst verilog-ovm-statement-re
1976 "`ovm_analysis_imp_decl"
1977 "`ovm_blocking_get_imp_decl"
1978 "`ovm_blocking_get_peek_imp_decl"
1979 "`ovm_blocking_master_imp_decl"
1980 "`ovm_blocking_peek_imp_decl"
1981 "`ovm_blocking_put_imp_decl"
1982 "`ovm_blocking_slave_imp_decl"
1983 "`ovm_blocking_transport_imp_decl"
1984 "`ovm_component_registry"
1985 "`ovm_component_registry_param"
1986 "`ovm_component_utils"
1989 "`ovm_declare_sequence_lib"
1996 "`ovm_field_aa_int_byte"
1997 "`ovm_field_aa_int_byte_unsigned"
1998 "`ovm_field_aa_int_int"
1999 "`ovm_field_aa_int_int_unsigned"
2000 "`ovm_field_aa_int_integer"
2001 "`ovm_field_aa_int_integer_unsigned"
2002 "`ovm_field_aa_int_key"
2003 "`ovm_field_aa_int_longint"
2004 "`ovm_field_aa_int_longint_unsigned"
2005 "`ovm_field_aa_int_shortint"
2006 "`ovm_field_aa_int_shortint_unsigned"
2007 "`ovm_field_aa_int_string"
2008 "`ovm_field_aa_object_int"
2009 "`ovm_field_aa_object_string"
2010 "`ovm_field_aa_string_int"
2011 "`ovm_field_aa_string_string"
2012 "`ovm_field_array_int"
2013 "`ovm_field_array_object"
2014 "`ovm_field_array_string"
2019 "`ovm_field_queue_int"
2020 "`ovm_field_queue_object"
2021 "`ovm_field_queue_string"
2022 "`ovm_field_sarray_int"
2027 "`ovm_get_peek_imp_decl"
2034 "`ovm_master_imp_decl"
2036 "`ovm_non_blocking_transport_imp_decl"
2037 "`ovm_nonblocking_get_imp_decl"
2038 "`ovm_nonblocking_get_peek_imp_decl"
2039 "`ovm_nonblocking_master_imp_decl"
2040 "`ovm_nonblocking_peek_imp_decl"
2041 "`ovm_nonblocking_put_imp_decl"
2042 "`ovm_nonblocking_slave_imp_decl"
2043 "`ovm_object_registry"
2044 "`ovm_object_registry_param"
2046 "`ovm_peek_imp_decl"
2047 "`ovm_phase_func_decl"
2048 "`ovm_phase_task_decl"
2049 "`ovm_print_aa_int_object"
2050 "`ovm_print_aa_string_int"
2051 "`ovm_print_aa_string_object"
2052 "`ovm_print_aa_string_string"
2053 "`ovm_print_array_int"
2054 "`ovm_print_array_object"
2055 "`ovm_print_array_string"
2056 "`ovm_print_object_queue"
2057 "`ovm_print_queue_int"
2058 "`ovm_print_string_queue"
2061 "`ovm_rand_send_with"
2063 "`ovm_sequence_utils"
2064 "`ovm_slave_imp_decl"
2065 "`ovm_transport_imp_decl"
2066 "`ovm_update_sequence_lib"
2067 "`ovm_update_sequence_lib_and_item"
2070 "`static_message") nil )))
2072 (defconst verilog-uvm-statement-re
2077 "`uvm_analysis_imp_decl"
2078 "`uvm_blocking_get_imp_decl"
2079 "`uvm_blocking_get_peek_imp_decl"
2080 "`uvm_blocking_master_imp_decl"
2081 "`uvm_blocking_peek_imp_decl"
2082 "`uvm_blocking_put_imp_decl"
2083 "`uvm_blocking_slave_imp_decl"
2084 "`uvm_blocking_transport_imp_decl"
2085 "`uvm_component_param_utils"
2086 "`uvm_component_registry"
2087 "`uvm_component_registry_param"
2088 "`uvm_component_utils"
2091 "`uvm_create_seq" ;; Undocumented in 1.1
2092 "`uvm_declare_p_sequencer"
2093 "`uvm_declare_sequence_lib" ;; Deprecated in 1.1
2096 "`uvm_do_callbacks_exit_on"
2097 "`uvm_do_obj_callbacks"
2098 "`uvm_do_obj_callbacks_exit_on"
2101 "`uvm_do_on_pri_with"
2105 "`uvm_do_seq" ;; Undocumented in 1.1
2106 "`uvm_do_seq_with" ;; Undocumented in 1.1
2109 "`uvm_error_context"
2111 "`uvm_fatal_context"
2112 "`uvm_field_aa_int_byte"
2113 "`uvm_field_aa_int_byte_unsigned"
2114 "`uvm_field_aa_int_enum"
2115 "`uvm_field_aa_int_int"
2116 "`uvm_field_aa_int_int_unsigned"
2117 "`uvm_field_aa_int_integer"
2118 "`uvm_field_aa_int_integer_unsigned"
2119 "`uvm_field_aa_int_key"
2120 "`uvm_field_aa_int_longint"
2121 "`uvm_field_aa_int_longint_unsigned"
2122 "`uvm_field_aa_int_shortint"
2123 "`uvm_field_aa_int_shortint_unsigned"
2124 "`uvm_field_aa_int_string"
2125 "`uvm_field_aa_object_int"
2126 "`uvm_field_aa_object_string"
2127 "`uvm_field_aa_string_int"
2128 "`uvm_field_aa_string_string"
2129 "`uvm_field_array_enum"
2130 "`uvm_field_array_int"
2131 "`uvm_field_array_object"
2132 "`uvm_field_array_string"
2137 "`uvm_field_queue_enum"
2138 "`uvm_field_queue_int"
2139 "`uvm_field_queue_object"
2140 "`uvm_field_queue_string"
2142 "`uvm_field_sarray_enum"
2143 "`uvm_field_sarray_int"
2144 "`uvm_field_sarray_object"
2145 "`uvm_field_sarray_string"
2148 "`uvm_file" ;; Undocumented in 1.1, use `__FILE__
2150 "`uvm_get_peek_imp_decl"
2153 "`uvm_line" ;; Undocumented in 1.1, use `__LINE__
2154 "`uvm_master_imp_decl"
2155 "`uvm_non_blocking_transport_imp_decl" ;; Deprecated in 1.1
2156 "`uvm_nonblocking_get_imp_decl"
2157 "`uvm_nonblocking_get_peek_imp_decl"
2158 "`uvm_nonblocking_master_imp_decl"
2159 "`uvm_nonblocking_peek_imp_decl"
2160 "`uvm_nonblocking_put_imp_decl"
2161 "`uvm_nonblocking_slave_imp_decl"
2162 "`uvm_nonblocking_transport_imp_decl"
2163 "`uvm_object_param_utils"
2164 "`uvm_object_registry"
2165 "`uvm_object_registry_param" ;; Undocumented in 1.1
2179 "`uvm_peek_imp_decl"
2182 "`uvm_rand_send_pri"
2183 "`uvm_rand_send_pri_with"
2184 "`uvm_rand_send_with"
2185 "`uvm_record_attribute"
2190 "`uvm_sequence_utils" ;; Deprecated in 1.1
2191 "`uvm_set_super_type"
2192 "`uvm_slave_imp_decl"
2193 "`uvm_transport_imp_decl"
2195 "`uvm_unpack_arrayN"
2201 "`uvm_unpack_queueN"
2203 "`uvm_unpack_sarray"
2204 "`uvm_unpack_sarrayN"
2205 "`uvm_unpack_string"
2206 "`uvm_update_sequence_lib" ;; Deprecated in 1.1
2207 "`uvm_update_sequence_lib_and_item" ;; Deprecated in 1.1
2209 "`uvm_warning_context") nil )))
2213 ;; Regular expressions used to calculate indent, etc.
2215 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2222 (defconst verilog-assignment-operator-re
2226 ;; blocking assignment_operator
2227 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2228 ;; non blocking assignment operator
2231 "==" "!=" "===" "!===" "<=" ">=" "==\?" "!=\?"
2236 ;; Is this a legal verilog operator?
2240 (defconst verilog-assignment-operation-re
2242 ; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2243 ; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2244 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2246 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2247 (defconst verilog-property-re
2248 (concat "\\(" verilog-label-re "\\)?"
2249 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2250 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2252 (defconst verilog-no-indent-begin-re
2253 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
2255 (defconst verilog-ends-re
2256 ;; Parenthesis indicate type of keyword found
2258 "\\(\\<else\\>\\)\\|" ; 1
2259 "\\(\\<if\\>\\)\\|" ; 2
2260 "\\(\\<assert\\>\\)\\|" ; 3
2261 "\\(\\<end\\>\\)\\|" ; 3.1
2262 "\\(\\<endcase\\>\\)\\|" ; 4
2263 "\\(\\<endfunction\\>\\)\\|" ; 5
2264 "\\(\\<endtask\\>\\)\\|" ; 6
2265 "\\(\\<endspecify\\>\\)\\|" ; 7
2266 "\\(\\<endtable\\>\\)\\|" ; 8
2267 "\\(\\<endgenerate\\>\\)\\|" ; 9
2268 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2269 "\\(\\<endclass\\>\\)\\|" ; 11
2270 "\\(\\<endgroup\\>\\)\\|" ; 12
2272 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2273 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2274 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2275 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2276 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2278 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2279 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2280 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2281 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2282 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2284 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2285 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2286 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2287 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2288 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2291 (defconst verilog-auto-end-comment-lines-re
2292 ;; Matches to names in this list cause auto-end-commenting
2294 verilog-directive-re "\\)\\|\\("
2296 (verilog-regexp-words
2324 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2325 ;;; verilog-end-block-ordered-re matches exactly the same strings.
2326 (defconst verilog-end-block-ordered-re
2327 ;; Parenthesis indicate type of keyword found
2328 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2329 "\\(\\<end\\>\\)\\|" ; 2
2330 "\\(\\<end" ; 3, but not used
2331 "\\(" ; 4, but not used
2332 "\\(function\\)\\|" ; 5
2334 "\\(module\\)\\|" ; 7
2335 "\\(primitive\\)\\|" ; 8
2336 "\\(interface\\)\\|" ; 9
2337 "\\(package\\)\\|" ; 10
2338 "\\(class\\)\\|" ; 11
2339 "\\(group\\)\\|" ; 12
2340 "\\(program\\)\\|" ; 13
2341 "\\(sequence\\)\\|" ; 14
2342 "\\(clocking\\)\\|" ; 15
2344 (defconst verilog-end-block-re
2346 (verilog-regexp-words
2348 `("end" ;; closes begin
2349 "endcase" ;; closes any of case, casex casez or randcase
2350 "join" "join_any" "join_none" ;; closes fork
2365 "`ovm_component_utils_end"
2366 "`ovm_field_utils_end"
2367 "`ovm_object_utils_end"
2368 "`ovm_sequence_utils_end"
2369 "`ovm_sequencer_utils_end"
2371 "`uvm_component_utils_end"
2372 "`uvm_field_utils_end"
2373 "`uvm_object_utils_end"
2374 "`uvm_sequence_utils_end"
2375 "`uvm_sequencer_utils_end"
2377 "`vmm_data_member_end"
2378 "`vmm_env_member_end"
2379 "`vmm_scenario_member_end"
2380 "`vmm_subenv_member_end"
2381 "`vmm_xactor_member_end"
2385 (defconst verilog-endcomment-reason-re
2386 ;; Parenthesis indicate type of keyword found
2388 "\\(\\<begin\\>\\)\\|" ; 1
2389 "\\(\\<else\\>\\)\\|" ; 2
2390 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2391 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" ; 4
2392 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" ; 5
2393 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" ; 6
2394 "\\(\\<fork\\>\\)\\|" ; 7
2395 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
2397 verilog-property-re "\\|"
2398 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2399 "\\(\\<clocking\\>\\)\\|"
2400 "\\(\\<task\\>\\)\\|"
2401 "\\(\\<function\\>\\)\\|"
2402 "\\(\\<initial\\>\\)\\|"
2403 "\\(\\<interface\\>\\)\\|"
2404 "\\(\\<package\\>\\)\\|"
2405 "\\(\\<final\\>\\)\\|"
2407 "\\(\\<while\\>\\)\\|"
2408 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2409 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2412 (defconst verilog-named-block-re "begin[ \t]*:")
2414 ;; These words begin a block which can occur inside a module which should be indented,
2415 ;; and closed with the respective word from the end-block list
2417 (defconst verilog-beg-block-re
2419 (verilog-regexp-words
2421 "case" "casex" "casez" "randcase"
2431 "`ovm_component_utils_begin"
2432 "`ovm_component_param_utils_begin"
2433 "`ovm_field_utils_begin"
2434 "`ovm_object_utils_begin"
2435 "`ovm_object_param_utils_begin"
2436 "`ovm_sequence_utils_begin"
2437 "`ovm_sequencer_utils_begin"
2439 "`uvm_component_utils_begin"
2440 "`uvm_component_param_utils_begin"
2441 "`uvm_field_utils_begin"
2442 "`uvm_object_utils_begin"
2443 "`uvm_object_param_utils_begin"
2444 "`uvm_sequence_utils_begin"
2445 "`uvm_sequencer_utils_begin"
2447 "`vmm_data_member_begin"
2448 "`vmm_env_member_begin"
2449 "`vmm_scenario_member_begin"
2450 "`vmm_subenv_member_begin"
2451 "`vmm_xactor_member_begin"
2453 ;; These are the same words, in a specific order in the regular
2454 ;; expression so that matching will work nicely for
2455 ;; verilog-forward-sexp and verilog-calc-indent
2456 (defconst verilog-beg-block-re-ordered
2457 ( concat "\\(\\<begin\\>\\)" ;1
2458 "\\|\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2459 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2460 "\\|\\(\\<class\\>\\)" ;6
2461 "\\|\\(\\<table\\>\\)" ;7
2462 "\\|\\(\\<specify\\>\\)" ;8
2463 "\\|\\(\\<function\\>\\)" ;9
2464 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2465 "\\|\\(\\<task\\>\\)" ;14
2466 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2467 "\\|\\(\\<generate\\>\\)" ;18
2468 "\\|\\(\\<covergroup\\>\\)" ;16 20
2469 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2470 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2471 "\\|\\(\\<clocking\\>\\)" ;22 27
2472 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2473 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2477 (defconst verilog-end-block-ordered-rry
2478 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2479 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2480 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2481 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2482 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2483 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2484 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2485 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2486 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2487 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2488 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2489 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2490 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2493 (defconst verilog-nameable-item-re
2495 (verilog-regexp-words
2498 "join" "join_any" "join_none"
2515 (defconst verilog-declaration-opener
2517 (verilog-regexp-words
2518 `("module" "begin" "task" "function"))))
2520 (defconst verilog-declaration-prefix-re
2522 (verilog-regexp-words
2525 "inout" "input" "output" "ref"
2527 "const" "static" "protected" "local"
2529 "localparam" "parameter" "var"
2533 (defconst verilog-declaration-core-re
2535 (verilog-regexp-words
2537 ;; port direction (by themselves)
2538 "inout" "input" "output"
2539 ;; integer_atom_type
2540 "byte" "shortint" "int" "longint" "integer" "time"
2541 ;; integer_vector_type
2544 "shortreal" "real" "realtime"
2546 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2548 "string" "event" "chandle" "virtual" "enum" "genvar"
2551 "mailbox" "semaphore"
2553 (defconst verilog-declaration-re
2554 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2555 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2556 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
2557 (defconst verilog-optional-signed-range-re
2559 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2560 (defconst verilog-macroexp-re "`\\sw+")
2562 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2563 (defconst verilog-declaration-re-2-no-macro
2564 (concat "\\s-*" verilog-declaration-re
2565 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2567 (defconst verilog-declaration-re-2-macro
2568 (concat "\\s-*" verilog-declaration-re
2569 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2570 "\\|\\(" verilog-macroexp-re "\\)"
2572 (defconst verilog-declaration-re-1-macro
2573 (concat "^" verilog-declaration-re-2-macro))
2575 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2577 (defconst verilog-defun-re
2578 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2579 (defconst verilog-end-defun-re
2580 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2581 (defconst verilog-zero-indent-re
2582 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2583 (defconst verilog-inst-comment-re
2584 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2586 (defconst verilog-behavioral-block-beg-re
2587 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2588 "function" "task"))))
2589 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2590 (defconst verilog-in-constraint-re ;; keywords legal in constraint blocks starting a statement/block
2591 (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
2593 (defconst verilog-indent-re
2595 (verilog-regexp-words
2598 "always" "always_latch" "always_ff" "always_comb"
2600 ; "unique" "priority"
2601 "case" "casex" "casez" "randcase" "endcase"
2603 "clocking" "endclocking"
2604 "config" "endconfig"
2605 "covergroup" "endgroup"
2606 "fork" "join" "join_any" "join_none"
2607 "function" "endfunction"
2609 "generate" "endgenerate"
2611 "interface" "endinterface"
2612 "module" "macromodule" "endmodule"
2613 "package" "endpackage"
2614 "primitive" "endprimitive"
2615 "program" "endprogram"
2616 "property" "endproperty"
2617 "sequence" "randsequence" "endsequence"
2618 "specify" "endspecify"
2625 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2626 "`while" "`endwhile"
2631 "`protect" "`endprotect"
2632 "`switch" "`endswitch"
2636 "`ovm_component_utils_begin"
2637 "`ovm_component_param_utils_begin"
2638 "`ovm_field_utils_begin"
2639 "`ovm_object_utils_begin"
2640 "`ovm_object_param_utils_begin"
2641 "`ovm_sequence_utils_begin"
2642 "`ovm_sequencer_utils_begin"
2644 "`ovm_component_utils_end"
2645 "`ovm_field_utils_end"
2646 "`ovm_object_utils_end"
2647 "`ovm_sequence_utils_end"
2648 "`ovm_sequencer_utils_end"
2650 "`uvm_component_utils_begin"
2651 "`uvm_component_param_utils_begin"
2652 "`uvm_field_utils_begin"
2653 "`uvm_object_utils_begin"
2654 "`uvm_object_param_utils_begin"
2655 "`uvm_sequence_utils_begin"
2656 "`uvm_sequencer_utils_begin"
2658 "`uvm_component_utils_end" ;; Typo in spec, it's not uvm_component_end
2659 "`uvm_field_utils_end"
2660 "`uvm_object_utils_end"
2661 "`uvm_sequence_utils_end"
2662 "`uvm_sequencer_utils_end"
2664 "`vmm_data_member_begin"
2665 "`vmm_env_member_begin"
2666 "`vmm_scenario_member_begin"
2667 "`vmm_subenv_member_begin"
2668 "`vmm_xactor_member_begin"
2670 "`vmm_data_member_end"
2671 "`vmm_env_member_end"
2672 "`vmm_scenario_member_end"
2673 "`vmm_subenv_member_end"
2674 "`vmm_xactor_member_end"
2677 (defconst verilog-defun-level-not-generate-re
2679 (verilog-regexp-words
2680 `( "module" "macromodule" "primitive" "class" "program"
2681 "interface" "package" "config"))))
2683 (defconst verilog-defun-level-re
2685 (verilog-regexp-words
2687 `( "module" "macromodule" "primitive" "class" "program"
2688 "interface" "package" "config")
2689 `( "initial" "final" "always" "always_comb" "always_ff"
2690 "always_latch" "endtask" "endfunction" )))))
2692 (defconst verilog-defun-level-generate-only-re
2694 (verilog-regexp-words
2695 `( "initial" "final" "always" "always_comb" "always_ff"
2696 "always_latch" "endtask" "endfunction" ))))
2698 (defconst verilog-cpp-level-re
2700 (verilog-regexp-words
2702 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2704 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2705 (defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
2706 (defconst verilog-extended-complete-re
2707 (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
2708 "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
2709 "\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<pure\\>\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
2710 "\\|" verilog-extended-case-re ))
2711 (defconst verilog-basic-complete-re
2713 (verilog-regexp-words
2715 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2716 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2717 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2719 (defconst verilog-complete-reg
2721 verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
2723 (defconst verilog-end-statement-re
2724 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2725 verilog-end-block-re "\\)"))
2727 (defconst verilog-endcase-re
2728 (concat verilog-extended-case-re "\\|"
2733 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2734 "String used to mark beginning of excluded text.")
2735 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2736 "String used to mark end of excluded text.")
2737 (defconst verilog-preprocessor-re
2739 (verilog-regexp-words
2741 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
2744 (defconst verilog-keywords
2745 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
2746 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
2747 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
2748 "`time_scale" "`undef" "`while"
2750 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2751 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2752 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2753 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2754 "config" "const" "constraint" "context" "continue" "cover"
2755 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2756 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2757 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2758 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2759 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2760 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2761 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2762 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2763 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2764 "include" "initial" "inout" "input" "inside" "instance" "int"
2765 "integer" "interface" "intersect" "join" "join_any" "join_none"
2766 "large" "liblist" "library" "local" "localparam" "logic"
2767 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2768 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2769 "notif0" "notif1" "null" "or" "output" "package" "packed"
2770 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2771 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2772 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2773 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2774 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2775 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2776 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2777 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2778 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2779 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2780 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2781 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2782 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2783 "wire" "with" "within" "wor" "xnor" "xor"
2785 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2786 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2787 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2788 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2790 "implements" "interconnect" "nettype" "soft"
2792 "List of Verilog keywords.")
2794 (defconst verilog-comment-start-regexp "//\\|/\\*"
2795 "Dual comment value for `comment-start-regexp'.")
2797 (defvar verilog-mode-syntax-table
2798 (let ((table (make-syntax-table)))
2799 ;; Populate the syntax TABLE.
2800 (modify-syntax-entry ?\\ "\\" table)
2801 (modify-syntax-entry ?+ "." table)
2802 (modify-syntax-entry ?- "." table)
2803 (modify-syntax-entry ?= "." table)
2804 (modify-syntax-entry ?% "." table)
2805 (modify-syntax-entry ?< "." table)
2806 (modify-syntax-entry ?> "." table)
2807 (modify-syntax-entry ?& "." table)
2808 (modify-syntax-entry ?| "." table)
2809 ;; FIXME: This goes against Emacs conventions. Use "_" syntax instead and
2810 ;; then use regexps with things like "\\_<...\\_>".
2811 (modify-syntax-entry ?` "w" table) ;; ` is part of definition symbols in Verilog
2812 (modify-syntax-entry ?_ "w" table)
2813 (modify-syntax-entry ?\' "." table)
2815 ;; Set up TABLE to handle block and line style comments.
2816 (if (featurep 'xemacs)
2818 ;; XEmacs (formerly Lucid) has the best implementation
2819 (modify-syntax-entry ?/ ". 1456" table)
2820 (modify-syntax-entry ?* ". 23" table)
2821 (modify-syntax-entry ?\n "> b" table))
2822 ;; Emacs does things differently, but we can work with it
2823 (modify-syntax-entry ?/ ". 124b" table)
2824 (modify-syntax-entry ?* ". 23" table)
2825 (modify-syntax-entry ?\n "> b" table))
2827 "Syntax table used in Verilog mode buffers.")
2829 (defvar verilog-font-lock-keywords nil
2830 "Default highlighting for Verilog mode.")
2832 (defvar verilog-font-lock-keywords-1 nil
2833 "Subdued level highlighting for Verilog mode.")
2835 (defvar verilog-font-lock-keywords-2 nil
2836 "Medium level highlighting for Verilog mode.
2837 See also `verilog-font-lock-extra-types'.")
2839 (defvar verilog-font-lock-keywords-3 nil
2840 "Gaudy level highlighting for Verilog mode.
2841 See also `verilog-font-lock-extra-types'.")
2843 (defvar verilog-font-lock-translate-off-face
2844 'verilog-font-lock-translate-off-face
2845 "Font to use for translated off regions.")
2846 (defface verilog-font-lock-translate-off-face
2849 (:background "gray90" :italic t ))
2852 (:background "gray10" :italic t ))
2853 (((class grayscale) (background light))
2854 (:foreground "DimGray" :italic t))
2855 (((class grayscale) (background dark))
2856 (:foreground "LightGray" :italic t))
2858 "Font lock mode face used to background highlight translate-off regions."
2859 :group 'font-lock-highlighting-faces)
2861 (defvar verilog-font-lock-p1800-face
2862 'verilog-font-lock-p1800-face
2863 "Font to use for p1800 keywords.")
2864 (defface verilog-font-lock-p1800-face
2867 (:foreground "DarkOrange3" :bold t ))
2870 (:foreground "orange1" :bold t ))
2872 "Font lock mode face used to highlight P1800 keywords."
2873 :group 'font-lock-highlighting-faces)
2875 (defvar verilog-font-lock-ams-face
2876 'verilog-font-lock-ams-face
2877 "Font to use for Analog/Mixed Signal keywords.")
2878 (defface verilog-font-lock-ams-face
2881 (:foreground "Purple" :bold t ))
2884 (:foreground "orange1" :bold t ))
2886 "Font lock mode face used to highlight AMS keywords."
2887 :group 'font-lock-highlighting-faces)
2889 (defvar verilog-font-grouping-keywords-face
2890 'verilog-font-lock-grouping-keywords-face
2891 "Font to use for Verilog Grouping Keywords (such as begin..end).")
2892 (defface verilog-font-lock-grouping-keywords-face
2895 (:foreground "red4" :bold t ))
2898 (:foreground "red4" :bold t ))
2900 "Font lock mode face used to highlight verilog grouping keywords."
2901 :group 'font-lock-highlighting-faces)
2903 (let* ((verilog-type-font-keywords
2907 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
2908 "event" "genvar" "inout" "input" "integer" "localparam"
2909 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
2910 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
2911 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
2912 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
2913 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
2914 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
2915 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
2918 (verilog-pragma-keywords
2921 '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
2924 (verilog-1800-2005-keywords
2927 '("alias" "assert" "assume" "automatic" "before" "bind"
2928 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
2929 "clocking" "config" "const" "constraint" "context" "continue"
2930 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
2931 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
2932 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
2933 "expect" "export" "extends" "extern" "first_match" "foreach"
2934 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
2935 "illegal_bins" "import" "incdir" "include" "inside" "instance"
2936 "int" "intersect" "large" "liblist" "library" "local" "longint"
2937 "matches" "medium" "modport" "new" "noshowcancelled" "null"
2938 "packed" "program" "property" "protected" "pull0" "pull1"
2939 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2940 "randcase" "randsequence" "ref" "release" "return" "scalared"
2941 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
2942 "specparam" "static" "string" "strong0" "strong1" "struct"
2943 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
2944 "type" "union" "unsigned" "use" "var" "virtual" "void"
2945 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
2948 (verilog-1800-2009-keywords
2951 '("accept_on" "checker" "endchecker" "eventually" "global"
2952 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
2953 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
2954 "sync_accept_on" "sync_reject_on" "unique0" "until"
2955 "until_with" "untyped" "weak" ) nil )))
2957 (verilog-1800-2012-keywords
2960 '("implements" "interconnect" "nettype" "soft" ) nil )))
2962 (verilog-ams-keywords
2965 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
2966 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
2967 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
2968 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
2969 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
2970 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
2971 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
2972 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
2973 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
2974 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
2975 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2977 (verilog-font-keywords
2981 "assign" "case" "casex" "casez" "randcase" "deassign"
2982 "default" "disable" "else" "endcase" "endfunction"
2983 "endgenerate" "endinterface" "endmodule" "endprimitive"
2984 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2985 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2986 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2987 "package" "endpackage" "always" "always_comb" "always_ff"
2988 "always_latch" "posedge" "primitive" "priority" "release"
2989 "repeat" "specify" "table" "task" "unique" "wait" "while"
2990 "class" "program" "endclass" "endprogram"
2993 (verilog-font-grouping-keywords
2996 '( "begin" "end" ) nil ))))
2998 (setq verilog-font-lock-keywords
3000 ;; Fontify all builtin keywords
3001 (concat "\\<\\(" verilog-font-keywords "\\|"
3002 ;; And user/system tasks and functions
3003 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
3005 ;; Fontify all types
3006 (if verilog-highlight-grouping-keywords
3007 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3008 'verilog-font-lock-ams-face)
3009 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3010 'font-lock-type-face))
3011 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
3012 'font-lock-type-face)
3013 ;; Fontify IEEE-1800-2005 keywords appropriately
3014 (if verilog-highlight-p1800-keywords
3015 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3016 'verilog-font-lock-p1800-face)
3017 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3018 'font-lock-type-face))
3019 ;; Fontify IEEE-1800-2009 keywords appropriately
3020 (if verilog-highlight-p1800-keywords
3021 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3022 'verilog-font-lock-p1800-face)
3023 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3024 'font-lock-type-face))
3025 ;; Fontify IEEE-1800-2012 keywords appropriately
3026 (if verilog-highlight-p1800-keywords
3027 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3028 'verilog-font-lock-p1800-face)
3029 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3030 'font-lock-type-face))
3031 ;; Fontify Verilog-AMS keywords
3032 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
3033 'verilog-font-lock-ams-face)))
3035 (setq verilog-font-lock-keywords-1
3036 (append verilog-font-lock-keywords
3038 ;; Fontify module definitions
3040 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
3041 '(1 font-lock-keyword-face)
3042 '(3 font-lock-function-name-face 'prepend))
3043 ;; Fontify function definitions
3045 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
3046 '(1 font-lock-keyword-face)
3047 '(3 font-lock-constant-face prepend))
3048 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
3049 (1 font-lock-keyword-face)
3050 (2 font-lock-constant-face append))
3051 '("\\<function\\>\\s-+\\(\\sw+\\)"
3052 1 'font-lock-constant-face append))))
3054 (setq verilog-font-lock-keywords-2
3055 (append verilog-font-lock-keywords-1
3058 (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
3059 ;; Fontify escaped names
3060 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
3061 ;; Fontify macro definitions/ uses
3062 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
3063 'font-lock-preprocessor-face
3064 'font-lock-type-face))
3065 ;; Fontify delays/numbers
3066 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
3067 0 font-lock-type-face append)
3068 ;; Fontify instantiation names
3069 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
3072 (setq verilog-font-lock-keywords-3
3073 (append verilog-font-lock-keywords-2
3074 (when verilog-highlight-translate-off
3076 ;; Fontify things in translate off regions
3077 '(verilog-match-translate-off
3078 (0 'verilog-font-lock-translate-off-face prepend))
3082 ;; Buffer state preservation
3084 (defmacro verilog-save-buffer-state (&rest body)
3085 "Execute BODY forms, saving state around insignificant change.
3086 Changes in text properties like `face' or `syntax-table' are
3087 considered insignificant. This macro allows text properties to
3088 be changed, even in a read-only buffer.
3090 A change is considered significant if it affects the buffer text
3091 in any way that isn't completely restored again. Any
3092 user-visible changes to the buffer must not be within a
3093 `verilog-save-buffer-state'."
3094 ;; From c-save-buffer-state
3095 `(let* ((modified (buffer-modified-p))
3096 (buffer-undo-list t)
3097 (inhibit-read-only t)
3098 (inhibit-point-motion-hooks t)
3099 (verilog-no-change-functions t)
3100 before-change-functions
3101 after-change-functions
3103 buffer-file-name ; Prevent primitives checking
3104 buffer-file-truename) ; for file modification
3109 (set-buffer-modified-p nil)))))
3111 (defmacro verilog-save-no-change-functions (&rest body)
3112 "Execute BODY forms, disabling all change hooks in BODY.
3113 For insignificant changes, see instead `verilog-save-buffer-state'."
3114 `(let* ((inhibit-point-motion-hooks t)
3115 (verilog-no-change-functions t)
3116 before-change-functions
3117 after-change-functions)
3120 (defvar verilog-save-font-mod-hooked nil
3121 "Local variable when inside a `verilog-save-font-mods' block.")
3122 (make-variable-buffer-local 'verilog-save-font-mod-hooked)
3124 (defmacro verilog-save-font-mods (&rest body)
3125 "Execute BODY forms, disabling text modifications to allow performing BODY.
3126 Includes temporary disabling of `font-lock' to restore the buffer
3127 to full text form for parsing. Additional actions may be specified with
3128 `verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
3129 ;; Before version 20, match-string with font-lock returns a
3130 ;; vector that is not equal to the string. IE if on "input"
3131 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
3132 `(let* ((hooked (unless verilog-save-font-mod-hooked
3133 (verilog-run-hooks 'verilog-before-save-font-hook)
3135 (verilog-save-font-mod-hooked t)
3136 (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
3142 (when fontlocked (font-lock-mode t))
3143 (when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
3146 ;; Comment detection and caching
3148 (defvar verilog-scan-cache-preserving nil
3149 "If true, the specified buffer's comment properties are static.
3150 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3151 and `verilog-scan'.")
3153 (defvar verilog-scan-cache-tick nil
3154 "Modification tick at which `verilog-scan' was last completed.")
3155 (make-variable-buffer-local 'verilog-scan-cache-tick)
3157 (defun verilog-scan-cache-flush ()
3158 "Flush the `verilog-scan' cache."
3159 (setq verilog-scan-cache-tick nil))
3161 (defun verilog-scan-cache-ok-p ()
3162 "Return t iff the scan cache is up to date."
3163 (or (and verilog-scan-cache-preserving
3164 (eq verilog-scan-cache-preserving (current-buffer))
3165 verilog-scan-cache-tick)
3166 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3168 (defmacro verilog-save-scan-cache (&rest body)
3169 "Execute the BODY forms, allowing scan cache preservation within BODY.
3170 This requires that insertions must use `verilog-insert'."
3171 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3172 ;; Note this must work properly if there's multiple layers of calls
3173 ;; to verilog-save-scan-cache even with differing ticks.
3175 (unless (verilog-scan-cache-ok-p) ;; Must be before let
3176 (setq verilog-scan-cache-tick nil))
3177 (let* ((verilog-scan-cache-preserving (current-buffer)))
3180 (defun verilog-scan-region (beg end)
3181 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3182 This creates v-cmts properties where comments are in force."
3183 ;; Why properties and not overlays? Overlays have much slower non O(1)
3185 ;; This function is warm - called on every verilog-insert
3188 (verilog-save-buffer-state
3191 (while (< (point) end)
3192 (cond ((looking-at "//")
3194 (or (search-forward "\n" end t)
3196 ;; "1+": The leading // or /* itself isn't considered as
3197 ;; being "inside" the comment, so that a (search-backward)
3198 ;; that lands at the start of the // won't mis-indicate
3199 ;; it's inside a comment. Also otherwise it would be
3200 ;; hard to find a commented out /*AS*/ vs one that isn't
3201 (put-text-property (1+ pt) (point) 'v-cmts t))
3202 ((looking-at "/\\*")
3204 (or (search-forward "*/" end t)
3205 ;; No error - let later code indicate it so we can
3206 ;; use inside functions on-the-fly
3207 ;;(error "%s: Unmatched /* */, at char %d"
3208 ;; (verilog-point-text) (point))
3210 (put-text-property (1+ pt) (point) 'v-cmts t))
3213 (or (re-search-forward "[^\\]\"" end t) ;; don't forward-char first, since we look for a non backslash first
3214 ;; No error - let later code indicate it so we can
3216 (put-text-property (1+ pt) (point) 'v-cmts t))
3219 (if (re-search-forward "[/\"]" end t)
3221 (goto-char end))))))))))
3223 (defun verilog-scan ()
3224 "Parse the buffer, marking all comments with properties.
3225 Also assumes any text inserted since `verilog-scan-cache-tick'
3226 either is ok to parse as a non-comment, or `verilog-insert' was used."
3227 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3228 (unless (verilog-scan-cache-ok-p)
3230 (verilog-save-buffer-state
3232 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3233 verilog-scan-cache-preserving verilog-scan-cache-tick
3234 (buffer-chars-modified-tick)))
3235 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3236 (verilog-scan-region (point-min) (point-max))
3237 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3238 (when verilog-debug (message "Scanning... done"))))))
3240 (defun verilog-scan-debug ()
3241 "For debugging, show with display face results of `verilog-scan'."
3243 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3245 (goto-char (point-min))
3246 (remove-text-properties (point-min) (point-max) '(face nil))
3248 (cond ((get-text-property (point) 'v-cmts)
3249 (put-text-property (point) (1+ (point)) `face 'underline)
3250 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3253 (goto-char (or (next-property-change (point)) (point-max))))))))
3255 (defun verilog-scan-and-debug ()
3256 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3257 (let (verilog-scan-cache-preserving
3258 verilog-scan-cache-tick)
3259 (goto-char (point-min))
3261 (verilog-scan-debug)))
3263 (defun verilog-inside-comment-or-string-p (&optional pos)
3264 "Check if optional point POS is inside a comment.
3265 This may require a slow pre-parse of the buffer with `verilog-scan'
3266 to establish comment properties on all text."
3267 ;; This function is very hot
3270 (and (>= pos (point-min))
3271 (get-text-property pos 'v-cmts))
3272 (get-text-property (point) 'v-cmts)))
3274 (defun verilog-insert (&rest stuff)
3275 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3276 Any insert that includes a comment must have the entire comment
3277 inserted using a single call to `verilog-insert'."
3280 (insert (car stuff))
3281 (setq stuff (cdr stuff)))
3282 (verilog-scan-region pt (point))))
3286 (defun verilog-declaration-end ()
3287 (search-forward ";"))
3289 (defun verilog-point-text (&optional pointnum)
3290 "Return text describing where POINTNUM or current point is (for errors).
3291 Use filename, if current buffer being edited shorten to just buffer name."
3292 (concat (or (and (equal (window-buffer) (current-buffer))
3296 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3298 (defun electric-verilog-backward-sexp ()
3299 "Move backward over one balanced expression."
3301 ;; before that see if we are in a comment
3302 (verilog-backward-sexp))
3304 (defun electric-verilog-forward-sexp ()
3305 "Move forward over one balanced expression."
3307 ;; before that see if we are in a comment
3308 (verilog-forward-sexp))
3310 ;;;used by hs-minor-mode
3311 (defun verilog-forward-sexp-function (arg)
3313 (verilog-backward-sexp)
3314 (verilog-forward-sexp)))
3317 (defun verilog-backward-sexp ()
3322 (if (not (looking-at "\\<"))
3325 ((verilog-skip-backward-comment-or-string))
3326 ((looking-at "\\<else\\>")
3328 verilog-end-block-re
3329 "\\|\\(\\<else\\>\\)"
3330 "\\|\\(\\<if\\>\\)"))
3331 (while (and (not found)
3332 (verilog-re-search-backward reg nil 'move))
3334 ((match-end 1) ; matched verilog-end-block-re
3335 ; try to leap back to matching outward block by striding across
3336 ; indent level changing tokens then immediately
3337 ; previous line governs indentation.
3338 (verilog-leap-to-head))
3339 ((match-end 2) ; else, we're in deep
3340 (setq elsec (1+ elsec)))
3341 ((match-end 3) ; found it
3342 (setq elsec (1- elsec))
3344 ;; Now previous line describes syntax
3345 (setq found 't))))))
3346 ((looking-at verilog-end-block-re)
3347 (verilog-leap-to-head))
3348 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3351 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3353 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3355 (verilog-re-search-backward "\\<class\\>" nil 'move))
3357 (verilog-re-search-backward "\\<program\\>" nil 'move))
3359 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3361 (verilog-re-search-backward "\\<package\\>" nil 'move))
3364 (backward-sexp 1))))
3369 (defun verilog-forward-sexp ()
3374 (if (not (looking-at "\\<"))
3377 ((verilog-skip-forward-comment-or-string)
3378 (verilog-forward-syntactic-ws))
3379 ((looking-at verilog-beg-block-re-ordered)
3382 ;; Search forward for matching end
3383 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3385 ;; Search forward for matching endcase
3386 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique0?\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3387 (setq md 3) ;; ender is third item in regexp
3390 ;; might be "disable fork" or "wait fork"
3394 (looking-at verilog-disable-fork-re)
3395 (and (looking-at "fork")
3397 (setq here (point)) ;; sometimes a fork is just a fork
3399 (looking-at verilog-disable-fork-re))))
3400 (progn ;; it is a disable fork; ignore it
3401 (goto-char (match-end 0))
3404 (progn ;; it is a nice simple fork
3405 (goto-char here) ;; return from looking for "disable fork"
3406 ;; Search forward for matching join
3407 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3409 ;; Search forward for matching endclass
3410 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3413 ;; Search forward for matching endtable
3414 (setq reg "\\<endtable\\>" )
3417 ;; Search forward for matching endspecify
3418 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3420 ;; Search forward for matching endfunction
3421 (setq reg "\\<endfunction\\>" )
3424 ;; Search forward for matching endfunction
3425 (setq reg "\\<endfunction\\>" )
3428 ;; Search forward for matching endtask
3429 (setq reg "\\<endtask\\>" )
3432 ;; Search forward for matching endtask
3433 (setq reg "\\<endtask\\>" )
3436 ;; Search forward for matching endgenerate
3437 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3439 ;; Search forward for matching endgroup
3440 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3442 ;; Search forward for matching endproperty
3443 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3445 ;; Search forward for matching endsequence
3446 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3447 (setq md 3)) ; 3 to get to endsequence in the reg above
3449 ;; Search forward for matching endclocking
3450 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3457 (while (verilog-re-search-forward reg nil 'move)
3459 ((match-end md) ; a closer in regular expression, so we are climbing out
3460 (setq depth (1- depth))
3461 (if (= 0 depth) ; we are out!
3463 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3464 (setq here (point)) ; remember where we started
3465 (goto-char (match-beginning 1))
3468 (looking-at verilog-disable-fork-re)
3469 (and (looking-at "fork")
3472 (looking-at verilog-disable-fork-re))))
3473 (progn ;; it is a disable fork; another false alarm
3474 (goto-char (match-end 0)))
3475 (progn ;; it is a simple fork (or has nothing to do with fork)
3477 (setq depth (1+ depth))))))))))
3478 (if (verilog-re-search-forward reg nil 'move)
3479 (throw 'skip 1))))))
3481 ((looking-at (concat
3482 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3483 "\\(\\<primitive\\>\\)\\|"
3484 "\\(\\<class\\>\\)\\|"
3485 "\\(\\<program\\>\\)\\|"
3486 "\\(\\<interface\\>\\)\\|"
3487 "\\(\\<package\\>\\)"))
3490 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3492 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3494 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3496 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3498 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3500 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3503 (if (= (following-char) ?\) )
3505 (forward-sexp 1)))))
3508 (if (= (following-char) ?\) )
3510 (forward-sexp 1))))))
3512 (defun verilog-declaration-beg ()
3513 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3519 (defvar verilog-which-tool 1)
3521 (define-derived-mode verilog-mode prog-mode "Verilog"
3522 "Major mode for editing Verilog code.
3523 \\<verilog-mode-map>
3524 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3525 AUTOs can improve coding efficiency.
3527 Use \\[verilog-faq] for a pointer to frequently asked questions.
3529 NEWLINE, TAB indents for Verilog code.
3530 Delete converts tabs to spaces as it moves back.
3532 Supports highlighting.
3534 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3535 with no args, if that value is non-nil.
3537 Variables controlling indentation/edit style:
3539 variable `verilog-indent-level' (default 3)
3540 Indentation of Verilog statements with respect to containing block.
3541 `verilog-indent-level-module' (default 3)
3542 Absolute indentation of Module level Verilog statements.
3543 Set to 0 to get initial and always statements lined up
3544 on the left side of your screen.
3545 `verilog-indent-level-declaration' (default 3)
3546 Indentation of declarations with respect to containing block.
3547 Set to 0 to get them list right under containing block.
3548 `verilog-indent-level-behavioral' (default 3)
3549 Indentation of first begin in a task or function block
3550 Set to 0 to get such code to lined up underneath the task or
3552 `verilog-indent-level-directive' (default 1)
3553 Indentation of `ifdef/`endif blocks.
3554 `verilog-cexp-indent' (default 1)
3555 Indentation of Verilog statements broken across lines i.e.:
3558 `verilog-case-indent' (default 2)
3559 Indentation for case statements.
3560 `verilog-auto-newline' (default nil)
3561 Non-nil means automatically newline after semicolons and the punctuation
3563 `verilog-auto-indent-on-newline' (default t)
3564 Non-nil means automatically indent line after newline.
3565 `verilog-tab-always-indent' (default t)
3566 Non-nil means TAB in Verilog mode should always reindent the current line,
3567 regardless of where in the line point is when the TAB command is used.
3568 `verilog-indent-begin-after-if' (default t)
3569 Non-nil means to indent begin statements following a preceding
3570 if, else, while, for and repeat statements, if any. Otherwise,
3571 the begin is lined up with the preceding token. If t, you get:
3573 begin // amount of indent based on `verilog-cexp-indent'
3577 `verilog-auto-endcomments' (default t)
3578 Non-nil means a comment /* ... */ is set after the ends which ends
3579 cases, tasks, functions and modules.
3580 The type and name of the object will be set between the braces.
3581 `verilog-minimum-comment-distance' (default 10)
3582 Minimum distance (in lines) between begin and end required before a comment
3583 will be inserted. Setting this variable to zero results in every
3584 end acquiring a comment; the default avoids too many redundant
3585 comments in tight quarters.
3586 `verilog-auto-lineup' (default 'declarations)
3587 List of contexts where auto lineup of code should be done.
3589 Variables controlling other actions:
3591 `verilog-linter' (default surelint)
3592 Unix program to call to run the lint checker. This is the default
3593 command for \\[compile-command] and \\[verilog-auto-save-compile].
3595 See \\[customize] for the complete list of variables.
3597 AUTO expansion functions are, in part:
3599 \\[verilog-auto] Expand AUTO statements.
3600 \\[verilog-delete-auto] Remove the AUTOs.
3601 \\[verilog-inject-auto] Insert AUTOs for the first time.
3603 Some other functions are:
3605 \\[verilog-complete-word] Complete word with appropriate possibilities.
3606 \\[verilog-mark-defun] Mark function.
3607 \\[verilog-beg-of-defun] Move to beginning of current function.
3608 \\[verilog-end-of-defun] Move to end of current function.
3609 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3611 \\[verilog-comment-region] Put marked area in a comment.
3612 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3613 \\[verilog-insert-block] Insert begin ... end.
3614 \\[verilog-star-comment] Insert /* ... */.
3616 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3617 \\[verilog-sk-begin] Insert a begin .. end block.
3618 \\[verilog-sk-case] Insert a case block, prompting for details.
3619 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3620 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3621 \\[verilog-sk-header] Insert a header block at the top of file.
3622 \\[verilog-sk-initial] Insert an initial begin .. end block.
3623 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3624 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3625 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3626 \\[verilog-sk-uvm-object] Insert an UVM Object block.
3627 \\[verilog-sk-uvm-component] Insert an UVM Component block.
3628 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3629 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3630 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3631 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3632 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3633 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3634 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3635 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3636 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3637 \\[verilog-sk-comment] Insert a comment block.
3638 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3639 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3640 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3641 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3642 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3643 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3644 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3645 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3646 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3648 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3649 Key bindings specific to `verilog-mode-map' are:
3651 \\{verilog-mode-map}"
3652 :abbrev-table verilog-mode-abbrev-table
3653 (set (make-local-variable 'beginning-of-defun-function)
3654 'verilog-beg-of-defun)
3655 (set (make-local-variable 'end-of-defun-function)
3656 'verilog-end-of-defun)
3657 (set-syntax-table verilog-mode-syntax-table)
3658 (set (make-local-variable 'indent-line-function)
3659 #'verilog-indent-line-relative)
3660 (set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
3661 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3662 (set (make-local-variable 'comment-start) "// ")
3663 (set (make-local-variable 'comment-end) "")
3664 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3665 (set (make-local-variable 'comment-multi-line) nil)
3666 ;; Set up for compilation
3667 (setq verilog-which-tool 1)
3668 (setq verilog-tool 'verilog-linter)
3669 (verilog-set-compile-command)
3670 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
3671 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3674 (when (featurep 'xemacs)
3675 (easy-menu-add verilog-stmt-menu)
3676 (easy-menu-add verilog-menu)
3677 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3679 ;; Stuff for GNU Emacs
3680 (set (make-local-variable 'font-lock-defaults)
3681 `((verilog-font-lock-keywords
3682 verilog-font-lock-keywords-1
3683 verilog-font-lock-keywords-2
3684 verilog-font-lock-keywords-3)
3686 ,(if (functionp 'syntax-ppss)
3687 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3688 ;; font-lock-beginning-of-syntax-function, so
3689 ;; font-lock-beginning-of-syntax-function, can't use
3690 ;; verilog-beg-of-defun.
3692 'verilog-beg-of-defun)))
3693 ;;------------------------------------------------------------
3694 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3695 ;; all buffer local:
3696 (unless noninteractive ;; Else can't see the result, and change hooks are slow
3697 (when (featurep 'xemacs)
3698 (make-local-hook 'font-lock-mode-hook)
3699 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3700 (make-local-hook 'after-change-functions))
3701 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3702 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3703 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3705 ;; Tell imenu how to handle Verilog.
3706 (set (make-local-variable 'imenu-generic-expression)
3707 verilog-imenu-generic-expression)
3708 ;; Tell which-func-modes that imenu knows about verilog
3709 (when (and (boundp 'which-func-modes) (listp which-func-modes))
3710 (add-to-list 'which-func-modes 'verilog-mode))
3712 (when (boundp 'hs-special-modes-alist)
3713 (unless (assq 'verilog-mode hs-special-modes-alist)
3714 (setq hs-special-modes-alist
3715 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3716 verilog-forward-sexp-function)
3717 hs-special-modes-alist))))
3720 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3721 ;; verilog-mode-hook call added by define-derived-mode
3726 ;; Electric functions
3728 (defun electric-verilog-terminate-line (&optional arg)
3729 "Terminate line and indent next line.
3730 With optional ARG, remove existing end of line comments."
3732 ;; before that see if we are in a comment
3733 (let ((state (save-excursion (verilog-syntax-ppss))))
3735 ((nth 7 state) ; Inside // comment
3738 (delete-horizontal-space)
3743 (beginning-of-line)))
3744 (verilog-indent-line))
3745 ((nth 4 state) ; Inside any comment (hence /**/)
3747 (verilog-more-comment))
3749 ;; First, check if current line should be indented
3751 (delete-horizontal-space)
3753 (skip-chars-forward " \t")
3754 (if (looking-at verilog-auto-end-comment-lines-re)
3755 (let ((indent-str (verilog-indent-line)))
3756 ;; Maybe we should set some endcomments
3757 (if verilog-auto-endcomments
3758 (verilog-set-auto-endcomments indent-str arg))
3760 (delete-horizontal-space)
3767 (delete-horizontal-space)
3769 ;; see if we should line up assignments
3771 (if (or (eq 'all verilog-auto-lineup)
3772 (eq 'assignments verilog-auto-lineup))
3773 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3777 (if verilog-auto-indent-on-newline
3778 (verilog-indent-line)))
3782 (defun electric-verilog-terminate-and-indent ()
3783 "Insert a newline and indent for the next statement."
3785 (electric-verilog-terminate-line 1))
3787 (defun electric-verilog-semi ()
3788 "Insert `;' character and reindent the line."
3790 (verilog-insert-last-command-event)
3792 (if (or (verilog-in-comment-or-string-p)
3793 (verilog-in-escaped-name-p))
3797 (verilog-forward-ws&directives)
3798 (verilog-indent-line))
3799 (if (and verilog-auto-newline
3800 (not (verilog-parenthesis-depth)))
3801 (electric-verilog-terminate-line))))
3803 (defun electric-verilog-semi-with-comment ()
3804 "Insert `;' character, reindent the line and indent for comment."
3809 (verilog-indent-line))
3810 (indent-for-comment))
3812 (defun electric-verilog-colon ()
3813 "Insert `:' and do all indentations except line indent on this line."
3815 (verilog-insert-last-command-event)
3816 ;; Do nothing if within string.
3818 (verilog-within-string)
3819 (not (verilog-in-case-region-p)))
3823 (lim (progn (verilog-beg-of-statement) (point))))
3825 (verilog-backward-case-item lim)
3826 (verilog-indent-line)))
3827 ;; (let ((verilog-tab-always-indent nil))
3828 ;; (verilog-indent-line))
3831 ;;(defun electric-verilog-equal ()
3832 ;; "Insert `=', and do indentation if within block."
3834 ;; (verilog-insert-last-command-event)
3835 ;; Could auto line up expressions, but not yet
3836 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3837 ;; (let ((verilog-tab-always-indent nil))
3838 ;; (verilog-indent-command)))
3841 (defun electric-verilog-tick ()
3842 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3844 (verilog-insert-last-command-event)
3846 (if (verilog-in-directive-p)
3847 (verilog-indent-line))))
3849 (defun electric-verilog-tab ()
3850 "Function called when TAB is pressed in Verilog mode."
3852 ;; If verilog-tab-always-indent, indent the beginning of the line.
3854 ;; The region is active, indent it.
3855 ((and (region-active-p)
3856 (not (eq (region-beginning) (region-end))))
3857 (indent-region (region-beginning) (region-end) nil))
3858 ((or verilog-tab-always-indent
3860 (skip-chars-backward " \t")
3862 (let* ((oldpnt (point))
3866 (skip-chars-forward " \t")
3867 (verilog-indent-line)
3868 (back-to-indentation)
3870 (if (< (point) boi-point)
3871 (back-to-indentation)
3872 (cond ((not verilog-tab-to-comment))
3876 (indent-for-comment)
3877 (when (and (eolp) (= oldpnt (point)))
3878 ; kill existing comment
3880 (re-search-forward comment-start-skip oldpnt 'move)
3881 (goto-char (match-beginning 0))
3882 (skip-chars-backward " \t")
3883 (kill-region (point) oldpnt)))))))
3884 (t (progn (insert "\t")))))
3889 ;; Interactive functions
3892 (defun verilog-indent-buffer ()
3893 "Indent-region the entire buffer as Verilog code.
3894 To call this from the command line, see \\[verilog-batch-indent]."
3897 (indent-region (point-min) (point-max) nil))
3899 (defun verilog-insert-block ()
3900 "Insert Verilog begin ... end; block in the code with right indentation."
3902 (verilog-indent-line)
3904 (electric-verilog-terminate-line)
3906 (electric-verilog-terminate-line)
3909 (verilog-indent-line)))
3911 (defun verilog-star-comment ()
3912 "Insert Verilog star comment at point."
3914 (verilog-indent-line)
3922 (defun verilog-insert-1 (fmt max)
3923 "Use format string FMT to insert integers 0 to MAX - 1.
3924 Inserts one integer per line, at the current column. Stops early
3925 if it reaches the end of the buffer."
3926 (let ((col (current-column))
3930 (insert (format fmt n))
3932 ;; Note that this function does not bother to check for lines
3933 ;; shorter than col.
3937 (move-to-column col))))))
3939 (defun verilog-insert-indices (max)
3940 "Insert a set of indices into a rectangle.
3941 The upper left corner is defined by point. Indices begin with 0
3942 and extend to the MAX - 1. If no prefix arg is given, the user
3943 is prompted for a value. The indices are surrounded by square
3944 brackets \[]. For example, the following code with the point
3945 located after the first 'a' gives:
3951 a = b ==> insert-indices ==> a[ 4] = b
3957 (interactive "NMAX: ")
3958 (verilog-insert-1 "[%3d]" max))
3960 (defun verilog-generate-numbers (max)
3961 "Insert a set of generated numbers into a rectangle.
3962 The upper left corner is defined by point. The numbers are padded to three
3963 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
3964 is supplied, then the user is prompted for the MAX number. Consider the
3965 following code fragment:
3971 buf buf ==> generate-numbers ==> buf buf004
3977 (interactive "NMAX: ")
3978 (verilog-insert-1 "%3.3d" max))
3980 (defun verilog-mark-defun ()
3981 "Mark the current Verilog function (or procedure).
3982 This puts the mark at the end, and point at the beginning."
3984 (if (featurep 'xemacs)
3987 (verilog-end-of-defun)
3989 (verilog-beg-of-defun)
3990 (if (fboundp 'zmacs-activate-region)
3991 (zmacs-activate-region)))
3994 (defun verilog-comment-region (start end)
3995 ; checkdoc-params: (start end)
3996 "Put the region into a Verilog comment.
3997 The comments that are in this area are \"deformed\":
3998 `*)' becomes `!(*' and `}' becomes `!{'.
3999 These deformed comments are returned to normal if you use
4000 \\[verilog-uncomment-region] to undo the commenting.
4002 The commented area starts with `verilog-exclude-str-start', and ends with
4003 `verilog-exclude-str-end'. But if you change these variables,
4004 \\[verilog-uncomment-region] won't recognize the comments."
4007 ;; Insert start and endcomments
4009 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
4010 (not (save-excursion (skip-chars-backward " \t") (bolp))))
4012 (beginning-of-line))
4013 (insert verilog-exclude-str-end)
4018 (insert verilog-exclude-str-start)
4020 ;; Replace end-comments within commented area
4023 (while (re-search-backward "\\*/" start t)
4024 (replace-match "*-/" t t)))
4026 (let ((s+1 (1+ start)))
4027 (while (re-search-backward "/\\*" s+1 t)
4028 (replace-match "/-*" t t))))))
4030 (defun verilog-uncomment-region ()
4031 "Uncomment a commented area; change deformed comments back to normal.
4032 This command does nothing if the pointer is not in a commented
4033 area. See also `verilog-comment-region'."
4036 (let ((start (point))
4038 ;; Find the boundaries of the comment
4040 (setq start (progn (search-backward verilog-exclude-str-start nil t)
4042 (setq end (progn (search-forward verilog-exclude-str-end nil t)
4044 ;; Check if we're really inside a comment
4045 (if (or (equal start (point)) (<= end (point)))
4046 (message "Not standing within commented area.")
4048 ;; Remove endcomment
4051 (let ((pos (point)))
4053 (delete-region pos (1+ (point))))
4054 ;; Change comments back to normal
4056 (while (re-search-backward "\\*-/" start t)
4057 (replace-match "*/" t t)))
4059 (while (re-search-backward "/-\\*" start t)
4060 (replace-match "/*" t t)))
4061 ;; Remove start comment
4064 (let ((pos (point)))
4066 (delete-region pos (1+ (point)))))))))
4068 (defun verilog-beg-of-defun ()
4069 "Move backward to the beginning of the current function or procedure."
4071 (verilog-re-search-backward verilog-defun-re nil 'move))
4073 (defun verilog-beg-of-defun-quick ()
4074 "Move backward to the beginning of the current function or procedure.
4075 Uses `verilog-scan' cache."
4077 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
4079 (defun verilog-end-of-defun ()
4080 "Move forward to the end of the current function or procedure."
4082 (verilog-re-search-forward verilog-end-defun-re nil 'move))
4084 (defun verilog-get-end-of-defun ()
4086 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
4089 (error "%s: Can't find endmodule" (verilog-point-text))
4092 (defun verilog-label-be ()
4093 "Label matching begin ... end, fork ... join and case ... endcase statements."
4098 (verilog-beg-of-defun)
4101 (verilog-end-of-defun)
4103 (goto-char (marker-position b))
4105 (message "Relabeling module..."))
4107 (> (marker-position e) (point))
4108 (verilog-re-search-forward
4110 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
4111 "\\|\\(`endif\\)\\|\\(`else\\)")
4113 (goto-char (match-beginning 0))
4114 (let ((indent-str (verilog-indent-line)))
4115 (verilog-set-auto-endcomments indent-str 't)
4117 (delete-horizontal-space))
4119 (if (= 9 (% cnt 10))
4120 (message "%d..." cnt)))
4125 (message "%d lines auto commented" cnt))))
4127 (defun verilog-beg-of-statement ()
4128 "Move backward to beginning of statement."
4130 ;; Move back token by token until we see the end
4131 ;; of some earlier line.
4134 ;; If the current point does not begin a new
4135 ;; statement, as in the character ahead of us is a ';', or SOF
4136 ;; or the string after us unambiguously starts a statement,
4137 ;; or the token before us unambiguously ends a statement,
4138 ;; then move back a token and test again.
4140 ;; stop if beginning of buffer
4142 ;; stop if we find a ;
4143 (= (preceding-char) ?\;)
4144 ;; stop if we see a named coverpoint
4145 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4146 ;; keep going if we are in the middle of a word
4147 (not (or (looking-at "\\<") (forward-word -1)))
4148 ;; stop if we see an assertion (perhaps labeled)
4150 (looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4154 (verilog-backward-token)
4155 (if (looking-at verilog-label-re)
4158 ;; stop if we see an extended complete reg, perhaps a complete one
4160 (looking-at verilog-complete-reg)
4162 (while (and (looking-at verilog-extended-complete-re)
4163 (progn (setq p (point))
4164 (verilog-backward-token)
4167 ;; stop if we see a complete reg (previous found extended ones)
4168 (looking-at verilog-basic-complete-re)
4169 ;; stop if previous token is an ender
4171 (verilog-backward-token)
4173 (looking-at verilog-end-block-re)
4174 (looking-at verilog-preprocessor-re))))) ;; end of test
4175 (verilog-backward-syntactic-ws)
4176 (verilog-backward-token))
4177 ;; Now point is where the previous line ended.
4178 (verilog-forward-syntactic-ws)))
4180 (defun verilog-beg-of-statement-1 ()
4181 "Move backward to beginning of statement."
4183 (if (verilog-in-comment-p)
4184 (verilog-backward-syntactic-ws))
4187 (while (not (looking-at verilog-complete-reg))
4189 (verilog-backward-syntactic-ws)
4191 (= (preceding-char) ?\;)
4193 (verilog-backward-token)
4194 (looking-at verilog-ends-re)))
4198 (verilog-backward-token))))
4199 (verilog-forward-syntactic-ws)))
4202 ; (not (looking-at verilog-complete-reg))
4204 ; (not (= (preceding-char) ?\;)))
4205 ; (verilog-backward-token)
4206 ; (verilog-backward-syntactic-ws)
4207 ; (setq pt (point)))
4209 ; ;(verilog-forward-syntactic-ws)
4211 (defun verilog-end-of-statement ()
4212 "Move forward to end of current statement."
4216 ((verilog-in-directive-p)
4220 ((looking-at verilog-beg-block-re)
4221 (verilog-forward-sexp))
4223 ((equal (char-after) ?\})
4226 ;; Skip to end of statement
4227 ((condition-case nil
4232 (verilog-skip-forward-comment-or-string)
4235 (cond ((looking-at "[ \t]*;")
4236 (skip-chars-forward "^;")
4238 (throw 'found (point)))
4241 (looking-at verilog-beg-block-re))
4242 (goto-char (match-beginning 0))
4244 ((looking-at "[ \t]*)")
4245 (throw 'found (point)))
4247 (throw 'found (point)))
4253 ;; Skip a whole block
4256 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4257 (setq nest (if (match-end 1)
4261 (throw 'found (point)))
4263 (throw 'found (verilog-end-of-statement))))))
4266 (defun verilog-in-case-region-p ()
4267 "Return true if in a case region.
4268 More specifically, point @ in the line foo : @ begin"
4272 (progn (verilog-forward-syntactic-ws)
4273 (looking-at "\\<begin\\>"))
4274 (progn (verilog-backward-syntactic-ws)
4275 (= (preceding-char) ?\:)))
4279 (verilog-re-search-backward
4280 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4281 "\\(\\<endcase\\>\\)\\>")
4285 (setq nest (1+ nest)))
4289 (setq nest (1- nest)))
4291 (throw 'found (= nest 0)))))))
4294 (defun verilog-backward-up-list (arg)
4295 "Call `backward-up-list' ARG, ignoring comments."
4296 (let ((parse-sexp-ignore-comments t))
4297 (backward-up-list arg)))
4299 (defun verilog-forward-sexp-cmt (arg)
4300 "Call `forward-sexp' ARG, inside comments."
4301 (let ((parse-sexp-ignore-comments nil))
4302 (forward-sexp arg)))
4304 (defun verilog-forward-sexp-ign-cmt (arg)
4305 "Call `forward-sexp' ARG, ignoring comments."
4306 (let ((parse-sexp-ignore-comments t))
4307 (forward-sexp arg)))
4309 (defun verilog-in-generate-region-p ()
4310 "Return true if in a generate region.
4311 More specifically, after a generate and before an endgenerate."
4318 (verilog-re-search-backward
4319 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4321 ((match-end 1) ; module - we have crawled out
4323 ((match-end 2) ; generate
4324 (setq nest (1- nest)))
4325 ((match-end 3) ; endgenerate
4326 (setq nest (1+ nest))))))))
4327 (= nest 0) )) ; return nest
4329 (defun verilog-in-fork-region-p ()
4330 "Return true if between a fork and join."
4332 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4337 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4339 ((match-end 1) ; fork
4340 (setq nest (1- nest)))
4341 ((match-end 2) ; join
4342 (setq nest (1+ nest)))))))
4343 (= nest 0) )) ; return nest
4345 (defun verilog-backward-case-item (lim)
4346 "Skip backward to nearest enclosing case item.
4347 Limit search to point LIM."
4353 (verilog-re-search-backward verilog-endcomment-reason-re
4356 ;; Try to find the real :
4357 (if (save-excursion (search-backward ":" lim1 t))
4363 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4367 (setq colon (1+ colon))
4369 (error "%s: unbalanced [" (verilog-point-text))))
4371 (setq colon (1- colon)))
4374 (setq colon (1+ colon)))))
4375 ;; Skip back to beginning of case item
4376 (skip-chars-backward "\t ")
4377 (verilog-skip-backward-comment-or-string)
4382 (verilog-re-search-backward
4383 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4387 (goto-char (match-end 1))
4388 (verilog-forward-ws&directives)
4389 (if (looking-at "(")
4392 (verilog-forward-ws&directives)))
4395 (goto-char (match-end 0))
4396 (verilog-forward-ws&directives)
4398 (error "Malformed case item"))))
4399 (setq str (buffer-substring b e))
4403 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4404 (setq str (concat (substring str 0 e) "...")))
4413 (defun verilog-kill-existing-comment ()
4414 "Kill auto comment on this line."
4422 (search-forward "//" e t))))
4424 (delete-region (- b 2) e)))))
4426 (defconst verilog-directive-nest-re
4427 (concat "\\(`else\\>\\)\\|"
4428 "\\(`endif\\>\\)\\|"
4430 "\\(`ifdef\\>\\)\\|"
4431 "\\(`ifndef\\>\\)\\|"
4433 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4434 "Add ending comment with given INDENT-STR.
4435 With KILL-EXISTING-COMMENT, remove what was there before.
4436 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4437 Insert `// case expr ' if this line ends a case block.
4438 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4439 Insert `// NAME ' if this line ends a function, task, module,
4440 primitive or interface named NAME."
4443 (; Comment close preprocessor directives
4445 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4446 (or kill-existing-comment
4447 (not (save-excursion
4449 (search-backward "//" (point-at-bol) t)))))
4452 (else (if (match-end 2) "!" " ")))
4454 (if kill-existing-comment
4455 (verilog-kill-existing-comment))
4456 (delete-horizontal-space)
4459 (while (and (/= nest 0)
4460 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4462 ((match-end 1) ; `else
4465 ((match-end 2) ; `endif
4466 (setq nest (1+ nest)))
4467 ((match-end 3) ; `if
4468 (setq nest (1- nest)))
4469 ((match-end 4) ; `ifdef
4470 (setq nest (1- nest)))
4471 ((match-end 5) ; `ifndef
4472 (setq nest (1- nest)))
4473 ((match-end 6) ; `elsif
4484 (skip-chars-forward "^ \t")
4485 (verilog-forward-syntactic-ws)
4488 (skip-chars-forward "a-zA-Z0-9_")
4491 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4492 (insert (concat " // " else m " " (buffer-substring b e))))
4494 (insert " // unmatched `else, `elsif or `endif")
4497 (; Comment close case/class/function/task/module and named block
4498 (and (looking-at "\\<end")
4499 (or kill-existing-comment
4500 (not (save-excursion
4502 (search-backward "//" (point-at-bol) t)))))
4503 (let ((type (car indent-str)))
4504 (unless (eq type 'declaration)
4505 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
4506 (if (looking-at verilog-end-block-ordered-re)
4508 (;- This is a case block; search back for the start of this case
4509 (match-end 1) ;; of verilog-end-block-ordered-re
4512 (str "UNMATCHED!!"))
4514 (verilog-leap-to-head)
4516 ((looking-at "\\<randcase\\>")
4517 (setq str "randcase")
4519 ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4520 (goto-char (match-end 0))
4521 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4525 (if kill-existing-comment
4526 (verilog-kill-existing-comment))
4527 (delete-horizontal-space)
4528 (insert (concat " // " str ))
4529 (if err (ding 't))))
4531 (;- This is a begin..end block
4532 (match-end 2) ;; of verilog-end-block-ordered-re
4533 (let ((str " // UNMATCHED !!")
4539 (verilog-leap-to-head)
4540 (setq there (point))
4541 (if (not (match-end 0))
4545 (if kill-existing-comment
4546 (verilog-kill-existing-comment))
4547 (delete-horizontal-space)
4551 (save-excursion (verilog-beg-of-defun) (point)))
4554 (;-- handle named block differently
4555 (looking-at verilog-named-block-re)
4556 (search-forward ":")
4557 (setq there (point))
4558 (setq str (verilog-get-expr))
4560 (setq str (concat " // block: " str )))
4562 ((verilog-in-case-region-p) ;-- handle case item differently
4564 (setq str (verilog-backward-case-item lim))
4565 (setq there (point))
4567 (setq str (concat " // case: " str )))
4569 (;- try to find "reason" for this begin
4573 ;; (verilog-backward-token)
4574 (verilog-beg-of-statement)
4578 ((looking-at verilog-endcomment-reason-re)
4579 (setq there (match-end 0))
4580 (setq cntx (concat (match-string 0) " "))
4586 (if (and (verilog-continued-line)
4587 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4589 (goto-char (match-end 0))
4590 (setq there (point))
4592 (concat " // " (match-string 0) " " (verilog-get-expr))))
4598 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4600 (while (verilog-re-search-backward reg nil 'move)
4602 ((match-end 1) ; begin
4603 (setq nest (1- nest)))
4604 ((match-end 2) ; end
4605 (setq nest (1+ nest)))
4609 (goto-char (match-end 0))
4610 (setq there (point))
4612 (setq str (verilog-get-expr))
4613 (setq str (concat " // else: !if" str ))
4618 (goto-char (match-end 0))
4619 (setq there (point))
4621 (setq str (verilog-get-expr))
4622 (setq str (concat " // else: !assert " str ))
4623 (throw 'skip 1)))))))))
4628 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4630 (while (verilog-re-search-backward reg nil 'move)
4632 ((match-end 1) ; begin
4633 (setq nest (1- nest)))
4634 ((match-end 2) ; end
4635 (setq nest (1+ nest)))
4639 (goto-char (match-end 0))
4640 (setq there (point))
4642 (setq str (verilog-get-expr))
4643 (setq str (concat " // else: !if" str ))
4648 (goto-char (match-end 0))
4649 (setq there (point))
4651 (setq str (verilog-get-expr))
4652 (setq str (concat " // else: !assert " str ))
4653 (throw 'skip 1)))))))))
4655 (; always_comb, always_ff, always_latch
4656 (or (match-end 4) (match-end 5) (match-end 6))
4657 (goto-char (match-end 0))
4658 (setq there (point))
4660 (setq str (concat " // " cntx )))
4662 (;- task/function/initial et cetera
4665 (goto-char (match-end 0))
4666 (setq there (point))
4668 (setq str (concat " // " cntx (verilog-get-expr))))
4671 (setq str " // auto-endcomment confused "))))
4674 (verilog-in-case-region-p) ;-- handle case item differently
4676 (setq there (point))
4678 (setq str (verilog-backward-case-item lim))))
4680 (setq str (concat " // case: " str )))
4682 ((verilog-in-fork-region-p)
4684 (setq str " // fork branch" ))
4686 ((looking-at "\\<end\\>")
4689 (verilog-forward-syntactic-ws)
4691 (setq str (verilog-get-expr))
4692 (setq str (concat " // " cntx str )))
4697 (if kill-existing-comment
4698 (verilog-kill-existing-comment))
4699 (delete-horizontal-space)
4701 (> (count-lines here there) verilog-minimum-comment-distance))
4705 (;- this is endclass, which can be nested
4706 (match-end 11) ;; of verilog-end-block-ordered-re
4709 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4713 (while (verilog-re-search-backward reg nil 'move)
4715 ((match-end 3) ; endclass
4717 (setq string "unmatched endclass")
4720 ((match-end 2) ; endclass
4721 (setq nest (1+ nest)))
4723 ((match-end 1) ; class
4724 (setq nest (1- nest))
4727 (goto-char (match-end 0))
4730 (skip-chars-forward "^ \t")
4731 (verilog-forward-ws&directives)
4734 (skip-chars-forward "a-zA-Z0-9_")
4736 (setq string (buffer-substring b e)))
4740 (insert (concat " // " string ))))
4742 (;- this is end{function,generate,task,module,primitive,table,generate}
4743 ;- which can not be nested.
4745 (let (string reg (name-re nil))
4747 (if kill-existing-comment
4749 (verilog-kill-existing-comment)))
4750 (delete-horizontal-space)
4753 ((match-end 5) ;; of verilog-end-block-ordered-re
4754 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4755 (setq name-re "\\w+\\s-*("))
4756 ((match-end 6) ;; of verilog-end-block-ordered-re
4757 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4758 (setq name-re "\\w+\\s-*("))
4759 ((match-end 7) ;; of verilog-end-block-ordered-re
4760 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4761 ((match-end 8) ;; of verilog-end-block-ordered-re
4762 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4763 ((match-end 9) ;; of verilog-end-block-ordered-re
4764 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4765 ((match-end 10) ;; of verilog-end-block-ordered-re
4766 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4767 ((match-end 11) ;; of verilog-end-block-ordered-re
4768 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4769 ((match-end 12) ;; of verilog-end-block-ordered-re
4770 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4771 ((match-end 13) ;; of verilog-end-block-ordered-re
4772 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4773 ((match-end 14) ;; of verilog-end-block-ordered-re
4774 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4775 ((match-end 15) ;; of verilog-end-block-ordered-re
4776 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4778 (t (error "Problem in verilog-set-auto-endcomments")))
4781 (verilog-re-search-backward reg nil 'move)
4785 (skip-chars-forward "^ \t")
4786 (verilog-forward-ws&directives)
4787 (if (looking-at "static\\|automatic")
4789 (goto-char (match-end 0))
4790 (verilog-forward-ws&directives)))
4791 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4793 (goto-char (match-beginning 0))
4794 (verilog-forward-ws&directives)))
4797 (skip-chars-forward "a-zA-Z0-9_")
4799 (setq string (buffer-substring b e)))
4802 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4804 (insert (concat " // " string )))
4807 (defun verilog-get-expr()
4808 "Grab expression at point, e.g., case ( a | b & (c ^d))."
4810 (verilog-forward-syntactic-ws)
4811 (skip-chars-forward " \t")
4817 (verilog-forward-syntactic-ws)
4818 (if (looking-at "(")
4821 (while (and (/= par 0)
4822 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4825 (setq par (1+ par)))
4827 (setq par (1- par)))))))
4831 (while (and (/= par 0)
4832 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4835 (setq par (1+ par)))
4837 (setq par (1- par)))))
4841 (while (and (/= par 0)
4842 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
4845 (setq par (1+ par)))
4847 (setq par (1- par)))))
4848 (verilog-forward-syntactic-ws)
4849 (skip-chars-forward "^ \t\n\f")
4851 ((looking-at "/[/\\*]")
4854 (skip-chars-forward "^: \t\n\f")
4856 (str (buffer-substring b e)))
4857 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4858 (setq str (concat (substring str 0 e) "...")))
4861 (defun verilog-expand-vector ()
4862 "Take a signal vector on the current line and expand it to multiple lines.
4863 Useful for creating tri's and other expanded fields."
4865 (verilog-expand-vector-internal "[" "]"))
4867 (defun verilog-expand-vector-internal (bra ket)
4868 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
4871 (let ((signal-string (buffer-substring (point)
4873 (end-of-line) (point)))))
4877 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
4879 "\\(.*\\)$") signal-string)
4880 (let* ((sig-head (match-string 1 signal-string))
4881 (vec-start (string-to-number (match-string 2 signal-string)))
4882 (vec-end (if (= (match-beginning 3) (match-end 3))
4885 (substring signal-string (1+ (match-beginning 3))
4888 (if (= (match-beginning 4) (match-end 4))
4891 (substring signal-string (+ 2 (match-beginning 4))
4893 (sig-tail (match-string 5 signal-string))
4898 (let ((tmp vec-start))
4899 (setq vec-start vec-end
4901 vec-range (- vec-range))))
4902 (if (< vec-end vec-start)
4903 (while (<= vec-end vec-start)
4904 (setq vec (append vec (list vec-start)))
4905 (setq vec-start (- vec-start vec-range)))
4906 (while (<= vec-start vec-end)
4907 (setq vec (append vec (list vec-start)))
4908 (setq vec-start (+ vec-start vec-range))))
4910 ;; Delete current line
4911 (delete-region (point) (progn (forward-line 0) (point)))
4915 (insert (concat sig-head bra
4916 (int-to-string (car vec)) ket sig-tail "\n"))
4917 (setq vec (cdr vec)))
4922 (defun verilog-strip-comments ()
4923 "Strip all comments from the Verilog code."
4925 (goto-char (point-min))
4926 (while (re-search-forward "//" nil t)
4927 (if (verilog-within-string)
4928 (re-search-forward "\"" nil t)
4929 (if (verilog-in-star-comment-p)
4930 (re-search-forward "\*/" nil t)
4931 (let ((bpt (- (point) 2)))
4933 (delete-region bpt (point))))))
4935 (goto-char (point-min))
4936 (while (re-search-forward "/\\*" nil t)
4937 (if (verilog-within-string)
4938 (re-search-forward "\"" nil t)
4939 (let ((bpt (- (point) 2)))
4940 (re-search-forward "\\*/")
4941 (delete-region bpt (point))))))
4943 (defun verilog-one-line ()
4944 "Convert structural Verilog instances to occupy one line."
4946 (goto-char (point-min))
4947 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
4948 (replace-match "\\1 " nil nil)))
4950 (defun verilog-linter-name ()
4951 "Return name of linter, either surelint or verilint."
4952 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4954 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4956 (cond ((equal compile-word1 "surelint") `surelint)
4957 ((equal compile-word1 "verilint") `verilint)
4958 ((equal lint-word1 "surelint") `surelint)
4959 ((equal lint-word1 "verilint") `verilint)
4960 (t `surelint)))) ;; back compatibility
4962 (defun verilog-lint-off ()
4963 "Convert a Verilog linter warning line into a disable statement.
4965 pci_bfm_null.v, line 46: Unused input: pci_rst_
4966 becomes a comment for the appropriate tool.
4968 The first word of the `compile-command' or `verilog-linter'
4969 variables is used to determine which product is being used.
4971 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
4973 (let ((linter (verilog-linter-name)))
4974 (cond ((equal linter `surelint)
4975 (verilog-surelint-off))
4976 ((equal linter `verilint)
4977 (verilog-verilint-off))
4978 (t (error "Linter name not set")))))
4980 (defvar compilation-last-buffer)
4981 (defvar next-error-last-buffer)
4983 (defun verilog-surelint-off ()
4984 "Convert a SureLint warning line into a disable statement.
4985 Run from Verilog source window; assumes there is a *compile* buffer
4986 with point set appropriately.
4989 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
4991 // surefire lint_line_off UDDONX"
4993 (let ((buff (if (boundp 'next-error-last-buffer)
4994 next-error-last-buffer
4995 compilation-last-buffer)))
4996 (when (buffer-live-p buff)
4998 (switch-to-buffer buff)
5001 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
5002 (let* ((code (match-string 2))
5003 (file (match-string 3))
5004 (line (match-string 4))
5005 (buffer (get-file-buffer file))
5010 (and (file-exists-p file)
5011 (find-file-noselect file)))
5013 (let* ((pop-up-windows t))
5014 (let ((name (expand-file-name
5016 (format "Find this error in: (default %s) "
5019 (if (file-directory-p name)
5020 (setq name (expand-file-name filename name)))
5022 (and (file-exists-p name)
5023 (find-file-noselect name))))))))
5024 (switch-to-buffer buffer)
5025 (goto-char (point-min))
5026 (forward-line (- (string-to-number line)))
5030 ((verilog-in-slash-comment-p)
5031 (re-search-backward "//")
5033 ((looking-at "// surefire lint_off_line ")
5034 (goto-char (match-end 0))
5035 (let ((lim (point-at-eol)))
5036 (if (re-search-forward code lim 'move)
5038 (insert (concat " " code)))))
5041 ((verilog-in-star-comment-p)
5042 (re-search-backward "/\*")
5043 (insert (format " // surefire lint_off_line %6s" code )))
5045 (insert (format " // surefire lint_off_line %6s" code ))
5048 (defun verilog-verilint-off ()
5049 "Convert a Verilint warning line into a disable statement.
5052 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
5054 //Verilint 240 off // WARNING: Unused input"
5058 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
5059 (replace-match (format
5060 ;; %3s makes numbers 1-999 line up nicely
5061 "\\1//Verilint %3s off // WARNING: \\3"
5064 (verilog-indent-line))))
5066 (defun verilog-auto-save-compile ()
5067 "Update automatics with \\[verilog-auto], save the buffer, and compile."
5069 (verilog-auto) ; Always do it for safety
5071 (compile compile-command))
5073 (defun verilog-preprocess (&optional command filename)
5074 "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
5075 Takes optional COMMAND or defaults to `verilog-preprocessor', and
5076 FILENAME to find directory to run in, or defaults to `buffer-file-name`."
5079 (let ((default (verilog-expand-command verilog-preprocessor)))
5080 (set (make-local-variable `verilog-preprocessor)
5081 (read-from-minibuffer "Run Preprocessor (like this): "
5083 'verilog-preprocess-history default)))))
5084 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
5085 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
5086 (dir (file-name-directory (or filename buffer-file-name)))
5087 (cmd (concat "cd " dir "; " command)))
5088 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
5089 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
5090 (insert (concat "// " cmd "\n"))
5091 (call-process shell-file-name nil t nil shell-command-switch cmd)
5093 ;; Without this force, it takes a few idle seconds
5094 ;; to get the color, which is very jarring
5095 (when fontlocked (font-lock-fontify-buffer))))))
5102 (defun verilog-warn (string &rest args)
5103 "Print a warning with `format' using STRING and optional ARGS."
5104 (apply 'message (concat "%%Warning: " string) args))
5106 (defun verilog-warn-error (string &rest args)
5107 "Call `error' using STRING and optional ARGS.
5108 If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
5109 (if verilog-warn-fatal
5110 (apply 'error string args)
5111 (apply 'verilog-warn string args)))
5113 (defmacro verilog-batch-error-wrapper (&rest body)
5114 "Execute BODY and add error prefix to any errors found.
5115 This lets programs calling batch mode to easily extract error messages."
5116 `(let ((verilog-warn-fatal nil))
5120 (error "%%Error: %s%s" (error-message-string err)
5121 (if (featurep 'xemacs) "\n" "")))))) ;; XEmacs forgets to add a newline
5123 (defun verilog-batch-execute-func (funref &optional no-save)
5124 "Internal processing of a batch command.
5125 Runs FUNREF on all command arguments.
5126 Save the result unless optional NO-SAVE is t."
5127 (verilog-batch-error-wrapper
5128 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5129 ;; However, this function is called only when Emacs is being used as
5130 ;; a standalone language instead of as an editor, so we'll live.
5132 ;; General globals needed
5133 (setq make-backup-files nil)
5134 (setq-default make-backup-files nil)
5135 (setq enable-local-variables t)
5136 (setq enable-local-eval t)
5137 (setq create-lockfiles nil)
5138 ;; Make sure any sub-files we read get proper mode
5139 (setq-default major-mode 'verilog-mode)
5140 ;; Ditto files already read in
5142 (when (buffer-file-name buf)
5143 (with-current-buffer buf
5146 ;; Process the files
5147 (mapcar (lambda (buf)
5148 (when (buffer-file-name buf)
5150 (if (not (file-exists-p (buffer-file-name buf)))
5152 (concat "File not found: " (buffer-file-name buf))))
5153 (message (concat "Processing " (buffer-file-name buf)))
5156 (unless no-save (save-buffer)))))
5159 (defun verilog-batch-auto ()
5160 "For use with --batch, perform automatic expansions as a stand-alone tool.
5161 This sets up the appropriate Verilog mode environment, updates automatics
5162 with \\[verilog-auto] on all command-line files, and saves the buffers.
5163 For proper results, multiple filenames need to be passed on the command
5164 line in bottom-up order."
5165 (unless noninteractive
5166 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5167 (verilog-batch-execute-func `verilog-auto))
5169 (defun verilog-batch-delete-auto ()
5170 "For use with --batch, perform automatic deletion as a stand-alone tool.
5171 This sets up the appropriate Verilog mode environment, deletes automatics
5172 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5173 (unless noninteractive
5174 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5175 (verilog-batch-execute-func `verilog-delete-auto))
5177 (defun verilog-batch-delete-trailing-whitespace ()
5178 "For use with --batch, perform whitespace deletion as a stand-alone tool.
5179 This sets up the appropriate Verilog mode environment, removes
5180 whitespace with \\[verilog-delete-trailing-whitespace] on all
5181 command-line files, and saves the buffers."
5182 (unless noninteractive
5183 (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ;; Otherwise we'd mess up buffer modes
5184 (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
5186 (defun verilog-batch-diff-auto ()
5187 "For use with --batch, perform automatic differences as a stand-alone tool.
5188 This sets up the appropriate Verilog mode environment, expand automatics
5189 with \\[verilog-diff-auto] on all command-line files, and reports an error
5190 if any differences are observed. This is appropriate for adding to regressions
5191 to insure automatics are always properly maintained."
5192 (unless noninteractive
5193 (error "Use verilog-batch-diff-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5194 (verilog-batch-execute-func `verilog-diff-auto t))
5196 (defun verilog-batch-inject-auto ()
5197 "For use with --batch, perform automatic injection as a stand-alone tool.
5198 This sets up the appropriate Verilog mode environment, injects new automatics
5199 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5200 For proper results, multiple filenames need to be passed on the command
5201 line in bottom-up order."
5202 (unless noninteractive
5203 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5204 (verilog-batch-execute-func `verilog-inject-auto))
5206 (defun verilog-batch-indent ()
5207 "For use with --batch, reindent an entire file as a stand-alone tool.
5208 This sets up the appropriate Verilog mode environment, calls
5209 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5210 (unless noninteractive
5211 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
5212 (verilog-batch-execute-func `verilog-indent-buffer))
5218 (defconst verilog-indent-alist
5219 '((block . (+ ind verilog-indent-level))
5220 (case . (+ ind verilog-case-indent))
5221 (cparenexp . (+ ind verilog-indent-level))
5222 (cexp . (+ ind verilog-cexp-indent))
5223 (defun . verilog-indent-level-module)
5224 (declaration . verilog-indent-level-declaration)
5225 (directive . (verilog-calculate-indent-directive))
5226 (tf . verilog-indent-level)
5227 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5230 (comment . (verilog-comment-indent))
5234 (defun verilog-continued-line-1 (lim)
5235 "Return true if this is a continued line.
5236 Set point to where line starts. Limit search to point LIM."
5237 (let ((continued 't))
5238 (if (eq 0 (forward-line -1))
5241 (verilog-backward-ws&directives lim)
5243 (setq continued nil)
5244 (setq continued (verilog-backward-token))))
5245 (setq continued nil))
5248 (defun verilog-calculate-indent ()
5249 "Calculate the indent of the current Verilog line.
5250 Examine previous lines. Once a line is found that is definitive as to the
5251 type of the current line, return that lines' indent level and its type.
5252 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5254 (let* ((starting_position (point))
5256 (begin (looking-at "[ \t]*begin\\>"))
5257 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5259 (type (catch 'nesting
5260 ;; Keep working backwards until we can figure out
5261 ;; what type of statement this is.
5262 ;; Basically we need to figure out
5263 ;; 1) if this is a continuation of the previous line;
5264 ;; 2) are we in a block scope (begin..end)
5266 ;; if we are in a comment, done.
5267 (if (verilog-in-star-comment-p)
5268 (throw 'nesting 'comment))
5270 ;; if we have a directive, done.
5271 (if (save-excursion (beginning-of-line)
5272 (and (looking-at verilog-directive-re-1)
5273 (not (or (looking-at "[ \t]*`[ou]vm_")
5274 (looking-at "[ \t]*`vmm_")))))
5275 (throw 'nesting 'directive))
5276 ;; indent structs as if there were module level
5277 (setq structres (verilog-in-struct-nested-p))
5278 (cond ((not structres) nil)
5279 ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
5280 ((> structres 0) (throw 'nesting 'nested-struct))
5281 ((= structres 0) (throw 'nesting 'block))
5284 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5285 ;; unless we are in the newfangled coverpoint or constraint blocks
5287 verilog-indent-lists
5289 (not (verilog-in-coverage-p))
5292 (throw 'nesting 'block)))
5294 ;; See if we are continuing a previous line
5296 ;; trap out if we crawl off the top of the buffer
5297 (if (bobp) (throw 'nesting 'cpp))
5299 (if (and (verilog-continued-line-1 lim)
5300 (or (not (verilog-in-coverage-p))
5301 (looking-at verilog-in-constraint-re) )) ;; may still get hosed if concat in constraint
5304 (not (looking-at verilog-complete-reg))
5305 (verilog-continued-line-1 lim))
5306 (progn (goto-char sp)
5307 (throw 'nesting 'cexp))
5310 (if (and (verilog-in-coverage-p)
5311 (looking-at verilog-in-constraint-re))
5314 (skip-chars-forward " \t")
5315 (throw 'nesting 'constraint)))
5317 (not verilog-indent-begin-after-if)
5318 (looking-at verilog-no-indent-begin-re))
5321 (skip-chars-forward " \t")
5322 (throw 'nesting 'statement))
5324 (throw 'nesting 'cexp))))
5325 ;; not a continued line
5326 (goto-char starting_position))
5328 (if (looking-at "\\<else\\>")
5329 ;; search back for governing if, striding across begin..end pairs
5332 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5334 ((match-end 1) ; else, we're in deep
5335 (setq elsec (1+ elsec)))
5337 (setq elsec (1- elsec))
5339 (if verilog-align-ifelse
5340 (throw 'nesting 'statement)
5341 (progn ;; back up to first word on this line
5343 (verilog-forward-syntactic-ws)
5344 (throw 'nesting 'statement)))))
5345 ((match-end 3) ; assert block
5346 (setq elsec (1- elsec))
5347 (verilog-beg-of-statement) ;; doesn't get to beginning
5348 (if (looking-at verilog-property-re)
5349 (throw 'nesting 'statement) ; We don't need an endproperty for these
5350 (throw 'nesting 'block) ;We still need an endproperty
5353 ; try to leap back to matching outward block by striding across
5354 ; indent level changing tokens then immediately
5355 ; previous line governs indentation.
5356 (let (( reg) (nest 1))
5357 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5359 ((match-end 4) ; end
5360 ;; Search back for matching begin
5361 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5362 ((match-end 5) ; endcase
5363 ;; Search back for matching case
5364 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5365 ((match-end 6) ; endfunction
5366 ;; Search back for matching function
5367 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5368 ((match-end 7) ; endtask
5369 ;; Search back for matching task
5370 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5371 ((match-end 8) ; endspecify
5372 ;; Search back for matching specify
5373 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5374 ((match-end 9) ; endtable
5375 ;; Search back for matching table
5376 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5377 ((match-end 10) ; endgenerate
5378 ;; Search back for matching generate
5379 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5380 ((match-end 11) ; joins
5381 ;; Search back for matching fork
5382 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5383 ((match-end 12) ; class
5384 ;; Search back for matching class
5385 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5386 ((match-end 13) ; covergroup
5387 ;; Search back for matching covergroup
5388 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5390 (while (verilog-re-search-backward reg nil 'move)
5392 ((match-end 1) ; begin
5393 (setq nest (1- nest))
5396 ((match-end 2) ; end
5397 (setq nest (1+ nest)))))
5399 (throw 'nesting (verilog-calc-1)))
5403 ;; Return type of block and indent level.
5406 (if (> par 0) ; Unclosed Parenthesis
5407 (list 'cparenexp par)
5410 (list type (verilog-case-indent-level)))
5411 ((eq type 'statement)
5412 (list type (current-column)))
5415 ((eq type 'constraint)
5416 (list 'block (current-column)))
5417 ((eq type 'nested-struct)
5418 (list 'block structres))
5420 (list type (verilog-current-indent-level))))))))
5422 (defun verilog-wai ()
5423 "Show matching nesting block for debugging."
5426 (let* ((type (verilog-calc-1))
5428 ;; Return type of block and indent level.
5432 verilog-indent-lists
5433 (not(or (verilog-in-coverage-p)
5434 (verilog-in-struct-p)))
5439 (setq depth (verilog-case-indent-level)))
5440 ((eq type 'statement)
5441 (setq depth (current-column)))
5445 (setq depth (verilog-current-indent-level)))))
5446 (message "You are at nesting %s depth %d" type depth))))
5448 (defun verilog-calc-1 ()
5450 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))
5451 (inconstraint (verilog-in-coverage-p)))
5452 (while (verilog-re-search-backward re nil 'move)
5455 ((equal (char-after) ?\{)
5456 ;; block type returned based on outer constraint { or inner
5457 (if (verilog-at-constraint-p)
5458 (cond (inconstraint (throw 'nesting 'constraint))
5459 (t (throw 'nesting 'statement)))))
5460 ((equal (char-after) ?\})
5462 (there (verilog-at-close-constraint-p)))
5463 (if there ;; we are at the } that closes a constraint. Find the { that opens it
5465 (if (> (verilog-in-paren-count) 0)
5467 (setq par-pos (verilog-parenthesis-depth))
5472 (backward-char 1)))))))
5474 ((looking-at verilog-beg-block-re-ordered)
5476 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5477 (let ((here (point)))
5478 (verilog-beg-of-statement)
5479 (if (looking-at verilog-extended-case-re)
5480 (throw 'nesting 'case)
5482 (throw 'nesting 'case))
5484 ((match-end 4) ; *sigh* could be "disable fork"
5485 (let ((here (point)))
5486 (verilog-beg-of-statement)
5487 (if (looking-at verilog-disable-fork-re)
5488 t ; this is a normal statement
5489 (progn ; or is fork, starts a new block
5491 (throw 'nesting 'block)))))
5493 ((match-end 27) ; *sigh* might be a clocking declaration
5494 (let ((here (point)))
5495 (if (verilog-in-paren)
5496 t ; this is a normal statement
5497 (progn ; or is fork, starts a new block
5499 (throw 'nesting 'block)))))
5501 ;; need to consider typedef struct here...
5502 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5503 ; *sigh* These words have an optional prefix:
5504 ; extern {virtual|protected}? function a();
5505 ; typedef class foo;
5506 ; and we don't want to confuse this with
5511 (verilog-beg-of-statement)
5512 (if (looking-at verilog-beg-block-re-ordered)
5513 (throw 'nesting 'block)
5514 (throw 'nesting 'defun)))
5517 ((looking-at "\\<property\\>")
5519 ; {assert|assume|cover} property (); are complete
5520 ; and could also be labeled: - foo: assert property
5522 ; property ID () ... needs end_property
5523 (verilog-beg-of-statement)
5524 (if (looking-at verilog-property-re)
5525 (throw 'continue 'statement) ; We don't need an endproperty for these
5526 (throw 'nesting 'block) ;We still need an endproperty
5529 (t (throw 'nesting 'block))))
5531 ((looking-at verilog-end-block-re)
5532 (verilog-leap-to-head)
5533 (if (verilog-in-case-region-p)
5535 (verilog-leap-to-case-head)
5536 (if (looking-at verilog-extended-case-re)
5537 (throw 'nesting 'case)))))
5539 ((looking-at verilog-defun-level-re)
5540 (if (looking-at verilog-defun-level-generate-only-re)
5541 (if (verilog-in-generate-region-p)
5542 (throw 'continue 'foo) ; always block in a generate - keep looking
5543 (throw 'nesting 'defun))
5544 (throw 'nesting 'defun)))
5546 ((looking-at verilog-cpp-level-re)
5547 (throw 'nesting 'cpp))
5550 (throw 'nesting 'cpp)))))
5552 (throw 'nesting 'cpp))))
5554 (defun verilog-calculate-indent-directive ()
5555 "Return indentation level for directive.
5556 For speed, the searcher looks at the last directive, not the indent
5557 of the appropriate enclosing block."
5558 (let ((base -1) ;; Indent of the line that determines our indentation
5559 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
5560 ;; Start at current location, scan back for another directive
5564 (while (and (< base 0)
5565 (verilog-re-search-backward verilog-directive-re nil t))
5566 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5567 (setq base (current-indentation))))
5568 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
5569 (setq ind (- ind verilog-indent-level-directive)))
5570 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
5571 (setq ind (+ ind verilog-indent-level-directive)))
5572 ((looking-at verilog-directive-begin)
5573 (setq ind (+ ind verilog-indent-level-directive)))))
5574 ;; Adjust indent to starting indent of critical line
5575 (setq ind (max 0 (+ ind base))))
5579 (skip-chars-forward " \t")
5580 (cond ((or (looking-at verilog-directive-middle)
5581 (looking-at verilog-directive-end))
5582 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5585 (defun verilog-leap-to-case-head ()
5588 (verilog-re-search-backward
5590 "\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5591 "\\|\\(\\<endcase\\>\\)" )
5595 (let ((here (point)))
5596 (verilog-beg-of-statement)
5597 (unless (looking-at verilog-extended-case-re)
5599 (setq nest (1- nest)))
5601 (setq nest (1+ nest)))
5606 (defun verilog-leap-to-head ()
5607 "Move point to the head of this block.
5608 Jump from end to matching begin, from endcase to matching case, and so on."
5614 ((looking-at "\\<end\\>")
5615 ;; 1: Search back for matching begin
5616 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5617 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5618 ((looking-at "\\<endtask\\>")
5619 ;; 2: Search back for matching task
5620 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5622 ((looking-at "\\<endcase\\>")
5624 (verilog-leap-to-case-head) )
5625 (setq reg nil) ; to force skip
5628 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5629 ;; 4: Search back for matching fork
5630 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5631 ((looking-at "\\<endclass\\>")
5632 ;; 5: Search back for matching class
5633 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5634 ((looking-at "\\<endtable\\>")
5635 ;; 6: Search back for matching table
5636 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5637 ((looking-at "\\<endspecify\\>")
5638 ;; 7: Search back for matching specify
5639 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5640 ((looking-at "\\<endfunction\\>")
5641 ;; 8: Search back for matching function
5642 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5644 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5645 ((looking-at "\\<endgenerate\\>")
5646 ;; 8: Search back for matching generate
5647 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5648 ((looking-at "\\<endgroup\\>")
5649 ;; 10: Search back for matching covergroup
5650 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5651 ((looking-at "\\<endproperty\\>")
5652 ;; 11: Search back for matching property
5653 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5654 ((looking-at verilog-uvm-end-re)
5655 ;; 12: Search back for matching sequence
5656 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5657 ((looking-at verilog-ovm-end-re)
5658 ;; 12: Search back for matching sequence
5659 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5660 ((looking-at verilog-vmm-end-re)
5661 ;; 12: Search back for matching sequence
5662 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5663 ((looking-at "\\<endinterface\\>")
5664 ;; 12: Search back for matching interface
5665 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5666 ((looking-at "\\<endsequence\\>")
5667 ;; 12: Search back for matching sequence
5668 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5669 ((looking-at "\\<endclocking\\>")
5670 ;; 12: Search back for matching clocking
5671 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5674 (if (eq nesting 'yes)
5676 (while (verilog-re-search-backward reg nil 'move)
5678 ((match-end 1) ; begin
5679 (if (looking-at "fork")
5680 (let ((here (point)))
5681 (verilog-beg-of-statement)
5682 (unless (looking-at verilog-disable-fork-re)
5684 (setq nest (1- nest))))
5685 (setq nest (1- nest)))
5687 ;; Now previous line describes syntax
5692 ((match-end 2) ; end
5693 (setq nest (1+ nest)))
5695 ;; endcase, jump to case
5697 (setq nest (1+ nest))
5699 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5701 ;; join, jump to fork
5703 (setq nest (1+ nest))
5705 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5709 (verilog-re-search-backward reg nil 'move)
5710 (match-end 1)) ; task -> could be virtual and/or protected
5712 (verilog-beg-of-statement)
5714 (throw 'skip 1)))))))
5716 (defun verilog-continued-line ()
5717 "Return true if this is a continued line.
5718 Set point to where line starts."
5719 (let ((continued 't))
5720 (if (eq 0 (forward-line -1))
5723 (verilog-backward-ws&directives)
5725 (setq continued nil)
5726 (while (and continued
5728 (skip-chars-backward " \t")
5730 (setq continued (verilog-backward-token)))))
5731 (setq continued nil))
5734 (defun verilog-backward-token ()
5735 "Step backward token, returning true if this is a continued line."
5737 (verilog-backward-syntactic-ws)
5741 (;-- Anything ending in a ; is complete
5742 (= (preceding-char) ?\;)
5744 (; If a "}" is prefixed by a ";", then this is a complete statement
5745 ; i.e.: constraint foo { a = b; }
5746 (= (preceding-char) ?\})
5749 (not(verilog-at-close-constraint-p))))
5750 (;-- constraint foo { a = b }
5751 ; is a complete statement. *sigh*
5752 (= (preceding-char) ?\{)
5755 (not (verilog-at-constraint-p))))
5757 (= (preceding-char) ?\")
5759 (verilog-skip-backward-comment-or-string)
5763 (= (preceding-char) ?\])
5765 (verilog-backward-open-bracket)
5768 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5769 ; also could be simply '@(foo)'
5771 ; (b, ... which ISN'T complete
5772 ;;;; Do we need this???
5773 (= (preceding-char) ?\))
5776 (verilog-backward-up-list 1)
5777 (verilog-backward-syntactic-ws)
5778 (let ((back (point)))
5782 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5783 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5784 ((looking-at verilog-uvm-statement-re)
5786 ((looking-at verilog-uvm-begin-re)
5788 ((looking-at verilog-uvm-end-re)
5790 ((looking-at verilog-ovm-statement-re)
5792 ((looking-at verilog-ovm-begin-re)
5794 ((looking-at verilog-ovm-end-re)
5796 ;; JBA find VMM macros
5797 ((looking-at verilog-vmm-statement-re)
5799 ((looking-at verilog-vmm-begin-re)
5801 ((looking-at verilog-vmm-end-re)
5803 ;; JBA trying to catch macro lines with no ; at end
5804 ((looking-at "\\<`")
5809 ((= (preceding-char) ?\@)
5812 (verilog-backward-token)
5813 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5814 ((= (preceding-char) ?\#)
5818 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5821 (while (= (preceding-char) ?\_)
5824 ((looking-at "\\<else\\>")
5826 ((looking-at verilog-behavioral-block-beg-re)
5828 ((looking-at verilog-indent-re)
5833 (verilog-backward-syntactic-ws)
5835 ((= (preceding-char) ?\:)
5837 (verilog-backward-syntactic-ws)
5839 (if (looking-at verilog-nameable-item-re )
5842 ((= (preceding-char) ?\#)
5845 ((= (preceding-char) ?\`)
5853 (defun verilog-backward-syntactic-ws ()
5854 "Move backwards putting point after first non-whitespace non-comment."
5855 (verilog-skip-backward-comments)
5856 (forward-comment (- (buffer-size))))
5858 (defun verilog-backward-syntactic-ws-quick ()
5859 "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
5860 (while (cond ((bobp)
5862 ((> (skip-syntax-backward " ") 0)
5864 ((eq (preceding-char) ?\n) ;; \n's terminate // so aren't space syntax
5867 ((or (verilog-inside-comment-or-string-p (1- (point)))
5868 (verilog-inside-comment-or-string-p (point)))
5869 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
5872 (defun verilog-forward-syntactic-ws ()
5873 (verilog-skip-forward-comment-p)
5874 (forward-comment (buffer-size)))
5876 (defun verilog-backward-ws&directives (&optional bound)
5877 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
5878 Optional BOUND limits search."
5880 (let* ((bound (or bound (point-min)))
5883 (if (< bound (point))
5885 (let ((state (save-excursion (verilog-syntax-ppss))))
5887 ((nth 7 state) ;; in // comment
5888 (verilog-re-search-backward "//" nil 'move)
5889 (skip-chars-backward "/"))
5890 ((nth 4 state) ;; in /* */ comment
5891 (verilog-re-search-backward "/\*" nil 'move))))
5892 (narrow-to-region bound (point))
5893 (while (/= here (point))
5895 (verilog-skip-backward-comments)
5900 ((and verilog-highlight-translate-off
5901 (verilog-within-translate-off))
5902 (verilog-back-to-start-translate-off (point-min)))
5903 ((looking-at verilog-directive-re-1)
5907 (if p (goto-char p))))))))
5909 (defun verilog-forward-ws&directives (&optional bound)
5910 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
5911 Optional BOUND limits search."
5913 (let* ((bound (or bound (point-max)))
5916 (if (> bound (point))
5918 (let ((state (save-excursion (verilog-syntax-ppss))))
5920 ((nth 7 state) ;; in // comment
5923 (skip-chars-forward " \t\n\f")
5925 ((nth 4 state) ;; in /* */ comment
5926 (verilog-re-search-forward "\*\/\\s-*" nil 'move))))
5927 (narrow-to-region (point) bound)
5928 (while (/= here (point))
5931 (forward-comment (buffer-size))
5932 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ;; Attribute
5933 (goto-char (match-end 0)))
5936 (if (looking-at verilog-directive-re-1)
5939 (beginning-of-line 2))))))))
5941 (defun verilog-in-comment-p ()
5942 "Return true if in a star or // comment."
5943 (let ((state (save-excursion (verilog-syntax-ppss))))
5944 (or (nth 4 state) (nth 7 state))))
5946 (defun verilog-in-star-comment-p ()
5947 "Return true if in a star comment."
5948 (let ((state (save-excursion (verilog-syntax-ppss))))
5950 (nth 4 state) ; t if in a comment of style a // or b /**/
5952 (nth 7 state) ; t if in a comment of style b /**/
5955 (defun verilog-in-slash-comment-p ()
5956 "Return true if in a slash comment."
5957 (let ((state (save-excursion (verilog-syntax-ppss))))
5960 (defun verilog-in-comment-or-string-p ()
5961 "Return true if in a string or comment."
5962 (let ((state (save-excursion (verilog-syntax-ppss))))
5963 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
5965 (defun verilog-in-attribute-p ()
5966 "Return true if point is in an attribute (* [] attribute *)."
5969 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
5970 (numberp (match-beginning 1)))))
5972 (defun verilog-in-parameter-p ()
5973 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
5976 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
5977 (numberp (match-beginning 1)))))
5979 (defun verilog-in-escaped-name-p ()
5980 "Return true if in an escaped name."
5983 (skip-chars-backward "^ \t\n\f")
5984 (if (equal (char-after (point) ) ?\\ )
5987 (defun verilog-in-directive-p ()
5988 "Return true if in a directive."
5991 (looking-at verilog-directive-re-1)))
5993 (defun verilog-in-parenthesis-p ()
5994 "Return true if in a ( ) expression (but not { } or [ ])."
5997 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
5998 (numberp (match-beginning 1)))))
6000 (defun verilog-in-paren ()
6001 "Return true if in a parenthetical expression.
6002 May cache result using `verilog-syntax-ppss'."
6003 (let ((state (save-excursion (verilog-syntax-ppss))))
6004 (> (nth 0 state) 0 )))
6006 (defun verilog-in-paren-count ()
6007 "Return paren depth, floor to 0.
6008 May cache result using `verilog-syntax-ppss'."
6009 (let ((state (save-excursion (verilog-syntax-ppss))))
6010 (if (> (nth 0 state) 0)
6014 (defun verilog-in-paren-quick ()
6015 "Return true if in a parenthetical expression.
6016 Always starts from `point-min', to allow inserts with hooks disabled."
6017 ;; The -quick refers to its use alongside the other -quick functions,
6018 ;; not that it's likely to be faster than verilog-in-paren.
6019 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
6020 (> (nth 0 state) 0 )))
6022 (defun verilog-in-struct-p ()
6023 "Return true if in a struct declaration."
6026 (if (verilog-in-paren)
6028 (verilog-backward-up-list 1)
6029 (verilog-at-struct-p)
6033 (defun verilog-in-struct-nested-p ()
6034 "Return nil for not in struct.
6035 Return 0 for in non-nested struct.
6036 Return >0 for nested struct."
6040 (if (verilog-in-paren)
6042 (verilog-backward-up-list 1)
6043 (setq col (verilog-at-struct-mv-p))
6045 (if (verilog-in-struct-p) (current-column) 0)))
6048 (defun verilog-in-coverage-p ()
6049 "Return true if in a constraint or coverpoint expression."
6052 (if (verilog-in-paren)
6054 (verilog-backward-up-list 1)
6055 (verilog-at-constraint-p)
6058 (defun verilog-at-close-constraint-p ()
6059 "If at the } that closes a constraint or covergroup, return true."
6061 (equal (char-after) ?\})
6062 (verilog-in-coverage-p))
6065 (verilog-backward-ws&directives)
6066 (if (or (equal (char-before) ?\;)
6067 (equal (char-before) ?\}) ;; can end with inner constraint { } block or ;
6068 (equal (char-before) ?\{)) ;; empty constraint block
6072 (defun verilog-at-constraint-p ()
6073 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
6076 (equal (char-after) ?\{)
6078 (progn (backward-char 1)
6079 (verilog-backward-ws&directives)
6080 (or (equal (char-before) ?\{) ;; empty case
6081 (equal (char-before) ?\;)
6082 (equal (char-before) ?\})))))
6084 (let ( (pt (point)) (pass 0))
6085 (verilog-backward-ws&directives)
6086 (verilog-backward-token)
6087 (if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
6088 (progn (setq pass 1)
6089 (if (looking-at "\\<with\\>")
6090 (progn (verilog-backward-ws&directives)
6091 (beginning-of-line) ;; 1
6092 (verilog-forward-ws&directives)
6094 (verilog-beg-of-statement)
6096 ;; if first word token not keyword, it maybe the instance name
6097 ;; check next word token
6098 (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\w+")
6099 (progn (verilog-beg-of-statement)
6100 (if (looking-at (concat "\\<\\(constraint\\|"
6101 "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
6102 "\\|with\\)\\>\\|" verilog-in-constraint-re))
6105 (progn (goto-char pt) nil) 1)))
6109 (defun verilog-at-struct-p ()
6110 "If at the { of a struct, return true, not moving point."
6112 (if (and (equal (char-after) ?\{)
6113 (verilog-backward-token))
6114 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6117 (defun verilog-at-struct-mv-p ()
6118 "If at the { of a struct, return true, moving point to struct."
6120 (if (and (equal (char-after) ?\{)
6121 (verilog-backward-token))
6122 (if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6123 (progn (verilog-beg-of-statement) (point))
6124 (progn (goto-char pt) nil))
6125 (progn (goto-char pt) nil))))
6127 (defun verilog-at-close-struct-p ()
6128 "If at the } that closes a struct, return true."
6130 (equal (char-after) ?\})
6131 (verilog-in-struct-p))
6134 (if (looking-at "}\\(?:\\s-*\\w+\\s-*\\)?;") 1))
6138 (defun verilog-parenthesis-depth ()
6139 "Return non zero if in parenthetical-expression."
6140 (save-excursion (nth 1 (verilog-syntax-ppss))))
6143 (defun verilog-skip-forward-comment-or-string ()
6144 "Return true if in a string or comment."
6145 (let ((state (save-excursion (verilog-syntax-ppss))))
6147 ((nth 3 state) ;Inside string
6148 (search-forward "\"")
6150 ((nth 7 state) ;Inside // comment
6153 ((nth 4 state) ;Inside any comment (hence /**/)
6154 (search-forward "*/"))
6158 (defun verilog-skip-backward-comment-or-string ()
6159 "Return true if in a string or comment."
6160 (let ((state (save-excursion (verilog-syntax-ppss))))
6162 ((nth 3 state) ;Inside string
6163 (search-backward "\"")
6165 ((nth 7 state) ;Inside // comment
6166 (search-backward "//")
6167 (skip-chars-backward "/")
6169 ((nth 4 state) ;Inside /* */ comment
6170 (search-backward "/*")
6175 (defun verilog-skip-backward-comments ()
6176 "Return true if a comment was skipped."
6180 (let ((state (save-excursion (verilog-syntax-ppss))))
6182 ((nth 7 state) ;Inside // comment
6183 (search-backward "//")
6184 (skip-chars-backward "/")
6185 (skip-chars-backward " \t\n\f")
6187 ((nth 4 state) ;Inside /* */ comment
6188 (search-backward "/*")
6189 (skip-chars-backward " \t\n\f")
6192 (= (char-before) ?\/)
6193 (= (char-before (1- (point))) ?\*))
6194 (goto-char (- (point) 2))
6195 t) ;; Let nth 4 state handle the rest
6197 (= (char-before) ?\))
6198 (= (char-before (1- (point))) ?\*))
6199 (goto-char (- (point) 2))
6200 (if (search-backward "(*" nil t)
6202 (skip-chars-backward " \t\n\f")
6205 (goto-char (+ (point) 2))
6208 (/= (skip-chars-backward " \t\n\f") 0))))))))
6210 (defun verilog-skip-forward-comment-p ()
6211 "If in comment, move to end and return true."
6213 (state (save-excursion (verilog-syntax-ppss)))
6215 ((nth 3 state) ;Inside string
6217 ((nth 7 state) ;Inside // comment
6221 ((nth 4 state) ;Inside /* comment
6222 (search-forward "*/")
6224 ((verilog-in-attribute-p) ;Inside (* attribute
6225 (search-forward "*)" nil t)
6228 (skip-chars-forward " \t\n\f")
6231 ((looking-at "\\/\\*")
6234 (goto-char (match-end 0))
6235 (if (search-forward "*/" nil t)
6237 (skip-chars-forward " \t\n\f")
6242 ((looking-at "(\\*")
6245 (goto-char (match-end 0))
6246 (if (search-forward "*)" nil t)
6248 (skip-chars-forward " \t\n\f")
6256 (defun verilog-indent-line-relative ()
6257 "Cheap version of indent line.
6258 Only look at a few lines to determine indent level."
6262 (if (looking-at "^[ \t]*$")
6263 (cond ;- A blank line; No need to be too smart.
6265 (setq indent-str (list 'cpp 0)))
6266 ((verilog-continued-line)
6267 (let ((sp1 (point)))
6268 (if (verilog-continued-line)
6272 (list 'statement (verilog-current-indent-level))))
6274 (setq indent-str (list 'block (verilog-current-indent-level)))))
6277 (setq indent-str (verilog-calculate-indent))))
6278 (progn (skip-chars-forward " \t")
6279 (setq indent-str (verilog-calculate-indent))))
6280 (verilog-do-indent indent-str)))
6282 (defun verilog-indent-line ()
6283 "Indent for special part of code."
6284 (verilog-do-indent (verilog-calculate-indent)))
6286 (defun verilog-do-indent (indent-str)
6287 (let ((type (car indent-str))
6288 (ind (car (cdr indent-str))))
6290 (; handle continued exp
6292 (let ((here (point)))
6293 (verilog-backward-syntactic-ws)
6296 (= (preceding-char) ?\,)
6297 (= (preceding-char) ?\])
6299 (verilog-beg-of-statement-1)
6300 (looking-at verilog-declaration-re)))
6305 (verilog-beg-of-statement-1)
6307 (if (looking-at verilog-declaration-re)
6308 (progn ;; we have multiple words
6309 (goto-char (match-end 0))
6310 (skip-chars-forward " \t")
6312 ((and verilog-indent-declaration-macros
6313 (= (following-char) ?\`))
6317 (skip-chars-forward " \t")))
6318 ((= (following-char) ?\[)
6321 (verilog-backward-up-list -1)
6322 (skip-chars-forward " \t"))))
6326 (+ (current-column) verilog-cexp-indent))))))
6328 (indent-line-to val)
6329 (if (and (not verilog-indent-lists)
6331 (verilog-pretty-declarations-auto))
6333 ((= (preceding-char) ?\) )
6335 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6336 (indent-line-to val)))
6340 (verilog-beg-of-statement-1)
6341 (if (and (< (point) here)
6342 (verilog-re-search-forward "=[ \\t]*" here 'move))
6343 (setq val (current-column))
6344 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6346 (indent-line-to val))))))
6348 (; handle inside parenthetical expressions
6349 (eq type 'cparenexp)
6351 (val (save-excursion
6352 (verilog-backward-up-list 1)
6354 (if verilog-indent-lists
6355 (skip-chars-forward " \t")
6356 (verilog-forward-syntactic-ws))
6360 (decl (save-excursion
6362 (verilog-forward-syntactic-ws)
6364 (looking-at verilog-declaration-re))))
6365 (indent-line-to val)
6367 (verilog-pretty-declarations-auto))))
6369 (;-- Handle the ends
6371 (looking-at verilog-end-block-re)
6372 (verilog-at-close-constraint-p)
6373 (verilog-at-close-struct-p))
6374 (let ((val (if (eq type 'statement)
6375 (- ind verilog-indent-level)
6377 (indent-line-to val)))
6379 (;-- Case -- maybe line 'em up
6380 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6383 ((looking-at "\\<endcase\\>")
6384 (indent-line-to ind))
6386 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6387 (indent-line-to val))))))
6390 (and (eq type 'defun)
6391 (looking-at verilog-zero-indent-re))
6398 (looking-at verilog-declaration-re))
6399 (verilog-indent-declaration ind))
6401 (;-- Everything else
6403 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6404 (indent-line-to val))))
6406 (if (looking-at "[ \t]+$")
6407 (skip-chars-forward " \t"))
6408 indent-str ; Return indent data
6411 (defun verilog-current-indent-level ()
6412 "Return the indent-level of the current statement."
6416 (setq par-pos (verilog-parenthesis-depth))
6420 (setq par-pos (verilog-parenthesis-depth)))
6421 (skip-chars-forward " \t")
6424 (defun verilog-case-indent-level ()
6425 "Return the indent-level of the current statement.
6426 Do not count named blocks or case-statements."
6428 (skip-chars-forward " \t")
6430 ((looking-at verilog-named-block-re)
6432 ((and (not (looking-at verilog-extended-case-re))
6433 (looking-at "^[^:;]+[ \t]*:"))
6434 (verilog-re-search-forward ":" nil t)
6435 (skip-chars-forward " \t")
6438 (current-column)))))
6440 (defun verilog-indent-comment ()
6441 "Indent current line as comment."
6444 ((verilog-in-star-comment-p)
6446 (re-search-backward "/\\*" nil t)
6447 (1+(current-column))))
6452 (re-search-backward "//" nil t)
6453 (current-column))))))
6454 (indent-line-to stcol)
6457 (defun verilog-more-comment ()
6458 "Make more comment lines like the previous."
6462 ((verilog-in-star-comment-p)
6465 (re-search-backward "/\\*" nil t)
6466 (1+(current-column))))
6471 (re-search-backward "//" nil t)
6472 (current-column))))))
6478 (skip-chars-forward " \t")
6482 (defun verilog-comment-indent (&optional _arg)
6483 "Return the column number the line should be indented to.
6484 _ARG is ignored, for `comment-indent-function' compatibility."
6486 ((verilog-in-star-comment-p)
6488 (re-search-backward "/\\*" nil t)
6489 (1+(current-column))))
6494 (re-search-backward "//" nil t)
6495 (current-column)))))
6499 (defun verilog-pretty-declarations-auto (&optional quiet)
6500 "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
6501 (when (or (eq 'all verilog-auto-lineup)
6502 (eq 'declarations verilog-auto-lineup))
6503 (verilog-pretty-declarations quiet)))
6505 (defun verilog-pretty-declarations (&optional quiet)
6506 "Line up declarations around point.
6507 Be verbose about progress unless optional QUIET set."
6509 (let* ((m1 (make-marker))
6523 ; (verilog-beg-of-statement-1)
6525 (verilog-forward-syntactic-ws)
6526 (and (not (verilog-in-directive-p)) ;; could have `define input foo
6527 (looking-at verilog-declaration-re)))
6529 (if (verilog-parenthesis-depth)
6530 ;; in an argument list or parameter block
6531 (setq el (verilog-backward-up-list -1)
6534 (verilog-backward-up-list 1)
6535 (forward-line) ;; ignore ( input foo,
6536 (verilog-re-search-forward verilog-declaration-re el 'move)
6537 (goto-char (match-beginning 0))
6538 (skip-chars-backward " \t")
6540 startpos (set-marker (make-marker) start)
6543 (verilog-backward-up-list -1)
6545 (verilog-backward-syntactic-ws)
6547 endpos (set-marker (make-marker) end)
6551 (skip-chars-forward " \t")
6554 ;; in a declaration block (not in argument list)
6557 (verilog-beg-of-statement-1)
6558 (while (and (looking-at verilog-declaration-re)
6560 (skip-chars-backward " \t")
6563 (verilog-backward-syntactic-ws)
6565 (verilog-beg-of-statement-1))
6567 startpos (set-marker (make-marker) start)
6570 (verilog-end-of-statement)
6571 (setq e (point)) ;Might be on last line
6572 (verilog-forward-syntactic-ws)
6573 (while (looking-at verilog-declaration-re)
6574 (verilog-end-of-statement)
6576 (verilog-forward-syntactic-ws))
6578 endpos (set-marker (make-marker) end)
6581 (verilog-do-indent (verilog-calculate-indent))
6582 (verilog-forward-ws&directives)
6584 ;; OK, start and end are set
6585 (goto-char (marker-position startpos))
6586 (if (and (not quiet)
6587 (> (- end start) 100))
6588 (message "Lining up declarations..(please stand by)"))
6589 ;; Get the beginning of line indent first
6590 (while (progn (setq e (marker-position endpos))
6593 ((save-excursion (skip-chars-backward " \t")
6595 (verilog-forward-ws&directives)
6596 (indent-line-to base-ind)
6597 (verilog-forward-ws&directives)
6599 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6602 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6605 ;; Now find biggest prefix
6606 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6607 ;; Now indent each line.
6608 (goto-char (marker-position startpos))
6609 (while (progn (setq e (marker-position endpos))
6610 (setq r (- e (point)))
6613 (unless quiet (message "%d" r))
6614 ;;(verilog-do-indent (verilog-calculate-indent)))
6615 (verilog-forward-ws&directives)
6617 ((or (and verilog-indent-declaration-macros
6618 (looking-at verilog-declaration-re-2-macro))
6619 (looking-at verilog-declaration-re-2-no-macro))
6620 (let ((p (match-end 0)))
6622 (if (verilog-re-search-forward "[[#`]" p 'move)
6626 (goto-char (marker-position m1))
6632 ((verilog-continued-line-1 (marker-position startpos))
6634 (indent-line-to ind))
6635 ((verilog-in-struct-p)
6636 ;; could have a declaration of a user defined item
6638 (verilog-end-of-statement))
6639 (t ; Must be comment or white space
6641 (verilog-forward-ws&directives)
6644 (unless quiet (message "")))))))
6646 (defun verilog-pretty-expr (&optional quiet _myre)
6647 "Line up expressions around point, optionally QUIET with regexp _MYRE ignored."
6649 (if (not (verilog-in-comment-or-string-p))
6651 (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
6652 (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
6654 (if (and (not (looking-at rexp ))
6655 (looking-at verilog-assignment-operation-re)
6657 (goto-char (match-end 2))
6658 (and (not (verilog-in-attribute-p))
6659 (not (verilog-in-parameter-p))
6660 (not (verilog-in-comment-or-string-p)))))
6661 (let* ((here (point))
6667 (verilog-backward-syntactic-ws)
6669 (while (and (not (looking-at rexp1))
6670 (looking-at verilog-assignment-operation-re)
6674 (verilog-backward-syntactic-ws)
6676 ) ;Ack, need to grok `define
6682 (setq e (point)) ;Might be on last line
6683 (verilog-forward-syntactic-ws)
6686 (not (looking-at rexp1 ))
6687 (looking-at verilog-assignment-operation-re)
6690 (not (eq e (point)))))
6692 (verilog-forward-syntactic-ws)
6696 (endpos (set-marker (make-marker) end))
6700 (verilog-do-indent (verilog-calculate-indent))
6701 (if (and (not quiet)
6702 (> (- end start) 100))
6703 (message "Lining up expressions..(please stand by)"))
6705 ;; Set indent to minimum throughout region
6706 (while (< (point) (marker-position endpos))
6708 (verilog-just-one-space verilog-assignment-operation-re)
6710 (verilog-do-indent (verilog-calculate-indent))
6712 (verilog-forward-syntactic-ws)
6715 ;; Now find biggest prefix
6716 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6718 ;; Now indent each line.
6720 (while (progn (setq e (marker-position endpos))
6721 (setq r (- e (point)))
6724 (if (not quiet) (message "%d" r))
6726 ((looking-at verilog-assignment-operation-re)
6727 (goto-char (match-beginning 2))
6728 (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone
6729 (verilog-in-coverage-p)))
6730 (if (eq (char-after) ?=)
6731 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6735 ((verilog-continued-line-1 start)
6737 (indent-line-to ind))
6738 (t ; Must be comment or white space
6740 (verilog-forward-ws&directives)
6744 (unless quiet (message ""))
6747 (defun verilog-just-one-space (myre)
6748 "Remove extra spaces around regular expression MYRE."
6750 (if (and (not(looking-at verilog-complete-reg))
6752 (let ((p1 (match-end 1))
6758 (just-one-space)))))
6760 (defun verilog-indent-declaration (baseind)
6761 "Indent current lines as declaration.
6762 Line up the variable names based on previous declaration's indentation.
6763 BASEIND is the base indent to offset everything."
6765 (let ((pos (point-marker))
6766 (lim (save-excursion
6767 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6768 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6774 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6775 (indent-line-to val)
6777 ;; Use previous declaration (in this module) as template.
6778 (if (or (eq 'all verilog-auto-lineup)
6779 (eq 'declarations verilog-auto-lineup))
6780 (if (verilog-re-search-backward
6781 (or (and verilog-indent-declaration-macros
6782 verilog-declaration-re-1-macro)
6783 verilog-declaration-re-1-no-macro) lim t)
6785 (goto-char (match-end 0))
6786 (skip-chars-forward " \t")
6787 (setq ind (current-column))
6791 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6792 (indent-line-to val)
6793 (if (and verilog-indent-declaration-macros
6794 (looking-at verilog-declaration-re-2-macro))
6795 (let ((p (match-end 0)))
6797 (if (verilog-re-search-forward "[[#`]" p 'move)
6801 (goto-char (marker-position m1))
6804 (if (/= (current-column) ind)
6808 (if (looking-at verilog-declaration-re-2-no-macro)
6809 (let ((p (match-end 0)))
6811 (if (verilog-re-search-forward "[[`#]" p 'move)
6815 (goto-char (marker-position m1))
6818 (if (/= (current-column) ind)
6821 (indent-to ind))))))))))
6824 (defun verilog-get-lineup-indent (b edpos)
6825 "Return the indent level that will line up several lines within the region.
6826 Region is defined by B and EDPOS."
6830 ;; Get rightmost position
6831 (while (progn (setq e (marker-position edpos))
6833 (if (verilog-re-search-forward
6834 (or (and verilog-indent-declaration-macros
6835 verilog-declaration-re-1-macro)
6836 verilog-declaration-re-1-no-macro) e 'move)
6838 (goto-char (match-end 0))
6839 (verilog-backward-syntactic-ws)
6840 (if (> (current-column) ind)
6841 (setq ind (current-column)))
6842 (goto-char (match-end 0)))))
6845 ;; No lineup-string found
6848 (verilog-backward-syntactic-ws)
6849 ;;(skip-chars-backward " \t")
6850 (1+ (current-column))))))
6852 (defun verilog-get-lineup-indent-2 (myre b edpos)
6853 "Return the indent level that will line up several lines within the region."
6857 ;; Get rightmost position
6858 (while (progn (setq e (marker-position edpos))
6860 (if (and (verilog-re-search-forward myre e 'move)
6861 (not (verilog-in-attribute-p))) ;; skip attribute exprs
6863 (goto-char (match-beginning 2))
6864 (verilog-backward-syntactic-ws)
6865 (if (> (current-column) ind)
6866 (setq ind (current-column)))
6867 (goto-char (match-end 0)))
6871 ;; No lineup-string found
6874 (skip-chars-backward " \t")
6875 (1+ (current-column))))))
6877 (defun verilog-comment-depth (type val)
6878 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
6885 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
6887 (replace-match " /* -# ## */")
6891 (insert " /* ## ## */"))))
6894 (format "%s %d" type val))))
6900 (defvar verilog-str nil)
6901 (defvar verilog-all nil)
6902 (defvar verilog-pred nil)
6903 (defvar verilog-buffer-to-use nil)
6904 (defvar verilog-flag nil)
6905 (defvar verilog-toggle-completions nil
6906 "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
6907 Repeated use of \\[verilog-complete-word] will show you all of them.
6908 Normally, when there is more than one possible completion,
6909 it displays a list of all possible completions.")
6912 (defvar verilog-type-keywords
6914 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
6915 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
6916 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
6917 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
6918 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
6919 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
6921 "Keywords for types used when completing a word in a declaration or parmlist.
6922 \(integer, real, reg...)")
6924 (defvar verilog-cpp-keywords
6925 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
6927 "Keywords to complete when at first word of a line in declarative scope.
6928 \(initial, always, begin, assign...)
6929 The procedures and variables defined within the Verilog program
6930 will be completed at runtime and should not be added to this list.")
6932 (defvar verilog-defun-keywords
6935 "always" "always_comb" "always_ff" "always_latch" "assign"
6936 "begin" "end" "generate" "endgenerate" "module" "endmodule"
6937 "specify" "endspecify" "function" "endfunction" "initial" "final"
6938 "task" "endtask" "primitive" "endprimitive"
6940 verilog-type-keywords)
6941 "Keywords to complete when at first word of a line in declarative scope.
6942 \(initial, always, begin, assign...)
6943 The procedures and variables defined within the Verilog program
6944 will be completed at runtime and should not be added to this list.")
6946 (defvar verilog-block-keywords
6948 "begin" "break" "case" "continue" "else" "end" "endfunction"
6949 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
6950 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
6952 "Keywords to complete when at first word of a line in behavioral scope.
6953 \(begin, if, then, else, for, fork...)
6954 The procedures and variables defined within the Verilog program
6955 will be completed at runtime and should not be added to this list.")
6957 (defvar verilog-tf-keywords
6958 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
6959 "Keywords to complete when at first word of a line in a task or function.
6960 \(begin, if, then, else, for, fork.)
6961 The procedures and variables defined within the Verilog program
6962 will be completed at runtime and should not be added to this list.")
6964 (defvar verilog-case-keywords
6965 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
6966 "Keywords to complete when at first word of a line in case scope.
6967 \(begin, if, then, else, for, fork...)
6968 The procedures and variables defined within the Verilog program
6969 will be completed at runtime and should not be added to this list.")
6971 (defvar verilog-separator-keywords
6972 '("else" "then" "begin")
6973 "Keywords to complete when NOT standing at the first word of a statement.
6974 \(else, then, begin...)
6975 Variables and function names defined within the Verilog program
6976 will be completed at runtime and should not be added to this list.")
6978 (defvar verilog-gate-ios
6979 ;; All these have an implied {"input"...} at the end
6993 ("pulldown" "output")
6998 ("rtran" "inout" "inout")
6999 ("rtranif0" "inout" "inout")
7000 ("rtranif1" "inout" "inout")
7001 ("tran" "inout" "inout")
7002 ("tranif0" "inout" "inout")
7003 ("tranif1" "inout" "inout")
7006 "Map of direction for each positional argument to each gate primitive.")
7008 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
7009 "Keywords for gate primitives.")
7011 (defun verilog-string-diff (str1 str2)
7012 "Return index of first letter where STR1 and STR2 differs."
7016 (if (or (> (1+ diff) (length str1))
7017 (> (1+ diff) (length str2)))
7019 (or (equal (aref str1 diff) (aref str2 diff))
7021 (setq diff (1+ diff))))))
7023 ;; Calculate all possible completions for functions if argument is `function',
7024 ;; completions for procedures if argument is `procedure' or both functions and
7025 ;; procedures otherwise.
7027 (defun verilog-func-completion (type)
7028 "Build regular expression for module/task/function names.
7029 TYPE is 'module, 'tf for task or function, or t if unknown."
7030 (if (string= verilog-str "")
7031 (setq verilog-str "[a-zA-Z_]"))
7032 (let ((verilog-str (concat (cond
7033 ((eq type 'module) "\\<\\(module\\)\\s +")
7034 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
7035 (t "\\<\\(task\\|function\\|module\\)\\s +"))
7036 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
7039 (if (not (looking-at verilog-defun-re))
7040 (verilog-re-search-backward verilog-defun-re nil t))
7043 ;; Search through all reachable functions
7044 (goto-char (point-min))
7045 (while (verilog-re-search-forward verilog-str (point-max) t)
7046 (progn (setq match (buffer-substring (match-beginning 2)
7048 (if (or (null verilog-pred)
7049 (funcall verilog-pred match))
7050 (setq verilog-all (cons match verilog-all)))))
7051 (if (match-beginning 0)
7052 (goto-char (match-beginning 0)))))
7054 (defun verilog-get-completion-decl (end)
7055 "Macro for searching through current declaration (var, type or const)
7056 for matches of `str' and adding the occurrence tp `all' through point END."
7057 (let ((re (or (and verilog-indent-declaration-macros
7058 verilog-declaration-re-2-macro)
7059 verilog-declaration-re-2-no-macro))
7062 (while (and (< (point) end)
7063 (verilog-re-search-forward re end t))
7064 ;; Traverse current line
7065 (setq decl-end (save-excursion (verilog-declaration-end)))
7066 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
7067 (not (match-end 1)))
7068 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
7069 (if (string-match (concat "\\<" verilog-str) match)
7070 (if (or (null verilog-pred)
7071 (funcall verilog-pred match))
7072 (setq verilog-all (cons match verilog-all)))))
7076 (defun verilog-var-completion ()
7077 "Calculate all possible completions for variables (or constants)."
7078 (let ((start (point)))
7079 ;; Search for all reachable var declarations
7080 (verilog-beg-of-defun)
7082 ;; Check var declarations
7083 (verilog-get-completion-decl start))))
7085 (defun verilog-keyword-completion (keyword-list)
7086 "Give list of all possible completions of keywords in KEYWORD-LIST."
7088 (if (string-match (concat "\\<" verilog-str) s)
7089 (if (or (null verilog-pred)
7090 (funcall verilog-pred s))
7091 (setq verilog-all (cons s verilog-all)))))
7095 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
7096 "Function passed to `completing-read', `try-completion' or `all-completions'.
7097 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
7098 must be a function to be called for every match to check if this should
7099 really be a match. If VERILOG-FLAG is t, the function returns a list of
7100 all possible completions. If VERILOG-FLAG is nil it returns a string,
7101 the longest possible completion, or t if VERILOG-STR is an exact match.
7102 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
7103 exact match, nil otherwise."
7105 (let ((verilog-all nil))
7106 ;; Set buffer to use for searching labels. This should be set
7107 ;; within functions which use verilog-completions
7108 (set-buffer verilog-buffer-to-use)
7110 ;; Determine what should be completed
7111 (let ((state (car (verilog-calculate-indent))))
7112 (cond ((eq state 'defun)
7113 (save-excursion (verilog-var-completion))
7114 (verilog-func-completion 'module)
7115 (verilog-keyword-completion verilog-defun-keywords))
7117 ((eq state 'behavioral)
7118 (save-excursion (verilog-var-completion))
7119 (verilog-func-completion 'module)
7120 (verilog-keyword-completion verilog-defun-keywords))
7123 (save-excursion (verilog-var-completion))
7124 (verilog-func-completion 'tf)
7125 (verilog-keyword-completion verilog-block-keywords))
7128 (save-excursion (verilog-var-completion))
7129 (verilog-func-completion 'tf)
7130 (verilog-keyword-completion verilog-case-keywords))
7133 (save-excursion (verilog-var-completion))
7134 (verilog-func-completion 'tf)
7135 (verilog-keyword-completion verilog-tf-keywords))
7138 (save-excursion (verilog-var-completion))
7139 (verilog-keyword-completion verilog-cpp-keywords))
7141 ((eq state 'cparenexp)
7142 (save-excursion (verilog-var-completion)))
7145 (save-excursion (verilog-var-completion))
7146 (verilog-func-completion 'both)
7147 (verilog-keyword-completion verilog-separator-keywords))))
7149 ;; Now we have built a list of all matches. Give response to caller
7150 (verilog-completion-response))))
7152 (defun verilog-completion-response ()
7153 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
7154 ;; This was not called by all-completions
7155 (if (null verilog-all)
7156 ;; Return nil if there was no matching label
7158 ;; Get longest string common in the labels
7159 ;; FIXME: Why not use `try-completion'?
7160 (let* ((elm (cdr verilog-all))
7161 (match (car verilog-all))
7162 (min (length match))
7164 (if (string= match verilog-str)
7165 ;; Return t if first match was an exact match
7167 (while (not (null elm))
7168 ;; Find longest common string
7169 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
7172 (setq match (substring match 0 min))))
7173 ;; Terminate with match=t if this is an exact match
7174 (if (string= (car elm) verilog-str)
7178 (setq elm (cdr elm)))))
7179 ;; If this is a test just for exact match, return nil ot t
7180 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
7183 ;; If flag is t, this was called by all-completions. Return
7184 ;; list of all possible completions
7188 (defvar verilog-last-word-numb 0)
7189 (defvar verilog-last-word-shown nil)
7190 (defvar verilog-last-completions nil)
7192 (defun verilog-complete-word ()
7193 "Complete word at current point.
7194 \(See also `verilog-toggle-completions', `verilog-type-keywords',
7195 and `verilog-separator-keywords'.)"
7196 ;; FIXME: Provide completion-at-point-function.
7198 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7199 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7200 (verilog-str (buffer-substring b e))
7201 ;; The following variable is used in verilog-completion
7202 (verilog-buffer-to-use (current-buffer))
7203 (allcomp (if (and verilog-toggle-completions
7204 (string= verilog-last-word-shown verilog-str))
7205 verilog-last-completions
7206 (all-completions verilog-str 'verilog-completion)))
7207 (match (if verilog-toggle-completions
7209 verilog-str (mapcar (lambda (elm)
7210 (cons elm 0)) allcomp)))))
7211 ;; Delete old string
7214 ;; Toggle-completions inserts whole labels
7215 (if verilog-toggle-completions
7217 ;; Update entry number in list
7218 (setq verilog-last-completions allcomp
7219 verilog-last-word-numb
7220 (if (>= verilog-last-word-numb (1- (length allcomp)))
7222 (1+ verilog-last-word-numb)))
7223 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7224 ;; Display next match or same string if no match was found
7225 (if (not (null allcomp))
7226 (insert "" verilog-last-word-shown)
7227 (insert "" verilog-str)
7228 (message "(No match)")))
7229 ;; The other form of completion does not necessarily do that.
7231 ;; Insert match if found, or the original string if no match
7232 (if (or (null match) (equal match 't))
7233 (progn (insert "" verilog-str)
7234 (message "(No match)"))
7236 ;; Give message about current status of completion
7237 (cond ((equal match 't)
7238 (if (not (null (cdr allcomp)))
7239 (message "(Complete but not unique)")
7240 (message "(Sole completion)")))
7241 ;; Display buffer if the current completion didn't help
7242 ;; on completing the label.
7243 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7245 (with-output-to-temp-buffer "*Completions*"
7246 (display-completion-list allcomp))
7247 ;; Wait for a key press. Then delete *Completion* window
7248 (momentary-string-display "" (point))
7249 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7252 (defun verilog-show-completions ()
7253 "Show all possible completions at current point."
7255 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7256 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7257 (verilog-str (buffer-substring b e))
7258 ;; The following variable is used in verilog-completion
7259 (verilog-buffer-to-use (current-buffer))
7260 (allcomp (if (and verilog-toggle-completions
7261 (string= verilog-last-word-shown verilog-str))
7262 verilog-last-completions
7263 (all-completions verilog-str 'verilog-completion))))
7264 ;; Show possible completions in a temporary buffer.
7265 (with-output-to-temp-buffer "*Completions*"
7266 (display-completion-list allcomp))
7267 ;; Wait for a key press. Then delete *Completion* window
7268 (momentary-string-display "" (point))
7269 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7272 (defun verilog-get-default-symbol ()
7273 "Return symbol around current point as a string."
7275 (buffer-substring (progn
7276 (skip-chars-backward " \t")
7277 (skip-chars-backward "a-zA-Z0-9_")
7280 (skip-chars-forward "a-zA-Z0-9_")
7283 (defun verilog-build-defun-re (str &optional arg)
7284 "Return function/task/module starting with STR as regular expression.
7285 With optional second ARG non-nil, STR is the complete name of the instruction."
7287 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7288 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7290 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7291 "Function passed to `completing-read', `try-completion' or `all-completions'.
7292 Returns a completion on any function name based on VERILOG-STR prefix. If
7293 VERILOG-PRED is non-nil, it must be a function to be called for every match
7294 to check if this should really be a match. If VERILOG-FLAG is t, the
7295 function returns a list of all possible completions. If it is nil it
7296 returns a string, the longest possible completion, or t if VERILOG-STR is
7297 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
7298 VERILOG-STR is an exact match, nil otherwise."
7300 (let ((verilog-all nil)
7303 ;; Set buffer to use for searching labels. This should be set
7304 ;; within functions which use verilog-completions
7305 (set-buffer verilog-buffer-to-use)
7307 (let ((verilog-str verilog-str))
7308 ;; Build regular expression for functions
7309 (if (string= verilog-str "")
7310 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7311 (setq verilog-str (verilog-build-defun-re verilog-str)))
7312 (goto-char (point-min))
7314 ;; Build a list of all possible completions
7315 (while (verilog-re-search-forward verilog-str nil t)
7316 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7317 (if (or (null verilog-pred)
7318 (funcall verilog-pred match))
7319 (setq verilog-all (cons match verilog-all)))))
7321 ;; Now we have built a list of all matches. Give response to caller
7322 (verilog-completion-response))))
7324 (defun verilog-goto-defun ()
7325 "Move to specified Verilog module/interface/task/function.
7326 The default is a name found in the buffer around point.
7327 If search fails, other files are checked based on
7328 `verilog-library-flags'."
7330 (let* ((default (verilog-get-default-symbol))
7331 ;; The following variable is used in verilog-comp-function
7332 (verilog-buffer-to-use (current-buffer))
7333 (label (if (not (string= default ""))
7334 ;; Do completion with default
7335 (completing-read (concat "Goto-Label: (default "
7337 'verilog-comp-defun nil nil "")
7338 ;; There is no default value. Complete without it
7339 (completing-read "Goto-Label: "
7340 'verilog-comp-defun nil nil "")))
7342 ;; Make sure library paths are correct, in case need to resolve module
7343 (verilog-auto-reeval-locals)
7344 (verilog-getopt-flags)
7345 ;; If there was no response on prompt, use default value
7346 (if (string= label "")
7347 (setq label default))
7348 ;; Goto right place in buffer if label is not an empty string
7349 (or (string= label "")
7352 (goto-char (point-min))
7354 (re-search-forward (verilog-build-defun-re label t) nil t)))
7357 (beginning-of-line))
7359 (verilog-goto-defun-file label))))
7361 ;; Eliminate compile warning
7362 (defvar occur-pos-list)
7364 (defun verilog-showscopes ()
7365 "List all scopes in this module."
7367 (let ((buffer (current-buffer))
7371 (prevpos (point-min))
7372 (final-context-start (make-marker))
7373 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7374 (with-output-to-temp-buffer "*Occur*"
7376 (message (format "Searching for %s ..." regexp))
7377 ;; Find next match, but give up if prev match was at end of buffer.
7378 (while (and (not (= prevpos (point-max)))
7379 (verilog-re-search-forward regexp nil t))
7380 (goto-char (match-beginning 0))
7383 (setq linenum (+ linenum (count-lines prevpos (point)))))
7384 (setq prevpos (point))
7385 (goto-char (match-end 0))
7386 (let* ((start (save-excursion
7387 (goto-char (match-beginning 0))
7388 (forward-line (if (< nlines 0) nlines (- nlines)))
7390 (end (save-excursion
7391 (goto-char (match-end 0))
7393 (forward-line (1+ nlines))
7396 (tag (format "%3d" linenum))
7397 (empty (make-string (length tag) ?\ ))
7400 (setq tem (make-marker))
7401 (set-marker tem (point))
7402 (set-buffer standard-output)
7403 (setq occur-pos-list (cons tem occur-pos-list))
7404 (or first (zerop nlines)
7405 (insert "--------\n"))
7407 (insert-buffer-substring buffer start end)
7408 (backward-char (- end start))
7409 (setq tem (if (< nlines 0) (- nlines) nlines))
7413 (setq tem (1- tem)))
7414 (let ((this-linenum linenum))
7415 (set-marker final-context-start
7416 (+ (point) (- (match-end 0) (match-beginning 0))))
7417 (while (< (point) final-context-start)
7419 (setq tag (format "%3d" this-linenum)))
7420 (insert tag ?:)))))))
7421 (set-buffer-modified-p nil))))
7424 ;; Highlight helper functions
7425 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7426 (defun verilog-within-translate-off ()
7427 "Return point if within translate-off region, else nil."
7428 (and (save-excursion
7430 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7432 (equal "off" (match-string 2))
7435 (defun verilog-start-translate-off (limit)
7436 "Return point before translate-off directive if before LIMIT, else nil."
7437 (when (re-search-forward
7438 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7440 (match-beginning 0)))
7442 (defun verilog-back-to-start-translate-off (limit)
7443 "Return point before translate-off directive if before LIMIT, else nil."
7444 (when (re-search-backward
7445 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7447 (match-beginning 0)))
7449 (defun verilog-end-translate-off (limit)
7450 "Return point after translate-on directive if before LIMIT, else nil."
7452 (re-search-forward (concat
7453 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7455 (defun verilog-match-translate-off (limit)
7456 "Match a translate-off block, setting `match-data' and returning t, else nil.
7457 Bound search by LIMIT."
7458 (when (< (point) limit)
7459 (let ((start (or (verilog-within-translate-off)
7460 (verilog-start-translate-off limit)))
7461 (case-fold-search t))
7463 (let ((end (or (verilog-end-translate-off limit) limit)))
7464 (set-match-data (list start end))
7465 (goto-char end))))))
7467 (defun verilog-font-lock-match-item (limit)
7468 "Match, and move over, any declaration item after point.
7469 Bound search by LIMIT. Adapted from
7470 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7473 (narrow-to-region (point-min) limit)
7475 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7477 (goto-char (match-end 1))
7478 ;; move to next item
7479 (if (looking-at "\\(\\s-*,\\)")
7480 (goto-char (match-end 1))
7485 ;; Added by Subbu Meiyappan for Header
7487 (defun verilog-header ()
7488 "Insert a standard Verilog file header.
7489 See also `verilog-sk-header' for an alternative format."
7491 (let ((start (point)))
7493 //-----------------------------------------------------------------------------
7495 // Project : <project>
7496 //-----------------------------------------------------------------------------
7497 // File : <filename>
7498 // Author : <author>
7499 // Created : <credate>
7500 // Last modified : <moddate>
7501 //-----------------------------------------------------------------------------
7504 //-----------------------------------------------------------------------------
7505 // Copyright (c) <copydate> by <company> This model is the confidential and
7506 // proprietary property of <company> and the possession or use of this
7507 // file requires a written license from <company>.
7508 //------------------------------------------------------------------------------
7509 // Modification history :
7511 //-----------------------------------------------------------------------------
7515 (search-forward "<filename>")
7516 (replace-match (buffer-name) t t)
7517 (search-forward "<author>") (replace-match "" t t)
7518 (insert (user-full-name))
7519 (insert " <" (user-login-name) "@" (system-name) ">")
7520 (search-forward "<credate>") (replace-match "" t t)
7521 (verilog-insert-date)
7522 (search-forward "<moddate>") (replace-match "" t t)
7523 (verilog-insert-date)
7524 (search-forward "<copydate>") (replace-match "" t t)
7525 (verilog-insert-year)
7526 (search-forward "<modhist>") (replace-match "" t t)
7527 (verilog-insert-date)
7528 (insert " : created")
7531 (setq string (read-string "title: "))
7532 (search-forward "<title>")
7533 (replace-match string t t)
7534 (setq string (read-string "project: " verilog-project))
7535 (setq verilog-project string)
7536 (search-forward "<project>")
7537 (replace-match string t t)
7538 (setq string (read-string "Company: " verilog-company))
7539 (setq verilog-company string)
7540 (search-forward "<company>")
7541 (replace-match string t t)
7542 (search-forward "<company>")
7543 (replace-match string t t)
7544 (search-forward "<company>")
7545 (replace-match string t t)
7546 (search-backward "<description>")
7547 (replace-match "" t t))))
7549 ;; verilog-header Uses the verilog-insert-date function
7551 (defun verilog-insert-date ()
7552 "Insert date from the system."
7554 (if verilog-date-scientific-format
7555 (insert (format-time-string "%Y/%m/%d"))
7556 (insert (format-time-string "%d.%m.%Y"))))
7558 (defun verilog-insert-year ()
7559 "Insert year from the system."
7561 (insert (format-time-string "%Y")))
7565 ;; Signal list parsing
7568 ;; Elements of a signal list
7569 ;; Unfortunately we use 'assoc' on this, so can't be a vector
7570 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7571 (list name bits comment mem enum signed type multidim modport))
7572 (defsubst verilog-sig-name (sig)
7574 (defsubst verilog-sig-bits (sig) ;; First element of packed array (pre signal-name)
7576 (defsubst verilog-sig-comment (sig)
7578 (defsubst verilog-sig-memory (sig) ;; Unpacked array (post signal-name)
7580 (defsubst verilog-sig-enum (sig)
7582 (defsubst verilog-sig-signed (sig)
7584 (defsubst verilog-sig-type (sig)
7586 (defsubst verilog-sig-type-set (sig type)
7587 (setcar (nthcdr 6 sig) type))
7588 (defsubst verilog-sig-multidim (sig) ;; Second and additional elements of packed array
7590 (defsubst verilog-sig-multidim-string (sig)
7591 (if (verilog-sig-multidim sig)
7592 (let ((str "") (args (verilog-sig-multidim sig)))
7594 (setq str (concat str (car args)))
7595 (setq args (cdr args)))
7597 (defsubst verilog-sig-modport (sig)
7599 (defsubst verilog-sig-width (sig)
7600 (verilog-make-width-expression (verilog-sig-bits sig)))
7602 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7603 (vector outputs-del outputs-imm temps inputs))
7604 (defsubst verilog-alw-get-outputs-delayed (sigs)
7606 (defsubst verilog-alw-get-outputs-immediate (sigs)
7608 (defsubst verilog-alw-get-temps (sigs)
7610 (defsubst verilog-alw-get-inputs (sigs)
7612 (defsubst verilog-alw-get-uses-delayed (sigs)
7615 (defsubst verilog-modport-new (name clockings decls)
7616 (list name clockings decls))
7617 (defsubst verilog-modport-name (sig)
7619 (defsubst verilog-modport-clockings (sig)
7620 (nth 1 sig)) ;; Returns list of names
7621 (defsubst verilog-modport-clockings-add (sig val)
7622 (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
7623 (defsubst verilog-modport-decls (sig)
7624 (nth 2 sig)) ;; Returns verilog-decls-* structure
7625 (defsubst verilog-modport-decls-set (sig val)
7626 (setcar (nthcdr 2 sig) val))
7628 (defsubst verilog-modi-new (name fob pt type)
7629 (vector name fob pt type))
7630 (defsubst verilog-modi-name (modi)
7632 (defsubst verilog-modi-file-or-buffer (modi)
7634 (defsubst verilog-modi-get-point (modi)
7636 (defsubst verilog-modi-get-type (modi) ;; "module" or "interface"
7638 (defsubst verilog-modi-get-decls (modi)
7639 (verilog-modi-cache-results modi 'verilog-read-decls))
7640 (defsubst verilog-modi-get-sub-decls (modi)
7641 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7643 ;; Signal reading for given module
7644 ;; Note these all take modi's - as returned from verilog-modi-current
7645 (defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
7646 (vector out inout in vars modports assigns consts gparams interfaces))
7647 (defsubst verilog-decls-append (a b)
7648 (cond ((not a) b) ((not b) a)
7649 (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
7650 (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
7651 (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
7652 (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
7653 (append (aref a 8) (aref b 8))))))
7654 (defsubst verilog-decls-get-outputs (decls)
7656 (defsubst verilog-decls-get-inouts (decls)
7658 (defsubst verilog-decls-get-inputs (decls)
7660 (defsubst verilog-decls-get-vars (decls)
7662 (defsubst verilog-decls-get-modports (decls) ;; Also for clocking blocks; contains another verilog-decls struct
7663 (aref decls 4)) ;; Returns verilog-modport* structure
7664 (defsubst verilog-decls-get-assigns (decls)
7666 (defsubst verilog-decls-get-consts (decls)
7668 (defsubst verilog-decls-get-gparams (decls)
7670 (defsubst verilog-decls-get-interfaces (decls)
7674 (defsubst verilog-subdecls-new (out inout in intf intfd)
7675 (vector out inout in intf intfd))
7676 (defsubst verilog-subdecls-get-outputs (subdecls)
7678 (defsubst verilog-subdecls-get-inouts (subdecls)
7680 (defsubst verilog-subdecls-get-inputs (subdecls)
7682 (defsubst verilog-subdecls-get-interfaces (subdecls)
7684 (defsubst verilog-subdecls-get-interfaced (subdecls)
7687 (defun verilog-signals-from-signame (signame-list)
7688 "Return signals in standard form from SIGNAME-LIST, a simple list of names."
7689 (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
7692 (defun verilog-signals-in (in-list not-list)
7693 "Return list of signals in IN-LIST that are also in NOT-LIST.
7694 Also remove any duplicates in IN-LIST.
7695 Signals must be in standard (base vector) form."
7696 ;; This function is hot, so implemented as O(1)
7697 (cond ((eval-when-compile (fboundp 'make-hash-table))
7698 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7699 (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
7702 (puthash (car (car not-list)) t ht-not)
7703 (setq not-list (cdr not-list)))
7705 (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
7706 (not (gethash (verilog-sig-name (car in-list)) ht)))
7707 (setq out-list (cons (car in-list) out-list))
7708 (puthash (verilog-sig-name (car in-list)) t ht))
7709 (setq in-list (cdr in-list)))
7710 (nreverse out-list)))
7711 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7715 (if (and (assoc (verilog-sig-name (car in-list)) not-list)
7716 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7717 (setq out-list (cons (car in-list) out-list)))
7718 (setq in-list (cdr in-list)))
7719 (nreverse out-list)))))
7720 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
7722 (defun verilog-signals-not-in (in-list not-list)
7723 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7724 Also remove any duplicates in IN-LIST.
7725 Signals must be in standard (base vector) form."
7726 ;; This function is hot, so implemented as O(1)
7727 (cond ((eval-when-compile (fboundp 'make-hash-table))
7728 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7731 (puthash (car (car not-list)) t ht)
7732 (setq not-list (cdr not-list)))
7734 (when (not (gethash (verilog-sig-name (car in-list)) ht))
7735 (setq out-list (cons (car in-list) out-list))
7736 (puthash (verilog-sig-name (car in-list)) t ht))
7737 (setq in-list (cdr in-list)))
7738 (nreverse out-list)))
7739 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7743 (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
7744 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7745 (setq out-list (cons (car in-list) out-list)))
7746 (setq in-list (cdr in-list)))
7747 (nreverse out-list)))))
7748 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7750 (defun verilog-signals-memory (in-list)
7751 "Return list of signals in IN-LIST that are memorized (multidimensional)."
7754 (if (nth 3 (car in-list))
7755 (setq out-list (cons (car in-list) out-list)))
7756 (setq in-list (cdr in-list)))
7758 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7760 (defun verilog-signals-sort-compare (a b)
7761 "Compare signal A and B for sorting."
7762 (string< (verilog-sig-name a) (verilog-sig-name b)))
7764 (defun verilog-signals-not-params (in-list)
7765 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
7768 ;; Namespace intentionally short for AUTOs and compatibility
7769 (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
7770 (setq out-list (cons (car in-list) out-list)))
7771 (setq in-list (cdr in-list)))
7772 (nreverse out-list)))
7774 (defun verilog-signals-with (func in-list)
7775 "Return list of signals where FUNC is true executed on each signal in IN-LIST."
7778 (when (funcall func (car in-list))
7779 (setq out-list (cons (car in-list) out-list)))
7780 (setq in-list (cdr in-list)))
7781 (nreverse out-list)))
7783 (defun verilog-signals-combine-bus (in-list)
7784 "Return a list of signals in IN-LIST, with buses combined.
7785 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
7788 sig highbit lowbit ; Temp information about current signal
7789 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
7790 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
7793 ;; Shove signals so duplicated signals will be adjacent
7794 (setq in-list (sort in-list `verilog-signals-sort-compare))
7796 (setq sig (car in-list))
7797 ;; No current signal; form from existing details
7799 (setq sv-name (verilog-sig-name sig)
7802 sv-comment (verilog-sig-comment sig)
7803 sv-memory (verilog-sig-memory sig)
7804 sv-enum (verilog-sig-enum sig)
7805 sv-signed (verilog-sig-signed sig)
7806 sv-type (verilog-sig-type sig)
7807 sv-multidim (verilog-sig-multidim sig)
7808 sv-modport (verilog-sig-modport sig)
7811 ;; Extract bus details
7812 (setq bus (verilog-sig-bits sig))
7813 (setq bus (and bus (verilog-simplify-range-expression bus)))
7815 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
7816 (setq highbit (string-to-number (match-string 1 bus))
7817 lowbit (string-to-number
7818 (match-string 2 bus))))
7819 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
7820 (setq highbit (string-to-number (match-string 1 bus))
7822 ;; Combine bits in bus
7824 (setq sv-highbit (max highbit sv-highbit)
7825 sv-lowbit (min lowbit sv-lowbit))
7826 (setq sv-highbit highbit
7829 ;; String, probably something like `preproc:0
7830 (setq sv-busstring bus)))
7831 ;; Peek ahead to next signal
7832 (setq in-list (cdr in-list))
7833 (setq sig (car in-list))
7834 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
7835 ;; Combine with this signal
7836 (when (and sv-busstring
7837 (not (equal sv-busstring (verilog-sig-bits sig))))
7838 (when nil ;; Debugging
7839 (message (concat "Warning, can't merge into single bus "
7841 ", the AUTOs may be wrong")))
7842 (setq buswarn ", Couldn't Merge"))
7843 (if (verilog-sig-comment sig) (setq combo ", ..."))
7844 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
7845 sv-enum (or sv-enum (verilog-sig-enum sig))
7846 sv-signed (or sv-signed (verilog-sig-signed sig))
7847 sv-type (or sv-type (verilog-sig-type sig))
7848 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
7849 sv-modport (or sv-modport (verilog-sig-modport sig))))
7850 ;; Doesn't match next signal, add to queue, zero in prep for next
7851 ;; Note sig may also be nil for the last signal in the list
7854 (cons (verilog-sig-new
7858 (concat "[" (int-to-string sv-highbit) ":"
7859 (int-to-string sv-lowbit) "]")))
7860 (concat sv-comment combo buswarn)
7861 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
7867 (defun verilog-sig-tieoff (sig)
7868 "Return tieoff expression for given SIG, with appropriate width.
7869 Tieoff value uses `verilog-active-low-regexp' and
7870 `verilog-auto-reset-widths'."
7872 (if (and verilog-active-low-regexp
7873 (verilog-string-match-fold verilog-active-low-regexp (verilog-sig-name sig)))
7875 (cond ((not verilog-auto-reset-widths)
7877 ((equal verilog-auto-reset-widths 'unbased)
7879 ;; Else presume verilog-auto-reset-widths is true
7881 (let* ((width (verilog-sig-width sig)))
7884 ((string-match "^[0-9]+$" width)
7885 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
7887 (concat "{" width "{1'b0}}"))))))))
7893 (defun verilog-decls-princ (decls &optional header prefix)
7894 "For debug, dump the `verilog-read-decls' structure DECLS."
7896 (if header (princ header))
7897 (setq prefix (or prefix ""))
7898 (verilog-signals-princ (verilog-decls-get-outputs decls)
7899 (concat prefix "Outputs:\n") (concat prefix " "))
7900 (verilog-signals-princ (verilog-decls-get-inouts decls)
7901 (concat prefix "Inout:\n") (concat prefix " "))
7902 (verilog-signals-princ (verilog-decls-get-inputs decls)
7903 (concat prefix "Inputs:\n") (concat prefix " "))
7904 (verilog-signals-princ (verilog-decls-get-vars decls)
7905 (concat prefix "Vars:\n") (concat prefix " "))
7906 (verilog-signals-princ (verilog-decls-get-assigns decls)
7907 (concat prefix "Assigns:\n") (concat prefix " "))
7908 (verilog-signals-princ (verilog-decls-get-consts decls)
7909 (concat prefix "Consts:\n") (concat prefix " "))
7910 (verilog-signals-princ (verilog-decls-get-gparams decls)
7911 (concat prefix "Gparams:\n") (concat prefix " "))
7912 (verilog-signals-princ (verilog-decls-get-interfaces decls)
7913 (concat prefix "Interfaces:\n") (concat prefix " "))
7914 (verilog-modport-princ (verilog-decls-get-modports decls)
7915 (concat prefix "Modports:\n") (concat prefix " "))
7918 (defun verilog-signals-princ (signals &optional header prefix)
7919 "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
7921 (if header (princ header))
7923 (let ((sig (car signals)))
7924 (setq signals (cdr signals))
7926 (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
7927 (princ " bits=") (princ (verilog-sig-bits sig))
7928 (princ " cmt=") (princ (verilog-sig-comment sig))
7929 (princ " mem=") (princ (verilog-sig-memory sig))
7930 (princ " enum=") (princ (verilog-sig-enum sig))
7931 (princ " sign=") (princ (verilog-sig-signed sig))
7932 (princ " type=") (princ (verilog-sig-type sig))
7933 (princ " dim=") (princ (verilog-sig-multidim sig))
7934 (princ " modp=") (princ (verilog-sig-modport sig))
7937 (defun verilog-modport-princ (modports &optional header prefix)
7938 "For debug, dump internal MODPORT structures, with HEADER and PREFIX."
7940 (if header (princ header))
7942 (let ((sig (car modports)))
7943 (setq modports (cdr modports))
7945 (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
7946 (princ " clockings=") (princ (verilog-modport-clockings sig))
7948 (verilog-decls-princ (verilog-modport-decls sig)
7949 (concat prefix " syms:\n")
7950 (concat prefix " "))))))
7953 ;; Port/Wire/Etc Reading
7956 (defun verilog-read-inst-backward-name ()
7957 "Internal. Move point back to beginning of inst-name."
7958 (verilog-backward-open-paren)
7961 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
7962 (cond ((looking-at ")")
7963 (verilog-backward-open-paren))
7964 (t (setq done t)))))
7965 (while (looking-at "\\]")
7966 (verilog-backward-open-bracket)
7967 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
7968 (skip-chars-backward "a-zA-Z0-9`_$"))
7970 (defun verilog-read-inst-module-matcher ()
7971 "Set match data 0 with module_name when point is inside instantiation."
7972 (verilog-read-inst-backward-name)
7973 ;; Skip over instantiation name
7974 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7975 ;; Check for parameterized instantiations
7976 (when (looking-at ")")
7977 (verilog-backward-open-paren)
7978 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
7979 (skip-chars-backward "a-zA-Z0-9'_$")
7980 ;; #1 is legal syntax for gate primitives
7981 (when (save-excursion
7982 (verilog-backward-syntactic-ws-quick)
7983 (eq ?# (char-before)))
7984 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
7985 (skip-chars-backward "a-zA-Z0-9'_$"))
7986 (looking-at "[a-zA-Z0-9`_\$]+")
7987 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7988 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
7989 ;; Caller assumes match-beginning/match-end is still set
7992 (defun verilog-read-inst-module ()
7993 "Return module_name when point is inside instantiation."
7995 (verilog-read-inst-module-matcher)))
7997 (defun verilog-read-inst-name ()
7998 "Return instance_name when point is inside instantiation."
8000 (verilog-read-inst-backward-name)
8001 (looking-at "[a-zA-Z0-9`_\$]+")
8002 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8003 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
8005 (defun verilog-read-module-name ()
8006 "Return module name when after its ( or ;."
8008 (re-search-backward "[(;]")
8009 ;; Due to "module x import y (" we must search for declaration begin
8010 (verilog-re-search-backward-quick verilog-defun-re nil nil)
8011 (goto-char (match-end 0))
8012 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_\$]+" nil nil)
8013 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8014 (verilog-symbol-detick
8015 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
8017 (defun verilog-read-inst-param-value ()
8018 "Return list of parameters and values when point is inside instantiation."
8020 (verilog-read-inst-backward-name)
8021 ;; Skip over instantiation name
8022 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
8023 ;; If there are parameterized instantiations
8024 (when (looking-at ")")
8025 (let ((end-pt (point))
8027 param-name paren-beg-pt param-value)
8028 (verilog-backward-open-paren)
8029 (while (verilog-re-search-forward-quick "\\." end-pt t)
8030 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
8031 (skip-chars-backward "a-zA-Z0-9'_$")
8032 (looking-at "[a-zA-Z0-9`_\$]+")
8033 (setq param-name (buffer-substring-no-properties
8034 (match-beginning 0) (match-end 0)))
8035 (verilog-re-search-forward-quick "(" nil nil)
8036 (setq paren-beg-pt (point))
8037 (verilog-forward-close-paren)
8038 (setq param-value (verilog-string-remove-spaces
8039 (buffer-substring-no-properties
8040 paren-beg-pt (1- (point)))))
8041 (setq params (cons (list param-name param-value) params)))
8044 (defun verilog-read-auto-params (num-param &optional max-param)
8045 "Return parameter list inside auto.
8046 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
8049 ;; /*AUTOPUNT("parameter", "parameter")*/
8051 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
8052 (setq olist (cons (match-string 1) olist))
8053 (goto-char (match-end 0))))
8054 (or (eq nil num-param)
8055 (<= num-param (length olist))
8056 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
8057 (if (eq max-param nil) (setq max-param num-param))
8058 (or (eq nil max-param)
8059 (>= max-param (length olist))
8060 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
8063 (defun verilog-read-decls ()
8064 "Compute signal declaration information for the current module at point.
8065 Return an array of [outputs inouts inputs wire reg assign const]."
8066 (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
8067 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
8068 in-modport in-clocking ptype ign-prop
8069 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
8070 sigs-gparam sigs-intf sigs-modports
8071 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
8074 ;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
8076 (verilog-beg-of-defun-quick)
8077 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
8078 (while (< (point) end-mod-point)
8079 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
8082 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8083 (setq enum (match-string 2)))
8084 (search-forward "\n"))
8085 ((looking-at "/\\*")
8087 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8088 (setq enum (match-string 2)))
8089 (or (search-forward "*/")
8090 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8091 ((looking-at "(\\*")
8092 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8094 (or (search-forward "*)")
8095 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8096 ((eq ?\" (following-char))
8097 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
8098 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8099 ((eq ?\; (following-char))
8100 (when (and in-modport (not (eq in-modport t))) ;; end of a modport declaration
8101 (verilog-modport-decls-set
8103 (verilog-decls-new sigs-out sigs-inout sigs-in
8104 nil nil nil nil nil nil))
8105 ;; Pop from varstack to restore state to pre-clocking
8106 (setq tmp (car varstack)
8107 varstack (cdr varstack)
8108 sigs-out (aref tmp 0)
8109 sigs-inout (aref tmp 1)
8110 sigs-in (aref tmp 2)))
8111 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8112 v2kargs-ok nil in-modport nil ign-prop nil)
8114 ((eq ?= (following-char))
8115 (setq rvalue t newsig nil)
8117 ((and (eq ?, (following-char))
8118 (eq paren sig-paren))
8121 ;; ,'s can occur inside {} & funcs
8122 ((looking-at "[{(]")
8123 (setq paren (1+ paren))
8125 ((looking-at "[})]")
8126 (setq paren (1- paren))
8128 (when (< paren sig-paren)
8129 (setq expect-signal nil rvalue nil))) ; ) that ends variables inside v2k arg list
8130 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
8131 (goto-char (match-end 0))
8132 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
8133 (setcar (cdr (cdr (cdr newsig)))
8134 (if (verilog-sig-memory newsig)
8135 (concat (verilog-sig-memory newsig) (match-string 1))
8137 (vec ;; Multidimensional
8138 (setq multidim (cons vec multidim))
8139 (setq vec (verilog-string-replace-matches
8140 "\\s-+" "" nil nil (match-string 1))))
8142 (setq vec (verilog-string-replace-matches
8143 "\\s-+" "" nil nil (match-string 1))))))
8144 ;; Normal or escaped identifier -- note we remember the \ if escaped
8145 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8146 (goto-char (match-end 0))
8147 (setq keywd (match-string 1))
8148 (when (string-match "^\\\\" (match-string 1))
8149 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
8150 ;; Add any :: package names to same identifier
8151 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8152 (goto-char (match-end 0))
8153 (setq keywd (concat keywd "::" (match-string 1)))
8154 (when (string-match "^\\\\" (match-string 1))
8155 (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
8156 (cond ((equal keywd "input")
8157 (setq vec nil enum nil rvalue nil newsig nil signed nil
8158 typedefed nil multidim nil ptype nil modport nil
8159 expect-signal 'sigs-in io t sig-paren paren))
8160 ((equal keywd "output")
8161 (setq vec nil enum nil rvalue nil newsig nil signed nil
8162 typedefed nil multidim nil ptype nil modport nil
8163 expect-signal 'sigs-out io t sig-paren paren))
8164 ((equal keywd "inout")
8165 (setq vec nil enum nil rvalue nil newsig nil signed nil
8166 typedefed nil multidim nil ptype nil modport nil
8167 expect-signal 'sigs-inout io t sig-paren paren))
8168 ((equal keywd "parameter")
8169 (setq vec nil enum nil rvalue nil signed nil
8170 typedefed nil multidim nil ptype nil modport nil
8171 expect-signal 'sigs-gparam io t sig-paren paren))
8172 ((member keywd '("wire" "reg" ; Fast
8174 "tri" "tri0" "tri1" "triand" "trior" "trireg"
8175 "uwire" "wand" "wor"
8176 ;; integer_atom_type
8177 "byte" "shortint" "int" "longint" "integer" "time"
8179 ;; integer_vector_type - "reg" above
8182 "shortreal" "real" "realtime"
8184 "string" "event" "chandle"))
8187 (if typedefed (concat typedefed " " keywd) keywd)))
8188 (t (setq vec nil enum nil rvalue nil signed nil
8189 typedefed nil multidim nil sig-paren paren
8190 expect-signal 'sigs-var modport nil))))
8191 ((equal keywd "assign")
8192 (setq vec nil enum nil rvalue nil signed nil
8193 typedefed nil multidim nil ptype nil modport nil
8194 expect-signal 'sigs-assign sig-paren paren))
8195 ((member keywd '("localparam" "genvar"))
8197 (setq vec nil enum nil rvalue nil signed nil
8198 typedefed nil multidim nil ptype nil modport nil
8199 expect-signal 'sigs-const sig-paren paren)))
8200 ((member keywd '("signed" "unsigned"))
8201 (setq signed keywd))
8202 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
8204 ((member keywd '("class" "covergroup" "function"
8205 "property" "randsequence" "sequence" "task"))
8207 (setq functask (1+ functask))))
8208 ((member keywd '("endclass" "endgroup" "endfunction"
8209 "endproperty" "endsequence" "endtask"))
8210 (setq functask (1- functask)))
8211 ((equal keywd "modport")
8212 (setq in-modport t))
8213 ((equal keywd "clocking")
8214 (setq in-clocking t))
8215 ((equal keywd "type")
8217 ;; Ifdef? Ignore name of define
8218 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8222 (verilog-typedef-name-p keywd))
8225 (if typedefed (concat typedefed " " keywd) keywd)))
8226 (t (setq vec nil enum nil rvalue nil signed nil
8227 typedefed nil multidim nil sig-paren paren
8228 expect-signal 'sigs-var modport nil))))
8229 ;; Interface with optional modport in v2k arglist?
8230 ;; Skip over parsing modport, and take the interface name as the type
8234 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
8235 (when (match-end 2) (goto-char (match-end 2)))
8236 (setq vec nil enum nil rvalue nil signed nil
8237 typedefed keywd multidim nil ptype nil modport (match-string 2)
8238 newsig nil sig-paren paren
8239 expect-signal 'sigs-intf io t ))
8240 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
8241 ((looking-at "\\s-*\\.")
8242 (goto-char (match-end 0))
8244 (setq expect-signal nil)))
8245 ;; "modport <keywd>"
8246 ((and (eq in-modport t)
8247 (not (member keywd verilog-keywords)))
8248 (setq in-modport (verilog-modport-new keywd nil nil))
8249 (setq sigs-modports (cons in-modport sigs-modports))
8250 ;; Push old sig values to stack and point to new signal list
8251 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8253 (setq sigs-in nil sigs-inout nil sigs-out nil))
8254 ;; "modport x (clocking <keywd>)"
8255 ((and in-modport in-clocking)
8256 (verilog-modport-clockings-add in-modport keywd)
8257 (setq in-clocking nil))
8260 (equal keywd "endclocking"))
8261 (unless (eq in-clocking t)
8262 (verilog-modport-decls-set
8264 (verilog-decls-new sigs-out sigs-inout sigs-in
8265 nil nil nil nil nil nil))
8266 ;; Pop from varstack to restore state to pre-clocking
8267 (setq tmp (car varstack)
8268 varstack (cdr varstack)
8269 sigs-out (aref tmp 0)
8270 sigs-inout (aref tmp 1)
8271 sigs-in (aref tmp 2)))
8272 (setq in-clocking nil))
8273 ;; "clocking <keywd>"
8274 ((and (eq in-clocking t)
8275 (not (member keywd verilog-keywords)))
8276 (setq in-clocking (verilog-modport-new keywd nil nil))
8277 (setq sigs-modports (cons in-clocking sigs-modports))
8278 ;; Push old sig values to stack and point to new signal list
8279 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8281 (setq sigs-in nil sigs-inout nil sigs-out nil))
8282 ;; New signal, maybe?
8286 (not (member keywd verilog-keywords)))
8287 ;; Add new signal to expect-signal's variable
8288 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
8289 (set expect-signal (cons newsig
8290 (symbol-value expect-signal))))))
8293 (skip-syntax-forward " "))
8295 (setq tmp (verilog-decls-new (nreverse sigs-out)
8296 (nreverse sigs-inout)
8299 (nreverse sigs-modports)
8300 (nreverse sigs-assign)
8301 (nreverse sigs-const)
8302 (nreverse sigs-gparam)
8303 (nreverse sigs-intf)))
8304 ;;(if dbg (verilog-decls-princ tmp))
8307 (defvar verilog-read-sub-decls-in-interfaced nil
8308 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
8310 (defvar verilog-read-sub-decls-gate-ios nil
8311 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
8314 ;; Prevent compile warnings; these are let's, not globals
8315 ;; Do not remove the eval-when-compile
8316 ;; - we want an error when we are debugging this code if they are refed.
8324 (defvar sigs-out-unk)
8326 ;; These are known to be from other packages and may not be defined
8327 (defvar diff-command nil)
8328 (defvar vector-skip-list)
8329 ;; There are known to be from newer versions of Emacs
8330 (defvar create-lockfiles))
8332 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
8333 "For `verilog-read-sub-decls-line', add a signal."
8334 ;; sig eq t to indicate .name syntax
8335 ;;(message "vrsds: %s(%S)" port sig)
8336 (let ((dotname (eq sig t))
8339 (setq port (verilog-symbol-detick-denumber port))
8340 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
8341 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
8342 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
8343 (unless (or (not sig)
8344 (equal sig "")) ;; Ignore .foo(1'b1) assignments
8345 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
8346 (equal "inout" verilog-read-sub-decls-gate-ios))
8348 (cons (verilog-sig-new
8350 (if dotname (verilog-sig-bits portdata) vec)
8351 (concat "To/From " comment)
8352 (verilog-sig-memory portdata)
8354 (verilog-sig-signed portdata)
8355 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8356 (verilog-sig-type portdata))
8359 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
8360 (equal "output" verilog-read-sub-decls-gate-ios))
8362 (cons (verilog-sig-new
8364 (if dotname (verilog-sig-bits portdata) vec)
8365 (concat "From " comment)
8366 (verilog-sig-memory portdata)
8368 (verilog-sig-signed portdata)
8369 ;; Though ok in SV, in V2K code, propagating the
8370 ;; "reg" in "output reg" upwards isn't legal.
8371 ;; Also for backwards compatibility we don't propagate
8372 ;; "input wire" upwards.
8373 ;; See also `verilog-signals-edit-wire-reg'.
8374 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8375 (verilog-sig-type portdata))
8378 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
8379 (equal "input" verilog-read-sub-decls-gate-ios))
8381 (cons (verilog-sig-new
8383 (if dotname (verilog-sig-bits portdata) vec)
8384 (concat "To " comment)
8385 (verilog-sig-memory portdata)
8387 (verilog-sig-signed portdata)
8388 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8389 (verilog-sig-type portdata))
8392 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
8394 (cons (verilog-sig-new
8396 (if dotname (verilog-sig-bits portdata) vec)
8397 (concat "To/From " comment)
8398 (verilog-sig-memory portdata)
8400 (verilog-sig-signed portdata)
8401 (verilog-sig-type portdata)
8404 ((setq portdata (and verilog-read-sub-decls-in-interfaced
8405 (assoc port (verilog-decls-get-vars submoddecls))))
8407 (cons (verilog-sig-new
8409 (if dotname (verilog-sig-bits portdata) vec)
8410 (concat "To/From " comment)
8411 (verilog-sig-memory portdata)
8413 (verilog-sig-signed portdata)
8414 (verilog-sig-type portdata)
8417 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
8420 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
8421 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
8422 ;;(message "vrsde: '%s'" expr)
8423 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
8424 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
8425 ;; Remove front operators
8426 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8429 ;; {..., a, b} requires us to recurse on a,b
8430 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
8431 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
8432 (unless verilog-auto-ignore-concat
8433 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
8435 (while (setq mstr (pop mlst))
8436 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
8438 (let (sig vec multidim)
8439 ;; Remove leading reduction operators, etc
8440 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8441 ;;(message "vrsde-ptop: '%s'" expr)
8442 (cond ;; Find \signal. Final space is part of escaped signal name
8443 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8444 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8445 (setq sig (match-string 1 expr)
8446 expr (substring expr (match-end 0))))
8448 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8449 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8450 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8451 expr (substring expr (match-end 0)))))
8452 ;; Find [vector] or [multi][multi][multi][vector]
8453 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8454 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
8455 (when vec (setq multidim (cons vec multidim)))
8456 (setq vec (match-string 1 expr)
8457 expr (substring expr (match-end 0))))
8458 ;; If found signal, and nothing unrecognized, add the signal
8459 ;;(message "vrsde-rem: '%s'" expr)
8460 (when (and sig (string-match "^\\s-*$" expr))
8461 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
8463 (defun verilog-read-sub-decls-line (submoddecls comment)
8464 "For `verilog-read-sub-decls', read lines of port defs until none match.
8465 Inserts the list of signals found, using submodi to look up each port."
8471 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8472 (setq port (match-string 1))
8473 (goto-char (match-end 0)))
8475 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8476 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
8477 (goto-char (match-end 0)))
8479 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8480 (verilog-read-sub-decls-sig
8481 submoddecls comment (match-string 1) t ; sig==t for .name
8482 nil nil) ; vec multidim
8485 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8486 (verilog-read-sub-decls-sig
8487 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
8488 nil nil) ; vec multidim
8491 ((looking-at "\\s-*\\.[^(]*(")
8492 (setq port nil) ;; skip this line
8493 (goto-char (match-end 0)))
8495 (setq port nil done t))) ;; Unknown, ignore rest of line
8496 ;; Get signal name. Point is at the first-non-space after (
8497 ;; We intentionally ignore (non-escaped) signals with .s in them
8498 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8500 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8501 (verilog-read-sub-decls-sig
8502 submoddecls comment port
8503 (verilog-string-remove-spaces (match-string 1)) ; sig
8504 nil nil)) ; vec multidim
8506 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8507 (verilog-read-sub-decls-sig
8508 submoddecls comment port
8509 (verilog-string-remove-spaces (match-string 1)) ; sig
8510 (match-string 2) nil)) ; vec multidim
8511 ;; Fastpath was above looking-at's.
8512 ;; For something more complicated invoke a parser
8513 ((looking-at "[^)]+")
8514 (verilog-read-sub-decls-expr
8515 submoddecls comment port
8517 (point) (1- (progn (search-backward "(") ; start at (
8518 (verilog-forward-sexp-ign-cmt 1)
8519 (point)))))))) ; expr
8521 (forward-line 1)))))
8523 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8524 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8525 Inserts the list of signals found."
8527 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8528 (while (< (point) end-inst-point)
8529 ;; Get primitive's signal name, as will never have port, and no trailing )
8530 (cond ((looking-at "//")
8531 (search-forward "\n"))
8532 ((looking-at "/\\*")
8533 (or (search-forward "*/")
8534 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8535 ((looking-at "(\\*")
8536 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8538 (or (search-forward "*)")
8539 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8540 ;; On pins, parse and advance to next pin
8541 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8542 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8543 (goto-char (match-end 0))
8544 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8545 iolist (cdr iolist))
8546 (verilog-read-sub-decls-expr
8547 submoddecls comment "primitive_port"
8551 (skip-syntax-forward " ")))))))
8553 (defun verilog-read-sub-decls ()
8554 "Internally parse signals going to modules under this module.
8555 Return an array of [ outputs inouts inputs ] signals for modules that are
8556 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8557 is an output, then SIG will be included in the list.
8559 This only works on instantiations created with /*AUTOINST*/ converted by
8560 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8561 component library to determine connectivity of the design.
8563 One work around for this problem is to manually create // Inputs and //
8564 Outputs comments above subcell signals, for example:
8572 (let ((end-mod-point (verilog-get-end-of-defun))
8573 st-point end-inst-point
8574 ;; below 3 modified by verilog-read-sub-decls-line
8575 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8576 (verilog-beg-of-defun-quick)
8577 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8579 (goto-char (match-beginning 0))
8580 (unless (verilog-inside-comment-or-string-p)
8581 ;; Attempt to snarf a comment
8582 (let* ((submod (verilog-read-inst-module))
8583 (inst (verilog-read-inst-name))
8584 (subprim (member submod verilog-gate-keywords))
8585 (comment (concat inst " of " submod ".v"))
8586 submodi submoddecls)
8589 (setq submodi `primitive
8590 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8591 comment (concat inst " of " submod))
8592 (verilog-backward-open-paren)
8593 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8597 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8600 (when (setq submodi (verilog-modi-lookup submod t))
8601 (setq submoddecls (verilog-modi-get-decls submodi)
8602 verilog-read-sub-decls-gate-ios nil)
8603 (verilog-backward-open-paren)
8604 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8607 ;; This could have used a list created by verilog-auto-inst
8608 ;; However I want it to be runnable even on user's manually added signals
8609 (let ((verilog-read-sub-decls-in-interfaced t))
8610 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8611 (verilog-read-sub-decls-line submoddecls comment))) ;; Modifies sigs-ifd
8612 (goto-char st-point)
8613 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8614 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8615 (goto-char st-point)
8616 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8617 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8618 (goto-char st-point)
8619 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8620 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
8621 (goto-char st-point)
8622 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8623 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
8625 ;; Combine duplicate bits
8626 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8627 (verilog-subdecls-new
8628 (verilog-signals-combine-bus (nreverse sigs-out))
8629 (verilog-signals-combine-bus (nreverse sigs-inout))
8630 (verilog-signals-combine-bus (nreverse sigs-in))
8631 (verilog-signals-combine-bus (nreverse sigs-intf))
8632 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8634 (defun verilog-read-inst-pins ()
8635 "Return an array of [ pins ] for the current instantiation at point.
8636 For example if declare A A (.B(SIG)) then B will be included in the list."
8638 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
8640 (verilog-backward-open-paren)
8641 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8642 (setq pin (match-string 1))
8643 (unless (verilog-inside-comment-or-string-p)
8644 (setq pins (cons (list pin) pins))
8645 (when (looking-at "(")
8646 (verilog-forward-sexp-ign-cmt 1))))
8649 (defun verilog-read-arg-pins ()
8650 "Return an array of [ pins ] for the current argument declaration at point."
8652 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
8654 (verilog-backward-open-paren)
8655 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8656 (setq pin (match-string 1))
8657 (unless (verilog-inside-comment-or-string-p)
8658 (setq pins (cons (list pin) pins))))
8661 (defun verilog-read-auto-constants (beg end-mod-point)
8662 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8665 (let (sig-list tpl-end-pt)
8667 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8668 (if (not (looking-at "\\s *("))
8669 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8670 (search-forward "(" end-mod-point)
8671 (setq tpl-end-pt (save-excursion
8673 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8676 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8677 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8680 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8681 (make-variable-buffer-local 'verilog-cache-has-lisp)
8683 (defun verilog-read-auto-lisp-present ()
8684 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8686 (goto-char (point-min))
8687 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8689 (defun verilog-read-auto-lisp (start end)
8690 "Look for and evaluate an AUTO_LISP between START and END.
8691 Must call `verilog-read-auto-lisp-present' before this function."
8692 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8693 (when verilog-cache-has-lisp
8696 (while (re-search-forward "\\<AUTO_LISP(" end t)
8698 (let* ((beg-pt (prog1 (point)
8699 (verilog-forward-sexp-cmt 1))) ;; Closing paren
8701 (verilog-in-hooks t))
8702 (eval-region beg-pt end-pt nil))))))
8704 (defun verilog-read-always-signals-recurse
8705 (exit-keywd rvalue temp-next)
8706 "Recursive routine for parentheses/bracket matching.
8707 EXIT-KEYWD is expression to stop at, nil if top level.
8708 RVALUE is true if at right hand side of equal.
8709 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8710 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
8711 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8713 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8714 (while (not (or (eobp) gotend))
8717 (search-forward "\n"))
8718 ((looking-at "/\\*")
8719 (or (search-forward "*/")
8720 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8721 ((looking-at "(\\*")
8722 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8724 (or (search-forward "*)")
8725 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8726 (t (setq keywd (buffer-substring-no-properties
8728 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8731 sig-last-tolk sig-tolk
8733 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
8736 (or (re-search-forward "[^\\]\"" nil t)
8737 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8738 ;; else at top level loop, keep parsing
8739 ((and end-else-check (equal keywd "else"))
8740 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
8741 ;; no forward movement, want to see else in lower loop
8742 (setq end-else-check nil))
8743 ;; End at top level loop
8744 ((and end-else-check (looking-at "[^ \t\n\f]"))
8745 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
8748 ((and exit-keywd (equal keywd exit-keywd))
8750 (forward-char (length keywd)))
8751 ;; Standard tokens...
8753 (setq ignore-next nil rvalue semi-rvalue)
8754 ;; Final statement at top level loop?
8755 (when (not exit-keywd)
8756 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
8757 (setq end-else-check t))
8760 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
8761 (goto-char (match-end 0))
8763 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
8764 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
8765 (setq ignore-next nil rvalue nil))
8766 ((equal "?" exit-keywd) ;; x?y:z rvalue
8768 ((equal "]" exit-keywd) ;; [x:y] rvalue
8770 (got-sig ;; label: statement
8771 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
8772 ((not rvalue) ;; begin label
8773 (setq ignore-next t rvalue nil)))
8777 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
8778 (set got-list (cons got-sig (symbol-value got-list)))
8781 (if (eq (char-before) ?< )
8782 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
8784 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8786 (setq ignore-next nil rvalue t)
8790 (verilog-read-always-signals-recurse ":" rvalue nil))
8793 (verilog-read-always-signals-recurse "]" t nil))
8796 (cond (sig-last-tolk ;; Function call; zap last signal
8797 (setq got-sig nil)))
8798 (cond ((equal last-keywd "for")
8799 ;; temp-next: Variables on LHS are lvalues, but generally we want
8800 ;; to ignore them, assuming they are loop increments
8801 (verilog-read-always-signals-recurse ";" nil t)
8802 (verilog-read-always-signals-recurse ";" t nil)
8803 (verilog-read-always-signals-recurse ")" nil nil))
8804 (t (verilog-read-always-signals-recurse ")" t nil))))
8805 ((equal keywd "begin")
8806 (skip-syntax-forward "w_")
8807 (verilog-read-always-signals-recurse "end" nil nil)
8808 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
8809 (setq ignore-next nil rvalue semi-rvalue)
8810 (if (not exit-keywd) (setq end-else-check t)))
8811 ((member keywd '("case" "casex" "casez"))
8812 (skip-syntax-forward "w_")
8813 (verilog-read-always-signals-recurse "endcase" t nil)
8814 (setq ignore-next nil rvalue semi-rvalue)
8815 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
8816 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
8817 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8818 (setq ignore-next t))
8820 (member keywd verilog-keywords)
8821 (string-match "^\\$" keywd)) ;; PLI task
8822 (setq ignore-next nil))
8824 (setq keywd (verilog-symbol-detick-denumber keywd))
8826 (set got-list (cons got-sig (symbol-value got-list)))
8827 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
8829 (setq got-list (cond (temp-next 'sigs-temp)
8832 got-sig (if (or (not keywd)
8833 (assoc keywd (symbol-value got-list)))
8834 nil (list keywd nil nil))
8837 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8840 ;; End of non-comment token
8841 (setq last-keywd keywd)))
8842 (skip-syntax-forward " "))
8843 ;; Append the final pending signal
8845 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
8846 (set got-list (cons got-sig (symbol-value got-list)))
8848 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
8851 (defun verilog-read-always-signals ()
8852 "Parse always block at point and return list of (outputs inout inputs)."
8855 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
8856 (search-forward ")")
8857 (verilog-read-always-signals-recurse nil nil nil)
8858 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8860 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
8861 ;; Return what was found
8862 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
8864 (defun verilog-read-instants ()
8865 "Parse module at point and return list of ( ( file instance ) ... )."
8866 (verilog-beg-of-defun-quick)
8867 (let* ((end-mod-point (verilog-get-end-of-defun))
8869 (instants-list nil))
8871 (while (< (point) end-mod-point)
8872 ;; Stay at level 0, no comments
8874 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
8875 (or (> (car state) 0) ; in parens
8876 (nth 5 state) ; comment
8880 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
8881 ;;(if (looking-at "^\\(.+\\)$")
8882 (let ((module (match-string 1))
8883 (instant (match-string 2)))
8884 (if (not (member module verilog-keywords))
8885 (setq instants-list (cons (list module instant) instants-list)))))
8890 (defun verilog-read-auto-template-middle ()
8891 "With point in middle of an AUTO_TEMPLATE, parse it.
8892 Returns REGEXP and list of ( (signal_name connection_name)... )."
8895 (let ((tpl-regexp "\\([0-9]+\\)")
8896 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
8898 tpl-sig-list tpl-wild-list tpl-end-pt rep)
8900 ;; We reserve @"..." for future lisp expressions that evaluate
8901 ;; once-per-AUTOINST
8902 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
8903 (setq tpl-regexp (match-string 1))
8904 (goto-char (match-end 0)))
8905 (search-forward "(")
8906 ;; Parse lines in the template
8907 (when (or verilog-auto-inst-template-numbers
8908 verilog-auto-template-warn-unused)
8910 (let ((pre-pt (point)))
8911 (goto-char (point-min))
8912 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
8913 (setq templateno (1+ templateno)))
8914 (while (< (point) pre-pt)
8916 (setq lineno (1+ lineno))))))
8917 (setq tpl-end-pt (save-excursion
8919 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8923 (while (< (point) tpl-end-pt)
8924 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8927 (match-string-no-properties 1)
8928 (match-string-no-properties 2)
8931 (goto-char (match-end 0)))
8934 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
8935 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8936 (setq rep (match-string-no-properties 3))
8937 (goto-char (match-end 0))
8941 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
8947 ((looking-at "[ \t\f]+")
8948 (goto-char (match-end 0)))
8950 (setq lineno (1+ lineno))
8951 (goto-char (match-end 0)))
8953 (search-forward "\n")
8954 (setq lineno (1+ lineno)))
8955 ((looking-at "/\\*")
8957 (or (search-forward "*/")
8958 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8960 (error "%s: AUTO_TEMPLATE parsing error: %s"
8961 (verilog-point-text)
8962 (progn (looking-at ".*$") (match-string 0))))))
8965 (list tpl-sig-list tpl-wild-list)))))
8967 (defun verilog-read-auto-template (module)
8968 "Look for an auto_template for the instantiation of the given MODULE.
8969 If found returns `verilog-read-auto-template-inside' structure."
8973 ;; Note this search is expensive, as we hunt from mod-begin to point
8974 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
8975 ;; So, we look first for an exact string rather than a slow regexp.
8976 ;; Someday we may keep a cache of every template, but this would also
8977 ;; need to record the relative position of each AUTOINST, as multiple
8978 ;; templates exist for each module, and we're inserting lines.
8980 ;; See also regexp in `verilog-auto-template-lint'
8981 (verilog-re-search-backward-substr
8983 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
8984 ;; Also try forward of this AUTOINST
8985 ;; This is for historical support; this isn't speced as working
8988 (verilog-re-search-forward-substr
8990 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
8991 (goto-char (match-end 0))
8992 (verilog-read-auto-template-middle))
8993 ;; If no template found
8994 (t (vector "" nil))))))
8995 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
8997 (defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
8998 (make-variable-buffer-local 'verilog-auto-template-hits)
9000 (defun verilog-read-auto-template-hit (tpl-ass)
9001 "Record that TPL-ASS template from `verilog-read-auto-template' was used."
9002 (when (eval-when-compile (fboundp 'make-hash-table)) ;; else feature not allowed
9003 (when verilog-auto-template-warn-unused
9004 (unless verilog-auto-template-hits
9005 (setq verilog-auto-template-hits
9006 (make-hash-table :test 'equal :rehash-size 4.0)))
9007 (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
9008 verilog-auto-template-hits))))
9010 (defun verilog-set-define (defname defvalue &optional buffer enumname)
9011 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
9012 Optionally associate it with the specified enumeration ENUMNAME."
9013 (with-current-buffer (or buffer (current-buffer))
9014 ;; Namespace intentionally short for AUTOs and compatibility
9015 (let ((mac (intern (concat "vh-" defname))))
9016 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9017 ;; Need to define to a constant if no value given
9018 (set (make-local-variable mac)
9019 (if (equal defvalue "") "1" defvalue)))
9021 ;; Namespace intentionally short for AUTOs and compatibility
9022 (let ((enumvar (intern (concat "venum-" enumname))))
9023 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9024 (unless (boundp enumvar) (set enumvar nil))
9025 (add-to-list (make-local-variable enumvar) defname)))))
9027 (defun verilog-read-defines (&optional filename recurse subcall)
9028 "Read `defines and parameters for the current file, or optional FILENAME.
9029 If the filename is provided, `verilog-library-flags' will be used to
9030 resolve it. If optional RECURSE is non-nil, recurse through `includes.
9032 Parameters must be simple assignments to constants, or have their own
9033 \"parameter\" label rather than a list of parameters. Thus:
9035 parameter X = 5, Y = 10; // Ok
9036 parameter X = {1'b1, 2'h2}; // Ok
9037 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
9039 Defines must be simple text substitutions, one on a line, starting
9040 at the beginning of the line. Any ifdefs or multiline comments around the
9043 Defines are stored inside Emacs variables using the name vh-{definename}.
9045 This function is useful for setting vh-* variables. The file variables
9046 feature can be used to set defines that `verilog-mode' can see; put at the
9047 *END* of your file something like:
9050 // vh-macro:\"macro_definition\"
9053 If macros are defined earlier in the same file and you want their values,
9054 you can read them automatically (provided `enable-local-eval' is on):
9057 // eval:(verilog-read-defines)
9058 // eval:(verilog-read-defines \"group_standard_includes.v\")
9061 Note these are only read when the file is first visited, you must use
9062 \\[find-alternate-file] RET to have these take effect after editing them!
9064 If you want to disable the \"Process `eval' or hook local variables\"
9065 warning message, you need to add to your init file:
9067 (setq enable-local-eval t)"
9068 (let ((origbuf (current-buffer)))
9070 (unless subcall (verilog-getopt-flags))
9072 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
9074 (set-buffer (find-file-noselect (car fns)))
9075 (error (concat (verilog-point-text)
9076 ": Can't find verilog-read-defines file: " filename)))))
9078 (goto-char (point-min))
9079 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9080 (let ((inc (verilog-string-replace-matches
9081 "\"" "" nil nil (match-string-no-properties 1))))
9082 (unless (verilog-inside-comment-or-string-p)
9083 (verilog-read-defines inc recurse t)))))
9085 ;; note we don't use verilog-re... it's faster this way, and that
9086 ;; function has problems when comments are at the end of the define
9087 (goto-char (point-min))
9088 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
9089 (let ((defname (match-string-no-properties 1))
9090 (defvalue (match-string-no-properties 2)))
9091 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9092 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
9093 (verilog-set-define defname defvalue origbuf))))
9094 ;; Hack: Read parameters
9095 (goto-char (point-min))
9096 (while (re-search-forward
9097 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
9099 ;; The primary way of getting defines is verilog-read-decls
9100 ;; However, that isn't called yet for included files, so we'll add another scheme
9101 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
9102 (setq enumname (match-string-no-properties 2)))
9103 (forward-comment 99999)
9104 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
9105 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
9106 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9107 (verilog-set-define (match-string-no-properties 1)
9108 (match-string-no-properties 2) origbuf enumname))
9109 (goto-char (match-end 0))
9110 (forward-comment 99999)))))))
9112 (defun verilog-read-includes ()
9113 "Read `includes for the current file.
9114 This will find all of the `includes which are at the beginning of lines,
9115 ignoring any ifdefs or multiline comments around them.
9116 `verilog-read-defines' is then performed on the current and each included
9119 It is often useful put at the *END* of your file something like:
9122 // eval:(verilog-read-defines)
9123 // eval:(verilog-read-includes)
9126 Note includes are only read when the file is first visited, you must use
9127 \\[find-alternate-file] RET to have these take effect after editing them!
9129 It is good to get in the habit of including all needed files in each .v
9130 file that needs it, rather than waiting for compile time. This will aid
9131 this process, Verilint, and readability. To prevent defining the same
9132 variable over and over when many modules are compiled together, put a test
9133 around the inside each include file:
9135 foo.v (an include file):
9136 `ifdef _FOO_V // include if not already included
9139 ... contents of file
9141 ;;slow: (verilog-read-defines nil t))
9143 (verilog-getopt-flags)
9144 (goto-char (point-min))
9145 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9146 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
9147 (verilog-read-defines inc nil t)))))
9149 (defun verilog-read-signals (&optional start end)
9150 "Return a simple list of all possible signals in the file.
9151 Bounded by optional region from START to END. Overly aggressive but fast.
9152 Some macros and such are also found and included. For dinotrace.el."
9153 (let (sigs-all keywd)
9154 (progn;save-excursion
9155 (goto-char (or start (point-min)))
9156 (setq end (or end (point-max)))
9157 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
9161 (search-forward "\n"))
9162 ((looking-at "/\\*")
9163 (search-forward "*/"))
9164 ((looking-at "(\\*")
9165 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
9166 (search-forward "*)")))
9167 ((eq ?\" (following-char))
9168 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
9169 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
9170 (goto-char (match-end 0))
9171 (setq keywd (match-string-no-properties 1))
9172 (or (member keywd verilog-keywords)
9173 (member keywd sigs-all)
9174 (setq sigs-all (cons keywd sigs-all))))
9175 (t (forward-char 1))))
9180 ;; Argument file parsing
9183 (defun verilog-getopt (arglist)
9184 "Parse -f, -v etc arguments in ARGLIST list or string."
9185 (unless (listp arglist) (setq arglist (list arglist)))
9186 (let ((space-args '())
9188 ;; Split on spaces, so users can pass whole command lines
9190 (setq arg (car arglist)
9191 arglist (cdr arglist))
9192 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
9193 (setq space-args (append space-args
9194 (list (match-string-no-properties 1 arg))))
9195 (setq arg (match-string 2 arg))))
9198 (setq arg (car space-args)
9199 space-args (cdr space-args))
9203 (setq next-param arg))
9205 (setq next-param arg))
9207 (setq next-param arg))
9208 ;; +libext+(ext1)+(ext2)...
9209 ((string-match "^\\+libext\\+\\(.*\\)" arg)
9210 (setq arg (match-string 1 arg))
9211 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
9212 (verilog-add-list-unique `verilog-library-extensions
9213 (match-string 1 arg))
9214 (setq arg (match-string 2 arg))))
9216 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
9217 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
9218 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
9219 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
9220 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
9222 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
9223 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
9224 (verilog-add-list-unique `verilog-library-directories
9225 (match-string 1 (substitute-in-file-name arg))))
9227 ((equal "+librescan" arg))
9228 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
9229 ;; Second parameters
9230 ((equal next-param "-f")
9231 (setq next-param nil)
9232 (verilog-getopt-file (substitute-in-file-name arg)))
9233 ((equal next-param "-v")
9234 (setq next-param nil)
9235 (verilog-add-list-unique `verilog-library-files
9236 (substitute-in-file-name arg)))
9237 ((equal next-param "-y")
9238 (setq next-param nil)
9239 (verilog-add-list-unique `verilog-library-directories
9240 (substitute-in-file-name arg)))
9242 ((string-match "^[^-+]" arg)
9243 (verilog-add-list-unique `verilog-library-files
9244 (substitute-in-file-name arg)))
9245 ;; Default - ignore; no warning
9247 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
9249 (defun verilog-getopt-file (filename)
9250 "Read Verilog options from the specified FILENAME."
9252 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
9253 (orig-buffer (current-buffer))
9256 (set-buffer (find-file-noselect (car fns)))
9257 (error (concat (verilog-point-text)
9258 ": Can't find verilog-getopt-file -f file: " filename)))
9259 (goto-char (point-min))
9261 (setq line (buffer-substring (point) (point-at-eol)))
9263 (when (string-match "//" line)
9264 (setq line (substring line 0 (match-beginning 0))))
9265 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
9266 (verilog-getopt line))))))
9268 (defun verilog-getopt-flags ()
9269 "Convert `verilog-library-flags' into standard library variables."
9270 ;; If the flags are local, then all the outputs should be local also
9271 (when (local-variable-p `verilog-library-flags (current-buffer))
9272 (mapc 'make-local-variable '(verilog-library-extensions
9273 verilog-library-directories
9274 verilog-library-files
9275 verilog-library-flags)))
9276 ;; Allow user to customize
9277 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
9278 ;; Process arguments
9279 (verilog-getopt verilog-library-flags)
9280 ;; Allow user to customize
9281 (verilog-run-hooks 'verilog-getopt-flags-hook))
9283 (defun verilog-add-list-unique (varref object)
9284 "Append to VARREF list the given OBJECT,
9285 unless it is already a member of the variable's list."
9286 (unless (member object (symbol-value varref))
9287 (set varref (append (symbol-value varref) (list object))))
9289 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
9291 (defun verilog-current-flags ()
9292 "Convert `verilog-library-flags' and similar variables to command line.
9293 Used for __FLAGS__ in `verilog-expand-command'."
9294 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
9295 (when (equal cmd "")
9297 "+libext+" (mapconcat `concat verilog-library-extensions "+")
9298 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
9299 verilog-library-directories "")
9300 (mapconcat (lambda (i) (concat " -v " i))
9301 verilog-library-files ""))))
9303 ;;(verilog-current-flags)
9307 ;; Cached directory support
9310 (defvar verilog-dir-cache-preserving nil
9311 "If true, the directory cache is enabled, and file system changes are ignored.
9312 See `verilog-dir-exists-p' and `verilog-dir-files'.")
9314 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
9315 (defvar verilog-dir-cache-list nil
9316 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
9317 (defvar verilog-dir-cache-lib-filenames nil
9318 "Cached data for `verilog-library-filenames'.")
9320 (defmacro verilog-preserve-dir-cache (&rest body)
9321 "Execute the BODY forms, allowing directory cache preservation within BODY.
9322 This means that changes inside BODY made to the file system will not be
9323 seen by the `verilog-dir-files' and related functions."
9324 `(let ((verilog-dir-cache-preserving (current-buffer))
9325 verilog-dir-cache-list
9326 verilog-dir-cache-lib-filenames)
9329 (defun verilog-dir-files (dirname)
9330 "Return all filenames in the DIRNAME directory.
9331 Relative paths depend on the `default-directory'.
9332 Results are cached if inside `verilog-preserve-dir-cache'."
9333 (unless verilog-dir-cache-preserving
9334 (setq verilog-dir-cache-list nil)) ;; Cache disabled
9335 ;; We don't use expand-file-name on the dirname to make key, as it's slow
9336 (let* ((cache-key (list dirname default-directory))
9337 (fass (assoc cache-key verilog-dir-cache-list))
9339 (cond (fass ;; Return data from cache hit
9342 (setq exp-dirname (expand-file-name dirname)
9343 data (and (file-directory-p exp-dirname)
9344 (directory-files exp-dirname nil nil nil)))
9345 ;; Note we also encache nil for non-existing dirs.
9346 (setq verilog-dir-cache-list (cons (list cache-key data)
9347 verilog-dir-cache-list))
9349 ;; Miss-and-hit test:
9350 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
9351 ;; (prin1 (verilog-dir-files ".")) nil)
9353 (defun verilog-dir-file-exists-p (filename)
9354 "Return true if FILENAME exists.
9355 Like `file-exists-p' but results are cached if inside
9356 `verilog-preserve-dir-cache'."
9357 (let* ((dirname (file-name-directory filename))
9358 ;; Correct for file-name-nondirectory returning same if no slash.
9359 (dirnamed (if (or (not dirname) (equal dirname filename))
9360 default-directory dirname))
9361 (flist (verilog-dir-files dirnamed)))
9363 (member (file-name-nondirectory filename) flist)
9365 ;;(verilog-dir-file-exists-p "verilog-mode.el")
9366 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
9370 ;; Module name lookup
9373 (defun verilog-module-inside-filename-p (module filename)
9374 "Return modi if MODULE is specified inside FILENAME, else nil.
9375 Allows version control to check out the file if need be."
9376 (and (or (file-exists-p filename)
9377 (and (fboundp 'vc-backend)
9378 (vc-backend filename)))
9380 (with-current-buffer (find-file-noselect filename)
9382 (goto-char (point-min))
9384 ;; It may be tempting to look for verilog-defun-re,
9385 ;; don't, it slows things down a lot!
9386 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
9387 (setq type (match-string-no-properties 0))
9388 (verilog-re-search-forward-quick "[(;]" nil t))
9389 (if (equal module (verilog-read-module-name))
9390 (setq modi (verilog-modi-new module filename (point) type))))
9393 (defun verilog-is-number (symbol)
9394 "Return true if SYMBOL is number-like."
9395 (or (string-match "^[0-9 \t:]+$" symbol)
9396 (string-match "^[---]*[0-9]+$" symbol)
9397 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
9399 (defun verilog-symbol-detick (symbol wing-it)
9400 "Return an expanded SYMBOL name without any defines.
9401 If the variable vh-{symbol} is defined, return that value.
9402 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9403 (while (and symbol (string-match "^`" symbol))
9404 (setq symbol (substring symbol 1))
9406 ;; Namespace intentionally short for AUTOs and compatibility
9407 (if (boundp (intern (concat "vh-" symbol)))
9408 ;; Emacs has a bug where boundp on a buffer-local
9409 ;; variable in only one buffer returns t in another.
9410 ;; This can confuse, so check for nil.
9411 ;; Namespace intentionally short for AUTOs and compatibility
9412 (let ((val (eval (intern (concat "vh-" symbol)))))
9414 (if wing-it symbol nil)
9416 (if wing-it symbol nil))))
9418 ;;(verilog-symbol-detick "`mod" nil)
9420 (defun verilog-symbol-detick-denumber (symbol)
9421 "Return SYMBOL with defines converted and any numbers dropped to nil."
9422 (when (string-match "^`" symbol)
9423 ;; This only will work if the define is a simple signal, not
9424 ;; something like a[b]. Sorry, it should be substituted into the parser
9426 (verilog-string-replace-matches
9427 "\[[^0-9: \t]+\]" "" nil nil
9428 (or (verilog-symbol-detick symbol nil)
9429 (if verilog-auto-sense-defines-constant
9432 (if (verilog-is-number symbol)
9436 (defun verilog-symbol-detick-text (text)
9437 "Return TEXT without any known defines.
9438 If the variable vh-{symbol} is defined, substitute that value."
9439 (let ((ok t) symbol val)
9440 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
9441 (setq symbol (match-string 1 text))
9444 ;; Namespace intentionally short for AUTOs and compatibility
9445 (boundp (intern (concat "vh-" symbol)))
9446 ;; Emacs has a bug where boundp on a buffer-local
9447 ;; variable in only one buffer returns t in another.
9448 ;; This can confuse, so check for nil.
9449 ;; Namespace intentionally short for AUTOs and compatibility
9450 (setq val (eval (intern (concat "vh-" symbol)))))
9451 (setq text (replace-match val nil nil text)))
9452 (t (setq ok nil)))))
9454 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
9456 (defun verilog-expand-dirnames (&optional dirnames)
9457 "Return a list of existing directories given a list of wildcarded DIRNAMES.
9458 Or, just the existing dirnames themselves if there are no wildcards."
9459 ;; Note this function is performance critical.
9460 ;; Do not call anything that requires disk access that cannot be cached.
9462 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
9463 (setq dirnames (reverse dirnames)) ; not nreverse
9465 pattern dirfile dirfiles dirname root filename rest basefile)
9467 (setq dirname (substitute-in-file-name (car dirnames))
9468 dirnames (cdr dirnames))
9469 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
9470 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
9473 (setq root (match-string 1 dirname)
9474 filename (match-string 2 dirname)
9475 rest (match-string 3 dirname)
9477 ;; now replace those * and ? with .+ and .
9478 ;; use ^ and /> to get only whole file names
9479 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9480 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9481 pattern (concat "^" pattern "$")
9482 dirfiles (verilog-dir-files root))
9484 (setq basefile (car dirfiles)
9485 dirfile (expand-file-name (concat root basefile rest))
9486 dirfiles (cdr dirfiles))
9487 (if (and (string-match pattern basefile)
9488 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9489 (not (equal basefile "."))
9490 (not (equal basefile ".."))
9491 (file-directory-p dirfile))
9492 (setq dirlist (cons dirfile dirlist)))))
9495 (if (file-directory-p dirname)
9496 (setq dirlist (cons dirname dirlist))))))
9498 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9500 (defun verilog-library-filenames (filename &optional current check-ext)
9501 "Return a search path to find the given FILENAME or module name.
9502 Uses the optional CURRENT filename or variable `buffer-file-name', plus
9503 `verilog-library-directories' and `verilog-library-extensions'
9504 variables to build the path. With optional CHECK-EXT also check
9505 `verilog-library-extensions'."
9506 (unless current (setq current (buffer-file-name)))
9507 (unless verilog-dir-cache-preserving
9508 (setq verilog-dir-cache-lib-filenames nil))
9509 (let* ((cache-key (list filename current check-ext))
9510 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9511 chkdirs chkdir chkexts fn outlist)
9512 (cond (fass ;; Return data from cache hit
9515 ;; Note this expand can't be easily cached, as we need to
9516 ;; pick up buffer-local variables for newly read sub-module files
9517 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9519 (setq chkdir (expand-file-name (car chkdirs)
9520 (file-name-directory current))
9521 chkexts (if check-ext verilog-library-extensions `("")))
9523 (setq fn (expand-file-name (concat filename (car chkexts))
9525 ;;(message "Check for %s" fn)
9526 (if (verilog-dir-file-exists-p fn)
9527 (setq outlist (cons (expand-file-name
9528 fn (file-name-directory current))
9530 (setq chkexts (cdr chkexts)))
9531 (setq chkdirs (cdr chkdirs)))
9532 (setq outlist (nreverse outlist))
9533 (setq verilog-dir-cache-lib-filenames
9534 (cons (list cache-key outlist)
9535 verilog-dir-cache-lib-filenames))
9538 (defun verilog-module-filenames (module current)
9539 "Return a search path to find the given MODULE name.
9540 Uses the CURRENT filename, `verilog-library-extensions',
9541 `verilog-library-directories' and `verilog-library-files'
9542 variables to build the path."
9543 ;; Return search locations for it
9544 (append (list current) ; first, current buffer
9545 (verilog-library-filenames module current t)
9546 verilog-library-files)) ; finally, any libraries
9549 ;; Module Information
9551 ;; Many of these functions work on "modi" a module information structure
9552 ;; A modi is: [module-name-string file-name begin-point]
9554 (defvar verilog-cache-enabled t
9555 "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
9557 (defvar verilog-modi-cache-list nil
9558 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9559 For speeding up verilog-modi-get-* commands.
9561 (make-variable-buffer-local 'verilog-modi-cache-list)
9563 (defvar verilog-modi-cache-preserve-tick nil
9564 "Modification tick after which the cache is still considered valid.
9565 Use `verilog-preserve-modi-cache' to set it.")
9566 (defvar verilog-modi-cache-preserve-buffer nil
9567 "Modification tick after which the cache is still considered valid.
9568 Use `verilog-preserve-modi-cache' to set it.")
9569 (defvar verilog-modi-cache-current-enable nil
9570 "Non-nil means allow caching `verilog-modi-current', set by let().")
9571 (defvar verilog-modi-cache-current nil
9572 "Currently active `verilog-modi-current', if any, set by let().")
9573 (defvar verilog-modi-cache-current-max nil
9574 "Current endmodule point for `verilog-modi-cache-current', if any.")
9576 (defun verilog-modi-current ()
9577 "Return the modi structure for the module currently at point, possibly cached."
9578 (cond ((and verilog-modi-cache-current
9579 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9580 (<= (point) verilog-modi-cache-current-max))
9581 ;; Slow assertion, for debugging the cache:
9582 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9583 verilog-modi-cache-current)
9584 (verilog-modi-cache-current-enable
9585 (setq verilog-modi-cache-current (verilog-modi-current-get)
9586 verilog-modi-cache-current-max
9587 ;; The cache expires when we pass "endmodule" as then the
9588 ;; current modi may change to the next module
9589 ;; This relies on the AUTOs generally inserting, not deleting text
9591 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9592 verilog-modi-cache-current)
9594 (verilog-modi-current-get))))
9596 (defun verilog-modi-current-get ()
9597 "Return the modi structure for the module currently at point."
9598 (let* (name type pt)
9599 ;; read current module's name
9601 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9602 (setq type (match-string-no-properties 0))
9603 (verilog-re-search-forward-quick "(" nil nil)
9604 (setq name (verilog-read-module-name))
9606 ;; return modi - note this vector built two places
9607 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9609 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9610 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9611 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9612 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9614 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9615 "Find the file and point at which MODULE is defined.
9616 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9617 Return modi if successful, else print message unless IGNORE-ERROR is true."
9618 (let* ((current (or (buffer-file-name) (current-buffer)))
9621 ;;(message "verilog-modi-lookup: %s" module)
9622 (cond ((and verilog-modi-lookup-cache
9623 verilog-cache-enabled
9625 (setq modi (gethash module verilog-modi-lookup-cache))
9626 (equal verilog-modi-lookup-last-current current)
9627 ;; Iff hit is in current buffer, then tick must match
9628 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9629 (not (equal current (verilog-modi-file-or-buffer modi)))))
9630 ;;(message "verilog-modi-lookup: HIT %S" modi)
9633 (t (let* ((realname (verilog-symbol-detick module t))
9634 (orig-filenames (verilog-module-filenames realname current))
9635 (filenames orig-filenames)
9637 (while (and filenames (not mif))
9638 (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
9639 (setq filenames (cdr filenames))))
9640 ;; mif has correct form to become later elements of modi
9641 (cond (mif (setq modi mif))
9644 (error (concat (verilog-point-text)
9645 ": Can't locate " module " module definition"
9646 (if (not (equal module realname))
9647 (concat " (Expanded macro to " realname ")")
9649 "\n Check the verilog-library-directories variable."
9650 "\n I looked in (if not listed, doesn't exist):\n\t"
9651 (mapconcat 'concat orig-filenames "\n\t"))))))
9652 (when (eval-when-compile (fboundp 'make-hash-table))
9653 (unless verilog-modi-lookup-cache
9654 (setq verilog-modi-lookup-cache
9655 (make-hash-table :test 'equal :rehash-size 4.0)))
9656 (puthash module modi verilog-modi-lookup-cache))
9657 (setq verilog-modi-lookup-last-current current
9658 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9661 (defun verilog-modi-filename (modi)
9662 "Filename of MODI, or name of buffer if it's never been saved."
9663 (if (bufferp (verilog-modi-file-or-buffer modi))
9664 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9665 (buffer-name (verilog-modi-file-or-buffer modi)))
9666 (verilog-modi-file-or-buffer modi)))
9668 (defun verilog-modi-goto (modi)
9669 "Move point/buffer to specified MODI."
9670 (or modi (error "Passed unfound modi to goto, check earlier"))
9671 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9672 (verilog-modi-file-or-buffer modi)
9673 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9674 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
9676 (goto-char (verilog-modi-get-point modi)))
9678 (defun verilog-goto-defun-file (module)
9679 "Move point to the file at which a given MODULE is defined."
9680 (interactive "sGoto File for Module: ")
9681 (let* ((modi (verilog-modi-lookup module nil)))
9683 (verilog-modi-goto modi)
9684 (switch-to-buffer (current-buffer)))))
9686 (defun verilog-modi-cache-results (modi function)
9687 "Run on MODI the given FUNCTION. Locate the module in a file.
9688 Cache the output of function so next call may have faster access."
9690 (save-excursion ;; Cache is buffer-local so can't avoid this.
9691 (verilog-modi-goto modi)
9692 (if (and (setq fass (assoc (list modi function)
9693 verilog-modi-cache-list))
9694 ;; Destroy caching when incorrect; Modified or file changed
9695 (not (and verilog-cache-enabled
9696 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9697 (and verilog-modi-cache-preserve-tick
9698 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9699 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9700 (equal (visited-file-modtime) (nth 2 fass)))))
9701 (setq verilog-modi-cache-list nil
9704 ;; Return data from cache hit
9708 ;; Clear then restore any highlighting to make emacs19 happy
9710 (verilog-save-font-mods
9711 (setq func-returns (funcall function)))
9712 ;; Cache for next time
9713 (setq verilog-modi-cache-list
9714 (cons (list (list modi function)
9715 (buffer-chars-modified-tick)
9716 (visited-file-modtime)
9718 verilog-modi-cache-list))
9721 (defun verilog-modi-cache-add (modi function element sig-list)
9722 "Add function return results to the module cache.
9723 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
9724 function now contains the additional SIG-LIST parameters."
9727 (verilog-modi-goto modi)
9728 (if (setq fass (assoc (list modi function)
9729 verilog-modi-cache-list))
9730 (let ((func-returns (nth 3 fass)))
9731 (aset func-returns element
9732 (append sig-list (aref func-returns element))))))))
9734 (defmacro verilog-preserve-modi-cache (&rest body)
9735 "Execute the BODY forms, allowing cache preservation within BODY.
9736 This means that changes to the buffer will not result in the cache being
9737 flushed. If the changes affect the modsig state, they must call the
9738 modsig-cache-add-* function, else the results of later calls may be
9739 incorrect. Without this, changes are assumed to be adding/removing signals
9740 and invalidating the cache."
9741 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
9742 (verilog-modi-cache-preserve-buffer (current-buffer)))
9746 (defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
9747 "Given a MODI, return the declarations related to the given modport NAME."
9748 ;; Recursive routine - see below
9749 (let* ((realname (verilog-symbol-detick name t))
9750 (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
9751 (or modport ignore-error
9752 (error (concat (verilog-point-text)
9753 ": Can't locate " name " modport definition"
9754 (if (not (equal name realname))
9755 (concat " (Expanded macro to " realname ")")
9757 (let* ((decls (verilog-modport-decls modport))
9758 (clks (verilog-modport-clockings modport)))
9759 ;; Now expand any clocking's
9761 (setq decls (verilog-decls-append
9763 (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
9764 (setq clks (cdr clks)))
9767 (defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
9768 "Given a MODI, return the declarations related to the given modport NAME-RE.
9769 If the modport points to any clocking blocks, expand the signals to include
9770 those clocking block's signals."
9771 ;; Recursive routine - see below
9772 (let* ((mod-decls (verilog-modi-get-decls modi))
9773 (clks (verilog-decls-get-modports mod-decls))
9774 (name-re (concat "^" name-re "$"))
9775 (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
9776 ;; Pull in all modports
9778 (when (string-match name-re (verilog-modport-name (car clks)))
9779 (setq decls (verilog-decls-append
9781 (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
9782 (setq clks (cdr clks)))
9785 (defun verilog-signals-matching-enum (in-list enum)
9786 "Return all signals in IN-LIST matching the given ENUM."
9789 (if (equal (verilog-sig-enum (car in-list)) enum)
9790 (setq out-list (cons (car in-list) out-list)))
9791 (setq in-list (cdr in-list)))
9793 ;; Namespace intentionally short for AUTOs and compatibility
9794 (let* ((enumvar (intern (concat "venum-" enum)))
9795 (enumlist (and (boundp enumvar) (eval enumvar))))
9797 (add-to-list 'out-list (list (car enumlist)))
9798 (setq enumlist (cdr enumlist))))
9799 (nreverse out-list)))
9801 (defun verilog-signals-matching-regexp (in-list regexp)
9802 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
9803 (if (or (not regexp) (equal regexp ""))
9805 (let ((case-fold-search verilog-case-fold)
9808 (if (string-match regexp (verilog-sig-name (car in-list)))
9809 (setq out-list (cons (car in-list) out-list)))
9810 (setq in-list (cdr in-list)))
9811 (nreverse out-list))))
9813 (defun verilog-signals-not-matching-regexp (in-list regexp)
9814 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
9815 (if (or (not regexp) (equal regexp ""))
9817 (let ((case-fold-search verilog-case-fold)
9820 (if (not (string-match regexp (verilog-sig-name (car in-list))))
9821 (setq out-list (cons (car in-list) out-list)))
9822 (setq in-list (cdr in-list)))
9823 (nreverse out-list))))
9825 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
9826 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
9828 (if (or (not regexp) (equal regexp ""))
9830 (let (out-list to-match)
9832 ;; Note verilog-insert-one-definition matches on this order
9833 (setq to-match (concat
9835 " " (verilog-sig-signed (car in-list))
9836 " " (verilog-sig-multidim (car in-list))
9837 (verilog-sig-bits (car in-list))))
9838 (if (string-match regexp to-match)
9839 (setq out-list (cons (car in-list) out-list)))
9840 (setq in-list (cdr in-list)))
9841 (nreverse out-list))))
9843 (defun verilog-signals-edit-wire-reg (in-list)
9844 "Return all signals in IN-LIST with wire/reg data types made blank."
9845 (mapcar (lambda (sig)
9846 (when (member (verilog-sig-type sig) '("wire" "reg"))
9847 (verilog-sig-type-set sig nil))
9851 (defun verilog-decls-get-signals (decls)
9852 "Return all declared signals in DECLS, excluding 'assign' statements."
9854 (verilog-decls-get-outputs decls)
9855 (verilog-decls-get-inouts decls)
9856 (verilog-decls-get-inputs decls)
9857 (verilog-decls-get-vars decls)
9858 (verilog-decls-get-consts decls)
9859 (verilog-decls-get-gparams decls)))
9861 (defun verilog-decls-get-ports (decls)
9863 (verilog-decls-get-outputs decls)
9864 (verilog-decls-get-inouts decls)
9865 (verilog-decls-get-inputs decls)))
9867 (defun verilog-decls-get-iovars (decls)
9869 (verilog-decls-get-vars decls)
9870 (verilog-decls-get-outputs decls)
9871 (verilog-decls-get-inouts decls)
9872 (verilog-decls-get-inputs decls)))
9874 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
9875 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
9876 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
9877 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
9878 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
9879 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
9880 (defsubst verilog-modi-cache-add-vars (modi sig-list)
9881 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
9882 (defsubst verilog-modi-cache-add-gparams (modi sig-list)
9883 (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
9887 ;; Auto creation utilities
9890 (defun verilog-auto-re-search-do (search-for func)
9891 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
9892 (goto-char (point-min))
9893 (while (verilog-re-search-forward-quick search-for nil t)
9896 (defun verilog-insert-one-definition (sig type indent-pt)
9897 "Print out a definition for SIG of the given TYPE,
9898 with appropriate INDENT-PT indentation."
9899 (indent-to indent-pt)
9900 ;; Note verilog-signals-matching-dir-re matches on this order
9902 (when (verilog-sig-modport sig)
9903 (insert "." (verilog-sig-modport sig)))
9904 (when (verilog-sig-signed sig)
9905 (insert " " (verilog-sig-signed sig)))
9906 (when (verilog-sig-multidim sig)
9907 (insert " " (verilog-sig-multidim-string sig)))
9908 (when (verilog-sig-bits sig)
9909 (insert " " (verilog-sig-bits sig)))
9910 (indent-to (max 24 (+ indent-pt 16)))
9911 (unless (= (char-syntax (preceding-char)) ?\ )
9912 (insert " ")) ; Need space between "]name" if indent-to did nothing
9913 (insert (verilog-sig-name sig))
9914 (when (verilog-sig-memory sig)
9915 (insert " " (verilog-sig-memory sig))))
9917 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
9918 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
9919 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
9920 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
9921 When MODI is non-null, also add to modi-cache, for tracking."
9923 (cond ((equal direction "wire")
9924 (verilog-modi-cache-add-vars modi sigs))
9925 ((equal direction "reg")
9926 (verilog-modi-cache-add-vars modi sigs))
9927 ((equal direction "output")
9928 (verilog-modi-cache-add-outputs modi sigs)
9929 (when verilog-auto-declare-nettype
9930 (verilog-modi-cache-add-vars modi sigs)))
9931 ((equal direction "input")
9932 (verilog-modi-cache-add-inputs modi sigs)
9933 (when verilog-auto-declare-nettype
9934 (verilog-modi-cache-add-vars modi sigs)))
9935 ((equal direction "inout")
9936 (verilog-modi-cache-add-inouts modi sigs)
9937 (when verilog-auto-declare-nettype
9938 (verilog-modi-cache-add-vars modi sigs)))
9939 ((equal direction "interface"))
9940 ((equal direction "parameter")
9941 (verilog-modi-cache-add-gparams modi sigs))
9943 (error "Unsupported verilog-insert-definition direction: %s" direction))))
9945 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
9947 (let ((sig (car sigs)))
9948 (verilog-insert-one-definition
9950 ;; Want "type x" or "output type x", not "wire type x"
9951 (cond ((or (verilog-sig-type sig)
9952 verilog-auto-wire-type)
9954 (when (member direction '("input" "output" "inout"))
9955 (concat direction " "))
9956 (or (verilog-sig-type sig)
9957 verilog-auto-wire-type)))
9958 ((and verilog-auto-declare-nettype
9959 (member direction '("input" "output" "inout")))
9960 (concat direction " " verilog-auto-declare-nettype))
9964 (insert (if v2k "," ";"))
9965 (if (or (not (verilog-sig-comment sig))
9966 (equal "" (verilog-sig-comment sig)))
9968 (indent-to (max 48 (+ indent-pt 40)))
9969 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
9970 (setq sigs (cdr sigs)))))
9973 (if (not (boundp 'indent-pt))
9974 (defvar indent-pt nil "Local used by insert-indent")))
9976 (defun verilog-insert-indent (&rest stuff)
9977 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
9978 Presumes that any newlines end a list element."
9979 (let ((need-indent t))
9981 (if need-indent (indent-to indent-pt))
9982 (setq need-indent nil)
9983 (verilog-insert (car stuff))
9984 (setq need-indent (string-match "\n$" (car stuff))
9985 stuff (cdr stuff)))))
9986 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
9988 (defun verilog-forward-or-insert-line ()
9989 "Move forward a line, unless at EOB, then insert a newline."
9990 (if (eobp) (insert "\n")
9993 (defun verilog-repair-open-comma ()
9994 "Insert comma if previous argument is other than an open parenthesis or endif."
9995 ;; We can't just search backward for ) as it might be inside another expression.
9996 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
9998 (verilog-backward-syntactic-ws-quick)
9999 (when (and (not (save-excursion ;; Not beginning (, or existing ,
10001 (looking-at "[(,]")))
10002 (not (save-excursion ;; Not `endif, or user define
10004 (skip-chars-backward "[a-zA-Z0-9_`]")
10005 (looking-at "`"))))
10008 (defun verilog-repair-close-comma ()
10009 "If point is at a comma followed by a close parenthesis, fix it.
10010 This repairs those mis-inserted by an AUTOARG."
10011 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
10013 (verilog-forward-close-paren)
10015 (verilog-backward-syntactic-ws-quick)
10017 (when (looking-at ",")
10020 (defun verilog-make-width-expression (range-exp)
10021 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
10022 ;; strip off the []
10023 (cond ((not range-exp)
10026 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
10027 (setq range-exp (match-string 1 range-exp)))
10028 (cond ((not range-exp)
10030 ;; [#:#] We can compute a numeric result
10031 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
10034 (1+ (abs (- (string-to-number (match-string 1 range-exp))
10035 (string-to-number (match-string 2 range-exp)))))))
10036 ;; [PARAM-1:0] can just return PARAM
10037 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
10038 (match-string 1 range-exp))
10039 ;; [arbitrary] need math
10040 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
10041 (concat "(1+(" (match-string 1 range-exp) ")"
10042 (if (equal "0" (match-string 2 range-exp))
10043 "" ;; Don't bother with -(0)
10044 (concat "-(" (match-string 2 range-exp) ")"))
10047 ;;(verilog-make-width-expression "`A:`B")
10049 (defun verilog-simplify-range-expression (expr)
10050 "Return a simplified range expression with constants eliminated from EXPR."
10051 ;; Note this is always called with brackets; ie [z] or [z:z]
10052 (if (not (string-match "[---+*()]" expr))
10053 expr ;; short-circuit
10056 (while (not (equal last-pass out))
10057 (setq last-pass out)
10058 ;; Prefix regexp needs beginning of match, or some symbol of
10059 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
10061 (while (string-match
10062 (concat "\\([[({:*+-]\\)" ; - must be last
10063 "(\\<\\([0-9A-Za-z_]+\\))"
10066 (setq out (replace-match "\\1\\2\\3" nil nil out)))
10067 (while (string-match
10068 (concat "\\([[({:*+-]\\)" ; - must be last
10069 "\\$clog2\\s *(\\<\\([0-9]+\\))"
10072 (setq out (replace-match
10074 (match-string 1 out)
10075 (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
10076 (match-string 3 out))
10078 ;; For precedence do * before +/-
10079 (while (string-match
10080 (concat "\\([[({:*+-]\\)"
10081 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
10084 (setq out (replace-match
10085 (concat (match-string 1 out)
10086 (int-to-string (* (string-to-number (match-string 2 out))
10087 (string-to-number (match-string 4 out))))
10088 (match-string 5 out))
10090 (while (string-match
10091 (concat "\\([[({:+-]\\)" ; No * here as higher prec
10092 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
10095 (let ((pre (match-string 1 out))
10096 (lhs (string-to-number (match-string 2 out)))
10097 (rhs (string-to-number (match-string 4 out)))
10098 (post (match-string 5 out))
10100 (when (equal pre "-")
10101 (setq lhs (- lhs)))
10102 (setq val (if (equal (match-string 3 out) "-")
10106 (concat (if (and (equal pre "-")
10108 "" ;; Not "--20" but just "-20"
10110 (int-to-string val)
10115 ;;(verilog-simplify-range-expression "[1:3]") ;; 1
10116 ;;(verilog-simplify-range-expression "[(1):3]") ;; 1
10117 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ;;20
10118 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ;; 48
10119 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ;; FOO*4-2
10120 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ;; FOO*4+0
10121 ;;(verilog-simplify-range-expression "[(func(BAR))]") ;; func(BAR)
10122 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ;; FOO-0
10123 ;;(verilog-simplify-range-expression "[$clog2(2)]") ;; 1
10124 ;;(verilog-simplify-range-expression "[$clog2(7)]") ;; 3
10126 (defun verilog-clog2 (value)
10127 "Compute $clog2 - ceiling log2 of VALUE."
10130 (ceiling (/ (log value) (log 2)))))
10132 (defun verilog-typedef-name-p (variable-name)
10133 "Return true if the VARIABLE-NAME is a type definition."
10134 (when verilog-typedef-regexp
10135 (verilog-string-match-fold verilog-typedef-regexp variable-name)))
10141 (defun verilog-delete-autos-lined ()
10142 "Delete autos that occupy multiple lines, between begin and end comments."
10143 ;; The newline must not have a comment property, so we must
10144 ;; delete the end auto's newline, not the first newline
10146 (let ((pt (point)))
10148 (looking-at "\\s-*// Beginning")
10149 (search-forward "// End of automatic" nil t))
10153 (delete-region pt (point)))))
10155 (defun verilog-delete-empty-auto-pair ()
10156 "Delete begin/end auto pair at point, if empty."
10158 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
10159 "\\s-*// End of automatics\n"))
10160 (delete-region (point) (save-excursion (forward-line 2) (point)))))
10162 (defun verilog-forward-close-paren ()
10163 "Find the close parenthesis that match the current point.
10164 Ignore other close parenthesis with matching open parens."
10166 (while (> parens 0)
10167 (unless (verilog-re-search-forward-quick "[()]" nil t)
10168 (error "%s: Mismatching ()" (verilog-point-text)))
10169 (cond ((= (preceding-char) ?\( )
10170 (setq parens (1+ parens)))
10171 ((= (preceding-char) ?\) )
10172 (setq parens (1- parens)))))))
10174 (defun verilog-backward-open-paren ()
10175 "Find the open parenthesis that match the current point.
10176 Ignore other open parenthesis with matching close parens."
10178 (while (> parens 0)
10179 (unless (verilog-re-search-backward-quick "[()]" nil t)
10180 (error "%s: Mismatching ()" (verilog-point-text)))
10181 (cond ((= (following-char) ?\) )
10182 (setq parens (1+ parens)))
10183 ((= (following-char) ?\( )
10184 (setq parens (1- parens)))))))
10186 (defun verilog-backward-open-bracket ()
10187 "Find the open bracket that match the current point.
10188 Ignore other open bracket with matching close bracket."
10190 (while (> parens 0)
10191 (unless (verilog-re-search-backward-quick "[][]" nil t)
10192 (error "%s: Mismatching []" (verilog-point-text)))
10193 (cond ((= (following-char) ?\] )
10194 (setq parens (1+ parens)))
10195 ((= (following-char) ?\[ )
10196 (setq parens (1- parens)))))))
10198 (defun verilog-delete-to-paren ()
10199 "Delete the automatic inst/sense/arg created by autos.
10200 Deletion stops at the matching end parenthesis, outside comments."
10201 (delete-region (point)
10203 (verilog-backward-open-paren)
10204 (verilog-forward-sexp-ign-cmt 1) ;; Moves to paren that closes argdecl's
10208 (defun verilog-auto-star-safe ()
10209 "Return if a .* AUTOINST is safe to delete or expand.
10210 It was created by the AUTOS themselves, or by the user."
10211 (and verilog-auto-star-expand
10213 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
10215 (defun verilog-delete-auto-star-all ()
10216 "Delete a .* AUTOINST, if it is safe."
10217 (when (verilog-auto-star-safe)
10218 (verilog-delete-to-paren)))
10220 (defun verilog-delete-auto-star-implicit ()
10221 "Delete all .* implicit connections created by `verilog-auto-star'.
10222 This function will be called automatically at save unless
10223 `verilog-auto-star-save' is set, any non-templated expanded pins will be
10226 (let (paren-pt indent have-close-paren)
10228 (goto-char (point-min))
10229 ;; We need to match these even outside of comments.
10230 ;; For reasonable performance, we don't check if inside comments, sorry.
10231 (while (re-search-forward "// Implicit \\.\\*" nil t)
10232 (setq paren-pt (point))
10233 (beginning-of-line)
10234 (setq have-close-paren
10236 (when (search-forward ");" paren-pt t)
10237 (setq indent (current-indentation))
10239 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
10240 (when have-close-paren
10241 ;; Delete extra commentary
10245 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
10246 (delete-region (match-beginning 0) (match-end 0))))
10247 ;; If it is simple, we can put the ); on the same line as the last text
10248 (let ((rtn-pt (point)))
10250 (while (progn (backward-char 1)
10251 (looking-at "[ \t\n\f]")))
10252 (when (looking-at ",")
10253 (delete-region (+ 1 (point)) rtn-pt))))
10255 (indent-to indent))
10257 ;; Still need to kill final comma - always is one as we put one after the .*
10258 (re-search-backward ",")
10259 (delete-char 1))))))
10261 (defun verilog-delete-auto ()
10262 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
10263 Use \\[verilog-auto] to re-insert the updated AUTOs.
10265 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
10266 called before and after this function, respectively."
10269 (if (buffer-file-name)
10270 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
10271 (verilog-save-no-change-functions
10272 (verilog-save-scan-cache
10273 ;; Allow user to customize
10274 (verilog-run-hooks 'verilog-before-delete-auto-hook)
10276 ;; Remove those that have multi-line insertions, possibly with parameters
10277 ;; We allow anything beginning with AUTO, so that users can add their own
10279 (verilog-auto-re-search-do
10280 (concat "/\\*AUTO[A-Za-z0-9_]+"
10281 ;; Optional parens or quoted parameter or .* for (((...)))
10282 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
10284 'verilog-delete-autos-lined)
10285 ;; Remove those that are in parenthesis
10286 (verilog-auto-re-search-do
10289 (verilog-regexp-words
10290 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
10293 'verilog-delete-to-paren)
10294 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
10295 (verilog-auto-re-search-do "\\.\\*"
10296 'verilog-delete-auto-star-all)
10297 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
10298 (goto-char (point-min))
10299 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
10300 (replace-match ""))
10303 (verilog-run-hooks 'verilog-delete-auto-hook)))))
10309 (defun verilog-inject-auto ()
10310 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
10312 Any always @ blocks with sensitivity lists that match computed lists will
10313 be replaced with /*AS*/ comments.
10315 Any cells will get /*AUTOINST*/ added to the end of the pin list.
10316 Pins with have identical names will be deleted.
10318 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
10319 support adding new ports. You may wish to delete older ports yourself.
10323 module ExampInject (i, o);
10329 InstModule instName
10334 Typing \\[verilog-inject-auto] will make this into:
10336 module ExampInject (i, o/*AUTOARG*/
10341 always @ (/*AS*/i or j)
10343 InstModule instName
10352 (defun verilog-inject-arg ()
10353 "Inject AUTOARG into new code. See `verilog-inject-auto'."
10354 ;; Presume one module per file.
10356 (goto-char (point-min))
10357 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
10358 (let ((endmodp (save-excursion
10359 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
10361 ;; See if there's already a comment .. inside a comment so not verilog-re-search
10362 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
10363 (verilog-re-search-forward-quick ";" nil t)
10365 (verilog-backward-syntactic-ws-quick)
10366 (backward-char 1) ; Moves to paren that closes argdecl's
10367 (when (looking-at ")")
10368 (verilog-insert "/*AUTOARG*/")))))))
10370 (defun verilog-inject-sense ()
10371 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
10373 (goto-char (point-min))
10374 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
10375 (let* ((start-pt (point))
10376 (modi (verilog-modi-current))
10377 (moddecls (verilog-modi-get-decls modi))
10381 (verilog-forward-sexp-ign-cmt 1)
10382 (backward-char 1) ;; End )
10383 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
10384 (setq pre-sigs (verilog-signals-from-signame
10385 (verilog-read-signals start-pt (point)))
10386 got-sigs (verilog-auto-sense-sigs moddecls nil))
10387 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
10388 (verilog-signals-not-in got-sigs pre-sigs)))
10389 (delete-region start-pt (point))
10390 (verilog-insert "/*AS*/")))))))
10392 (defun verilog-inject-inst ()
10393 "Inject AUTOINST into new code. See `verilog-inject-auto'."
10395 (goto-char (point-min))
10396 ;; It's hard to distinguish modules; we'll instead search for pins.
10397 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
10398 (verilog-backward-open-paren) ;; Inst start
10400 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
10402 (verilog-forward-close-paren)) ;; Parameters done
10405 (let ((indent-pt (+ (current-column)))
10406 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
10407 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
10408 (goto-char end-pt)) ;; Already there, continue search with next instance
10410 ;; Delete identical interconnect
10411 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
10412 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
10413 (delete-region (match-beginning 0) (match-end 0))
10414 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
10415 (while (or (looking-at "[ \t\n\f,]+")
10416 (looking-at "//[^\n]*"))
10417 (delete-region (match-beginning 0) (match-end 0))
10418 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
10419 (verilog-forward-close-paren)
10421 ;; Not verilog-re-search, as we don't want to strip comments
10422 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
10423 (delete-region (match-beginning 0) (match-end 0)))
10424 (verilog-insert "\n")
10425 (verilog-insert-indent "/*AUTOINST*/")))))))))
10431 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace)
10432 "Return nil if buffers B1 and B2 have same contents.
10433 Else, return point in B1 that first mismatches.
10434 If optional WHITESPACE true, ignore whitespace."
10436 (let* ((case-fold-search nil) ;; compare-buffer-substrings cares
10437 (p1 (with-current-buffer b1 (goto-char (point-min))))
10438 (p2 (with-current-buffer b2 (goto-char (point-min))))
10439 (maxp1 (with-current-buffer b1 (point-max)))
10440 (maxp2 (with-current-buffer b2 (point-max)))
10443 (while (not (and (eq p1 op1) (eq p2 op2)))
10444 ;; If both windows have whitespace optionally skip over it.
10446 ;; skip-syntax-* doesn't count \n
10447 (with-current-buffer b1
10449 (skip-chars-forward " \t\n\r\f\v")
10451 (with-current-buffer b2
10453 (skip-chars-forward " \t\n\r\f\v")
10454 (setq p2 (point))))
10455 (setq size (min (- maxp1 p1) (- maxp2 p2)))
10456 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
10457 b1 p1 (+ size p1)))
10458 (setq progress (if (zerop progress) size (1- (abs progress))))
10459 (setq op1 p1 op2 p2
10461 p2 (+ p2 progress)))
10463 (if (and (eq p1 maxp1) (eq p2 maxp2))
10466 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
10467 "View the differences between file F1 and buffer B2.
10468 This requires the external program `diff-command' to be in your `exec-path',
10469 and uses `diff-switches' in which you may want to have \"-u\" flag.
10470 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
10471 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
10472 ;; call `diff' as `diff' has different calling semantics on different
10473 ;; versions of Emacs.
10474 (if (not (file-exists-p f1))
10475 (message "Buffer %s has no associated file on disc" (buffer-name b2))
10476 (with-temp-buffer "*Verilog-Diff*"
10477 (let ((outbuf (current-buffer))
10478 (f2 (make-temp-file "vm-diff-auto-")))
10481 (with-current-buffer b2
10484 (write-region (point-min) (point-max) f2 nil 'nomessage)))
10485 (call-process diff-command nil outbuf t
10486 diff-switches ;; User may want -u in diff-switches
10487 (if whitespace "-b" "")
10489 ;; Print out results. Alternatively we could have call-processed
10490 ;; ourself, but this way we can reuse diff switches
10492 (with-current-buffer outbuf (message "%s" (buffer-string))))))
10494 (when (file-exists-p f2)
10495 (delete-file f2))))))
10497 (defun verilog-diff-report (b1 b2 diffpt)
10498 "Report differences detected with `verilog-diff-auto'.
10499 Differences are between buffers B1 and B2, starting at point
10500 DIFFPT. This function is called via `verilog-diff-function'."
10501 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
10502 (verilog-warn "%s:%d: Difference in AUTO expansion found"
10503 name1 (with-current-buffer b1
10504 (count-lines (point-min) diffpt)))
10505 (cond (noninteractive
10506 (verilog-diff-file-with-buffer name1 b2 t t))
10508 (ediff-buffers b1 b2)))))
10510 (defun verilog-diff-auto ()
10511 "Expand AUTOs in a temporary buffer and indicate any change.
10512 Whitespace differences are ignored to determine identicalness, but
10513 once a difference is detected, whitespace differences may be shown.
10515 To call this from the command line, see \\[verilog-batch-diff-auto].
10517 The action on differences is selected with
10518 `verilog-diff-function'. The default is `verilog-diff-report'
10519 which will report an error and run `ediff' in interactive mode,
10520 or `diff' in batch mode."
10522 (let ((b1 (current-buffer)) b2 diffpt
10523 (name1 (buffer-file-name))
10524 (newname "*Verilog-Diff*"))
10526 (when (get-buffer newname)
10527 (kill-buffer newname))
10528 (setq b2 (let (buffer-file-name) ;; Else clone is upset
10529 (clone-buffer newname)))
10530 (with-current-buffer b2
10531 ;; auto requires the filename, but can't have same filename in two
10532 ;; buffers; so override both b1 and b2's names
10533 (let ((buffer-file-name name1))
10536 (with-current-buffer b1 (setq buffer-file-name nil))
10538 (when (not verilog-auto-star-save)
10539 (verilog-delete-auto-star-implicit)))
10540 ;; Restore name if unwind
10541 (with-current-buffer b1 (setq buffer-file-name name1)))))
10543 (setq diffpt (verilog-diff-buffers-p b1 b2 t))
10544 (cond ((not diffpt)
10545 (unless noninteractive (message "AUTO expansion identical"))
10546 (kill-buffer newname)) ;; Nice to cleanup after oneself
10548 (funcall verilog-diff-function b1 b2 diffpt)))
10549 ;; Return result of compare
10557 (defun verilog-auto-save-check ()
10558 "On saving see if we need auto update."
10559 (cond ((not verilog-auto-save-policy)) ; disabled
10560 ((not (save-excursion
10562 (let ((case-fold-search nil))
10563 (goto-char (point-min))
10564 (re-search-forward "AUTO" nil t))))))
10565 ((eq verilog-auto-save-policy 'force)
10567 ((not (buffer-modified-p)))
10568 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10569 ((eq verilog-auto-save-policy 'detect)
10572 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10574 ;; Don't ask again if didn't update
10575 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10576 (when (not verilog-auto-star-save)
10577 (verilog-delete-auto-star-implicit))
10578 nil) ;; Always return nil -- we don't write the file ourselves
10580 (defun verilog-auto-read-locals ()
10581 "Return file local variable segment at bottom of file."
10583 (goto-char (point-max))
10584 (if (re-search-backward "Local Variables:" nil t)
10585 (buffer-substring-no-properties (point) (point-max))
10588 (defun verilog-auto-reeval-locals (&optional force)
10589 "Read file local variable segment at bottom of file if it has changed.
10590 If FORCE, always reread it."
10591 (let ((curlocal (verilog-auto-read-locals)))
10592 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10593 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10594 ;; Note this may cause this function to be recursively invoked,
10595 ;; because hack-local-variables may call (verilog-mode)
10596 ;; The above when statement will prevent it from recursing forever.
10597 (hack-local-variables)
10604 (defun verilog-auto-arg-ports (sigs message indent-pt)
10605 "Print a list of ports for an AUTOINST.
10606 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10608 (when verilog-auto-arg-sort
10609 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10611 (indent-to indent-pt)
10615 (indent-to indent-pt)
10617 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10619 (indent-to indent-pt))
10620 (t (insert space)))
10621 (insert (verilog-sig-name (car sigs)) ",")
10622 (setq sigs (cdr sigs)
10625 (defun verilog-auto-arg ()
10626 "Expand AUTOARG statements.
10627 Replace the argument declarations at the beginning of the
10628 module with ones automatically derived from input and output
10629 statements. This can be dangerous if the module is instantiated
10630 using position-based connections, so use only name-based when
10631 instantiating the resulting module. Long lines are split based
10632 on the `fill-column', see \\[set-fill-column].
10635 Concatenation and outputting partial buses is not supported.
10637 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10641 module ExampArg (/*AUTOARG*/);
10646 Typing \\[verilog-auto] will make this into:
10648 module ExampArg (/*AUTOARG*/
10658 The argument declarations may be printed in declaration order to best suit
10659 order based instantiations, or alphabetically, based on the
10660 `verilog-auto-arg-sort' variable.
10662 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10663 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10664 conservative guess on adding a comma for the first signal, if you have
10665 any ifdefs or complicated expressions before the AUTOARG you will need
10666 to choose the comma yourself.
10668 Avoid declaring ports manually, as it makes code harder to maintain."
10670 (let* ((modi (verilog-modi-current))
10671 (moddecls (verilog-modi-get-decls modi))
10672 (skip-pins (aref (verilog-read-arg-pins) 0)))
10673 (verilog-repair-open-comma)
10674 (verilog-auto-arg-ports (verilog-signals-not-in
10675 (verilog-decls-get-outputs moddecls)
10678 verilog-indent-level-declaration)
10679 (verilog-auto-arg-ports (verilog-signals-not-in
10680 (verilog-decls-get-inouts moddecls)
10683 verilog-indent-level-declaration)
10684 (verilog-auto-arg-ports (verilog-signals-not-in
10685 (verilog-decls-get-inputs moddecls)
10688 verilog-indent-level-declaration)
10689 (verilog-repair-close-comma)
10690 (unless (eq (char-before) ?/ )
10692 (indent-to verilog-indent-level-declaration))))
10694 (defun verilog-auto-assign-modport ()
10695 "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
10696 Take input/output/inout statements from the specified interface
10697 and modport and use to build assignments into the modport, for
10698 making verification modules that connect to UVM interfaces.
10700 The first parameter is the name of an interface.
10702 The second parameter is a regexp of modports to read from in
10705 The third parameter is the instance name to use to dot reference into.
10707 The optional fourth parameter is a regular expression, and only
10708 signals matching the regular expression will be included.
10712 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
10714 Inouts are not supported, as assignments must be unidirectional.
10716 If a signal is part of the interface header and in both a
10717 modport and the interface itself, it will not be listed. (As
10718 this would result in a syntax error when the connections are
10721 See the example in `verilog-auto-inout-modport'."
10723 (let* ((params (verilog-read-auto-params 3 4))
10724 (submod (nth 0 params))
10725 (modport-re (nth 1 params))
10726 (inst-name (nth 2 params))
10727 (regexp (nth 3 params))
10728 direction-re submodi) ;; direction argument not supported until requested
10729 ;; Lookup position, etc of co-module
10730 ;; Note this may raise an error
10731 (when (setq submodi (verilog-modi-lookup submod t))
10732 (let* ((indent-pt (current-indentation))
10733 (submoddecls (verilog-modi-get-decls submodi))
10734 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
10735 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
10736 (verilog-decls-get-vars submoddecls)
10737 (verilog-signals-not-in
10738 (verilog-decls-get-inputs submodportdecls)
10739 (verilog-decls-get-ports submoddecls))))
10740 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
10741 (verilog-decls-get-vars submoddecls)
10742 (verilog-signals-not-in
10743 (verilog-decls-get-outputs submodportdecls)
10744 (verilog-decls-get-ports submoddecls)))))
10746 (setq sig-list-i (verilog-signals-edit-wire-reg
10747 (verilog-signals-matching-dir-re
10748 (verilog-signals-matching-regexp sig-list-i regexp)
10749 "input" direction-re))
10750 sig-list-o (verilog-signals-edit-wire-reg
10751 (verilog-signals-matching-dir-re
10752 (verilog-signals-matching-regexp sig-list-o regexp)
10753 "output" direction-re)))
10754 (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
10755 (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
10756 (when (or sig-list-i sig-list-o)
10757 (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
10758 ;; Don't sort them so an upper AUTOINST will match the main module
10759 (let ((sigs sig-list-o))
10761 (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
10763 "." (verilog-sig-name (car sigs)) ";\n")
10764 (setq sigs (cdr sigs))))
10765 (let ((sigs sig-list-i))
10767 (verilog-insert-indent "assign " inst-name
10768 "." (verilog-sig-name (car sigs))
10769 " = " (verilog-sig-name (car sigs)) ";\n")
10770 (setq sigs (cdr sigs))))
10771 (verilog-insert-indent "// End of automatics\n")))))))
10773 (defun verilog-auto-inst-port-map (_port-st)
10776 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
10777 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10778 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
10779 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10780 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
10781 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
10782 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10783 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10785 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
10786 "Print out an instantiation connection for this PORT-ST.
10787 Insert to INDENT-PT, use template TPL-LIST.
10788 @ are instantiation numbers, replaced with TPL-NUM.
10789 @\"(expression @)\" are evaluated, with @ as a variable.
10790 If FOR-STAR add comment it is a .* expansion.
10791 If PAR-VALUES replace final strings with these parameter values."
10792 (let* ((port (verilog-sig-name port-st))
10793 (tpl-ass (or (assoc port (car tpl-list))
10794 (verilog-auto-inst-port-map port-st)))
10795 ;; vl-* are documented for user use
10796 (vl-name (verilog-sig-name port-st))
10797 (vl-width (verilog-sig-width port-st))
10798 (vl-modport (verilog-sig-modport port-st))
10799 (vl-mbits (if (verilog-sig-multidim port-st)
10800 (verilog-sig-multidim-string port-st) ""))
10801 (vl-bits (if (or verilog-auto-inst-vector
10802 (not (assoc port vector-skip-list))
10803 (not (equal (verilog-sig-bits port-st)
10804 (verilog-sig-bits (assoc port vector-skip-list)))))
10805 (or (verilog-sig-bits port-st) "")
10807 (case-fold-search nil)
10808 (check-values par-values)
10810 ;; Replace parameters in bit-width
10811 (when (and check-values
10812 (not (equal vl-bits "")))
10813 (while check-values
10814 (setq vl-bits (verilog-string-replace-matches
10815 (concat "\\<" (nth 0 (car check-values)) "\\>")
10816 (concat "(" (nth 1 (car check-values)) ")")
10818 vl-mbits (verilog-string-replace-matches
10819 (concat "\\<" (nth 0 (car check-values)) "\\>")
10820 (concat "(" (nth 1 (car check-values)) ")")
10822 check-values (cdr check-values)))
10823 (setq vl-bits (verilog-simplify-range-expression vl-bits)
10824 vl-mbits (verilog-simplify-range-expression vl-mbits)
10825 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
10826 ;; Default net value if not found
10827 (setq dflt-bits (if (and (verilog-sig-bits port-st)
10828 (or (verilog-sig-multidim port-st)
10829 (verilog-sig-memory port-st)))
10830 (concat "/*" vl-mbits vl-bits "*/")
10832 tpl-net (concat port
10833 (if vl-modport (concat "." vl-modport) "")
10836 (cond (tpl-ass ; Template of exact port name
10837 (setq tpl-net (nth 1 tpl-ass)))
10838 ((nth 1 tpl-list) ; Wildcards in template, search them
10839 (let ((wildcards (nth 1 tpl-list)))
10841 (when (string-match (nth 0 (car wildcards)) port)
10842 (setq tpl-ass (car wildcards) ; so allow @ parsing
10843 tpl-net (replace-match (nth 1 (car wildcards))
10845 (setq wildcards (cdr wildcards))))))
10846 ;; Parse Templated variable
10848 ;; Evaluate @"(lispcode)"
10849 (when (string-match "@\".*[^\\]\"" tpl-net)
10850 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
10853 (substring tpl-net 0 (match-beginning 0))
10855 (let* ((expr (match-string 1 tpl-net))
10858 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
10859 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
10860 (prin1 (eval (car (read-from-string expr)))
10861 (lambda (_ch) ())))))
10862 (if (numberp value) (setq value (number-to-string value)))
10864 (substring tpl-net (match-end 0))))))
10865 ;; Replace @ and [] magic variables in final output
10866 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
10867 (setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
10868 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
10870 (indent-to indent-pt)
10872 (unless (and verilog-auto-inst-dot-name
10873 (equal port tpl-net))
10874 (indent-to verilog-auto-inst-column)
10875 (insert "(" tpl-net ")"))
10878 (verilog-read-auto-template-hit tpl-ass)
10879 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10880 verilog-auto-inst-column))
10881 ;; verilog-insert requires the complete comment in one call - including the newline
10882 (cond ((equal verilog-auto-inst-template-numbers `lhs)
10883 (verilog-insert " // Templated"
10884 " LHS: " (nth 0 tpl-ass)
10886 (verilog-auto-inst-template-numbers
10887 (verilog-insert " // Templated"
10888 " T" (int-to-string (nth 2 tpl-ass))
10889 " L" (int-to-string (nth 3 tpl-ass))
10892 (verilog-insert " // Templated\n"))))
10894 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10895 verilog-auto-inst-column))
10896 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
10899 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
10900 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
10901 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
10903 (defun verilog-auto-inst-port-list (sig-list indent-pt tpl-list tpl-num for-star par-values)
10904 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
10905 (when verilog-auto-inst-sort
10906 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
10907 (mapc (lambda (port)
10908 (verilog-auto-inst-port port indent-pt
10909 tpl-list tpl-num for-star par-values))
10912 (defun verilog-auto-inst-first ()
10913 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
10914 ;; Do we need a trailing comma?
10915 ;; There maybe an ifdef or something similar before us. What a mess. Thus
10916 ;; to avoid trouble we only insert on preceding ) or *.
10917 ;; Insert first port on new line
10918 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
10920 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
10921 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
10925 (defun verilog-auto-star ()
10926 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
10928 If `verilog-auto-star-expand' is set, .* pins are treated if they were
10929 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
10930 will also ignore any .* that are not last in your pin list (this prevents
10931 it from deleting pins following the .* when it expands the AUTOINST.)
10933 On writing your file, unless `verilog-auto-star-save' is set, any
10934 non-templated expanded pins will be removed. You may do this at any time
10935 with \\[verilog-delete-auto-star-implicit].
10937 If you are converting a module to use .* for the first time, you may wish
10938 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
10940 See `verilog-auto-inst' for examples, templates, and more information."
10941 (when (verilog-auto-star-safe)
10942 (verilog-auto-inst)))
10944 (defun verilog-auto-inst ()
10945 "Expand AUTOINST statements, as part of \\[verilog-auto].
10946 Replace the pin connections to an instantiation or interface
10947 declaration with ones automatically derived from the module or
10948 interface header of the instantiated item.
10950 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
10951 and delete them before saving unless `verilog-auto-star-save' is set.
10952 See `verilog-auto-star' for more information.
10954 The pins are printed in declaration order or alphabetically,
10955 based on the `verilog-auto-inst-sort' variable.
10958 Module names must be resolvable to filenames by adding a
10959 `verilog-library-extensions', and being found in the same directory, or
10960 by changing the variable `verilog-library-flags' or
10961 `verilog-library-directories'. Macros `modname are translated through the
10962 vh-{name} Emacs variable, if that is not found, it just ignores the `.
10964 In templates you must have one signal per line, ending in a ), or ));,
10965 and have proper () nesting, including a final ); to end the template.
10967 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10969 SystemVerilog multidimensional input/output has only experimental support.
10971 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
10973 Parameters referenced by the instantiation will remain symbolic, unless
10974 `verilog-auto-inst-param-value' is set.
10976 Gate primitives (and/or) may have AUTOINST for the purpose of
10977 AUTOWIRE declarations, etc. Gates are the only case when
10978 position based connections are passed.
10980 The array part of arrayed instances are ignored; this may
10981 result in undesirable default AUTOINST connections; use a
10984 For example, first take the submodule InstModule.v:
10986 module InstModule (o,i);
10989 wire [31:0] o = {32{i}};
10992 This is then used in an upper level module:
10994 module ExampInst (o,i);
10997 InstModule instName
11001 Typing \\[verilog-auto] will make this into:
11003 module ExampInst (o,i);
11006 InstModule instName
11014 Where the list of inputs and outputs came from the inst module.
11018 Unless you are instantiating a module multiple times, or the module is
11019 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
11020 It just makes for unmaintainable code. To sanitize signal names, try
11021 vrename from URL `http://www.veripool.org'.
11023 When you need to violate this suggestion there are two ways to list
11024 exceptions, placing them before the AUTOINST, or using templates.
11026 Any ports defined before the /*AUTOINST*/ are not included in the list of
11027 automatics. This is similar to making a template as described below, but
11028 is restricted to simple connections just like you normally make. Also note
11029 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
11030 you have the appropriate // Input or // Output comment, and exactly the
11031 same line formatting as AUTOINST itself uses.
11033 InstModule instName
11035 .i (my_i_dont_mess_with_it),
11043 For multiple instantiations based upon a single template, create a
11044 commented out template:
11046 /* InstModule AUTO_TEMPLATE (
11051 Templates go ABOVE the instantiation(s). When an instantiation is
11052 expanded `verilog-mode' simply searches up for the closest template.
11053 Thus you can have multiple templates for the same module, just alternate
11054 between the template for an instantiation and the instantiation itself.
11055 (For backward compatibility if no template is found above, it
11056 will also look below, but do not use this behavior in new designs.)
11058 The module name must be the same as the name of the module in the
11059 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
11060 words and capitalized. Only signals that must be different for each
11061 instantiation need to be listed.
11063 Inside a template, a [] in a connection name (with nothing else
11064 inside the brackets) will be replaced by the same bus subscript
11065 as it is being connected to, or the [] will be removed if it is
11066 a single bit signal.
11068 Inside a template, a [][] in a connection name will behave
11069 similarly to a [] for scalar or single-dimensional connection;
11070 for a multidimensional connection it will print a comment
11071 similar to that printed when a template is not used. Generally
11072 it is a good idea to do this for all connections in a template,
11073 as then they will work for any width signal, and with AUTOWIRE.
11074 See PTL_BUS becoming PTL_BUSNEW below.
11076 Inside a template, a [] in a connection name (with nothing else inside
11077 the brackets) will be replaced by the same bus subscript as it is being
11078 connected to, or the [] will be removed if it is a single bit signal.
11079 Generally it is a good idea to do this for all connections in a template,
11080 as then they will work for any width signal, and with AUTOWIRE. See
11081 PTL_BUS becoming PTL_BUSNEW below.
11083 If you have a complicated template, set `verilog-auto-inst-template-numbers'
11084 to see which regexps are matching. Don't leave that mode set after
11085 debugging is completed though, it will result in lots of extra differences
11086 and merge conflicts.
11088 Setting `verilog-auto-template-warn-unused' will report errors
11089 if any template lines are unused.
11093 /* InstModule AUTO_TEMPLATE (
11094 .ptl_bus (ptl_busnew[]),
11097 InstModule ms2m (/*AUTOINST*/);
11099 Typing \\[verilog-auto] will make this into:
11101 InstModule ms2m (/*AUTOINST*/
11103 .NotInTemplate (NotInTemplate),
11104 .ptl_bus (ptl_busnew[3:0]), // Templated
11108 Multiple Module Templates:
11110 The same template lines can be applied to multiple modules with
11111 the syntax as follows:
11113 /* InstModuleA AUTO_TEMPLATE
11114 InstModuleB AUTO_TEMPLATE
11115 InstModuleC AUTO_TEMPLATE
11116 InstModuleD AUTO_TEMPLATE (
11117 .ptl_bus (ptl_busnew[]),
11121 Note there is only one AUTO_TEMPLATE opening parenthesis.
11125 It is common to instantiate a cell multiple times, so templates make it
11126 trivial to substitute part of the cell name into the connection name.
11128 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
11130 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
11134 If no regular expression is provided immediately after the AUTO_TEMPLATE
11135 keyword, then the @ character in any connection names will be replaced
11136 with the instantiation number; the first digits found in the cell's
11137 instantiation name.
11139 If a regular expression is provided, the @ character will be replaced
11140 with the first \(\) grouping that matches against the cell name. Using a
11141 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
11142 regexp is provided. If you use multiple layers of parenthesis,
11143 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
11144 characters after test and before _, whereas
11145 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
11150 /* InstModule AUTO_TEMPLATE (
11151 .ptl_mapvalidx (ptl_mapvalid[@]),
11152 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11155 InstModule ms2m (/*AUTOINST*/);
11157 Typing \\[verilog-auto] will make this into:
11159 InstModule ms2m (/*AUTOINST*/
11161 .ptl_mapvalidx (ptl_mapvalid[2]),
11162 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11164 Note the @ character was replaced with the 2 from \"ms2m\".
11166 Alternatively, using a regular expression for @:
11168 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11169 .ptl_mapvalidx (@_ptl_mapvalid),
11170 .ptl_mapvalidp1x (ptl_mapvalid_@),
11173 InstModule ms2_FOO (/*AUTOINST*/);
11174 InstModule ms2_BAR (/*AUTOINST*/);
11176 Typing \\[verilog-auto] will make this into:
11178 InstModule ms2_FOO (/*AUTOINST*/
11180 .ptl_mapvalidx (FOO_ptl_mapvalid),
11181 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11182 InstModule ms2_BAR (/*AUTOINST*/
11184 .ptl_mapvalidx (BAR_ptl_mapvalid),
11185 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11190 A template entry of the form
11192 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11194 will apply an Emacs style regular expression search for any port beginning
11195 in pci_req followed by numbers and ending in _l and connecting that to
11196 the pci_req_jtag_[] net, with the bus subscript coming from what matches
11197 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
11199 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
11200 does the same thing. (Note a @ in the connection/replacement text is
11201 completely different -- still use \\1 there!) Thus this is the same as
11202 the above template:
11204 .pci_req@_l (pci_req_jtag_[\\1]),
11206 Here's another example to remove the _l, useful when naming conventions
11207 specify _ alone to mean active low. Note the use of [] to keep the bus
11210 .\\(.*\\)_l (\\1_[]),
11214 First any regular expression template is expanded.
11216 If the syntax @\"( ... )\" is found in a connection, the expression in
11217 quotes will be evaluated as a Lisp expression, with @ replaced by the
11218 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
11219 4 into the brackets. Quote all double-quotes inside the expression with
11220 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
11221 regexp template backslash the backslash quote (\\\\\"...\\\\\").
11223 There are special variables defined that are useful in these
11226 vl-name Name portion of the input/output port.
11227 vl-bits Bus bits portion of the input/output port ('[2:0]').
11228 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
11229 vl-width Width of the input/output port ('3' for [2:0]).
11230 May be a (...) expression if bits isn't a constant.
11231 vl-dir Direction of the pin input/output/inout/interface.
11232 vl-modport The modport, if an interface with a modport.
11233 vl-cell-type Module name/type of the cell ('InstModule').
11234 vl-cell-name Instance name of the cell ('instName').
11236 Normal Lisp variables may be used in expressions. See
11237 `verilog-read-defines' which can set vh-{definename} variables for use
11238 here. Also, any comments of the form:
11240 /*AUTO_LISP(setq foo 1)*/
11242 will evaluate any Lisp expression inside the parenthesis between the
11243 beginning of the buffer and the point of the AUTOINST. This allows
11244 functions to be defined or variables to be changed between instantiations.
11245 (See also `verilog-auto-insert-lisp' if you want the output from your
11246 lisp function to be inserted.)
11248 Note that when using lisp expressions errors may occur when @ is not a
11249 number; you may need to use the standard Emacs Lisp functions
11250 `number-to-string' and `string-to-number'.
11252 After the evaluation is completed, @ substitution and [] substitution
11255 For more information see the \\[verilog-faq] and forums at URL
11256 `http://www.veripool.org'."
11259 (let* ((pt (point))
11260 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
11261 (indent-pt (save-excursion (verilog-backward-open-paren)
11262 (1+ (current-column))))
11263 (verilog-auto-inst-column (max verilog-auto-inst-column
11264 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11265 (modi (verilog-modi-current))
11266 (moddecls (verilog-modi-get-decls modi))
11267 (vector-skip-list (unless verilog-auto-inst-vector
11268 (verilog-decls-get-signals moddecls)))
11269 submod submodi submoddecls
11270 inst skip-pins tpl-list tpl-num did-first par-values)
11272 ;; Find module name that is instantiated
11273 (setq submod (verilog-read-inst-module)
11274 inst (verilog-read-inst-name)
11275 vl-cell-type submod
11277 skip-pins (aref (verilog-read-inst-pins) 0))
11279 ;; Parse any AUTO_LISP() before here
11280 (verilog-read-auto-lisp (point-min) pt)
11282 ;; Read parameters (after AUTO_LISP)
11283 (setq par-values (and verilog-auto-inst-param-value
11284 (verilog-read-inst-param-value)))
11286 ;; Lookup position, etc of submodule
11287 ;; Note this may raise an error
11288 (when (and (not (member submod verilog-gate-keywords))
11289 (setq submodi (verilog-modi-lookup submod t)))
11290 (setq submoddecls (verilog-modi-get-decls submodi))
11291 ;; If there's a number in the instantiation, it may be an argument to the
11292 ;; automatic variable instantiation program.
11293 (let* ((tpl-info (verilog-read-auto-template submod))
11294 (tpl-regexp (aref tpl-info 0)))
11295 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11296 (match-string 1 inst)
11298 tpl-list (aref tpl-info 1)))
11299 ;; Find submodule's signals and dump
11300 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
11301 (verilog-signals-not-in
11302 (verilog-decls-get-vars submoddecls)
11304 (vl-dir "interfaced"))
11305 (when (and sig-list
11306 verilog-auto-inst-interfaced-ports)
11307 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11308 ;; Note these are searched for in verilog-read-sub-decls.
11309 (verilog-insert-indent "// Interfaced\n")
11310 (verilog-auto-inst-port-list sig-list indent-pt
11311 tpl-list tpl-num for-star par-values)))
11312 (let ((sig-list (verilog-signals-not-in
11313 (verilog-decls-get-interfaces submoddecls)
11315 (vl-dir "interface"))
11317 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11318 ;; Note these are searched for in verilog-read-sub-decls.
11319 (verilog-insert-indent "// Interfaces\n")
11320 (verilog-auto-inst-port-list sig-list indent-pt
11321 tpl-list tpl-num for-star par-values)))
11322 (let ((sig-list (verilog-signals-not-in
11323 (verilog-decls-get-outputs submoddecls)
11327 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11328 (verilog-insert-indent "// Outputs\n")
11329 (verilog-auto-inst-port-list sig-list indent-pt
11330 tpl-list tpl-num for-star par-values)))
11331 (let ((sig-list (verilog-signals-not-in
11332 (verilog-decls-get-inouts submoddecls)
11336 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11337 (verilog-insert-indent "// Inouts\n")
11338 (verilog-auto-inst-port-list sig-list indent-pt
11339 tpl-list tpl-num for-star par-values)))
11340 (let ((sig-list (verilog-signals-not-in
11341 (verilog-decls-get-inputs submoddecls)
11345 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11346 (verilog-insert-indent "// Inputs\n")
11347 (verilog-auto-inst-port-list sig-list indent-pt
11348 tpl-list tpl-num for-star par-values)))
11352 (re-search-backward "," pt t)
11355 (search-forward "\n") ;; Added by inst-port
11357 (if (search-forward ")" nil t) ;; From user, moved up a line
11359 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
11360 (delete-char -1)))))))))
11362 (defun verilog-auto-inst-param ()
11363 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
11364 Replace the parameter connections to an instantiation with ones
11365 automatically derived from the module header of the instantiated netlist.
11367 See \\[verilog-auto-inst] for limitations, and templates to customize the
11370 For example, first take the submodule InstModule.v:
11372 module InstModule (o,i);
11376 This is then used in an upper level module:
11378 module ExampInst (o,i);
11380 InstModule #(/*AUTOINSTPARAM*/)
11381 instName (/*AUTOINST*/);
11384 Typing \\[verilog-auto] will make this into:
11386 module ExampInst (o,i);
11389 InstModule #(/*AUTOINSTPARAM*/
11392 instName (/*AUTOINST*/);
11395 Where the list of parameter connections come from the inst module.
11399 You can customize the parameter connections using AUTO_TEMPLATEs,
11400 just as you would with \\[verilog-auto-inst]."
11403 (let* ((pt (point))
11404 (indent-pt (save-excursion (verilog-backward-open-paren)
11405 (1+ (current-column))))
11406 (verilog-auto-inst-column (max verilog-auto-inst-column
11407 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11408 (modi (verilog-modi-current))
11409 (moddecls (verilog-modi-get-decls modi))
11410 (vector-skip-list (unless verilog-auto-inst-vector
11411 (verilog-decls-get-signals moddecls)))
11412 submod submodi submoddecls
11413 inst skip-pins tpl-list tpl-num did-first)
11414 ;; Find module name that is instantiated
11415 (setq submod (save-excursion
11416 ;; Get to the point where AUTOINST normally is to read the module
11417 (verilog-re-search-forward-quick "[(;]" nil nil)
11418 (verilog-read-inst-module))
11419 inst (save-excursion
11420 ;; Get to the point where AUTOINST normally is to read the module
11421 (verilog-re-search-forward-quick "[(;]" nil nil)
11422 (verilog-read-inst-name))
11423 vl-cell-type submod
11425 skip-pins (aref (verilog-read-inst-pins) 0))
11427 ;; Parse any AUTO_LISP() before here
11428 (verilog-read-auto-lisp (point-min) pt)
11430 ;; Lookup position, etc of submodule
11431 ;; Note this may raise an error
11432 (when (setq submodi (verilog-modi-lookup submod t))
11433 (setq submoddecls (verilog-modi-get-decls submodi))
11434 ;; If there's a number in the instantiation, it may be an argument to the
11435 ;; automatic variable instantiation program.
11436 (let* ((tpl-info (verilog-read-auto-template submod))
11437 (tpl-regexp (aref tpl-info 0)))
11438 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11439 (match-string 1 inst)
11441 tpl-list (aref tpl-info 1)))
11442 ;; Find submodule's signals and dump
11443 (let ((sig-list (verilog-signals-not-in
11444 (verilog-decls-get-gparams submoddecls)
11446 (vl-dir "parameter"))
11448 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11449 ;; Note these are searched for in verilog-read-sub-decls.
11450 (verilog-insert-indent "// Parameters\n")
11451 (verilog-auto-inst-port-list sig-list indent-pt
11452 tpl-list tpl-num nil nil)))
11456 (re-search-backward "," pt t)
11459 (search-forward "\n") ;; Added by inst-port
11461 (if (search-forward ")" nil t) ;; From user, moved up a line
11462 (delete-char -1)))))))))
11464 (defun verilog-auto-reg ()
11465 "Expand AUTOREG statements, as part of \\[verilog-auto].
11466 Make reg statements for any output that isn't already declared,
11467 and isn't a wire output from a block. `verilog-auto-wire-type'
11468 may be used to change the datatype of the declarations.
11471 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11473 This does NOT work on memories, declare those yourself.
11477 module ExampReg (o,i);
11484 Typing \\[verilog-auto] will make this into:
11486 module ExampReg (o,i);
11490 // Beginning of automatic regs (for this module's undeclared outputs)
11492 // End of automatics
11496 ;; Point must be at insertion point.
11497 (let* ((indent-pt (current-indentation))
11498 (modi (verilog-modi-current))
11499 (moddecls (verilog-modi-get-decls modi))
11500 (modsubdecls (verilog-modi-get-sub-decls modi))
11501 (sig-list (verilog-signals-not-in
11502 (verilog-decls-get-outputs moddecls)
11503 (append (verilog-signals-with ;; ignore typed signals
11505 (verilog-decls-get-outputs moddecls))
11506 (verilog-decls-get-vars moddecls)
11507 (verilog-decls-get-assigns moddecls)
11508 (verilog-decls-get-consts moddecls)
11509 (verilog-decls-get-gparams moddecls)
11510 (verilog-subdecls-get-interfaced modsubdecls)
11511 (verilog-subdecls-get-outputs modsubdecls)
11512 (verilog-subdecls-get-inouts modsubdecls)))))
11514 (verilog-forward-or-insert-line)
11515 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
11516 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11517 (verilog-insert-indent "// End of automatics\n")))))
11519 (defun verilog-auto-reg-input ()
11520 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
11521 Make reg statements instantiation inputs that aren't already declared.
11522 This is useful for making a top level shell for testing the module that is
11523 to be instantiated.
11526 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
11528 This does NOT work on memories, declare those yourself.
11530 An example (see `verilog-auto-inst' for what else is going on here):
11532 module ExampRegInput (o,i);
11536 InstModule instName
11540 Typing \\[verilog-auto] will make this into:
11542 module ExampRegInput (o,i);
11546 // Beginning of automatic reg inputs (for undeclared ...
11547 reg [31:0] iv; // From inst of inst.v
11548 // End of automatics
11549 InstModule instName
11557 ;; Point must be at insertion point.
11558 (let* ((indent-pt (current-indentation))
11559 (modi (verilog-modi-current))
11560 (moddecls (verilog-modi-get-decls modi))
11561 (modsubdecls (verilog-modi-get-sub-decls modi))
11562 (sig-list (verilog-signals-combine-bus
11563 (verilog-signals-not-in
11564 (append (verilog-subdecls-get-inputs modsubdecls)
11565 (verilog-subdecls-get-inouts modsubdecls))
11566 (append (verilog-decls-get-signals moddecls)
11567 (verilog-decls-get-assigns moddecls))))))
11569 (verilog-forward-or-insert-line)
11570 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
11571 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11572 (verilog-insert-indent "// End of automatics\n")))))
11574 (defun verilog-auto-logic-setup ()
11575 "Prepare variables due to AUTOLOGIC."
11576 (unless verilog-auto-wire-type
11577 (set (make-local-variable 'verilog-auto-wire-type)
11580 (defun verilog-auto-logic ()
11581 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
11582 Make wire statements using the SystemVerilog logic keyword.
11583 This is currently equivalent to:
11587 with the below at the bottom of the file
11589 // Local Variables:
11590 // verilog-auto-logic-type:\"logic\"
11593 In the future AUTOLOGIC may declare additional identifiers,
11594 while AUTOWIRE will not."
11596 (verilog-auto-logic-setup)
11597 (verilog-auto-wire)))
11599 (defun verilog-auto-wire ()
11600 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
11601 Make wire statements for instantiations outputs that aren't
11602 already declared. `verilog-auto-wire-type' may be used to change
11603 the datatype of the declarations.
11606 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
11607 and all buses must have widths, such as those from AUTOINST, or using []
11610 This does NOT work on memories or SystemVerilog .name connections,
11611 declare those yourself.
11613 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
11614 determine how to bus together. This occurs when you have ports with
11615 non-numeric or non-sequential bus subscripts. If Verilog mode
11616 mis-guessed, you'll have to declare them yourself.
11618 An example (see `verilog-auto-inst' for what else is going on here):
11620 module ExampWire (o,i);
11624 InstModule instName
11628 Typing \\[verilog-auto] will make this into:
11630 module ExampWire (o,i);
11634 // Beginning of automatic wires
11635 wire [31:0] ov; // From inst of inst.v
11636 // End of automatics
11637 InstModule instName
11646 ;; Point must be at insertion point.
11647 (let* ((indent-pt (current-indentation))
11648 (modi (verilog-modi-current))
11649 (moddecls (verilog-modi-get-decls modi))
11650 (modsubdecls (verilog-modi-get-sub-decls modi))
11651 (sig-list (verilog-signals-combine-bus
11652 (verilog-signals-not-in
11653 (append (verilog-subdecls-get-outputs modsubdecls)
11654 (verilog-subdecls-get-inouts modsubdecls))
11655 (verilog-decls-get-signals moddecls)))))
11657 (verilog-forward-or-insert-line)
11658 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11659 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11660 (verilog-insert-indent "// End of automatics\n")
11661 ;; We used to optionally call verilog-pretty-declarations and
11662 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11663 ;; plus makes everyone's module change. Finally those call
11664 ;; syntax-ppss which is broken when change hooks are disabled.
11667 (defun verilog-auto-output ()
11668 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11669 Make output statements for any output signal from an /*AUTOINST*/ that
11670 isn't an input to another AUTOINST. This is useful for modules which
11671 only instantiate other modules.
11674 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11676 If placed inside the parenthesis of a module declaration, it creates
11677 Verilog 2001 style, else uses Verilog 1995 style.
11679 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11680 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11682 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11684 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11686 An example (see `verilog-auto-inst' for what else is going on here):
11688 module ExampOutput (ov,i);
11691 InstModule instName
11695 Typing \\[verilog-auto] will make this into:
11697 module ExampOutput (ov,i);
11700 // Beginning of automatic outputs (from unused autoinst outputs)
11701 output [31:0] ov; // From inst of inst.v
11702 // End of automatics
11703 InstModule instName
11711 You may also provide an optional regular expression, in which case only
11712 signals matching the regular expression will be included. For example the
11713 same expansion will result from only extracting outputs starting with ov:
11715 /*AUTOOUTPUT(\"^ov\")*/"
11717 ;; Point must be at insertion point.
11718 (let* ((indent-pt (current-indentation))
11719 (params (verilog-read-auto-params 0 1))
11720 (regexp (nth 0 params))
11721 (v2k (verilog-in-paren-quick))
11722 (modi (verilog-modi-current))
11723 (moddecls (verilog-modi-get-decls modi))
11724 (modsubdecls (verilog-modi-get-sub-decls modi))
11725 (sig-list (verilog-signals-not-in
11726 (verilog-subdecls-get-outputs modsubdecls)
11727 (append (verilog-decls-get-outputs moddecls)
11728 (verilog-decls-get-inouts moddecls)
11729 (verilog-decls-get-inputs moddecls)
11730 (verilog-subdecls-get-inputs modsubdecls)
11731 (verilog-subdecls-get-inouts modsubdecls)))))
11733 (setq sig-list (verilog-signals-matching-regexp
11735 (setq sig-list (verilog-signals-not-matching-regexp
11736 sig-list verilog-auto-output-ignore-regexp))
11737 (verilog-forward-or-insert-line)
11738 (when v2k (verilog-repair-open-comma))
11740 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
11741 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11742 (verilog-insert-indent "// End of automatics\n"))
11743 (when v2k (verilog-repair-close-comma)))))
11745 (defun verilog-auto-output-every ()
11746 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
11747 Make output statements for any signals that aren't primary inputs or
11748 outputs already. This makes every signal in the design an output. This is
11749 useful to get Synopsys to preserve every signal in the design, since it
11750 won't optimize away the outputs.
11754 module ExampOutputEvery (o,i,tempa,tempb);
11757 /*AUTOOUTPUTEVERY*/
11759 wire tempb = tempa;
11763 Typing \\[verilog-auto] will make this into:
11765 module ExampOutputEvery (o,i,tempa,tempb);
11768 /*AUTOOUTPUTEVERY*/
11769 // Beginning of automatic outputs (every signal)
11772 // End of automatics
11774 wire tempb = tempa;
11778 ;;Point must be at insertion point
11779 (let* ((indent-pt (current-indentation))
11780 (v2k (verilog-in-paren-quick))
11781 (modi (verilog-modi-current))
11782 (moddecls (verilog-modi-get-decls modi))
11783 (sig-list (verilog-signals-combine-bus
11784 (verilog-signals-not-in
11785 (verilog-decls-get-signals moddecls)
11786 (verilog-decls-get-ports moddecls)))))
11787 (verilog-forward-or-insert-line)
11788 (when v2k (verilog-repair-open-comma))
11790 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
11791 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11792 (verilog-insert-indent "// End of automatics\n"))
11793 (when v2k (verilog-repair-close-comma)))))
11795 (defun verilog-auto-input ()
11796 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
11797 Make input statements for any input signal into an /*AUTOINST*/ that
11798 isn't declared elsewhere inside the module. This is useful for modules which
11799 only instantiate other modules.
11802 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11804 If placed inside the parenthesis of a module declaration, it creates
11805 Verilog 2001 style, else uses Verilog 1995 style.
11807 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11808 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11810 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11812 Signals matching `verilog-auto-input-ignore-regexp' are not included.
11814 An example (see `verilog-auto-inst' for what else is going on here):
11816 module ExampInput (ov,i);
11819 InstModule instName
11823 Typing \\[verilog-auto] will make this into:
11825 module ExampInput (ov,i);
11828 // Beginning of automatic inputs (from unused autoinst inputs)
11829 input i; // From inst of inst.v
11830 // End of automatics
11831 InstModule instName
11839 You may also provide an optional regular expression, in which case only
11840 signals matching the regular expression will be included. For example the
11841 same expansion will result from only extracting inputs starting with i:
11843 /*AUTOINPUT(\"^i\")*/"
11845 (let* ((indent-pt (current-indentation))
11846 (params (verilog-read-auto-params 0 1))
11847 (regexp (nth 0 params))
11848 (v2k (verilog-in-paren-quick))
11849 (modi (verilog-modi-current))
11850 (moddecls (verilog-modi-get-decls modi))
11851 (modsubdecls (verilog-modi-get-sub-decls modi))
11852 (sig-list (verilog-signals-not-in
11853 (verilog-subdecls-get-inputs modsubdecls)
11854 (append (verilog-decls-get-inputs moddecls)
11855 (verilog-decls-get-inouts moddecls)
11856 (verilog-decls-get-outputs moddecls)
11857 (verilog-decls-get-vars moddecls)
11858 (verilog-decls-get-consts moddecls)
11859 (verilog-decls-get-gparams moddecls)
11860 (verilog-subdecls-get-interfaced modsubdecls)
11861 (verilog-subdecls-get-outputs modsubdecls)
11862 (verilog-subdecls-get-inouts modsubdecls)))))
11864 (setq sig-list (verilog-signals-matching-regexp
11866 (setq sig-list (verilog-signals-not-matching-regexp
11867 sig-list verilog-auto-input-ignore-regexp))
11868 (verilog-forward-or-insert-line)
11869 (when v2k (verilog-repair-open-comma))
11871 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
11872 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
11873 (verilog-insert-indent "// End of automatics\n"))
11874 (when v2k (verilog-repair-close-comma)))))
11876 (defun verilog-auto-inout ()
11877 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
11878 Make inout statements for any inout signal in an /*AUTOINST*/ that
11879 isn't declared elsewhere inside the module.
11882 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11884 If placed inside the parenthesis of a module declaration, it creates
11885 Verilog 2001 style, else uses Verilog 1995 style.
11887 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11888 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11890 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11892 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
11894 An example (see `verilog-auto-inst' for what else is going on here):
11896 module ExampInout (ov,i);
11899 InstModule instName
11903 Typing \\[verilog-auto] will make this into:
11905 module ExampInout (ov,i);
11908 // Beginning of automatic inouts (from unused autoinst inouts)
11909 inout [31:0] ov; // From inst of inst.v
11910 // End of automatics
11911 InstModule instName
11919 You may also provide an optional regular expression, in which case only
11920 signals matching the regular expression will be included. For example the
11921 same expansion will result from only extracting inouts starting with i:
11923 /*AUTOINOUT(\"^i\")*/"
11925 ;; Point must be at insertion point.
11926 (let* ((indent-pt (current-indentation))
11927 (params (verilog-read-auto-params 0 1))
11928 (regexp (nth 0 params))
11929 (v2k (verilog-in-paren-quick))
11930 (modi (verilog-modi-current))
11931 (moddecls (verilog-modi-get-decls modi))
11932 (modsubdecls (verilog-modi-get-sub-decls modi))
11933 (sig-list (verilog-signals-not-in
11934 (verilog-subdecls-get-inouts modsubdecls)
11935 (append (verilog-decls-get-outputs moddecls)
11936 (verilog-decls-get-inouts moddecls)
11937 (verilog-decls-get-inputs moddecls)
11938 (verilog-subdecls-get-inputs modsubdecls)
11939 (verilog-subdecls-get-outputs modsubdecls)))))
11941 (setq sig-list (verilog-signals-matching-regexp
11943 (setq sig-list (verilog-signals-not-matching-regexp
11944 sig-list verilog-auto-inout-ignore-regexp))
11945 (verilog-forward-or-insert-line)
11946 (when v2k (verilog-repair-open-comma))
11948 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
11949 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
11950 (verilog-insert-indent "// End of automatics\n"))
11951 (when v2k (verilog-repair-close-comma)))))
11953 (defun verilog-auto-inout-module (&optional complement all-in)
11954 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
11955 Take input/output/inout statements from the specified module and insert
11956 into the current module. This is useful for making null templates and
11957 shell modules which need to have identical I/O with another module.
11958 Any I/O which are already defined in this module will not be redefined.
11959 For the complement of this function, see `verilog-auto-inout-comp',
11960 and to make monitors with all inputs, see `verilog-auto-inout-in'.
11963 If placed inside the parenthesis of a module declaration, it creates
11964 Verilog 2001 style, else uses Verilog 1995 style.
11966 Concatenation and outputting partial buses is not supported.
11968 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11970 Signals are not inserted in the same order as in the original module,
11971 though they will appear to be in the same order to an AUTOINST
11972 instantiating either module.
11974 Signals declared as \"output reg\" or \"output wire\" etc will
11975 lose the wire/reg declaration so that shell modules may
11976 generate those outputs differently. However, \"output logic\"
11981 module ExampShell (/*AUTOARG*/);
11982 /*AUTOINOUTMODULE(\"ExampMain\")*/
11985 module ExampMain (i,o,io);
11991 Typing \\[verilog-auto] will make this into:
11993 module ExampShell (/*AUTOARG*/i,o,io);
11994 /*AUTOINOUTMODULE(\"ExampMain\")*/
11995 // Beginning of automatic in/out/inouts (from specific module)
11999 // End of automatics
12002 You may also provide an optional regular expression, in which case only
12003 signals matching the regular expression will be included. For example the
12004 same expansion will result from only extracting signals starting with i:
12006 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12008 You may also provide an optional second regular expression, in
12009 which case only signals which have that pin direction and data
12010 type will be included. This matches against everything before
12011 the signal name in the declaration, for example against
12012 \"input\" (single bit), \"output logic\" (direction and type) or
12013 \"output [1:0]\" (direction and implicit type). You also
12014 probably want to skip spaces in your regexp.
12016 For example, the below will result in matching the output \"o\"
12017 against the previous example's module:
12019 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/"
12021 (let* ((params (verilog-read-auto-params 1 3))
12022 (submod (nth 0 params))
12023 (regexp (nth 1 params))
12024 (direction-re (nth 2 params))
12026 ;; Lookup position, etc of co-module
12027 ;; Note this may raise an error
12028 (when (setq submodi (verilog-modi-lookup submod t))
12029 (let* ((indent-pt (current-indentation))
12030 (v2k (verilog-in-paren-quick))
12031 (modi (verilog-modi-current))
12032 (moddecls (verilog-modi-get-decls modi))
12033 (submoddecls (verilog-modi-get-decls submodi))
12034 (sig-list-i (verilog-signals-not-in
12037 (verilog-decls-get-inputs submoddecls)
12038 (verilog-decls-get-inouts submoddecls)
12039 (verilog-decls-get-outputs submoddecls)))
12041 (verilog-decls-get-outputs submoddecls))
12042 (t (verilog-decls-get-inputs submoddecls)))
12043 (append (verilog-decls-get-inputs moddecls))))
12044 (sig-list-o (verilog-signals-not-in
12047 (verilog-decls-get-inputs submoddecls))
12048 (t (verilog-decls-get-outputs submoddecls)))
12049 (append (verilog-decls-get-outputs moddecls))))
12050 (sig-list-io (verilog-signals-not-in
12052 (t (verilog-decls-get-inouts submoddecls)))
12053 (append (verilog-decls-get-inouts moddecls))))
12054 (sig-list-if (verilog-signals-not-in
12055 (verilog-decls-get-interfaces submoddecls)
12056 (append (verilog-decls-get-interfaces moddecls)))))
12058 (setq sig-list-i (verilog-signals-edit-wire-reg
12059 (verilog-signals-matching-dir-re
12060 (verilog-signals-matching-regexp sig-list-i regexp)
12061 "input" direction-re))
12062 sig-list-o (verilog-signals-edit-wire-reg
12063 (verilog-signals-matching-dir-re
12064 (verilog-signals-matching-regexp sig-list-o regexp)
12065 "output" direction-re))
12066 sig-list-io (verilog-signals-edit-wire-reg
12067 (verilog-signals-matching-dir-re
12068 (verilog-signals-matching-regexp sig-list-io regexp)
12069 "inout" direction-re))
12070 sig-list-if (verilog-signals-matching-dir-re
12071 (verilog-signals-matching-regexp sig-list-if regexp)
12072 "interface" direction-re))
12073 (when v2k (verilog-repair-open-comma))
12074 (when (or sig-list-i sig-list-o sig-list-io)
12075 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
12076 ;; Don't sort them so an upper AUTOINST will match the main module
12077 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12078 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12079 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12080 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
12081 (verilog-insert-indent "// End of automatics\n"))
12082 (when v2k (verilog-repair-close-comma)))))))
12084 (defun verilog-auto-inout-comp ()
12085 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
12086 Take input/output/inout statements from the specified module and
12087 insert the inverse into the current module (inputs become outputs
12088 and vice-versa.) This is useful for making test and stimulus
12089 modules which need to have complementing I/O with another module.
12090 Any I/O which are already defined in this module will not be
12091 redefined. For the complement of this function, see
12092 `verilog-auto-inout-module'.
12095 If placed inside the parenthesis of a module declaration, it creates
12096 Verilog 2001 style, else uses Verilog 1995 style.
12098 Concatenation and outputting partial buses is not supported.
12100 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12102 Signals are not inserted in the same order as in the original module,
12103 though they will appear to be in the same order to an AUTOINST
12104 instantiating either module.
12108 module ExampShell (/*AUTOARG*/);
12109 /*AUTOINOUTCOMP(\"ExampMain\")*/
12112 module ExampMain (i,o,io);
12118 Typing \\[verilog-auto] will make this into:
12120 module ExampShell (/*AUTOARG*/i,o,io);
12121 /*AUTOINOUTCOMP(\"ExampMain\")*/
12122 // Beginning of automatic in/out/inouts (from specific module)
12126 // End of automatics
12129 You may also provide an optional regular expression, in which case only
12130 signals matching the regular expression will be included. For example the
12131 same expansion will result from only extracting signals starting with i:
12133 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
12134 (verilog-auto-inout-module t nil))
12136 (defun verilog-auto-inout-in ()
12137 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
12138 Take input/output/inout statements from the specified module and
12139 insert them as all inputs into the current module. This is
12140 useful for making monitor modules which need to see all signals
12141 as inputs based on another module. Any I/O which are already
12142 defined in this module will not be redefined. See also
12143 `verilog-auto-inout-module'.
12146 If placed inside the parenthesis of a module declaration, it creates
12147 Verilog 2001 style, else uses Verilog 1995 style.
12149 Concatenation and outputting partial buses is not supported.
12151 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12153 Signals are not inserted in the same order as in the original module,
12154 though they will appear to be in the same order to an AUTOINST
12155 instantiating either module.
12159 module ExampShell (/*AUTOARG*/);
12160 /*AUTOINOUTIN(\"ExampMain\")*/
12163 module ExampMain (i,o,io);
12169 Typing \\[verilog-auto] will make this into:
12171 module ExampShell (/*AUTOARG*/i,o,io);
12172 /*AUTOINOUTIN(\"ExampMain\")*/
12173 // Beginning of automatic in/out/inouts (from specific module)
12177 // End of automatics
12180 You may also provide an optional regular expression, in which case only
12181 signals matching the regular expression will be included. For example the
12182 same expansion will result from only extracting signals starting with i:
12184 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
12185 (verilog-auto-inout-module nil t))
12187 (defun verilog-auto-inout-param ()
12188 "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
12189 Take input/output/inout statements from the specified module and insert
12190 into the current module. This is useful for making null templates and
12191 shell modules which need to have identical I/O with another module.
12192 Any I/O which are already defined in this module will not be redefined.
12193 For the complement of this function, see `verilog-auto-inout-comp',
12194 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12197 If placed inside the parenthesis of a module declaration, it creates
12198 Verilog 2001 style, else uses Verilog 1995 style.
12200 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12202 Parameters are inserted in the same order as in the original module.
12204 Parameters do not have values, which is SystemVerilog 2009 syntax.
12208 module ExampShell ();
12209 /*AUTOINOUTPARAM(\"ExampMain\")*/
12212 module ExampMain ();
12213 parameter PARAM = 22;
12216 Typing \\[verilog-auto] will make this into:
12218 module ExampShell (/*AUTOARG*/i,o,io);
12219 /*AUTOINOUTPARAM(\"ExampMain\")*/
12220 // Beginning of automatic parameters (from specific module)
12222 // End of automatics
12225 You may also provide an optional regular expression, in which case only
12226 parameters matching the regular expression will be included. For example the
12227 same expansion will result from only extracting parameters starting with i:
12229 /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
12231 (let* ((params (verilog-read-auto-params 1 2))
12232 (submod (nth 0 params))
12233 (regexp (nth 1 params))
12235 ;; Lookup position, etc of co-module
12236 ;; Note this may raise an error
12237 (when (setq submodi (verilog-modi-lookup submod t))
12238 (let* ((indent-pt (current-indentation))
12239 (v2k (verilog-in-paren-quick))
12240 (modi (verilog-modi-current))
12241 (moddecls (verilog-modi-get-decls modi))
12242 (submoddecls (verilog-modi-get-decls submodi))
12243 (sig-list-p (verilog-signals-not-in
12244 (verilog-decls-get-gparams submoddecls)
12245 (append (verilog-decls-get-gparams moddecls)))))
12247 (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
12248 (when v2k (verilog-repair-open-comma))
12250 (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
12251 ;; Don't sort them so an upper AUTOINST will match the main module
12252 (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
12253 (verilog-insert-indent "// End of automatics\n"))
12254 (when v2k (verilog-repair-close-comma)))))))
12256 (defun verilog-auto-inout-modport ()
12257 "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
12258 Take input/output/inout statements from the specified interface
12259 and modport and insert into the current module. This is useful
12260 for making verification modules that connect to UVM interfaces.
12262 The first parameter is the name of an interface.
12264 The second parameter is a regexp of modports to read from in
12267 The optional third parameter is a regular expression, and only
12268 signals matching the regular expression will be included.
12271 If placed inside the parenthesis of a module declaration, it creates
12272 Verilog 2001 style, else uses Verilog 1995 style.
12274 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
12276 As with other autos, any inputs/outputs declared in the module
12277 will suppress the AUTO from redeclaring an inputs/outputs by
12283 ( input logic clk );
12285 logic [7:0] req_dat;
12286 clocking mon_clkblk @(posedge clk);
12290 modport mp(clocking mon_clkblk);
12295 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12296 // Beginning of automatic in/out/inouts (from modport)
12297 input [7:0] req_dat,
12299 // End of automatics
12301 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12304 Typing \\[verilog-auto] will make this into:
12309 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12310 // Beginning of automatic in/out/inouts (from modport)
12313 // End of automatics
12316 If the modport is part of a UVM monitor/driver class, this
12317 creates a wrapper module that may be used to instantiate the
12318 driver/monitor using AUTOINST in the testbench."
12320 (let* ((params (verilog-read-auto-params 2 3))
12321 (submod (nth 0 params))
12322 (modport-re (nth 1 params))
12323 (regexp (nth 2 params))
12324 direction-re submodi) ;; direction argument not supported until requested
12325 ;; Lookup position, etc of co-module
12326 ;; Note this may raise an error
12327 (when (setq submodi (verilog-modi-lookup submod t))
12328 (let* ((indent-pt (current-indentation))
12329 (v2k (verilog-in-paren-quick))
12330 (modi (verilog-modi-current))
12331 (moddecls (verilog-modi-get-decls modi))
12332 (submoddecls (verilog-modi-get-decls submodi))
12333 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
12334 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
12335 (verilog-decls-get-vars submoddecls)
12336 (verilog-signals-not-in
12337 (verilog-decls-get-inputs submodportdecls)
12338 (append (verilog-decls-get-ports submoddecls)
12339 (verilog-decls-get-ports moddecls)))))
12340 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
12341 (verilog-decls-get-vars submoddecls)
12342 (verilog-signals-not-in
12343 (verilog-decls-get-outputs submodportdecls)
12344 (append (verilog-decls-get-ports submoddecls)
12345 (verilog-decls-get-ports moddecls)))))
12346 (sig-list-io (verilog-signals-in ;; Decls doesn't have data types, must resolve
12347 (verilog-decls-get-vars submoddecls)
12348 (verilog-signals-not-in
12349 (verilog-decls-get-inouts submodportdecls)
12350 (append (verilog-decls-get-ports submoddecls)
12351 (verilog-decls-get-ports moddecls))))))
12353 (setq sig-list-i (verilog-signals-edit-wire-reg
12354 (verilog-signals-matching-dir-re
12355 (verilog-signals-matching-regexp sig-list-i regexp)
12356 "input" direction-re))
12357 sig-list-o (verilog-signals-edit-wire-reg
12358 (verilog-signals-matching-dir-re
12359 (verilog-signals-matching-regexp sig-list-o regexp)
12360 "output" direction-re))
12361 sig-list-io (verilog-signals-edit-wire-reg
12362 (verilog-signals-matching-dir-re
12363 (verilog-signals-matching-regexp sig-list-io regexp)
12364 "inout" direction-re)))
12365 (when v2k (verilog-repair-open-comma))
12366 (when (or sig-list-i sig-list-o sig-list-io)
12367 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
12368 ;; Don't sort them so an upper AUTOINST will match the main module
12369 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12370 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12371 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12372 (verilog-insert-indent "// End of automatics\n"))
12373 (when v2k (verilog-repair-close-comma)))))))
12375 (defun verilog-auto-insert-lisp ()
12376 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
12377 The Lisp code provided is called, and the Lisp code calls
12378 `insert` to insert text into the current file beginning on the
12379 line after the AUTOINSERTLISP.
12381 See also AUTO_LISP, which takes a Lisp expression and evaluates
12382 it during `verilog-auto-inst' but does not insert any text.
12386 module ExampInsertLisp;
12387 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
12390 // For this example we declare the function in the
12391 // module's file itself. Often you'd define it instead
12392 // in a site-start.el or init file.
12396 (defun my-verilog-insert-hello (who)
12397 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
12401 Typing \\[verilog-auto] will call my-verilog-insert-hello and
12402 expand the above into:
12404 // Beginning of automatic insert lisp
12405 initial $write(\"hello world\");
12406 // End of automatics
12408 You can also call an external program and insert the returned
12411 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
12412 // Beginning of automatic insert lisp
12414 // End of automatics"
12416 ;; Point is at end of /*AUTO...*/
12417 (let* ((indent-pt (current-indentation))
12418 (cmd-end-pt (save-excursion (search-backward ")")
12420 (point))) ;; Closing paren
12421 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
12422 (backward-sexp 1) ;; Inside comment
12423 (point))) ;; Beginning paren
12424 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
12425 (verilog-forward-or-insert-line)
12426 ;; Some commands don't move point (like insert-file) so we always
12427 ;; add the begin/end comments, then delete it if not needed
12428 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
12429 (verilog-insert-indent "// End of automatics\n")
12433 (setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
12434 (verilog-delete-empty-auto-pair))))
12436 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
12437 "Return list of signals for current AUTOSENSE block."
12438 (let* ((sigss (verilog-read-always-signals))
12439 (sig-list (verilog-signals-not-params
12440 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
12441 (append (and (not verilog-auto-sense-include-inputs)
12442 (verilog-alw-get-outputs-delayed sigss))
12443 (and (not verilog-auto-sense-include-inputs)
12444 (verilog-alw-get-outputs-immediate sigss))
12445 (verilog-alw-get-temps sigss)
12446 (verilog-decls-get-consts moddecls)
12447 (verilog-decls-get-gparams moddecls)
12451 (defun verilog-auto-sense ()
12452 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
12453 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
12454 with one automatically derived from all inputs declared in the always
12455 statement. Signals that are generated within the same always block are NOT
12456 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
12457 Long lines are split based on the `fill-column', see \\[set-fill-column].
12460 Verilog does not allow memories (multidimensional arrays) in sensitivity
12461 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
12464 AUTOSENSE cannot always determine if a `define is a constant or a signal
12465 (it could be in an include file for example). If a `define or other signal
12466 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
12467 declaration anywhere in the module (parenthesis are required):
12469 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
12471 Better yet, use a parameter, which will be understood to be constant
12475 If AUTOSENSE makes a mistake, please report it. (First try putting
12476 a begin/end after your always!) As a workaround, if a signal that
12477 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
12478 If a signal should be in the sensitivity list wasn't, placing it before
12479 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
12480 autos are updated (or added if it occurs there already).
12484 always @ (/*AS*/) begin
12485 /* AUTO_CONSTANT (`constant) */
12486 outin = ina | inb | `constant;
12490 Typing \\[verilog-auto] will make this into:
12492 always @ (/*AS*/ina or inb) begin
12493 /* AUTO_CONSTANT (`constant) */
12494 outin = ina | inb | `constant;
12498 Note in Verilog 2001, you can often get the same result from the new @*
12499 operator. (This was added to the language in part due to AUTOSENSE!)
12502 outin = ina | inb | `constant;
12507 (let* ((start-pt (save-excursion
12508 (verilog-re-search-backward-quick "(" nil t)
12510 (indent-pt (save-excursion
12511 (or (and (goto-char start-pt) (1+ (current-column)))
12512 (current-indentation))))
12513 (modi (verilog-modi-current))
12514 (moddecls (verilog-modi-get-decls modi))
12515 (sig-memories (verilog-signals-memory
12516 (verilog-decls-get-vars moddecls)))
12517 sig-list not-first presense-sigs)
12518 ;; Read signals in always, eliminate outputs from sense list
12519 (setq presense-sigs (verilog-signals-from-signame
12521 (verilog-read-signals start-pt (point)))))
12522 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
12524 (let ((tlen (length sig-list)))
12525 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
12526 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
12527 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
12528 (save-excursion (goto-char (point))
12529 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12530 (verilog-re-search-backward-quick "\\s-" start-pt t)
12531 (while (looking-at "\\s-`endif")
12532 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12533 (verilog-re-search-backward-quick "\\s-" start-pt t))
12534 (not (looking-at "\\s-or\\b"))))
12535 (setq not-first t))
12536 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12538 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
12540 (indent-to indent-pt)
12541 (if not-first (insert "or ")))
12542 (not-first (insert " or ")))
12543 (insert (verilog-sig-name (car sig-list)))
12544 (setq sig-list (cdr sig-list)
12547 (defun verilog-auto-reset ()
12548 "Expand AUTORESET statements, as part of \\[verilog-auto].
12549 Replace the /*AUTORESET*/ comment with code to initialize all
12550 registers set elsewhere in the always block.
12553 AUTORESET will not clear memories.
12555 AUTORESET uses <= if the signal has a <= assignment in the block,
12558 If <= is used, all = assigned variables are ignored if
12559 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
12562 /*AUTORESET*/ presumes that any signals mentioned between the previous
12563 begin/case/if statement and the AUTORESET comment are being reset manually
12564 and should not be automatically reset. This includes omitting any signals
12565 used on the right hand side of assignments.
12567 By default, AUTORESET will include the width of the signal in the
12568 autos, SystemVerilog designs may want to change this. To control
12569 this behavior, see `verilog-auto-reset-widths'. In some cases
12570 AUTORESET must use a '0 assignment and it will print NOWIDTH; use
12571 `verilog-auto-reset-widths' unbased to prevent this.
12573 AUTORESET ties signals to deasserted, which is presumed to be zero.
12574 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12577 AUTORESET may try to reset arrays or structures that cannot be
12578 reset by a simple assignment, resulting in compile errors. This
12579 is a feature to be taken as a hint that you need to reset these
12580 signals manually (or put them into a \"`ifdef NEVER signal<=`0;
12581 `endif\" so Verilog-Mode ignores them.)
12585 always @(posedge clk or negedge reset_l) begin
12586 if (!reset_l) begin
12597 Typing \\[verilog-auto] will make this into:
12599 always @(posedge core_clk or negedge reset_l) begin
12600 if (!reset_l) begin
12603 // Beginning of autoreset for uninitialized flops
12605 b = 0; // if `verilog-auto-reset-blocking-in-non' true
12606 // End of automatics
12618 (let* ((indent-pt (current-indentation))
12619 (modi (verilog-modi-current))
12620 (moddecls (verilog-modi-get-decls modi))
12621 (all-list (verilog-decls-get-signals moddecls))
12622 sigss sig-list dly-list prereset-sigs)
12623 ;; Read signals in always, eliminate outputs from reset list
12624 (setq prereset-sigs (verilog-signals-from-signame
12626 (verilog-read-signals
12628 (verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
12632 (verilog-re-search-backward-quick "@" nil t)
12633 (setq sigss (verilog-read-always-signals)))
12634 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
12635 (setq sig-list (verilog-signals-not-in (append
12636 (verilog-alw-get-outputs-delayed sigss)
12637 (when (or (not (verilog-alw-get-uses-delayed sigss))
12638 verilog-auto-reset-blocking-in-non)
12639 (verilog-alw-get-outputs-immediate sigss)))
12641 (verilog-alw-get-temps sigss)
12643 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12646 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
12648 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
12650 (indent-to indent-pt)
12651 (insert (verilog-sig-name sig)
12652 (if (assoc (verilog-sig-name sig) dly-list)
12653 (concat " <= " verilog-assignment-delay)
12655 (verilog-sig-tieoff sig)
12657 (setq sig-list (cdr sig-list))))
12658 (verilog-insert-indent "// End of automatics")))))
12660 (defun verilog-auto-tieoff ()
12661 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
12662 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
12663 signals to deasserted.
12665 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
12666 input/output list as another module, but no internals. Specifically, it
12667 finds all outputs in the module, and if that input is not otherwise declared
12668 as a register or wire, creates a tieoff.
12670 AUTORESET ties signals to deasserted, which is presumed to be zero.
12671 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12674 You can add signals you do not want included in AUTOTIEOFF with
12675 `verilog-auto-tieoff-ignore-regexp'.
12677 `verilog-auto-wire-type' may be used to change the datatype of
12680 `verilog-auto-reset-widths' may be used to change how the tieoff
12681 value's width is generated.
12683 An example of making a stub for another module:
12685 module ExampStub (/*AUTOINST*/);
12686 /*AUTOINOUTPARAM(\"Foo\")*/
12687 /*AUTOINOUTMODULE(\"Foo\")*/
12689 // verilator lint_off UNUSED
12690 wire _unused_ok = &{1'b0,
12693 // verilator lint_on UNUSED
12696 Typing \\[verilog-auto] will make this into:
12698 module ExampStub (/*AUTOINST*/...);
12699 /*AUTOINOUTPARAM(\"Foo\")*/
12700 /*AUTOINOUTMODULE(\"Foo\")*/
12701 // Beginning of autotieoff
12703 // End of automatics
12706 // Beginning of autotieoff
12707 wire [2:0] foo = 3'b0;
12708 // End of automatics
12714 (let* ((indent-pt (current-indentation))
12715 (modi (verilog-modi-current))
12716 (moddecls (verilog-modi-get-decls modi))
12717 (modsubdecls (verilog-modi-get-sub-decls modi))
12718 (sig-list (verilog-signals-not-in
12719 (verilog-decls-get-outputs moddecls)
12720 (append (verilog-decls-get-vars moddecls)
12721 (verilog-decls-get-assigns moddecls)
12722 (verilog-decls-get-consts moddecls)
12723 (verilog-decls-get-gparams moddecls)
12724 (verilog-subdecls-get-interfaced modsubdecls)
12725 (verilog-subdecls-get-outputs modsubdecls)
12726 (verilog-subdecls-get-inouts modsubdecls)))))
12727 (setq sig-list (verilog-signals-not-matching-regexp
12728 sig-list verilog-auto-tieoff-ignore-regexp))
12730 (verilog-forward-or-insert-line)
12731 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
12732 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12733 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
12735 (let ((sig (car sig-list)))
12736 (cond ((equal verilog-auto-tieoff-declaration "assign")
12737 (indent-to indent-pt)
12738 (insert "assign " (verilog-sig-name sig)))
12740 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
12741 (indent-to (max 48 (+ indent-pt 40)))
12742 (insert "= " (verilog-sig-tieoff sig)
12744 (setq sig-list (cdr sig-list))))
12745 (verilog-insert-indent "// End of automatics\n")))))
12747 (defun verilog-auto-undef ()
12748 "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
12749 Take any `defines since the last AUTOUNDEF in the current file
12750 and create `undefs for them. This is used to insure that
12751 file-local defines do not pollute the global `define name space.
12754 AUTOUNDEF presumes any identifier following `define is the
12755 name of a define. Any `ifdefs are ignored.
12757 AUTOUNDEF suppresses creating an `undef for any define that was
12758 `undefed before the AUTOUNDEF. This may be used to work around
12759 the ignoring of `ifdefs as shown below.
12768 `undef M_BAZ // Emacs will see this and not `undef M_BAZ
12773 Typing \\[verilog-auto] will make this into:
12777 // Beginning of automatic undefs
12780 // End of automatics
12782 You may also provide an optional regular expression, in which case only
12783 defines the regular expression will be undefed."
12785 (let* ((params (verilog-read-auto-params 0 1))
12786 (regexp (nth 0 params))
12787 (indent-pt (current-indentation))
12791 ;; Scan from start of file, or last AUTOUNDEF
12792 (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
12793 (goto-char (point-min)))
12794 (while (verilog-re-search-forward-quick
12795 "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
12796 (cond ((equal (match-string-no-properties 1) "define")
12797 (setq def (match-string-no-properties 2))
12798 (when (and (or (not regexp)
12799 (string-match regexp def))
12800 (not (member def defs))) ;; delete-dups not in 21.1
12801 (setq defs (cons def defs))))
12803 (setq defs (delete (match-string-no-properties 2) defs))))))
12805 (setq defs (sort defs 'string<))
12807 (verilog-forward-or-insert-line)
12808 (verilog-insert-indent "// Beginning of automatic undefs\n")
12810 (verilog-insert-indent "`undef " (car defs) "\n")
12811 (setq defs (cdr defs)))
12812 (verilog-insert-indent "// End of automatics\n")))))
12814 (defun verilog-auto-unused ()
12815 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
12816 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
12817 input and inout signals.
12819 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
12820 input/output list as another module, but no internals. Specifically, it
12821 finds all inputs and inouts in the module, and if that input is not otherwise
12822 used, adds it to a comma separated list.
12824 The comma separated list is intended to be used to create a _unused_ok
12825 signal. Using the exact name \"_unused_ok\" for name of the temporary
12826 signal is recommended as it will insure maximum forward compatibility, it
12827 also makes lint warnings easy to understand; ignore any unused warnings
12828 with \"unused\" in the signal name.
12830 To reduce simulation time, the _unused_ok signal should be forced to a
12831 constant to prevent wiggling. The easiest thing to do is use a
12832 reduction-and with 1'b0 as shown.
12834 This way all unused signals are in one place, making it convenient to add
12835 your tool's specific pragmas around the assignment to disable any unused
12838 You can add signals you do not want included in AUTOUNUSED with
12839 `verilog-auto-unused-ignore-regexp'.
12841 An example of making a stub for another module:
12843 module ExampStub (/*AUTOINST*/);
12844 /*AUTOINOUTPARAM(\"Examp\")*/
12845 /*AUTOINOUTMODULE(\"Examp\")*/
12847 // verilator lint_off UNUSED
12848 wire _unused_ok = &{1'b0,
12851 // verilator lint_on UNUSED
12854 Typing \\[verilog-auto] will make this into:
12857 // verilator lint_off UNUSED
12858 wire _unused_ok = &{1'b0,
12860 // Beginning of automatics
12864 // End of automatics
12866 // verilator lint_on UNUSED
12871 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
12872 (modi (verilog-modi-current))
12873 (moddecls (verilog-modi-get-decls modi))
12874 (modsubdecls (verilog-modi-get-sub-decls modi))
12875 (sig-list (verilog-signals-not-in
12876 (append (verilog-decls-get-inputs moddecls)
12877 (verilog-decls-get-inouts moddecls))
12878 (append (verilog-subdecls-get-inputs modsubdecls)
12879 (verilog-subdecls-get-inouts modsubdecls)))))
12880 (setq sig-list (verilog-signals-not-matching-regexp
12881 sig-list verilog-auto-unused-ignore-regexp))
12883 (verilog-forward-or-insert-line)
12884 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
12885 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12887 (let ((sig (car sig-list)))
12888 (indent-to indent-pt)
12889 (insert (verilog-sig-name sig) ",\n")
12890 (setq sig-list (cdr sig-list))))
12891 (verilog-insert-indent "// End of automatics\n")))))
12893 (defun verilog-enum-ascii (signm elim-regexp)
12894 "Convert an enum name SIGNM to an ascii string for insertion.
12895 Remove user provided prefix ELIM-REGEXP."
12896 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
12897 (let ((case-fold-search t))
12898 ;; All upper becomes all lower for readability
12899 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
12901 (defun verilog-auto-ascii-enum ()
12902 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
12903 Create a register to contain the ASCII decode of an enumerated signal type.
12904 This will allow trace viewers to show the ASCII name of states.
12906 First, parameters are built into an enumeration using the synopsys enum
12907 comment. The comment must be between the keyword and the symbol.
12908 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
12910 Next, registers which that enum applies to are also tagged with the same
12913 Finally, an AUTOASCIIENUM command is used.
12915 The first parameter is the name of the signal to be decoded.
12917 The second parameter is the name to store the ASCII code into. For the
12918 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
12919 a signal that is just for simulation, and the magic characters _ascii
12920 tell viewers like Dinotrace to display in ASCII format.
12922 The third optional parameter is a string which will be removed
12923 from the state names. It defaults to \"\" which removes nothing.
12925 The fourth optional parameter is \"onehot\" to force one-hot
12926 decoding. If unspecified, if and only if the first parameter
12927 width is 2^(number of states in enum) and does NOT match the
12928 width of the enum, the signal is assumed to be a one-hot
12929 decode. Otherwise, it's a normal encoded state vector.
12931 `verilog-auto-wire-type' may be used to change the datatype of
12934 \"auto enum\" may be used in place of \"synopsys enum\".
12938 //== State enumeration
12939 parameter [2:0] // synopsys enum state_info
12943 //== State variables
12944 reg [2:0] /* synopsys enum state_info */
12945 state_r; /* synopsys state_vector state_r */
12946 reg [2:0] /* synopsys enum state_info */
12949 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12951 Typing \\[verilog-auto] will make this into:
12953 ... same front matter ...
12955 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12956 // Beginning of automatic ASCII enum decoding
12957 reg [39:0] state_ascii_r; // Decode of state_r
12958 always @(state_r) begin
12960 SM_IDLE: state_ascii_r = \"idle \";
12961 SM_SEND: state_ascii_r = \"send \";
12962 SM_WAIT1: state_ascii_r = \"wait1\";
12963 default: state_ascii_r = \"%Erro\";
12966 // End of automatics"
12968 (let* ((params (verilog-read-auto-params 2 4))
12969 (undecode-name (nth 0 params))
12970 (ascii-name (nth 1 params))
12971 (elim-regexp (and (nth 2 params)
12972 (not (equal (nth 2 params) ""))
12974 (one-hot-flag (nth 3 params))
12976 (indent-pt (current-indentation))
12977 (modi (verilog-modi-current))
12978 (moddecls (verilog-modi-get-decls modi))
12980 (sig-list-consts (append (verilog-decls-get-consts moddecls)
12981 (verilog-decls-get-gparams moddecls)))
12982 (sig-list-all (verilog-decls-get-iovars moddecls))
12984 (undecode-sig (or (assoc undecode-name sig-list-all)
12985 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
12986 (undecode-enum (or (verilog-sig-enum undecode-sig)
12987 (error "%s: Signal %s does not have an enum tag" (verilog-point-text) undecode-name)))
12989 (enum-sigs (verilog-signals-not-in
12990 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
12991 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
12995 (string-match "onehot" (or one-hot-flag ""))
12996 (and ;; width(enum) != width(sig)
12997 (or (not (verilog-sig-bits (car enum-sigs)))
12998 (not (equal (verilog-sig-width (car enum-sigs))
12999 (verilog-sig-width undecode-sig))))
13000 ;; count(enums) == width(sig)
13001 (equal (number-to-string (length enum-sigs))
13002 (verilog-sig-width undecode-sig)))))
13006 ;; Find number of ascii chars needed
13007 (let ((tmp-sigs enum-sigs))
13009 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
13010 ascii-chars (max ascii-chars (length (verilog-enum-ascii
13011 (verilog-sig-name (car tmp-sigs))
13013 tmp-sigs (cdr tmp-sigs))))
13015 (verilog-forward-or-insert-line)
13016 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
13017 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
13018 (concat "Decode of " undecode-name) nil nil))))
13019 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
13021 (verilog-insert-indent "always @(" undecode-name ") begin\n")
13022 (setq indent-pt (+ indent-pt verilog-indent-level))
13023 (verilog-insert-indent "case ({" undecode-name "})\n")
13024 (setq indent-pt (+ indent-pt verilog-case-indent))
13026 (let ((tmp-sigs enum-sigs)
13027 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
13028 (+ (if one-hot 9 1) (max 8 enum-chars))
13029 ascii-name ascii-chars))
13030 (errname (substring "%Error" 0 (min 6 ascii-chars))))
13032 (verilog-insert-indent
13035 (concat (if one-hot "(")
13036 ;; Use enum-sigs length as that's numeric
13037 ;; verilog-sig-width undecode-sig might not be.
13038 (if one-hot (number-to-string (length enum-sigs)))
13039 ;; We use a shift instead of var[index]
13040 ;; so that a non-one hot value will show as error.
13041 (if one-hot "'b1<<")
13042 (verilog-sig-name (car tmp-sigs))
13043 (if one-hot ")") ":")
13044 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
13046 (setq tmp-sigs (cdr tmp-sigs)))
13047 (verilog-insert-indent (format chrfmt "default:" errname)))
13049 (setq indent-pt (- indent-pt verilog-case-indent))
13050 (verilog-insert-indent "endcase\n")
13051 (setq indent-pt (- indent-pt verilog-indent-level))
13052 (verilog-insert-indent "end\n"
13053 "// End of automatics\n"))))
13055 (defun verilog-auto-templated-rel ()
13056 "Replace Templated relative line numbers with absolute line numbers.
13057 Internal use only. This hacks around the line numbers in AUTOINST Templates
13058 being different from the final output's line numbering."
13059 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
13060 ;; Find line number each template is on
13061 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
13062 (goto-char (point-min))
13063 (while (not (eobp))
13064 (when (looking-at ".*AUTO_TEMPLATE")
13065 (setq templateno (1+ templateno))
13066 (setq template-line (cons buf-line template-line)))
13067 (setq buf-line (1+ buf-line))
13069 (setq template-line (nreverse template-line))
13070 ;; Replace T# L# with absolute line number
13071 (goto-char (point-min))
13072 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
13074 (concat " Templated "
13075 (int-to-string (+ (nth (string-to-number (match-string 1))
13077 (string-to-number (match-string 2)))))
13080 (defun verilog-auto-template-lint ()
13081 "Check AUTO_TEMPLATEs for unused lines.
13082 Enable with `verilog-auto-template-warn-unused'."
13083 (let ((name1 (or (buffer-file-name) (buffer-name))))
13085 (goto-char (point-min))
13086 (while (re-search-forward
13087 "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
13088 (let* ((tpl-info (verilog-read-auto-template-middle))
13089 (tpl-list (aref tpl-info 1))
13090 (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
13093 (setq tpl-ass (car tlines)
13094 tlines (cdr tlines))
13096 (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ;; Not supported, no warning
13097 (not verilog-auto-template-hits)
13098 (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
13099 verilog-auto-template-hits))
13100 (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
13102 (+ (elt tpl-ass 3) ;; Template line number
13103 (count-lines (point-min) (point)))
13104 (elt tpl-ass 0) (elt tpl-ass 1))
13112 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
13113 "Expand AUTO statements.
13114 Look for any /*AUTO...*/ commands in the code, as used in
13115 instantiations or argument headers. Update the list of signals
13116 following the /*AUTO...*/ command.
13118 Use \\[verilog-delete-auto] to remove the AUTOs.
13120 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
13122 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
13124 Use \\[verilog-faq] for a pointer to frequently asked questions.
13126 For new users, we recommend setting `verilog-case-fold' to nil
13127 and `verilog-auto-arg-sort' to t.
13129 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13130 called before and after this function, respectively.
13133 module ModuleName (/*AUTOARG*/);
13138 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13140 You can also update the AUTOs from the shell using:
13141 emacs --batch <filenames.v> -f verilog-batch-auto
13142 Or fix indentation with:
13143 emacs --batch <filenames.v> -f verilog-batch-indent
13144 Likewise, you can delete or inject AUTOs with:
13145 emacs --batch <filenames.v> -f verilog-batch-delete-auto
13146 emacs --batch <filenames.v> -f verilog-batch-inject-auto
13147 Or check if AUTOs have the same expansion
13148 emacs --batch <filenames.v> -f verilog-batch-diff-auto
13150 Using \\[describe-function], see also:
13151 `verilog-auto-arg' for AUTOARG module instantiations
13152 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
13153 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
13154 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
13155 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
13156 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
13157 `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
13158 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
13159 `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
13160 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
13161 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
13162 `verilog-auto-inst' for AUTOINST instantiation pins
13163 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
13164 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
13165 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
13166 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
13167 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
13168 `verilog-auto-reg' for AUTOREG registers
13169 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
13170 `verilog-auto-reset' for AUTORESET flop resets
13171 `verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
13172 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
13173 `verilog-auto-undef' for AUTOUNDEF `undef of local `defines
13174 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
13175 `verilog-auto-wire' for AUTOWIRE instantiation wires
13177 `verilog-read-defines' for reading `define values
13178 `verilog-read-includes' for reading `includes
13180 If you have bugs with these autos, please file an issue at
13181 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
13182 Wilson Snyder (wsnyder@wsnyder.org)."
13184 (unless noninteractive (message "Updating AUTOs..."))
13185 (if (fboundp 'dinotrace-unannotate-all)
13186 (dinotrace-unannotate-all))
13187 (verilog-save-font-mods
13188 (let ((oldbuf (if (not (buffer-modified-p))
13190 (case-fold-search verilog-case-fold)
13191 ;; Cache directories; we don't write new files, so can't change
13192 (verilog-dir-cache-preserving t)
13193 ;; Cache current module
13194 (verilog-modi-cache-current-enable t)
13195 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
13196 verilog-modi-cache-current)
13198 ;; Disable change hooks for speed
13199 ;; This let can't be part of above let; must restore
13200 ;; after-change-functions before font-lock resumes
13201 (verilog-save-no-change-functions
13202 (verilog-save-scan-cache
13204 ;; Wipe cache; otherwise if we AUTOed a block above this one,
13205 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
13206 (setq verilog-modi-cache-list nil)
13208 (setq verilog-auto-template-hits nil)
13209 ;; If we're not in verilog-mode, change syntax table so parsing works right
13210 (unless (eq major-mode `verilog-mode) (verilog-mode))
13211 ;; Allow user to customize
13212 (verilog-run-hooks 'verilog-before-auto-hook)
13213 ;; Try to save the user from needing to revert-file to reread file local-variables
13214 (verilog-auto-reeval-locals)
13215 (verilog-read-auto-lisp-present)
13216 (verilog-read-auto-lisp (point-min) (point-max))
13217 (verilog-getopt-flags)
13218 ;; From here on out, we can cache anything we read from disk
13219 (verilog-preserve-dir-cache
13220 ;; These two may seem obvious to do always, but on large includes it can be way too slow
13221 (when verilog-auto-read-includes
13222 (verilog-read-includes)
13223 (verilog-read-defines nil nil t))
13224 ;; Setup variables due to SystemVerilog expansion
13225 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
13226 ;; This particular ordering is important
13227 ;; INST: Lower modules correct, no internal dependencies, FIRST
13228 (verilog-preserve-modi-cache
13229 ;; Clear existing autos else we'll be screwed by existing ones
13230 (verilog-delete-auto)
13231 ;; Injection if appropriate
13233 (verilog-inject-inst)
13234 (verilog-inject-sense)
13235 (verilog-inject-arg))
13237 ;; Do user inserts first, so their code can insert AUTOs
13238 ;; We may provide an AUTOINSERTLISPLAST if another cleanup pass is needed
13239 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
13240 'verilog-auto-insert-lisp)
13241 ;; Expand instances before need the signals the instances input/output
13242 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
13243 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
13244 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
13245 ;; Doesn't matter when done, but combine it with a common changer
13246 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
13247 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
13248 ;; Must be done before autoin/out as creates a reg
13249 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
13251 ;; first in/outs from other files
13252 (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
13253 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
13254 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
13255 (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
13256 (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
13257 ;; next in/outs which need previous sucked inputs first
13258 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
13259 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
13260 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
13261 ;; Then tie off those in/outs
13262 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
13263 ;; These can be anywhere after AUTOINSERTLISP
13264 (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
13265 ;; Wires/regs must be after inputs/outputs
13266 (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
13267 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
13268 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
13269 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
13270 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
13271 ;; outputevery needs AUTOOUTPUTs done first
13272 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
13273 ;; After we've created all new variables
13274 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
13275 ;; Must be after all inputs outputs are generated
13276 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
13277 ;; Fix line numbers (comments only)
13278 (when verilog-auto-inst-template-numbers
13279 (verilog-auto-templated-rel))
13280 (when verilog-auto-template-warn-unused
13281 (verilog-auto-template-lint))))
13283 (verilog-run-hooks 'verilog-auto-hook)
13285 (when verilog-auto-delete-trailing-whitespace
13286 (verilog-delete-trailing-whitespace))
13288 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
13290 ;; If end result is same as when started, clear modified flag
13291 (cond ((and oldbuf (equal oldbuf (buffer-string)))
13292 (set-buffer-modified-p nil)
13293 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
13294 (t (unless noninteractive (message "Updating AUTOs...done"))))
13295 ;; End of after-change protection
13298 ;; Currently handled in verilog-save-font-mods
13303 ;; Skeleton based code insertion
13305 (defvar verilog-template-map
13306 (let ((map (make-sparse-keymap)))
13307 (define-key map "a" 'verilog-sk-always)
13308 (define-key map "b" 'verilog-sk-begin)
13309 (define-key map "c" 'verilog-sk-case)
13310 (define-key map "f" 'verilog-sk-for)
13311 (define-key map "g" 'verilog-sk-generate)
13312 (define-key map "h" 'verilog-sk-header)
13313 (define-key map "i" 'verilog-sk-initial)
13314 (define-key map "j" 'verilog-sk-fork)
13315 (define-key map "m" 'verilog-sk-module)
13316 (define-key map "o" 'verilog-sk-ovm-class)
13317 (define-key map "p" 'verilog-sk-primitive)
13318 (define-key map "r" 'verilog-sk-repeat)
13319 (define-key map "s" 'verilog-sk-specify)
13320 (define-key map "t" 'verilog-sk-task)
13321 (define-key map "u" 'verilog-sk-uvm-object)
13322 (define-key map "w" 'verilog-sk-while)
13323 (define-key map "x" 'verilog-sk-casex)
13324 (define-key map "z" 'verilog-sk-casez)
13325 (define-key map "?" 'verilog-sk-if)
13326 (define-key map ":" 'verilog-sk-else-if)
13327 (define-key map "/" 'verilog-sk-comment)
13328 (define-key map "A" 'verilog-sk-assign)
13329 (define-key map "F" 'verilog-sk-function)
13330 (define-key map "I" 'verilog-sk-input)
13331 (define-key map "O" 'verilog-sk-output)
13332 (define-key map "S" 'verilog-sk-state-machine)
13333 (define-key map "=" 'verilog-sk-inout)
13334 (define-key map "U" 'verilog-sk-uvm-component)
13335 (define-key map "W" 'verilog-sk-wire)
13336 (define-key map "R" 'verilog-sk-reg)
13337 (define-key map "D" 'verilog-sk-define-signal)
13339 "Keymap used in Verilog mode for smart template operations.")
13343 ;; Place the templates into Verilog Mode. They may be inserted under any key.
13344 ;; C-c C-t will be the default. If you use templates a lot, you
13345 ;; may want to consider moving the binding to another key in your init
13348 ;; Note \C-c and letter are reserved for users
13349 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
13351 ;;; ---- statement skeletons ------------------------------------------
13353 (define-skeleton verilog-sk-prompt-condition
13354 "Prompt for the loop condition."
13355 "[condition]: " str )
13357 (define-skeleton verilog-sk-prompt-init
13358 "Prompt for the loop init statement."
13359 "[initial statement]: " str )
13361 (define-skeleton verilog-sk-prompt-inc
13362 "Prompt for the loop increment statement."
13363 "[increment statement]: " str )
13365 (define-skeleton verilog-sk-prompt-name
13366 "Prompt for the name of something."
13369 (define-skeleton verilog-sk-prompt-clock
13370 "Prompt for the name of something."
13371 "name and edge of clock(s): " str)
13373 (defvar verilog-sk-reset nil)
13374 (defun verilog-sk-prompt-reset ()
13375 "Prompt for the name of a state machine reset."
13376 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
13379 (define-skeleton verilog-sk-prompt-state-selector
13380 "Prompt for the name of a state machine selector."
13381 "name of selector (eg {a,b,c,d}): " str )
13383 (define-skeleton verilog-sk-prompt-output
13384 "Prompt for the name of something."
13387 (define-skeleton verilog-sk-prompt-msb
13388 "Prompt for most significant bit specification."
13389 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
13391 (define-skeleton verilog-sk-prompt-lsb
13392 "Prompt for least significant bit specification."
13395 (defvar verilog-sk-p nil)
13396 (define-skeleton verilog-sk-prompt-width
13397 "Prompt for a width specification."
13400 (setq verilog-sk-p (point))
13401 (verilog-sk-prompt-msb)
13402 (if (> (point) verilog-sk-p) "] " " ")))
13404 (defun verilog-sk-header ()
13405 "Insert a descriptive header at the top of the file.
13406 See also `verilog-header' for an alternative format."
13409 (goto-char (point-min))
13410 (verilog-sk-header-tmpl)))
13412 (define-skeleton verilog-sk-header-tmpl
13413 "Insert a comment block containing the module title, author, etc."
13415 "// -*- Mode: Verilog -*-"
13416 "\n// Filename : " (buffer-name)
13417 "\n// Description : " str
13418 "\n// Author : " (user-full-name)
13419 "\n// Created On : " (current-time-string)
13420 "\n// Last Modified By: " (user-full-name)
13421 "\n// Last Modified On: " (current-time-string)
13422 "\n// Update Count : 0"
13423 "\n// Status : Unknown, Use with caution!"
13426 (define-skeleton verilog-sk-module
13427 "Insert a module definition."
13429 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
13431 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
13433 ;;; ------------------------------------------------------------------------
13434 ;;; Define a default OVM class, with macros and new()
13435 ;;; ------------------------------------------------------------------------
13437 (define-skeleton verilog-sk-ovm-class
13438 "Insert a class definition"
13440 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13442 > "`ovm_object_utils_begin(" name ")" \n
13443 > (- verilog-indent-level) " `ovm_object_utils_end" \n
13445 > "function new(name=\"" name "\");" \n
13446 > "super.new(name);" \n
13447 > (- verilog-indent-level) "endfunction" \n
13449 > "endclass" (progn (electric-verilog-terminate-line) nil))
13451 (define-skeleton verilog-sk-uvm-object
13452 "Insert a class definition"
13454 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13456 > "`uvm_object_utils_begin(" name ")" \n
13457 > (- verilog-indent-level) "`uvm_object_utils_end" \n
13459 > "function new(name=\"" name "\");" \n
13460 > "super.new(name);" \n
13461 > (- verilog-indent-level) "endfunction" \n
13463 > "endclass" (progn (electric-verilog-terminate-line) nil))
13465 (define-skeleton verilog-sk-uvm-component
13466 "Insert a class definition"
13468 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13470 > "`uvm_component_utils_begin(" name ")" \n
13471 > (- verilog-indent-level) "`uvm_component_utils_end" \n
13473 > "function new(name=\"\", uvm_component parent);" \n
13474 > "super.new(name, parent);" \n
13475 > (- verilog-indent-level) "endfunction" \n
13477 > "endclass" (progn (electric-verilog-terminate-line) nil))
13479 (define-skeleton verilog-sk-primitive
13480 "Insert a task definition."
13482 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
13484 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
13486 (define-skeleton verilog-sk-task
13487 "Insert a task definition."
13489 > "task " '(verilog-sk-prompt-name) & ?; \n
13493 > (- verilog-indent-level-behavioral) "end" \n
13494 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
13496 (define-skeleton verilog-sk-function
13497 "Insert a function definition."
13499 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
13503 > (- verilog-indent-level-behavioral) "end" \n
13504 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
13506 (define-skeleton verilog-sk-always
13507 "Insert always block. Uses the minibuffer to prompt
13508 for sensitivity list."
13510 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13512 > (- verilog-indent-level-behavioral) "end" \n >
13515 (define-skeleton verilog-sk-initial
13516 "Insert an initial block."
13518 > "initial begin\n"
13520 > (- verilog-indent-level-behavioral) "end" \n > )
13522 (define-skeleton verilog-sk-specify
13523 "Insert specify block. "
13527 > (- verilog-indent-level-behavioral) "endspecify" \n > )
13529 (define-skeleton verilog-sk-generate
13530 "Insert generate block. "
13534 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
13536 (define-skeleton verilog-sk-begin
13537 "Insert begin end block. Uses the minibuffer to prompt for name."
13539 > "begin" '(verilog-sk-prompt-name) \n
13541 > (- verilog-indent-level-behavioral) "end"
13544 (define-skeleton verilog-sk-fork
13545 "Insert a fork join block."
13550 > (- verilog-indent-level-behavioral) "end" \n
13553 > (- verilog-indent-level-behavioral) "end" \n
13554 > (- verilog-indent-level-behavioral) "join" \n
13558 (define-skeleton verilog-sk-case
13559 "Build skeleton case statement, prompting for the selector expression,
13560 and the case items."
13561 "[selector expression]: "
13562 > "case (" str ") " \n
13563 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13564 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13566 (define-skeleton verilog-sk-casex
13567 "Build skeleton casex statement, prompting for the selector expression,
13568 and the case items."
13569 "[selector expression]: "
13570 > "casex (" str ") " \n
13571 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13572 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13574 (define-skeleton verilog-sk-casez
13575 "Build skeleton casez statement, prompting for the selector expression,
13576 and the case items."
13577 "[selector expression]: "
13578 > "casez (" str ") " \n
13579 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13580 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13582 (define-skeleton verilog-sk-if
13583 "Insert a skeleton if statement."
13584 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
13586 > (- verilog-indent-level-behavioral) "end " \n )
13588 (define-skeleton verilog-sk-else-if
13589 "Insert a skeleton else if statement."
13590 > (verilog-indent-line) "else if ("
13591 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
13593 > "end" (progn (electric-verilog-terminate-line) nil))
13595 (define-skeleton verilog-sk-datadef
13596 "Common routine to get data definition."
13598 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
13600 (define-skeleton verilog-sk-input
13601 "Insert an input definition."
13603 > "input [" '(verilog-sk-datadef))
13605 (define-skeleton verilog-sk-output
13606 "Insert an output definition."
13608 > "output [" '(verilog-sk-datadef))
13610 (define-skeleton verilog-sk-inout
13611 "Insert an inout definition."
13613 > "inout [" '(verilog-sk-datadef))
13615 (defvar verilog-sk-signal nil)
13616 (define-skeleton verilog-sk-def-reg
13617 "Insert a reg definition."
13619 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
13621 (defun verilog-sk-define-signal ()
13622 "Insert a definition of signal under point at top of module."
13624 (let* ((sig-re "[a-zA-Z0-9_]*")
13625 (v1 (buffer-substring
13627 (skip-chars-backward sig-re)
13630 (skip-chars-forward sig-re)
13632 (if (not (member v1 verilog-keywords))
13634 (setq verilog-sk-signal v1)
13635 (verilog-beg-of-defun)
13636 (verilog-end-of-statement)
13637 (verilog-forward-syntactic-ws)
13638 (verilog-sk-def-reg)
13639 (message "signal at point is %s" v1))
13640 (message "object at point (%s) is a keyword" v1))))
13642 (define-skeleton verilog-sk-wire
13643 "Insert a wire definition."
13645 > "wire [" '(verilog-sk-datadef))
13647 (define-skeleton verilog-sk-reg
13648 "Insert a reg definition."
13650 > "reg [" '(verilog-sk-datadef))
13652 (define-skeleton verilog-sk-assign
13653 "Insert a skeleton assign statement."
13655 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
13657 (define-skeleton verilog-sk-while
13658 "Insert a skeleton while loop statement."
13660 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
13662 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13664 (define-skeleton verilog-sk-repeat
13665 "Insert a skeleton repeat loop statement."
13667 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
13669 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13671 (define-skeleton verilog-sk-for
13672 "Insert a skeleton while loop statement."
13675 '(verilog-sk-prompt-init) "; "
13676 '(verilog-sk-prompt-condition) "; "
13677 '(verilog-sk-prompt-inc)
13680 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13682 (define-skeleton verilog-sk-comment
13683 "Inserts three comment lines, making a display comment."
13689 (define-skeleton verilog-sk-state-machine
13690 "Insert a state machine definition."
13691 "Name of state variable: "
13692 '(setq input "state")
13693 > "// State registers for " str | -23 \n
13694 '(setq verilog-sk-state str)
13695 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
13698 > "// State FF for " verilog-sk-state \n
13699 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
13700 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
13701 > verilog-sk-state " = next_" verilog-sk-state ?; \n
13702 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
13704 > "// Next State Logic for " verilog-sk-state \n
13705 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13706 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
13707 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
13708 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
13709 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
13713 ;; Include file loading with mouse/return event
13715 ;; idea & first impl.: M. Rouat (eldo-mode.el)
13716 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
13718 (if (featurep 'xemacs)
13719 (require 'overlay))
13721 (defconst verilog-include-file-regexp
13722 "^`include\\s-+\"\\([^\n\"]*\\)\""
13723 "Regexp that matches the include file.")
13725 (defvar verilog-mode-mouse-map
13726 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
13727 (set-keymap-parent map verilog-mode-map)
13728 ;; mouse button bindings
13729 (define-key map "\r" 'verilog-load-file-at-point)
13730 (if (featurep 'xemacs)
13731 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
13732 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
13733 (if (featurep 'xemacs)
13734 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
13735 (define-key map [S-mouse-2] 'mouse-yank-at-click))
13737 "Map containing mouse bindings for `verilog-mode'.")
13740 (defun verilog-highlight-region (beg end _old-len)
13741 "Colorize included files and modules in the (changed?) region.
13742 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
13743 (when (or verilog-highlight-includes
13744 verilog-highlight-modules)
13746 (save-match-data ;; A query-replace may call this function - do not disturb
13747 (verilog-save-buffer-state
13748 (verilog-save-scan-cache
13751 (setq end-point (point-at-eol))
13753 (beginning-of-line) ; scan entire line
13754 ;; delete overlays existing on this line
13755 (let ((overlays (overlays-in (point) end-point)))
13758 (overlay-get (car overlays) 'detachable)
13759 (or (overlay-get (car overlays) 'verilog-include-file)
13760 (overlay-get (car overlays) 'verilog-inst-module)))
13761 (delete-overlay (car overlays)))
13762 (setq overlays (cdr overlays))))
13764 ;; make new include overlays
13765 (when verilog-highlight-includes
13766 (while (search-forward-regexp verilog-include-file-regexp end-point t)
13767 (goto-char (match-beginning 1))
13768 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
13769 (overlay-put ov 'start-closed 't)
13770 (overlay-put ov 'end-closed 't)
13771 (overlay-put ov 'evaporate 't)
13772 (overlay-put ov 'verilog-include-file 't)
13773 (overlay-put ov 'mouse-face 'highlight)
13774 (overlay-put ov 'local-map verilog-mode-mouse-map))))
13776 ;; make new module overlays
13778 ;; This scanner is syntax-fragile, so don't get bent
13779 (when verilog-highlight-modules
13780 (condition-case nil
13781 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
13783 (goto-char (match-beginning 0))
13784 (unless (verilog-inside-comment-or-string-p)
13785 (verilog-read-inst-module-matcher) ;; sets match 0
13786 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
13787 (overlay-put ov 'start-closed 't)
13788 (overlay-put ov 'end-closed 't)
13789 (overlay-put ov 'evaporate 't)
13790 (overlay-put ov 'verilog-inst-module 't)
13791 (overlay-put ov 'mouse-face 'highlight)
13792 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
13795 ;; Future highlights:
13796 ;; variables - make an Occur buffer of where referenced
13797 ;; pins - make an Occur buffer of the sig in the declaration module
13800 (defun verilog-highlight-buffer ()
13801 "Colorize included files and modules across the whole buffer."
13802 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
13804 ;; delete and remake overlays
13805 (verilog-highlight-region (point-min) (point-max) nil))
13807 ;; Deprecated, but was interactive, so we'll keep it around
13808 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
13810 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
13811 ;; so define this function to do more or less the same as ffap-at-mouse
13812 ;; but first resolve filename...
13813 (defun verilog-load-file-at-mouse (event)
13814 "Load file under button 2 click's EVENT.
13815 Files are checked based on `verilog-library-flags'."
13817 (save-excursion ;; implement a Verilog specific ffap-at-mouse
13818 (mouse-set-point event)
13819 (verilog-load-file-at-point t)))
13821 ;; ffap isn't usable for Verilog mode. It uses library paths.
13822 ;; so define this function to do more or less the same as ffap
13823 ;; but first resolve filename...
13824 (defun verilog-load-file-at-point (&optional warn)
13825 "Load file under point.
13826 If WARN, throw warning if not found.
13827 Files are checked based on `verilog-library-flags'."
13829 (save-excursion ;; implement a Verilog specific ffap
13830 (let ((overlays (overlays-in (point) (point)))
13832 (while (and overlays (not hit))
13833 (when (overlay-get (car overlays) 'verilog-inst-module)
13834 (verilog-goto-defun-file (buffer-substring
13835 (overlay-start (car overlays))
13836 (overlay-end (car overlays))))
13838 (setq overlays (cdr overlays)))
13840 (beginning-of-line)
13841 (when (and (not hit)
13842 (looking-at verilog-include-file-regexp))
13843 (if (and (car (verilog-library-filenames
13844 (match-string 1) (buffer-file-name)))
13845 (file-readable-p (car (verilog-library-filenames
13846 (match-string 1) (buffer-file-name)))))
13847 (find-file (car (verilog-library-filenames
13848 (match-string 1) (buffer-file-name))))
13851 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
13852 (match-string 1))))))))
13858 (defun verilog-faq ()
13859 "Tell the user their current version, and where to get the FAQ etc."
13861 (with-output-to-temp-buffer "*verilog-mode help*"
13862 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
13864 (princ "For new releases, see http://www.verilog.com\n")
13866 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
13868 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
13871 (autoload 'reporter-submit-bug-report "reporter")
13872 (defvar reporter-prompt-for-summary-p)
13874 (defun verilog-submit-bug-report ()
13875 "Submit via mail a bug report on verilog-mode.el."
13877 (let ((reporter-prompt-for-summary-p t))
13878 (reporter-submit-bug-report
13879 "mac@verilog.com, wsnyder@wsnyder.org"
13880 (concat "verilog-mode v" verilog-mode-version)
13882 verilog-active-low-regexp
13883 verilog-after-save-font-hook
13884 verilog-align-ifelse
13885 verilog-assignment-delay
13886 verilog-auto-arg-sort
13887 verilog-auto-declare-nettype
13888 verilog-auto-delete-trailing-whitespace
13889 verilog-auto-endcomments
13891 verilog-auto-ignore-concat
13892 verilog-auto-indent-on-newline
13893 verilog-auto-inout-ignore-regexp
13894 verilog-auto-input-ignore-regexp
13895 verilog-auto-inst-column
13896 verilog-auto-inst-dot-name
13897 verilog-auto-inst-interfaced-ports
13898 verilog-auto-inst-param-value
13899 verilog-auto-inst-sort
13900 verilog-auto-inst-template-numbers
13901 verilog-auto-inst-vector
13902 verilog-auto-lineup
13903 verilog-auto-newline
13904 verilog-auto-output-ignore-regexp
13905 verilog-auto-read-includes
13906 verilog-auto-reset-blocking-in-non
13907 verilog-auto-reset-widths
13908 verilog-auto-save-policy
13909 verilog-auto-sense-defines-constant
13910 verilog-auto-sense-include-inputs
13911 verilog-auto-star-expand
13912 verilog-auto-star-save
13913 verilog-auto-template-warn-unused
13914 verilog-auto-tieoff-declaration
13915 verilog-auto-tieoff-ignore-regexp
13916 verilog-auto-unused-ignore-regexp
13917 verilog-auto-wire-type
13918 verilog-before-auto-hook
13919 verilog-before-delete-auto-hook
13920 verilog-before-getopt-flags-hook
13921 verilog-before-save-font-hook
13922 verilog-cache-enabled
13924 verilog-case-indent
13925 verilog-cexp-indent
13928 verilog-delete-auto-hook
13929 verilog-getopt-flags-hook
13930 verilog-highlight-grouping-keywords
13931 verilog-highlight-includes
13932 verilog-highlight-modules
13933 verilog-highlight-p1800-keywords
13934 verilog-highlight-translate-off
13935 verilog-indent-begin-after-if
13936 verilog-indent-declaration-macros
13937 verilog-indent-level
13938 verilog-indent-level-behavioral
13939 verilog-indent-level-declaration
13940 verilog-indent-level-directive
13941 verilog-indent-level-module
13942 verilog-indent-lists
13943 verilog-library-directories
13944 verilog-library-extensions
13945 verilog-library-files
13946 verilog-library-flags
13948 verilog-minimum-comment-distance
13950 verilog-mode-release-emacs
13951 verilog-mode-version
13952 verilog-preprocessor
13954 verilog-tab-always-indent
13955 verilog-tab-to-comment
13956 verilog-typedef-regexp
13962 I want to report a bug.
13964 Before I go further, I want to say that Verilog mode has changed my life.
13965 I save so much time, my files are colored nicely, my co workers respect
13966 my coding ability... until now. I'd really appreciate anything you
13967 could do to help me out with this minor deficiency in the product.
13969 I've taken a look at the Verilog-Mode FAQ at
13970 http://www.veripool.org/verilog-mode-faq.html.
13972 And, I've considered filing the bug on the issue tracker at
13973 http://www.veripool.org/verilog-mode-bugs
13974 since I realize that public bugs are easier for you to track,
13975 and for others to search, but would prefer to email.
13977 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
13978 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
13979 the code included below.
13981 Given those lines, I expected [[Fill in here]] to happen;
13982 but instead, [[Fill in here]] happens!.
13984 == The code: =="))))
13986 (provide 'verilog-mode)
13988 ;; Local Variables:
13989 ;; checkdoc-permit-comma-termination-flag:t
13990 ;; checkdoc-force-docstrings-flag:nil
13993 ;;; verilog-mode.el ends here