IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2009, Intel Corporation
   5 All rights reserved. This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 #ifndef _EFI_PCI_BUS_H_
  17 #define _EFI_PCI_BUS_H_
  18
  19 #include <FrameworkDxe.h>
  20
  21 #include <Protocol/LoadedImage.h>
  22 #include <Protocol/PciHostBridgeResourceAllocation.h>
  23 #include <Protocol/PciIo.h>
  24 #include <Protocol/LoadFile2.h>
  25 #include <Protocol/PciRootBridgeIo.h>
  26 #include <Protocol/PciHotPlugRequest.h>
  27 #include <Protocol/DevicePath.h>
  28 #include <Protocol/PciPlatform.h>
  29 #include <Protocol/PciHotPlugInit.h>
  30 #include <Protocol/Decompress.h>
  31 #include <Protocol/BusSpecificDriverOverride.h>
  32 #include <Protocol/IncompatiblePciDeviceSupport.h>
  33
  34 #include <Library/DebugLib.h>
  35 #include <Library/UefiDriverEntryPoint.h>
  36 #include <Library/BaseLib.h>
  37 #include <Library/UefiLib.h>
  38 #include <Library/BaseMemoryLib.h>
  39 #include <Library/ReportStatusCodeLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/DevicePathLib.h>
  43 #include <Library/PcdLib.h>
  44 #include <Library/PeCoffLib.h>
  45
  46 #include <IndustryStandard/Pci.h>
  47 #include <IndustryStandard/PeImage.h>
  48 #include <IndustryStandard/Acpi.h>
  49
  50 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  51 typedef struct _PCI_BAR                    PCI_BAR;
  52
  53 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  54 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  55
  56 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  57 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  58 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  59
  60 typedef enum {
  61   PciBarTypeUnknown = 0,
  62   PciBarTypeIo16,
  63   PciBarTypeIo32,
  64   PciBarTypeMem32,
  65   PciBarTypePMem32,
  66   PciBarTypeMem64,
  67   PciBarTypePMem64,
  68   PciBarTypeIo,
  69   PciBarTypeMem,
  70   PciBarTypeMaxType
  71 } PCI_BAR_TYPE;
  72
  73 #include "ComponentName.h"
  74 #include "PciIo.h"
  75 #include "PciCommand.h"
  76 #include "PciDeviceSupport.h"
  77 #include "PciEnumerator.h"
  78 #include "PciEnumeratorSupport.h"
  79 #include "PciDriverOverride.h"
  80 #include "PciRomTable.h"
  81 #include "PciOptionRomSupport.h"
  82 #include "PciPowerManagement.h"
  83 #include "PciHotPlugSupport.h"
  84 #include "PciLib.h"
  85
  86 #define VGABASE1  0x3B0
  87 #define VGALIMIT1 0x3BB
  88
  89 #define VGABASE2  0x3C0
  90 #define VGALIMIT2 0x3DF
  91
  92 #define ISABASE   0x100
  93 #define ISALIMIT  0x3FF
  94
  95 //
  96 // PCI BAR parameters
  97 //
  98 struct _PCI_BAR {
  99   UINT64        BaseAddress;
 100   UINT64        Length;
 101   UINT64        Alignment;
 102   PCI_BAR_TYPE  BarType;
 103   BOOLEAN       Prefetchable;
 104   UINT8         MemType;
 105   UINT8         Offset;
 106 };
 107
 108 //
 109 // defined in PCI Card Specification, 8.0
 110 //
 111 #define PCI_CARD_MEMORY_BASE_0                0x1C
 112 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 113 #define PCI_CARD_MEMORY_BASE_1                0x24
 114 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 115 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 116 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 117 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 118 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 119 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 120 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 121 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 122 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 123 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 124
 125 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 126 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 127
 128 #define PPB_BAR_0                             0
 129 #define PPB_BAR_1                             1
 130 #define PPB_IO_RANGE                          2
 131 #define PPB_MEM32_RANGE                       3
 132 #define PPB_PMEM32_RANGE                      4
 133 #define PPB_PMEM64_RANGE                      5
 134 #define PPB_MEM64_RANGE                       0xFF
 135
 136 #define P2C_BAR_0                             0
 137 #define P2C_MEM_1                             1
 138 #define P2C_MEM_2                             2
 139 #define P2C_IO_1                              3
 140 #define P2C_IO_2                              4
 141
 142 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 143 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 144 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 145 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 146 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 147 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 148 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 149
 150 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 151
 152 //
 153 // Define option for attribute
 154 //
 155 #define EFI_SET_SUPPORTS    0
 156 #define EFI_SET_ATTRIBUTES  1
 157
 158 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 159
 160 struct _PCI_IO_DEVICE {
 161   UINT32                                    Signature;
 162   EFI_HANDLE                                Handle;
 163   EFI_PCI_IO_PROTOCOL                       PciIo;
 164   LIST_ENTRY                                Link;
 165
 166   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 167   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 168   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 169   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 170
 171   //
 172   // PCI configuration space header type
 173   //
 174   PCI_TYPE00                                Pci;
 175
 176   //
 177   // Bus number, Device number, Function number
 178   //
 179   UINT8                                     BusNumber;
 180   UINT8                                     DeviceNumber;
 181   UINT8                                     FunctionNumber;
 182
 183   //
 184   // BAR for this PCI Device
 185   //
 186   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 187
 188   //
 189   // The bridge device this pci device is subject to
 190   //
 191   PCI_IO_DEVICE                             *Parent;
 192
 193   //
 194   // A linked list for children Pci Device if it is bridge device
 195   //
 196   LIST_ENTRY                                ChildList;
 197
 198   //
 199   // TURE if the PCI bus driver creates the handle for this PCI device
 200   //
 201   BOOLEAN                                   Registered;
 202
 203   //
 204   // TRUE if the PCI bus driver successfully allocates the resource required by
 205   // this PCI device
 206   //
 207   BOOLEAN                                   Allocated;
 208
 209   //
 210   // The attribute this PCI device currently set
 211   //
 212   UINT64                                    Attributes;
 213
 214   //
 215   // The attributes this PCI device actually supports
 216   //
 217   UINT64                                    Supports;
 218
 219   //
 220   // The resource decode the bridge supports
 221   //
 222   UINT32                                    Decodes;
 223
 224   //
 225   // The OptionRom Size
 226   //
 227   UINT64                                    RomSize;
 228
 229   //
 230   // The OptionRom Size
 231   //
 232   UINT64                                    RomBase;
 233
 234   //
 235   // TRUE if all OpROM (in device or in platform specific position) have been processed
 236   //
 237   BOOLEAN                                   AllOpRomProcessed;
 238
 239   //
 240   // TRUE if there is any EFI driver in the OptionRom
 241   //
 242   BOOLEAN                                   BusOverride;
 243
 244   //
 245   // A list tracking reserved resource on a bridge device
 246   //
 247   LIST_ENTRY                                ReservedResourceList;
 248
 249   //
 250   // A list tracking image handle of platform specific overriding driver
 251   //
 252   LIST_ENTRY                                OptionRomDriverList;
 253
 254   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 255   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 256
 257   BOOLEAN                                   IsPciExp;
 258   //
 259   // For SR-IOV
 260   //
 261   UINT8                                     PciExpressCapabilityOffset;
 262   UINT32                                    AriCapabilityOffset;
 263   UINT32                                    SrIovCapabilityOffset;
 264   UINT32                                    MrIovCapabilityOffset;
 265   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 266   UINT32                                    SystemPageSize;
 267   UINT16                                    InitialVFs;
 268   UINT16                                    ReservedBusNum;
 269 };
 270
 271 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 272   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 273
 274 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 275   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 276
 277 #define PCI_IO_DEVICE_FROM_LINK(a) \
 278   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 279
 280 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 281   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 282
 283
 284
 285 //
 286 // Global Variables
 287 //
 288 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
 289 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 290 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 291 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 292 extern BOOLEAN                                      gFullEnumeration;
 293 extern UINTN                                        gPciHostBridgeNumber;
 294 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 295 extern UINT64                                       gAllOne;
 296 extern UINT64                                       gAllZero;
 297 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 298
 299
 300 /**
 301   Macro that checks whether device is a GFX device.
 302
 303   @param  _p      Specified device.
 304
 305   @retval TRUE    Device is a a GFX device.
 306   @retval FALSE   Device is not a a GFX device.
 307
 308 **/
 309 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 310
 311 /**
 312   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 313   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 314
 315   @param  This                Protocol instance pointer.
 316   @param  Controller          Handle of device to test.
 317   @param  RemainingDevicePath Optional parameter use to pick a specific child.
 318                               device to start.
 319
 320   @retval EFI_SUCCESS         This driver supports this device.
 321   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 322   @retval other               This driver does not support this device.
 323
 324 **/
 325 EFI_STATUS
 326 EFIAPI
 327 PciBusDriverBindingSupported (
 328   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 329   IN EFI_HANDLE                     Controller,
 330   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 331   );
 332
 333 /**
 334   Start this driver on ControllerHandle and enumerate Pci bus and start
 335   all device under PCI bus.
 336
 337   @param  This                 Protocol instance pointer.
 338   @param  Controller           Handle of device to bind driver to.
 339   @param  RemainingDevicePath  Optional parameter use to pick a specific child.
 340                                device to start.
 341
 342   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 343   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 344   @retval other                This driver does not support this device.
 345
 346 **/
 347 EFI_STATUS
 348 EFIAPI
 349 PciBusDriverBindingStart (
 350   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 351   IN EFI_HANDLE                     Controller,
 352   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 353   );
 354
 355 /**
 356   Stop this driver on ControllerHandle. Support stoping any child handles
 357   created by this driver.
 358
 359   @param  This              Protocol instance pointer.
 360   @param  Controller        Handle of device to stop driver on.
 361   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 362                             children is zero stop the entire bus driver.
 363   @param  ChildHandleBuffer List of Child Handles to Stop.
 364
 365   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 366   @retval other             This driver was not removed from this device.
 367
 368 **/
 369 EFI_STATUS
 370 EFIAPI
 371 PciBusDriverBindingStop (
 372   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 373   IN  EFI_HANDLE                    Controller,
 374   IN  UINTN                         NumberOfChildren,
 375   IN  EFI_HANDLE                    *ChildHandleBuffer
 376   );
 377
 378 #endif