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Modulize bwi(4) debug prints. Leave ATTACH/INIT/TXPOWER on by default.
[dragonfly/port-amd64.git] / sys / dev / netif / bwi / if_bwi.c
blobdec5089d811c1a30990e1c320be3ff47948183c2
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.10 2007/09/17 12:13:24 sephe Exp $
35 */
36
37 #include <sys/param.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/bus.h>
41 #include <sys/malloc.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/bpf.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/ifq_var.h>
56
57 #include <netproto/802_11/ieee80211_radiotap.h>
58 #include <netproto/802_11/ieee80211_var.h>
59
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
62 #include <bus/pci/pcidevs.h>
63
64 #include "bitops.h"
65 #include "if_bwireg.h"
66 #include "if_bwivar.h"
67 #include "bwimac.h"
68 #include "bwirf.h"
69
70 struct bwi_clock_freq {
71 u_int clkfreq_min;
72 u_int clkfreq_max;
73 };
74
75 struct bwi_myaddr_bssid {
76 uint8_t myaddr[IEEE80211_ADDR_LEN];
77 uint8_t bssid[IEEE80211_ADDR_LEN];
78 } __packed;
79
80 static int bwi_probe(device_t);
81 static int bwi_attach(device_t);
82 static int bwi_detach(device_t);
83 static int bwi_shutdown(device_t);
84
85 static void bwi_init(void *);
86 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
87 static void bwi_start(struct ifnet *);
88 static void bwi_watchdog(struct ifnet *);
89 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
90 static void bwi_updateslot(struct ifnet *);
91 static int bwi_media_change(struct ifnet *);
92
93 static void bwi_next_scan(void *);
94 static void bwi_calibrate(void *);
95
96 static int bwi_stop(struct bwi_softc *);
97 static int bwi_newbuf(struct bwi_softc *, int, int);
98 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
99 struct ieee80211_node **, int);
100
101 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
102 bus_addr_t, int, int);
103 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
104
105 static int bwi_init_tx_ring32(struct bwi_softc *, int);
106 static int bwi_init_rx_ring32(struct bwi_softc *);
107 static int bwi_init_txstats32(struct bwi_softc *);
108 static void bwi_free_tx_ring32(struct bwi_softc *, int);
109 static void bwi_free_rx_ring32(struct bwi_softc *);
110 static void bwi_free_txstats32(struct bwi_softc *);
111 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
112 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
113 int, bus_addr_t, int);
114 static void bwi_rxeof32(struct bwi_softc *);
115 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
116 static void bwi_txeof_status32(struct bwi_softc *);
117
118 static int bwi_init_tx_ring64(struct bwi_softc *, int);
119 static int bwi_init_rx_ring64(struct bwi_softc *);
120 static int bwi_init_txstats64(struct bwi_softc *);
121 static void bwi_free_tx_ring64(struct bwi_softc *, int);
122 static void bwi_free_rx_ring64(struct bwi_softc *);
123 static void bwi_free_txstats64(struct bwi_softc *);
124 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
125 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
126 int, bus_addr_t, int);
127 static void bwi_rxeof64(struct bwi_softc *);
128 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
129 static void bwi_txeof_status64(struct bwi_softc *);
130
131 static void bwi_intr(void *);
132 static void bwi_rxeof(struct bwi_softc *, int);
133 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
134 static void bwi_txeof(struct bwi_softc *);
135 static void bwi_txeof_status(struct bwi_softc *, int);
136 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
137 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
138 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
139 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
140 struct bwi_rxbuf_hdr *, const void *, int);
141
142 static int bwi_dma_alloc(struct bwi_softc *);
143 static void bwi_dma_free(struct bwi_softc *);
144 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
145 struct bwi_ring_data *, bus_size_t,
146 uint32_t);
147 static int bwi_dma_mbuf_create(struct bwi_softc *);
148 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
149 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
150 static void bwi_dma_txstats_free(struct bwi_softc *);
151 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
152 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
153 bus_size_t, int);
154
155 static void bwi_power_on(struct bwi_softc *, int);
156 static int bwi_power_off(struct bwi_softc *, int);
157 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
158 static int bwi_set_clock_delay(struct bwi_softc *);
159 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
160 static int bwi_get_pwron_delay(struct bwi_softc *sc);
161 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
162 const uint8_t *);
163 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
164 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
165
166 static void bwi_get_card_flags(struct bwi_softc *);
167 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
168
169 static int bwi_bus_attach(struct bwi_softc *);
170 static int bwi_bbp_attach(struct bwi_softc *);
171 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
172 static void bwi_bbp_power_off(struct bwi_softc *);
173
174 static const char *bwi_regwin_name(const struct bwi_regwin *);
175 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
176 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
177 static int bwi_regwin_select(struct bwi_softc *, int);
178
179 static const struct bwi_dev {
180 uint16_t vid;
181 uint16_t did;
182 const char *desc;
183 } bwi_devices[] = {
184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
185 "Broadcom BCM4301 802.11 Wireless Lan" },
186
187 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
188 "Broadcom BCM4307 802.11 Wireless Lan" },
189
190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
191 "Broadcom BCM4311 802.11 Wireless Lan" },
192
193 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
194 "Broadcom BCM4312 802.11 Wireless Lan" },
195
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
197 "Broadcom BCM4306 802.11 Wireless Lan" },
198
199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
200 "Broadcom BCM4306 802.11 Wireless Lan" },
201
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
203 "Broadcom BCM4306 802.11 Wireless Lan" },
204
205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
206 "Broadcom BCM4309 802.11 Wireless Lan" },
207
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
209 "Broadcom BCM4318 802.11 Wireless Lan" },
210
211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
212 "Broadcom BCM4319 802.11 Wireless Lan" }
213 };
214
215 static device_method_t bwi_methods[] = {
216 DEVMETHOD(device_probe, bwi_probe),
217 DEVMETHOD(device_attach, bwi_attach),
218 DEVMETHOD(device_detach, bwi_detach),
219 DEVMETHOD(device_shutdown, bwi_shutdown),
220 #if 0
221 DEVMETHOD(device_suspend, bwi_suspend),
222 DEVMETHOD(device_resume, bwi_resume),
223 #endif
224 { 0, 0 }
225 };
226
227 static driver_t bwi_driver = {
228 "bwi",
229 bwi_methods,
230 sizeof(struct bwi_softc)
231 };
232
233 static devclass_t bwi_devclass;
234
235 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, 0, 0);
236 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, 0, 0);
237
238 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
239 #if 0
240 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
241 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
242 #endif
243 MODULE_DEPEND(bwi, pci, 1, 1, 1);
244 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
245
246 static const struct {
247 uint16_t did_min;
248 uint16_t did_max;
249 uint16_t bbp_id;
250 } bwi_bbpid_map[] = {
251 { 0x4301, 0x4301, 0x4301 },
252 { 0x4305, 0x4307, 0x4307 },
253 { 0x4403, 0x4403, 0x4402 },
254 { 0x4610, 0x4615, 0x4610 },
255 { 0x4710, 0x4715, 0x4710 },
256 { 0x4720, 0x4725, 0x4309 }
257 };
258
259 static const struct {
260 uint16_t bbp_id;
261 int nregwin;
262 } bwi_regwin_count[] = {
263 { 0x4301, 5 },
264 { 0x4306, 6 },
265 { 0x4307, 5 },
266 { 0x4310, 8 },
267 { 0x4401, 3 },
268 { 0x4402, 3 },
269 { 0x4610, 9 },
270 { 0x4704, 9 },
271 { 0x4710, 9 },
272 { 0x5365, 7 }
273 };
274
275 #define CLKSRC(src) \
276 [BWI_CLKSRC_ ## src] = { \
277 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
278 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
279 }
280
281 static const struct {
282 u_int freq_min;
283 u_int freq_max;
284 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
285 CLKSRC(LP_OSC),
286 CLKSRC(CS_OSC),
287 CLKSRC(PCI)
288 };
289
290 #undef CLKSRC
291
292 #ifdef BWI_DEBUG
293 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
294 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
295 #endif
296
297 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
298
299 static const struct ieee80211_rateset bwi_rateset_11b =
300 { 4, { 2, 4, 11, 22 } };
301 static const struct ieee80211_rateset bwi_rateset_11g =
302 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
303
304 uint16_t
305 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
306 {
307 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
308 }
309
310 static __inline void
311 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
312 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
313 int tx)
314 {
315 struct bwi_desc32 *desc = &desc_array[desc_idx];
316 uint32_t ctrl, addr, addr_hi, addr_lo;
317
318 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
319 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
320
321 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
322 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
323
324 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
325 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
326 if (desc_idx == ndesc - 1)
327 ctrl |= BWI_DESC32_C_EOR;
328 if (tx) {
329 /* XXX */
330 ctrl |= BWI_DESC32_C_FRAME_START |
331 BWI_DESC32_C_FRAME_END |
332 BWI_DESC32_C_INTR;
333 }
334
335 desc->addr = htole32(addr);
336 desc->ctrl = htole32(ctrl);
337 }
338
339 static int
340 bwi_probe(device_t dev)
341 {
342 const struct bwi_dev *b;
343 uint16_t did, vid;
344
345 did = pci_get_device(dev);
346 vid = pci_get_vendor(dev);
347
348 for (b = bwi_devices; b->desc != NULL; ++b) {
349 if (b->did == did && b->vid == vid) {
350 device_set_desc(dev, b->desc);
351 return 0;
352 }
353 }
354 return ENXIO;
355 }
356
357 static int
358 bwi_attach(device_t dev)
359 {
360 struct bwi_softc *sc = device_get_softc(dev);
361 struct ieee80211com *ic = &sc->sc_ic;
362 struct ifnet *ifp = &ic->ic_if;
363 struct bwi_mac *mac;
364 struct bwi_phy *phy;
365 int i, error;
366
367 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
368 sc->sc_dev = dev;
369
370 /*
371 * Initialize sysctl variables
372 */
373 sc->sc_fw_version = BWI_FW_VERSION3;
374 sc->sc_dwell_time = 200;
375 #ifdef BWI_DEBUG
376 sc->sc_debug = bwi_debug;
377 #endif
378
379 callout_init(&sc->sc_scan_ch);
380 callout_init(&sc->sc_calib_ch);
381
382 #ifndef BURN_BRIDGES
383 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
384 uint32_t irq, mem;
385
386 /* XXX Save more PCIR */
387 irq = pci_read_config(dev, PCIR_INTLINE, 4);
388 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
389
390 device_printf(dev, "chip is in D%d power mode "
391 "-- setting to D0\n", pci_get_powerstate(dev));
392
393 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
394
395 pci_write_config(dev, PCIR_INTLINE, irq, 4);
396 pci_write_config(dev, BWI_PCIR_BAR, irq, 4);
397 }
398 #endif /* !BURN_BRIDGE */
399
400 pci_enable_busmaster(dev);
401
402 /* Get more PCI information */
403 sc->sc_pci_revid = pci_get_revid(dev);
404 sc->sc_pci_subvid = pci_get_subvendor(dev);
405 sc->sc_pci_subdid = pci_get_subdevice(dev);
406
407 /*
408 * Allocate IO memory
409 */
410 sc->sc_mem_rid = BWI_PCIR_BAR;
411 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
412 &sc->sc_mem_rid, RF_ACTIVE);
413 if (sc->sc_mem_res == NULL) {
414 device_printf(dev, "can't allocate IO memory\n");
415 return ENXIO;
416 }
417 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
418 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
419
420 /*
421 * Allocate IRQ
422 */
423 sc->sc_irq_rid = 0;
424 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
425 &sc->sc_irq_rid,
426 RF_SHAREABLE | RF_ACTIVE);
427 if (sc->sc_irq_res == NULL) {
428 device_printf(dev, "can't allocate irq\n");
429 error = ENXIO;
430 goto fail;
431 }
432
433 /*
434 * Create sysctl tree
435 */
436 sysctl_ctx_init(&sc->sc_sysctl_ctx);
437 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
438 SYSCTL_STATIC_CHILDREN(_hw),
439 OID_AUTO,
440 device_get_nameunit(dev),
441 CTLFLAG_RD, 0, "");
442 if (sc->sc_sysctl_tree == NULL) {
443 device_printf(dev, "can't add sysctl node\n");
444 error = ENXIO;
445 goto fail;
446 }
447
448 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
449 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
450 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
451 "Channel dwell time during scan (msec)");
452 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
453 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
454 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
455 "Firmware version");
456 #ifdef BWI_DEBUG
457 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
458 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
459 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
460 #endif
461
462 bwi_power_on(sc, 1);
463
464 error = bwi_bbp_attach(sc);
465 if (error)
466 goto fail;
467
468 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
469 if (error)
470 goto fail;
471
472 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
473 error = bwi_set_clock_delay(sc);
474 if (error)
475 goto fail;
476
477 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
478 if (error)
479 goto fail;
480
481 error = bwi_get_pwron_delay(sc);
482 if (error)
483 goto fail;
484 }
485
486 error = bwi_bus_attach(sc);
487 if (error)
488 goto fail;
489
490 bwi_get_card_flags(sc);
491
492 /* TODO: LED */
493
494 for (i = 0; i < sc->sc_nmac; ++i) {
495 struct bwi_regwin *old;
496
497 mac = &sc->sc_mac[i];
498 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
499 if (error)
500 goto fail;
501
502 error = bwi_mac_lateattach(mac);
503 if (error)
504 goto fail;
505
506 error = bwi_regwin_switch(sc, old, NULL);
507 if (error)
508 goto fail;
509 }
510
511 /*
512 * XXX First MAC is known to exist
513 * TODO2
514 */
515 mac = &sc->sc_mac[0];
516 phy = &mac->mac_phy;
517
518 bwi_bbp_power_off(sc);
519
520 error = bwi_dma_alloc(sc);
521 if (error)
522 goto fail;
523
524 ifp->if_softc = sc;
525 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
526 ifp->if_init = bwi_init;
527 ifp->if_ioctl = bwi_ioctl;
528 ifp->if_start = bwi_start;
529 ifp->if_watchdog = bwi_watchdog;
530 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
531 ifq_set_ready(&ifp->if_snd);
532
533 /* Get locale */
534 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
535 BWI_SPROM_CARD_INFO_LOCALE);
536 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
537
538 /*
539 * Setup ratesets, phytype, channels and get MAC address
540 */
541 if (phy->phy_mode == IEEE80211_MODE_11B ||
542 phy->phy_mode == IEEE80211_MODE_11G) {
543 uint16_t chan_flags;
544
545 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
546
547 if (phy->phy_mode == IEEE80211_MODE_11B) {
548 chan_flags = IEEE80211_CHAN_B;
549 ic->ic_phytype = IEEE80211_T_DS;
550 } else {
551 chan_flags = IEEE80211_CHAN_CCK |
552 IEEE80211_CHAN_OFDM |
553 IEEE80211_CHAN_DYN |
554 IEEE80211_CHAN_2GHZ;
555 ic->ic_phytype = IEEE80211_T_OFDM;
556 ic->ic_sup_rates[IEEE80211_MODE_11G] =
557 bwi_rateset_11g;
558 }
559
560 /* XXX depend on locale */
561 for (i = 1; i <= 14; ++i) {
562 ic->ic_channels[i].ic_freq =
563 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
564 ic->ic_channels[i].ic_flags = chan_flags;
565 }
566
567 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
568 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
569 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
570 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
571 device_printf(dev, "invalid MAC address: "
572 "%6D\n", ic->ic_myaddr, ":");
573 }
574 }
575 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
576 /* TODO:11A */
577 error = ENXIO;
578 goto fail;
579 } else {
580 panic("unknown phymode %d\n", phy->phy_mode);
581 }
582
583 ic->ic_caps = IEEE80211_C_SHSLOT |
584 IEEE80211_C_SHPREAMBLE |
585 IEEE80211_C_WPA |
586 IEEE80211_C_MONITOR;
587 ic->ic_state = IEEE80211_S_INIT;
588 ic->ic_opmode = IEEE80211_M_STA;
589
590 ic->ic_updateslot = bwi_updateslot;
591
592 ieee80211_ifattach(ic);
593
594 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
595 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
596
597 sc->sc_newstate = ic->ic_newstate;
598 ic->ic_newstate = bwi_newstate;
599
600 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
601
602 /*
603 * Attach radio tap
604 */
605 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
606 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
607 &sc->sc_drvbpf);
608
609 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
610 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
611 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
612
613 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
614 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
615 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
616
617 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
618 &sc->sc_irq_handle, ifp->if_serializer);
619 if (error) {
620 device_printf(dev, "can't setup intr\n");
621 bpfdetach(ifp);
622 ieee80211_ifdetach(ic);
623 goto fail;
624 }
625
626 if (bootverbose)
627 ieee80211_announce(ic);
628
629 return 0;
630 fail:
631 bwi_detach(dev);
632 return error;
633 }
634
635 static int
636 bwi_detach(device_t dev)
637 {
638 struct bwi_softc *sc = device_get_softc(dev);
639
640 if (device_is_attached(dev)) {
641 struct ifnet *ifp = &sc->sc_ic.ic_if;
642 int i;
643
644 lwkt_serialize_enter(ifp->if_serializer);
645 bwi_stop(sc);
646 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
647 lwkt_serialize_exit(ifp->if_serializer);
648
649 bpfdetach(ifp);
650 ieee80211_ifdetach(&sc->sc_ic);
651
652 for (i = 0; i < sc->sc_nmac; ++i)
653 bwi_mac_detach(&sc->sc_mac[i]);
654 }
655
656 if (sc->sc_sysctl_tree != NULL)
657 sysctl_ctx_free(&sc->sc_sysctl_ctx);
658
659 if (sc->sc_irq_res != NULL) {
660 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
661 sc->sc_irq_res);
662 }
663
664 if (sc->sc_mem_res != NULL) {
665 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
666 sc->sc_mem_res);
667 }
668
669 bwi_dma_free(sc);
670
671 return 0;
672 }
673
674 static int
675 bwi_shutdown(device_t dev)
676 {
677 struct bwi_softc *sc = device_get_softc(dev);
678 struct ifnet *ifp = &sc->sc_ic.ic_if;
679
680 lwkt_serialize_enter(ifp->if_serializer);
681 bwi_stop(sc);
682 lwkt_serialize_exit(ifp->if_serializer);
683 return 0;
684 }
685
686 static void
687 bwi_power_on(struct bwi_softc *sc, int with_pll)
688 {
689 uint32_t gpio_in, gpio_out, gpio_en;
690 uint16_t status;
691
692 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
693 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
694 goto back;
695
696 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
697 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
698
699 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
700 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
701 if (with_pll) {
702 /* Turn off PLL first */
703 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
704 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
705 }
706
707 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
708 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
709 DELAY(1000);
710
711 if (with_pll) {
712 /* Turn on PLL */
713 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
714 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
715 DELAY(5000);
716 }
717
718 back:
719 /* Clear "Signaled Target Abort" */
720 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
721 status &= ~PCIM_STATUS_STABORT;
722 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
723 }
724
725 static int
726 bwi_power_off(struct bwi_softc *sc, int with_pll)
727 {
728 uint32_t gpio_out, gpio_en;
729
730 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
731 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
732 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
733
734 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
735 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
736 if (with_pll) {
737 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
738 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
739 }
740
741 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
742 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
743 return 0;
744 }
745
746 int
747 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
748 struct bwi_regwin **old_rw)
749 {
750 int error;
751
752 if (old_rw != NULL)
753 *old_rw = NULL;
754
755 if (!BWI_REGWIN_EXIST(rw))
756 return EINVAL;
757
758 if (sc->sc_cur_regwin != rw) {
759 error = bwi_regwin_select(sc, rw->rw_id);
760 if (error) {
761 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
762 rw->rw_id);
763 return error;
764 }
765 }
766
767 if (old_rw != NULL)
768 *old_rw = sc->sc_cur_regwin;
769 sc->sc_cur_regwin = rw;
770 return 0;
771 }
772
773 static int
774 bwi_regwin_select(struct bwi_softc *sc, int id)
775 {
776 uint32_t win = BWI_PCIM_REGWIN(id);
777 int i;
778
779 #define RETRY_MAX 50
780 for (i = 0; i < RETRY_MAX; ++i) {
781 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
782 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
783 return 0;
784 DELAY(10);
785 }
786 #undef RETRY_MAX
787
788 return ENXIO;
789 }
790
791 static void
792 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
793 {
794 uint32_t val;
795
796 val = CSR_READ_4(sc, BWI_ID_HI);
797 *type = BWI_ID_HI_REGWIN_TYPE(val);
798 *rev = BWI_ID_HI_REGWIN_REV(val);
799
800 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
801 "vendor 0x%04x\n", *type, *rev,
802 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
803 }
804
805 static int
806 bwi_bbp_attach(struct bwi_softc *sc)
807 {
808 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
809 uint16_t bbp_id, rw_type;
810 uint8_t rw_rev;
811 uint32_t info;
812 int error, nregwin, i;
813
814 /*
815 * Get 0th regwin information
816 * NOTE: 0th regwin should exist
817 */
818 error = bwi_regwin_select(sc, 0);
819 if (error) {
820 device_printf(sc->sc_dev, "can't select regwin 0\n");
821 return error;
822 }
823 bwi_regwin_info(sc, &rw_type, &rw_rev);
824
825 /*
826 * Find out BBP id
827 */
828 bbp_id = 0;
829 info = 0;
830 if (rw_type == BWI_REGWIN_T_COM) {
831 info = CSR_READ_4(sc, BWI_INFO);
832 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
833
834 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
835
836 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
837 } else {
838 uint16_t did = pci_get_device(sc->sc_dev);
839 uint8_t revid = pci_get_revid(sc->sc_dev);
840
841 for (i = 0; i < N(bwi_bbpid_map); ++i) {
842 if (did >= bwi_bbpid_map[i].did_min &&
843 did <= bwi_bbpid_map[i].did_max) {
844 bbp_id = bwi_bbpid_map[i].bbp_id;
845 break;
846 }
847 }
848 if (bbp_id == 0) {
849 device_printf(sc->sc_dev, "no BBP id for device id "
850 "0x%04x\n", did);
851 return ENXIO;
852 }
853
854 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
855 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
856 }
857
858 /*
859 * Find out number of regwins
860 */
861 nregwin = 0;
862 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
863 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
864 } else {
865 for (i = 0; i < N(bwi_regwin_count); ++i) {
866 if (bwi_regwin_count[i].bbp_id == bbp_id) {
867 nregwin = bwi_regwin_count[i].nregwin;
868 break;
869 }
870 }
871 if (nregwin == 0) {
872 device_printf(sc->sc_dev, "no number of win for "
873 "BBP id 0x%04x\n", bbp_id);
874 return ENXIO;
875 }
876 }
877
878 /* Record BBP id/rev for later using */
879 sc->sc_bbp_id = bbp_id;
880 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
881 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
882 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
883 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
884
885 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
886 nregwin, sc->sc_cap);
887
888 /*
889 * Create rest of the regwins
890 */
891
892 /* Don't re-create common regwin, if it is already created */
893 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
894
895 for (; i < nregwin; ++i) {
896 /*
897 * Get regwin information
898 */
899 error = bwi_regwin_select(sc, i);
900 if (error) {
901 device_printf(sc->sc_dev,
902 "can't select regwin %d\n", i);
903 return error;
904 }
905 bwi_regwin_info(sc, &rw_type, &rw_rev);
906
907 /*
908 * Try attach:
909 * 1) Bus (PCI/PCIE) regwin
910 * 2) MAC regwin
911 * Ignore rest types of regwin
912 */
913 if (rw_type == BWI_REGWIN_T_BUSPCI ||
914 rw_type == BWI_REGWIN_T_BUSPCIE) {
915 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
916 device_printf(sc->sc_dev,
917 "bus regwin already exists\n");
918 } else {
919 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
920 rw_type, rw_rev);
921 }
922 } else if (rw_type == BWI_REGWIN_T_MAC) {
923 /* XXX ignore return value */
924 bwi_mac_attach(sc, i, rw_rev);
925 }
926 }
927
928 /* At least one MAC shold exist */
929 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
930 device_printf(sc->sc_dev, "no MAC was found\n");
931 return ENXIO;
932 }
933 KKASSERT(sc->sc_nmac > 0);
934
935 /* Bus regwin must exist */
936 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
937 device_printf(sc->sc_dev, "no bus regwin was found\n");
938 return ENXIO;
939 }
940
941 /* Start with first MAC */
942 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
943 if (error)
944 return error;
945
946 return 0;
947 #undef N
948 }
949
950 int
951 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
952 {
953 struct bwi_regwin *old, *bus;
954 uint32_t val;
955 int error;
956
957 bus = &sc->sc_bus_regwin;
958 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
959
960 /*
961 * Tell bus to generate requested interrupts
962 */
963 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
964 /*
965 * NOTE: Read BWI_FLAGS from MAC regwin
966 */
967 val = CSR_READ_4(sc, BWI_FLAGS);
968
969 error = bwi_regwin_switch(sc, bus, &old);
970 if (error)
971 return error;
972
973 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
974 } else {
975 uint32_t mac_mask;
976
977 mac_mask = 1 << mac->mac_id;
978
979 error = bwi_regwin_switch(sc, bus, &old);
980 if (error)
981 return error;
982
983 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
984 val |= mac_mask << 8;
985 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
986 }
987
988 if (sc->sc_flags & BWI_F_BUS_INITED)
989 goto back;
990
991 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
992 /*
993 * Enable prefetch and burst
994 */
995 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
996 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
997
998 if (bus->rw_rev < 5) {
999 struct bwi_regwin *com = &sc->sc_com_regwin;
1000
1001 /*
1002 * Configure timeouts for bus operation
1003 */
1004
1005 /*
1006 * Set service timeout and request timeout
1007 */
1008 CSR_SETBITS_4(sc, BWI_CONF_LO,
1009 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1010 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1011
1012 /*
1013 * If there is common regwin, we switch to that regwin
1014 * and switch back to bus regwin once we have done.
1015 */
1016 if (BWI_REGWIN_EXIST(com)) {
1017 error = bwi_regwin_switch(sc, com, NULL);
1018 if (error)
1019 return error;
1020 }
1021
1022 /* Let bus know what we have changed */
1023 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1024 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1025 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1026 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1027
1028 if (BWI_REGWIN_EXIST(com)) {
1029 error = bwi_regwin_switch(sc, bus, NULL);
1030 if (error)
1031 return error;
1032 }
1033 } else if (bus->rw_rev >= 11) {
1034 /*
1035 * Enable memory read multiple
1036 */
1037 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1038 }
1039 } else {
1040 /* TODO:PCIE */
1041 }
1042
1043 sc->sc_flags |= BWI_F_BUS_INITED;
1044 back:
1045 return bwi_regwin_switch(sc, old, NULL);
1046 }
1047
1048 static void
1049 bwi_get_card_flags(struct bwi_softc *sc)
1050 {
1051 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1052 if (sc->sc_card_flags == 0xffff)
1053 sc->sc_card_flags = 0;
1054
1055 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1056 sc->sc_pci_subdid == 0x4e && /* XXX */
1057 sc->sc_pci_revid > 0x40)
1058 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1059
1060 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1061 }
1062
1063 static void
1064 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1065 {
1066 int i;
1067
1068 for (i = 0; i < 3; ++i) {
1069 *((uint16_t *)eaddr + i) =
1070 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1071 }
1072 }
1073
1074 static void
1075 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1076 {
1077 struct bwi_regwin *com;
1078 uint32_t val;
1079 u_int div;
1080 int src;
1081
1082 bzero(freq, sizeof(*freq));
1083 com = &sc->sc_com_regwin;
1084
1085 KKASSERT(BWI_REGWIN_EXIST(com));
1086 KKASSERT(sc->sc_cur_regwin == com);
1087 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1088
1089 /*
1090 * Calculate clock frequency
1091 */
1092 src = -1;
1093 div = 0;
1094 if (com->rw_rev < 6) {
1095 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1096 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1097 src = BWI_CLKSRC_PCI;
1098 div = 64;
1099 } else {
1100 src = BWI_CLKSRC_CS_OSC;
1101 div = 32;
1102 }
1103 } else if (com->rw_rev < 10) {
1104 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1105
1106 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1107 if (src == BWI_CLKSRC_LP_OSC) {
1108 div = 1;
1109 } else {
1110 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1111
1112 /* Unknown source */
1113 if (src >= BWI_CLKSRC_MAX)
1114 src = BWI_CLKSRC_CS_OSC;
1115 }
1116 } else {
1117 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1118
1119 src = BWI_CLKSRC_CS_OSC;
1120 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1121 }
1122
1123 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1124 KKASSERT(div != 0);
1125
1126 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1127 src == BWI_CLKSRC_PCI ? "PCI" :
1128 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1129
1130 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1131 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1132
1133 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1134 freq->clkfreq_min, freq->clkfreq_max);
1135 }
1136
1137 static int
1138 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1139 {
1140 struct bwi_regwin *old, *com;
1141 uint32_t clk_ctrl, clk_src;
1142 int error, pwr_off = 0;
1143
1144 com = &sc->sc_com_regwin;
1145 if (!BWI_REGWIN_EXIST(com))
1146 return 0;
1147
1148 if (com->rw_rev >= 10 || com->rw_rev < 6)
1149 return 0;
1150
1151 /*
1152 * For common regwin whose rev is [6, 10), the chip
1153 * must be capable to change clock mode.
1154 */
1155 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1156 return 0;
1157
1158 error = bwi_regwin_switch(sc, com, &old);
1159 if (error)
1160 return error;
1161
1162 if (clk_mode == BWI_CLOCK_MODE_FAST)
1163 bwi_power_on(sc, 0); /* Don't turn on PLL */
1164
1165 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1166 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1167
1168 switch (clk_mode) {
1169 case BWI_CLOCK_MODE_FAST:
1170 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1171 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1172 break;
1173 case BWI_CLOCK_MODE_SLOW:
1174 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1175 break;
1176 case BWI_CLOCK_MODE_DYN:
1177 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1178 BWI_CLOCK_CTRL_IGNPLL |
1179 BWI_CLOCK_CTRL_NODYN);
1180 if (clk_src != BWI_CLKSRC_CS_OSC) {
1181 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1182 pwr_off = 1;
1183 }
1184 break;
1185 }
1186 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1187
1188 if (pwr_off)
1189 bwi_power_off(sc, 0); /* Leave PLL as it is */
1190
1191 return bwi_regwin_switch(sc, old, NULL);
1192 }
1193
1194 static int
1195 bwi_set_clock_delay(struct bwi_softc *sc)
1196 {
1197 struct bwi_regwin *old, *com;
1198 int error;
1199
1200 com = &sc->sc_com_regwin;
1201 if (!BWI_REGWIN_EXIST(com))
1202 return 0;
1203
1204 error = bwi_regwin_switch(sc, com, &old);
1205 if (error)
1206 return error;
1207
1208 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1209 if (sc->sc_bbp_rev == 0)
1210 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1211 else if (sc->sc_bbp_rev == 1)
1212 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1213 }
1214
1215 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1216 if (com->rw_rev >= 10) {
1217 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1218 } else {
1219 struct bwi_clock_freq freq;
1220
1221 bwi_get_clock_freq(sc, &freq);
1222 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1223 howmany(freq.clkfreq_max * 150, 1000000));
1224 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1225 howmany(freq.clkfreq_max * 15, 1000000));
1226 }
1227 }
1228
1229 return bwi_regwin_switch(sc, old, NULL);
1230 }
1231
1232 static void
1233 bwi_init(void *xsc)
1234 {
1235 struct bwi_softc *sc = xsc;
1236 struct ieee80211com *ic = &sc->sc_ic;
1237 struct ifnet *ifp = &ic->ic_if;
1238 struct bwi_mac *mac;
1239 int error;
1240
1241 ASSERT_SERIALIZED(ifp->if_serializer);
1242
1243 error = bwi_stop(sc);
1244 if (error) {
1245 if_printf(ifp, "can't stop\n");
1246 return;
1247 }
1248
1249 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1250
1251 /* TODO: 2 MAC */
1252
1253 mac = &sc->sc_mac[0];
1254 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1255 if (error)
1256 goto back;
1257
1258 error = bwi_mac_init(mac);
1259 if (error)
1260 goto back;
1261
1262 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1263
1264 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1265
1266 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1267 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1268
1269 bwi_mac_reset_hwkeys(mac);
1270
1271 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1272 int i;
1273
1274 #define NRETRY 1000
1275 /*
1276 * Drain any possible pending TX status
1277 */
1278 for (i = 0; i < NRETRY; ++i) {
1279 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1280 BWI_TXSTATUS0_VALID) == 0)
1281 break;
1282 CSR_READ_4(sc, BWI_TXSTATUS1);
1283 }
1284 if (i == NRETRY)
1285 if_printf(ifp, "can't drain TX status\n");
1286 #undef NRETRY
1287 }
1288
1289 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1290 bwi_mac_updateslot(mac, 1);
1291
1292 /* Start MAC */
1293 error = bwi_mac_start(mac);
1294 if (error)
1295 goto back;
1296
1297 /* Enable intrs */
1298 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1299
1300 ifp->if_flags |= IFF_RUNNING;
1301 ifp->if_flags &= ~IFF_OACTIVE;
1302
1303 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1304 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1305 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1306 } else {
1307 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1308 }
1309 back:
1310 if (error)
1311 bwi_stop(sc);
1312 }
1313
1314 static int
1315 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1316 {
1317 struct bwi_softc *sc = ifp->if_softc;
1318 int error = 0;
1319
1320 ASSERT_SERIALIZED(ifp->if_serializer);
1321
1322 switch (cmd) {
1323 case SIOCSIFFLAGS:
1324 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1325 (IFF_UP | IFF_RUNNING)) {
1326 struct bwi_mac *mac;
1327 int promisc = -1;
1328
1329 KKASSERT(sc->sc_cur_regwin->rw_type ==
1330 BWI_REGWIN_T_MAC);
1331 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1332
1333 if ((ifp->if_flags & IFF_PROMISC) &&
1334 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1335 promisc = 1;
1336 sc->sc_flags |= BWI_F_PROMISC;
1337 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1338 (sc->sc_flags & BWI_F_PROMISC)) {
1339 promisc = 0;
1340 sc->sc_flags &= ~BWI_F_PROMISC;
1341 }
1342
1343 if (promisc >= 0)
1344 bwi_mac_set_promisc(mac, promisc);
1345 }
1346
1347 if (ifp->if_flags & IFF_UP) {
1348 if ((ifp->if_flags & IFF_RUNNING) == 0)
1349 bwi_init(sc);
1350 } else {
1351 if (ifp->if_flags & IFF_RUNNING)
1352 bwi_stop(sc);
1353 }
1354 break;
1355 default:
1356 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1357 break;
1358 }
1359
1360 if (error == ENETRESET) {
1361 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1362 (IFF_UP | IFF_RUNNING))
1363 bwi_init(sc);
1364 error = 0;
1365 }
1366 return error;
1367 }
1368
1369 static void
1370 bwi_start(struct ifnet *ifp)
1371 {
1372 struct bwi_softc *sc = ifp->if_softc;
1373 struct ieee80211com *ic = &sc->sc_ic;
1374 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1375 int trans, idx;
1376
1377 ASSERT_SERIALIZED(ifp->if_serializer);
1378
1379 if ((ifp->if_flags & IFF_OACTIVE) ||
1380 (ifp->if_flags & IFF_RUNNING) == 0)
1381 return;
1382
1383 trans = 0;
1384 idx = tbd->tbd_idx;
1385
1386 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1387 struct ieee80211_frame *wh;
1388 struct ieee80211_node *ni;
1389 struct mbuf *m;
1390 int mgt_pkt = 0;
1391
1392 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1393 IF_DEQUEUE(&ic->ic_mgtq, m);
1394
1395 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1396 m->m_pkthdr.rcvif = NULL;
1397
1398 mgt_pkt = 1;
1399 } else if (!ifq_is_empty(&ifp->if_snd)) {
1400 struct ether_header *eh;
1401
1402 if (ic->ic_state != IEEE80211_S_RUN)
1403 break;
1404
1405 m = ifq_dequeue(&ifp->if_snd, NULL);
1406 if (m == NULL)
1407 break;
1408
1409 if (m->m_len < sizeof(*eh)) {
1410 m = m_pullup(m, sizeof(*eh));
1411 if (m == NULL) {
1412 ifp->if_oerrors++;
1413 continue;
1414 }
1415 }
1416 eh = mtod(m, struct ether_header *);
1417
1418 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1419 if (ni == NULL) {
1420 m_freem(m);
1421 ifp->if_oerrors++;
1422 continue;
1423 }
1424
1425 /* TODO: PS */
1426
1427 BPF_MTAP(ifp, m);
1428
1429 m = ieee80211_encap(ic, m, ni);
1430 if (m == NULL) {
1431 ieee80211_free_node(ni);
1432 ifp->if_oerrors++;
1433 continue;
1434 }
1435 } else {
1436 break;
1437 }
1438
1439 if (ic->ic_rawbpf != NULL)
1440 bpf_mtap(ic->ic_rawbpf, m);
1441
1442 wh = mtod(m, struct ieee80211_frame *);
1443 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1444 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1445 ieee80211_free_node(ni);
1446 m_freem(m);
1447 ifp->if_oerrors++;
1448 continue;
1449 }
1450 }
1451 wh = NULL; /* Catch any invalid use */
1452
1453 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1454 /* 'm' is freed in bwi_encap() if we reach here */
1455 if (ni != NULL)
1456 ieee80211_free_node(ni);
1457 ifp->if_oerrors++;
1458 continue;
1459 }
1460
1461 trans = 1;
1462 tbd->tbd_used++;
1463 idx = (idx + 1) % BWI_TX_NDESC;
1464
1465 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1466 ifp->if_flags |= IFF_OACTIVE;
1467 break;
1468 }
1469 }
1470 tbd->tbd_idx = idx;
1471
1472 if (trans)
1473 sc->sc_tx_timer = 5;
1474 ifp->if_timer = 1;
1475 }
1476
1477 static void
1478 bwi_watchdog(struct ifnet *ifp)
1479 {
1480 struct bwi_softc *sc = ifp->if_softc;
1481
1482 ASSERT_SERIALIZED(ifp->if_serializer);
1483
1484 ifp->if_timer = 0;
1485
1486 if ((ifp->if_flags & IFF_RUNNING) == 0)
1487 return;
1488
1489 if (sc->sc_tx_timer) {
1490 if (--sc->sc_tx_timer == 0) {
1491 if_printf(ifp, "watchdog timeout\n");
1492 ifp->if_oerrors++;
1493 /* TODO */
1494 } else {
1495 ifp->if_timer = 1;
1496 }
1497 }
1498 ieee80211_watchdog(&sc->sc_ic);
1499 }
1500
1501 static int
1502 bwi_stop(struct bwi_softc *sc)
1503 {
1504 struct ieee80211com *ic = &sc->sc_ic;
1505 struct ifnet *ifp = &ic->ic_if;
1506 struct bwi_mac *mac;
1507 int i, error, pwr_off = 0;
1508
1509 ASSERT_SERIALIZED(ifp->if_serializer);
1510
1511 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1512
1513 if (ifp->if_flags & IFF_RUNNING) {
1514 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1515 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1516
1517 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1518 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1519 bwi_mac_stop(mac);
1520 }
1521
1522 for (i = 0; i < sc->sc_nmac; ++i) {
1523 struct bwi_regwin *old_rw;
1524
1525 mac = &sc->sc_mac[i];
1526 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1527 continue;
1528
1529 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1530 if (error)
1531 continue;
1532
1533 bwi_mac_shutdown(mac);
1534 pwr_off = 1;
1535
1536 bwi_regwin_switch(sc, old_rw, NULL);
1537 }
1538
1539 if (pwr_off)
1540 bwi_bbp_power_off(sc);
1541
1542 sc->sc_tx_timer = 0;
1543 ifp->if_timer = 0;
1544 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1545 return 0;
1546 }
1547
1548 static void
1549 bwi_intr(void *xsc)
1550 {
1551 struct bwi_softc *sc = xsc;
1552 struct ifnet *ifp = &sc->sc_ic.ic_if;
1553 uint32_t intr_status;
1554 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1555 int i, txrx_error;
1556
1557 ASSERT_SERIALIZED(ifp->if_serializer);
1558
1559 if ((ifp->if_flags & IFF_RUNNING) == 0)
1560 return;
1561
1562 /*
1563 * Get interrupt status
1564 */
1565 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1566 if (intr_status == 0xffffffff) /* Not for us */
1567 return;
1568
1569 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1570
1571 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1572 if (intr_status == 0) /* Nothing is interesting */
1573 return;
1574
1575 txrx_error = 0;
1576 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1577 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1578 uint32_t mask;
1579
1580 if (BWI_TXRX_IS_RX(i))
1581 mask = BWI_TXRX_RX_INTRS;
1582 else
1583 mask = BWI_TXRX_TX_INTRS;
1584
1585 txrx_intr_status[i] =
1586 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1587
1588 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1589 i, txrx_intr_status[i]);
1590
1591 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1592 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1593 i, txrx_intr_status[i]);
1594 txrx_error = 1;
1595 }
1596 }
1597 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1598
1599 /*
1600 * Acknowledge interrupt
1601 */
1602 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1603
1604 for (i = 0; i < BWI_TXRX_NRING; ++i)
1605 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1606
1607 /* Disable all interrupts */
1608 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1609
1610 if (intr_status & BWI_INTR_PHY_TXERR)
1611 if_printf(ifp, "intr PHY TX error\n");
1612
1613 if (txrx_error) {
1614 /* TODO: reset device */
1615 }
1616
1617 if (intr_status & BWI_INTR_TBTT) {
1618 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1619 bwi_mac_config_ps((struct bwi_mac *)sc->sc_cur_regwin);
1620 }
1621
1622 if (intr_status & BWI_INTR_EO_ATIM)
1623 if_printf(ifp, "EO_ATIM\n");
1624
1625 if (intr_status & BWI_INTR_PMQ) {
1626 for (;;) {
1627 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1628 break;
1629 }
1630 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1631 }
1632
1633 if (intr_status & BWI_INTR_NOISE)
1634 if_printf(ifp, "intr noise\n");
1635
1636 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1637 sc->sc_rxeof(sc);
1638
1639 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX)
1640 sc->sc_txeof_status(sc);
1641
1642 if (intr_status & BWI_INTR_TX_DONE)
1643 bwi_txeof(sc);
1644
1645 /* TODO:LED */
1646
1647 /* Re-enable interrupts */
1648 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1649 }
1650
1651 static int
1652 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1653 {
1654 struct bwi_softc *sc = ic->ic_if.if_softc;
1655 struct ifnet *ifp = &ic->ic_if;
1656 int error;
1657
1658 ASSERT_SERIALIZED(ifp->if_serializer);
1659
1660 callout_stop(&sc->sc_scan_ch);
1661 callout_stop(&sc->sc_calib_ch);
1662
1663 if (nstate == IEEE80211_S_INIT)
1664 goto back;
1665
1666 error = bwi_set_chan(sc, ic->ic_curchan);
1667 if (error) {
1668 if_printf(ifp, "can't set channel to %u\n",
1669 ieee80211_chan2ieee(ic, ic->ic_curchan));
1670 return error;
1671 }
1672
1673 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1674 /* Nothing to do */
1675 } else if (nstate == IEEE80211_S_RUN) {
1676 struct bwi_mac *mac;
1677
1678 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1679
1680 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1681 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1682
1683 /* Initial TX power calibration */
1684 bwi_mac_calibrate_txpower(mac);
1685 } else {
1686 bwi_set_bssid(sc, bwi_zero_addr);
1687 }
1688
1689 back:
1690 error = sc->sc_newstate(ic, nstate, arg);
1691
1692 if (nstate == IEEE80211_S_SCAN) {
1693 callout_reset(&sc->sc_scan_ch,
1694 (sc->sc_dwell_time * hz) / 1000,
1695 bwi_next_scan, sc);
1696 } else if (nstate == IEEE80211_S_RUN) {
1697 /* XXX 15 seconds */
1698 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
1699 }
1700 return error;
1701 }
1702
1703 static int
1704 bwi_media_change(struct ifnet *ifp)
1705 {
1706 int error;
1707
1708 ASSERT_SERIALIZED(ifp->if_serializer);
1709
1710 error = ieee80211_media_change(ifp);
1711 if (error != ENETRESET)
1712 return error;
1713
1714 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1715 bwi_init(ifp->if_softc);
1716 return 0;
1717 }
1718
1719 static int
1720 bwi_dma_alloc(struct bwi_softc *sc)
1721 {
1722 int error, i, has_txstats;
1723 bus_addr_t lowaddr = 0;
1724 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1725 uint32_t txrx_ctrl_step = 0;
1726
1727 has_txstats = 0;
1728 for (i = 0; i < sc->sc_nmac; ++i) {
1729 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1730 has_txstats = 1;
1731 break;
1732 }
1733 }
1734
1735 switch (sc->sc_bus_space) {
1736 case BWI_BUS_SPACE_30BIT:
1737 case BWI_BUS_SPACE_32BIT:
1738 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1739 lowaddr = BWI_BUS_SPACE_MAXADDR;
1740 else
1741 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1742 desc_sz = sizeof(struct bwi_desc32);
1743 txrx_ctrl_step = 0x20;
1744
1745 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1746 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1747 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1748 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1749 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1750 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1751 sc->sc_rxeof = bwi_rxeof32;
1752 sc->sc_start_tx = bwi_start_tx32;
1753 if (has_txstats) {
1754 sc->sc_init_txstats = bwi_init_txstats32;
1755 sc->sc_free_txstats = bwi_free_txstats32;
1756 sc->sc_txeof_status = bwi_txeof_status32;
1757 }
1758 break;
1759
1760 case BWI_BUS_SPACE_64BIT:
1761 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1762 desc_sz = sizeof(struct bwi_desc64);
1763 txrx_ctrl_step = 0x40;
1764
1765 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1766 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1767 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1768 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1769 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1770 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1771 sc->sc_rxeof = bwi_rxeof64;
1772 sc->sc_start_tx = bwi_start_tx64;
1773 if (has_txstats) {
1774 sc->sc_init_txstats = bwi_init_txstats64;
1775 sc->sc_free_txstats = bwi_free_txstats64;
1776 sc->sc_txeof_status = bwi_txeof_status64;
1777 }
1778 break;
1779 }
1780
1781 KKASSERT(lowaddr != 0);
1782 KKASSERT(desc_sz != 0);
1783 KKASSERT(txrx_ctrl_step != 0);
1784
1785 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1786 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1787
1788 /*
1789 * Create top level DMA tag
1790 */
1791 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
1792 lowaddr, BUS_SPACE_MAXADDR,
1793 NULL, NULL,
1794 MAXBSIZE,
1795 BUS_SPACE_UNRESTRICTED,
1796 BUS_SPACE_MAXSIZE_32BIT,
1797 0, &sc->sc_parent_dtag);
1798 if (error) {
1799 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1800 return error;
1801 }
1802
1803 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1804
1805 /*
1806 * Create TX ring DMA stuffs
1807 */
1808 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
1809 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1810 NULL, NULL,
1811 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
1812 0, &sc->sc_txring_dtag);
1813 if (error) {
1814 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1815 return error;
1816 }
1817
1818 for (i = 0; i < BWI_TX_NRING; ++i) {
1819 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1820 &sc->sc_tx_rdata[i], tx_ring_sz,
1821 TXRX_CTRL(i));
1822 if (error) {
1823 device_printf(sc->sc_dev, "%dth TX ring "
1824 "DMA alloc failed\n", i);
1825 return error;
1826 }
1827 }
1828
1829 /*
1830 * Create RX ring DMA stuffs
1831 */
1832 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
1833 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1834 NULL, NULL,
1835 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
1836 0, &sc->sc_rxring_dtag);
1837 if (error) {
1838 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1839 return error;
1840 }
1841
1842 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1843 rx_ring_sz, TXRX_CTRL(0));
1844 if (error) {
1845 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1846 return error;
1847 }
1848
1849 if (has_txstats) {
1850 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1851 if (error) {
1852 device_printf(sc->sc_dev,
1853 "TX stats DMA alloc failed\n");
1854 return error;
1855 }
1856 }
1857
1858 #undef TXRX_CTRL
1859
1860 return bwi_dma_mbuf_create(sc);
1861 }
1862
1863 static void
1864 bwi_dma_free(struct bwi_softc *sc)
1865 {
1866 if (sc->sc_txring_dtag != NULL) {
1867 int i;
1868
1869 for (i = 0; i < BWI_TX_NRING; ++i) {
1870 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
1871
1872 if (rd->rdata_desc != NULL) {
1873 bus_dmamap_unload(sc->sc_txring_dtag,
1874 rd->rdata_dmap);
1875 bus_dmamem_free(sc->sc_txring_dtag,
1876 rd->rdata_desc,
1877 rd->rdata_dmap);
1878 }
1879 }
1880 bus_dma_tag_destroy(sc->sc_txring_dtag);
1881 }
1882
1883 if (sc->sc_rxring_dtag != NULL) {
1884 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
1885
1886 if (rd->rdata_desc != NULL) {
1887 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
1888 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
1889 rd->rdata_dmap);
1890 }
1891 bus_dma_tag_destroy(sc->sc_rxring_dtag);
1892 }
1893
1894 bwi_dma_txstats_free(sc);
1895 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
1896
1897 if (sc->sc_parent_dtag != NULL)
1898 bus_dma_tag_destroy(sc->sc_parent_dtag);
1899 }
1900
1901 static int
1902 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
1903 struct bwi_ring_data *rd, bus_size_t size,
1904 uint32_t txrx_ctrl)
1905 {
1906 int error;
1907
1908 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
1909 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1910 &rd->rdata_dmap);
1911 if (error) {
1912 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
1913 return error;
1914 }
1915
1916 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
1917 bwi_dma_ring_addr, &rd->rdata_paddr,
1918 BUS_DMA_WAITOK);
1919 if (error) {
1920 device_printf(sc->sc_dev, "can't load DMA mem\n");
1921 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
1922 rd->rdata_desc = NULL;
1923 return error;
1924 }
1925
1926 rd->rdata_txrx_ctrl = txrx_ctrl;
1927 return 0;
1928 }
1929
1930 static int
1931 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
1932 bus_size_t desc_sz)
1933 {
1934 struct bwi_txstats_data *st;
1935 bus_size_t dma_size;
1936 int error;
1937
1938 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
1939 sc->sc_txstats = st;
1940
1941 /*
1942 * Create TX stats descriptor DMA stuffs
1943 */
1944 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
1945
1946 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
1947 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1948 NULL, NULL,
1949 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
1950 0, &st->stats_ring_dtag);
1951 if (error) {
1952 device_printf(sc->sc_dev, "can't create txstats ring "
1953 "DMA tag\n");
1954 return error;
1955 }
1956
1957 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
1958 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1959 &st->stats_ring_dmap);
1960 if (error) {
1961 device_printf(sc->sc_dev, "can't allocate txstats ring "
1962 "DMA mem\n");
1963 bus_dma_tag_destroy(st->stats_ring_dtag);
1964 st->stats_ring_dtag = NULL;
1965 return error;
1966 }
1967
1968 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
1969 st->stats_ring, dma_size,
1970 bwi_dma_ring_addr, &st->stats_ring_paddr,
1971 BUS_DMA_WAITOK);
1972 if (error) {
1973 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
1974 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
1975 st->stats_ring_dmap);
1976 bus_dma_tag_destroy(st->stats_ring_dtag);
1977 st->stats_ring_dtag = NULL;
1978 return error;
1979 }
1980
1981 /*
1982 * Create TX stats DMA stuffs
1983 */
1984 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
1985 BWI_ALIGN);
1986
1987 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
1988 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1989 NULL, NULL,
1990 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
1991 0, &st->stats_dtag);
1992 if (error) {
1993 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
1994 return error;
1995 }
1996
1997 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
1998 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1999 &st->stats_dmap);
2000 if (error) {
2001 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2002 bus_dma_tag_destroy(st->stats_dtag);
2003 st->stats_dtag = NULL;
2004 return error;
2005 }
2006
2007 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2008 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2009 BUS_DMA_WAITOK);
2010 if (error) {
2011 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2012 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2013 bus_dma_tag_destroy(st->stats_dtag);
2014 st->stats_dtag = NULL;
2015 return error;
2016 }
2017
2018 st->stats_ctrl_base = ctrl_base;
2019 return 0;
2020 }
2021
2022 static void
2023 bwi_dma_txstats_free(struct bwi_softc *sc)
2024 {
2025 struct bwi_txstats_data *st;
2026
2027 if (sc->sc_txstats == NULL)
2028 return;
2029 st = sc->sc_txstats;
2030
2031 if (st->stats_ring_dtag != NULL) {
2032 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2033 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2034 st->stats_ring_dmap);
2035 bus_dma_tag_destroy(st->stats_ring_dtag);
2036 }
2037
2038 if (st->stats_dtag != NULL) {
2039 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2040 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2041 bus_dma_tag_destroy(st->stats_dtag);
2042 }
2043
2044 kfree(st, M_DEVBUF);
2045 }
2046
2047 static void
2048 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2049 {
2050 KASSERT(nseg == 1, ("too many segments\n"));
2051 *((bus_addr_t *)arg) = seg->ds_addr;
2052 }
2053
2054 static int
2055 bwi_dma_mbuf_create(struct bwi_softc *sc)
2056 {
2057 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2058 int i, j, k, ntx, error;
2059
2060 /*
2061 * Create TX/RX mbuf DMA tag
2062 */
2063 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2064 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2065 NULL, NULL, MCLBYTES, 1,
2066 BUS_SPACE_MAXSIZE_32BIT,
2067 0, &sc->sc_buf_dtag);
2068 if (error) {
2069 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2070 return error;
2071 }
2072
2073 ntx = 0;
2074
2075 /*
2076 * Create TX mbuf DMA map
2077 */
2078 for (i = 0; i < BWI_TX_NRING; ++i) {
2079 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2080
2081 for (j = 0; j < BWI_TX_NDESC; ++j) {
2082 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2083 &tbd->tbd_buf[j].tb_dmap);
2084 if (error) {
2085 device_printf(sc->sc_dev, "can't create "
2086 "%dth tbd, %dth DMA map\n", i, j);
2087
2088 ntx = i;
2089 for (k = 0; k < j; ++k) {
2090 bus_dmamap_destroy(sc->sc_buf_dtag,
2091 tbd->tbd_buf[k].tb_dmap);
2092 }
2093 goto fail;
2094 }
2095 }
2096 }
2097 ntx = BWI_TX_NRING;
2098
2099 /*
2100 * Create RX mbuf DMA map and a spare DMA map
2101 */
2102 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2103 &rbd->rbd_tmp_dmap);
2104 if (error) {
2105 device_printf(sc->sc_dev,
2106 "can't create spare RX buf DMA map\n");
2107 goto fail;
2108 }
2109
2110 for (j = 0; j < BWI_RX_NDESC; ++j) {
2111 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2112 &rbd->rbd_buf[j].rb_dmap);
2113 if (error) {
2114 device_printf(sc->sc_dev, "can't create %dth "
2115 "RX buf DMA map\n", j);
2116
2117 for (k = 0; k < j; ++k) {
2118 bus_dmamap_destroy(sc->sc_buf_dtag,
2119 rbd->rbd_buf[j].rb_dmap);
2120 }
2121 bus_dmamap_destroy(sc->sc_buf_dtag,
2122 rbd->rbd_tmp_dmap);
2123 goto fail;
2124 }
2125 }
2126
2127 return 0;
2128 fail:
2129 bwi_dma_mbuf_destroy(sc, ntx, 0);
2130 return error;
2131 }
2132
2133 static void
2134 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2135 {
2136 int i, j;
2137
2138 if (sc->sc_buf_dtag == NULL)
2139 return;
2140
2141 for (i = 0; i < ntx; ++i) {
2142 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2143
2144 for (j = 0; j < BWI_TX_NDESC; ++j) {
2145 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2146
2147 if (tb->tb_mbuf != NULL) {
2148 bus_dmamap_unload(sc->sc_buf_dtag,
2149 tb->tb_dmap);
2150 m_freem(tb->tb_mbuf);
2151 }
2152 if (tb->tb_ni != NULL)
2153 ieee80211_free_node(tb->tb_ni);
2154 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2155 }
2156 }
2157
2158 if (nrx) {
2159 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2160
2161 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2162 for (j = 0; j < BWI_RX_NDESC; ++j) {
2163 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2164
2165 if (rb->rb_mbuf != NULL) {
2166 bus_dmamap_unload(sc->sc_buf_dtag,
2167 rb->rb_dmap);
2168 m_freem(rb->rb_mbuf);
2169 }
2170 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2171 }
2172 }
2173
2174 bus_dma_tag_destroy(sc->sc_buf_dtag);
2175 sc->sc_buf_dtag = NULL;
2176 }
2177
2178 static void
2179 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2180 {
2181 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2182 }
2183
2184 static void
2185 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2186 {
2187 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2188 }
2189
2190 static int
2191 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2192 {
2193 struct bwi_ring_data *rd;
2194 struct bwi_txbuf_data *tbd;
2195 uint32_t val, addr_hi, addr_lo;
2196
2197 KKASSERT(ring_idx < BWI_TX_NRING);
2198 rd = &sc->sc_tx_rdata[ring_idx];
2199 tbd = &sc->sc_tx_bdata[ring_idx];
2200
2201 tbd->tbd_idx = 0;
2202 tbd->tbd_used = 0;
2203
2204 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2205 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2206 BUS_DMASYNC_PREWRITE);
2207
2208 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2209 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2210
2211 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2212 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2213 BWI_TXRX32_RINGINFO_FUNC_MASK);
2214 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2215
2216 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2217 BWI_TXRX32_CTRL_ENABLE;
2218 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2219
2220 return 0;
2221 }
2222
2223 static void
2224 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2225 bus_addr_t paddr, int hdr_size, int ndesc)
2226 {
2227 uint32_t val, addr_hi, addr_lo;
2228
2229 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2230 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2231
2232 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2233 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2234 BWI_TXRX32_RINGINFO_FUNC_MASK);
2235 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2236
2237 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2238 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2239 BWI_TXRX32_CTRL_ENABLE;
2240 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2241
2242 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2243 (ndesc - 1) * sizeof(struct bwi_desc32));
2244 }
2245
2246 static int
2247 bwi_init_rx_ring32(struct bwi_softc *sc)
2248 {
2249 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2250 int i, error;
2251
2252 sc->sc_rx_bdata.rbd_idx = 0;
2253
2254 for (i = 0; i < BWI_RX_NDESC; ++i) {
2255 error = bwi_newbuf(sc, i, 1);
2256 if (error) {
2257 if_printf(&sc->sc_ic.ic_if,
2258 "can't allocate %dth RX buffer\n", i);
2259 return error;
2260 }
2261 }
2262 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2263 BUS_DMASYNC_PREWRITE);
2264
2265 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2266 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2267 return 0;
2268 }
2269
2270 static int
2271 bwi_init_txstats32(struct bwi_softc *sc)
2272 {
2273 struct bwi_txstats_data *st = sc->sc_txstats;
2274 bus_addr_t stats_paddr;
2275 int i;
2276
2277 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2278 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2279
2280 st->stats_idx = 0;
2281
2282 stats_paddr = st->stats_paddr;
2283 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2284 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2285 stats_paddr, sizeof(struct bwi_txstats), 0);
2286 stats_paddr += sizeof(struct bwi_txstats);
2287 }
2288 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2289 BUS_DMASYNC_PREWRITE);
2290
2291 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2292 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2293 return 0;
2294 }
2295
2296 static void
2297 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2298 int buf_len)
2299 {
2300 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2301
2302 KKASSERT(buf_idx < BWI_RX_NDESC);
2303 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2304 paddr, buf_len, 0);
2305 }
2306
2307 static void
2308 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2309 int buf_idx, bus_addr_t paddr, int buf_len)
2310 {
2311 KKASSERT(buf_idx < BWI_TX_NDESC);
2312 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2313 paddr, buf_len, 1);
2314 }
2315
2316 static int
2317 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2318 {
2319 /* TODO:64 */
2320 return EOPNOTSUPP;
2321 }
2322
2323 static int
2324 bwi_init_rx_ring64(struct bwi_softc *sc)
2325 {
2326 /* TODO:64 */
2327 return EOPNOTSUPP;
2328 }
2329
2330 static int
2331 bwi_init_txstats64(struct bwi_softc *sc)
2332 {
2333 /* TODO:64 */
2334 return EOPNOTSUPP;
2335 }
2336
2337 static void
2338 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2339 int buf_len)
2340 {
2341 /* TODO:64 */
2342 }
2343
2344 static void
2345 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2346 int buf_idx, bus_addr_t paddr, int buf_len)
2347 {
2348 /* TODO:64 */
2349 }
2350
2351 static void
2352 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2353 bus_size_t mapsz __unused, int error)
2354 {
2355 if (!error) {
2356 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2357 *((bus_addr_t *)arg) = seg->ds_addr;
2358 }
2359 }
2360
2361 static int
2362 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2363 {
2364 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2365 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2366 struct bwi_rxbuf_hdr *hdr;
2367 bus_dmamap_t map;
2368 bus_addr_t paddr;
2369 struct mbuf *m;
2370 int error;
2371
2372 KKASSERT(buf_idx < BWI_RX_NDESC);
2373
2374 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2375 if (m == NULL) {
2376 error = ENOBUFS;
2377
2378 /*
2379 * If the NIC is up and running, we need to:
2380 * - Clear RX buffer's header.
2381 * - Restore RX descriptor settings.
2382 */
2383 if (init)
2384 return error;
2385 else
2386 goto back;
2387 }
2388 m->m_len = m->m_pkthdr.len = MCLBYTES;
2389
2390 /*
2391 * Try to load RX buf into temporary DMA map
2392 */
2393 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2394 bwi_dma_buf_addr, &paddr,
2395 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2396 if (error) {
2397 m_freem(m);
2398
2399 /*
2400 * See the comment above
2401 */
2402 if (init)
2403 return error;
2404 else
2405 goto back;
2406 }
2407
2408 if (!init)
2409 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2410 rxbuf->rb_mbuf = m;
2411 rxbuf->rb_paddr = paddr;
2412
2413 /*
2414 * Swap RX buf's DMA map with the loaded temporary one
2415 */
2416 map = rxbuf->rb_dmap;
2417 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2418 rbd->rbd_tmp_dmap = map;
2419
2420 back:
2421 /*
2422 * Clear RX buf header
2423 */
2424 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2425 bzero(hdr, sizeof(*hdr));
2426 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2427
2428 /*
2429 * Setup RX buf descriptor
2430 */
2431 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2432 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2433 return error;
2434 }
2435
2436 static void
2437 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2438 const uint8_t *addr)
2439 {
2440 int i;
2441
2442 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2443 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2444
2445 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2446 uint16_t addr_val;
2447
2448 addr_val = (uint16_t)addr[i * 2] |
2449 (((uint16_t)addr[(i * 2) + 1]) << 8);
2450 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2451 }
2452 }
2453
2454 static int
2455 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2456 {
2457 struct ieee80211com *ic = &sc->sc_ic;
2458 struct ifnet *ifp = &ic->ic_if;
2459 struct bwi_mac *mac;
2460 uint16_t flags;
2461 u_int chan;
2462
2463 ASSERT_SERIALIZED(ifp->if_serializer);
2464
2465 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2466 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2467
2468 chan = ieee80211_chan2ieee(ic, c);
2469
2470 bwi_rf_set_chan(mac, chan, 0);
2471
2472 /*
2473 * Setup radio tap channel freq and flags
2474 */
2475 if (IEEE80211_IS_CHAN_G(c))
2476 flags = IEEE80211_CHAN_G;
2477 else
2478 flags = IEEE80211_CHAN_B;
2479
2480 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2481 htole16(c->ic_freq);
2482 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2483 htole16(flags);
2484
2485 return 0;
2486 }
2487
2488 static void
2489 bwi_next_scan(void *xsc)
2490 {
2491 struct bwi_softc *sc = xsc;
2492 struct ieee80211com *ic = &sc->sc_ic;
2493 struct ifnet *ifp = &ic->ic_if;
2494
2495 lwkt_serialize_enter(ifp->if_serializer);
2496
2497 if (ic->ic_state == IEEE80211_S_SCAN)
2498 ieee80211_next_scan(ic);
2499
2500 lwkt_serialize_exit(ifp->if_serializer);
2501 }
2502
2503 static void
2504 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2505 {
2506 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2507 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2508 struct ieee80211com *ic = &sc->sc_ic;
2509 struct ifnet *ifp = &ic->ic_if;
2510 int idx;
2511
2512 idx = rbd->rbd_idx;
2513 while (idx != end_idx) {
2514 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2515 struct bwi_rxbuf_hdr *hdr;
2516 struct ieee80211_frame_min *wh;
2517 struct ieee80211_node *ni;
2518 struct mbuf *m;
2519 const uint8_t *plcp;
2520 uint16_t flags2;
2521 int buflen, wh_ofs, hdr_extra, rssi;
2522
2523 m = rb->rb_mbuf;
2524 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2525 BUS_DMASYNC_POSTREAD);
2526
2527 if (bwi_newbuf(sc, idx, 0)) {
2528 ifp->if_ierrors++;
2529 goto next;
2530 }
2531
2532 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2533 flags2 = le16toh(hdr->rxh_flags2);
2534
2535 hdr_extra = 0;
2536 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2537 hdr_extra = 2;
2538 wh_ofs = hdr_extra + 6; /* XXX magic number */
2539
2540 buflen = le16toh(hdr->rxh_buflen);
2541 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2542 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2543 buflen, hdr_extra);
2544 ifp->if_ierrors++;
2545 m_freem(m);
2546 goto next;
2547 }
2548
2549 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2550 rssi = bwi_calc_rssi(sc, hdr);
2551
2552 m->m_pkthdr.rcvif = ifp;
2553 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2554 m_adj(m, sizeof(*hdr) + wh_ofs);
2555
2556 /* RX radio tap */
2557 if (sc->sc_drvbpf != NULL)
2558 bwi_rx_radiotap(sc, m, hdr, plcp, rssi);
2559
2560 m_adj(m, -IEEE80211_CRC_LEN);
2561
2562 wh = mtod(m, struct ieee80211_frame_min *);
2563 ni = ieee80211_find_rxnode(ic, wh);
2564
2565 ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2566 le16toh(hdr->rxh_tsf));
2567 ieee80211_free_node(ni);
2568 next:
2569 idx = (idx + 1) % BWI_RX_NDESC;
2570 }
2571
2572 rbd->rbd_idx = idx;
2573 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2574 BUS_DMASYNC_PREWRITE);
2575 }
2576
2577 static void
2578 bwi_rxeof32(struct bwi_softc *sc)
2579 {
2580 uint32_t val, rx_ctrl;
2581 int end_idx;
2582
2583 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2584
2585 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2586 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2587 sizeof(struct bwi_desc32);
2588
2589 bwi_rxeof(sc, end_idx);
2590
2591 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2592 end_idx * sizeof(struct bwi_desc32));
2593 }
2594
2595 static void
2596 bwi_rxeof64(struct bwi_softc *sc)
2597 {
2598 /* TODO:64 */
2599 }
2600
2601 static void
2602 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2603 {
2604 int i;
2605
2606 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2607
2608 #define NRETRY 10
2609
2610 for (i = 0; i < NRETRY; ++i) {
2611 uint32_t status;
2612
2613 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2614 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2615 BWI_RX32_STATUS_STATE_DISABLED)
2616 break;
2617
2618 DELAY(1000);
2619 }
2620 if (i == NRETRY)
2621 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2622
2623 #undef NRETRY
2624
2625 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2626 }
2627
2628 static void
2629 bwi_free_txstats32(struct bwi_softc *sc)
2630 {
2631 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2632 }
2633
2634 static void
2635 bwi_free_rx_ring32(struct bwi_softc *sc)
2636 {
2637 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2638 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2639 int i;
2640
2641 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2642
2643 for (i = 0; i < BWI_RX_NDESC; ++i) {
2644 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2645
2646 if (rb->rb_mbuf != NULL) {
2647 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2648 m_freem(rb->rb_mbuf);
2649 rb->rb_mbuf = NULL;
2650 }
2651 }
2652 }
2653
2654 static void
2655 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2656 {
2657 struct bwi_ring_data *rd;
2658 struct bwi_txbuf_data *tbd;
2659 struct ifnet *ifp = &sc->sc_ic.ic_if;
2660 uint32_t state, val;
2661 int i;
2662
2663 KKASSERT(ring_idx < BWI_TX_NRING);
2664 rd = &sc->sc_tx_rdata[ring_idx];
2665 tbd = &sc->sc_tx_bdata[ring_idx];
2666
2667 #define NRETRY 10
2668
2669 for (i = 0; i < NRETRY; ++i) {
2670 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2671 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2672 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2673 state == BWI_TX32_STATUS_STATE_IDLE ||
2674 state == BWI_TX32_STATUS_STATE_STOPPED)
2675 break;
2676
2677 DELAY(1000);
2678 }
2679 if (i == NRETRY) {
2680 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2681 ring_idx);
2682 }
2683
2684 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2685 for (i = 0; i < NRETRY; ++i) {
2686 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2687 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2688 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2689 break;
2690
2691 DELAY(1000);
2692 }
2693 if (i == NRETRY)
2694 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2695
2696 #undef NRETRY
2697
2698 DELAY(1000);
2699
2700 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2701
2702 for (i = 0; i < BWI_TX_NDESC; ++i) {
2703 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2704
2705 if (tb->tb_mbuf != NULL) {
2706 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2707 m_freem(tb->tb_mbuf);
2708 tb->tb_mbuf = NULL;
2709 }
2710 if (tb->tb_ni != NULL) {
2711 ieee80211_free_node(tb->tb_ni);
2712 tb->tb_ni = NULL;
2713 }
2714 }
2715 }
2716
2717 static void
2718 bwi_free_txstats64(struct bwi_softc *sc)
2719 {
2720 /* TODO:64 */
2721 }
2722
2723 static void
2724 bwi_free_rx_ring64(struct bwi_softc *sc)
2725 {
2726 /* TODO:64 */
2727 }
2728
2729 static void
2730 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2731 {
2732 /* TODO:64 */
2733 }
2734
2735 /* XXX does not belong here */
2736 uint8_t
2737 bwi_rate2plcp(uint8_t rate)
2738 {
2739 rate &= IEEE80211_RATE_VAL;
2740
2741 switch (rate) {
2742 case 2: return 0xa;
2743 case 4: return 0x14;
2744 case 11: return 0x37;
2745 case 22: return 0x6e;
2746 case 44: return 0xdc;
2747
2748 case 12: return 0xb;
2749 case 18: return 0xf;
2750 case 24: return 0xa;
2751 case 36: return 0xe;
2752 case 48: return 0x9;
2753 case 72: return 0xd;
2754 case 96: return 0x8;
2755 case 108: return 0xc;
2756
2757 default:
2758 panic("unsupported rate %u\n", rate);
2759 }
2760 }
2761
2762 /* XXX does not belong here */
2763 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2764 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2765
2766 static __inline void
2767 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2768 {
2769 uint32_t plcp;
2770
2771 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
2772 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2773 *plcp0 = htole32(plcp);
2774 }
2775
2776 /* XXX does not belong here */
2777 struct ieee80211_ds_plcp_hdr {
2778 uint8_t i_signal;
2779 uint8_t i_service;
2780 uint16_t i_length;
2781 uint16_t i_crc;
2782 } __packed;
2783
2784 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
2785 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
2786 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
2787 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
2788 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
2789
2790 static __inline void
2791 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2792 uint8_t rate)
2793 {
2794 int len, service, pkt_bitlen;
2795
2796 pkt_bitlen = pkt_len * NBBY;
2797 len = howmany(pkt_bitlen * 2, rate);
2798
2799 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
2800 if (rate == (11 * 2)) {
2801 int pkt_bitlen1;
2802
2803 /*
2804 * PLCP service field needs to be adjusted,
2805 * if TX rate is 11Mbytes/s
2806 */
2807 pkt_bitlen1 = len * 11;
2808 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2809 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
2810 }
2811
2812 plcp->i_signal = bwi_rate2plcp(rate);
2813 plcp->i_service = service;
2814 plcp->i_length = htole16(len);
2815 /* NOTE: do NOT touch i_crc */
2816 }
2817
2818 static __inline void
2819 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
2820 {
2821 enum ieee80211_modtype modtype;
2822
2823 /*
2824 * Assume caller has zeroed 'plcp'
2825 */
2826
2827 modtype = ieee80211_rate2modtype(rate);
2828 if (modtype == IEEE80211_MODTYPE_OFDM)
2829 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2830 else if (modtype == IEEE80211_MODTYPE_DS)
2831 bwi_ds_plcp_header(plcp, pkt_len, rate);
2832 else
2833 panic("unsupport modulation type %u\n", modtype);
2834 }
2835
2836 static int
2837 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2838 struct ieee80211_node **ni0, int mgt_pkt)
2839 {
2840 struct ieee80211com *ic = &sc->sc_ic;
2841 struct ieee80211_node *ni = *ni0;
2842 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2843 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2844 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2845 struct bwi_mac *mac;
2846 struct bwi_txbuf_hdr *hdr;
2847 struct ieee80211_frame *wh;
2848 uint8_t rate, rate_fb;
2849 uint32_t mac_ctrl;
2850 uint16_t phy_ctrl;
2851 bus_addr_t paddr;
2852 int pkt_len, error, mcast_pkt = 0;
2853 #if 0
2854 const uint8_t *p;
2855 int i;
2856 #endif
2857
2858 KKASSERT(ni != NULL);
2859 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2860 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2861
2862 wh = mtod(m, struct ieee80211_frame *);
2863
2864 /* Get 802.11 frame len before prepending TX header */
2865 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2866
2867 /*
2868 * Find TX rate
2869 */
2870 bzero(tb->tb_rate_idx, sizeof(tb->tb_rate_idx));
2871 if (!mgt_pkt) {
2872 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
2873 int idx;
2874
2875 rate = IEEE80211_RS_RATE(&ni->ni_rates,
2876 ic->ic_fixed_rate);
2877
2878 if (ic->ic_fixed_rate >= 1)
2879 idx = ic->ic_fixed_rate - 1;
2880 else
2881 idx = 0;
2882 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
2883 } else {
2884 /* TODO: TX rate control */
2885 rate = rate_fb = (1 * 2);
2886 }
2887 } else {
2888 /* Fixed at 1Mbits/s for mgt frames */
2889 rate = rate_fb = (1 * 2);
2890 }
2891
2892 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2893 rate = rate_fb = ic->ic_mcast_rate;
2894 mcast_pkt = 1;
2895 }
2896
2897 if (rate == 0 || rate_fb == 0) {
2898 /* XXX this should not happen */
2899 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
2900 rate, rate_fb);
2901 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
2902 }
2903
2904 /*
2905 * TX radio tap
2906 */
2907 if (sc->sc_drvbpf != NULL) {
2908 sc->sc_tx_th.wt_flags = 0;
2909 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
2910 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2911 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
2912 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
2913 rate != (1 * 2)) {
2914 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2915 }
2916 sc->sc_tx_th.wt_rate = rate;
2917
2918 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
2919 }
2920
2921 /*
2922 * Setup the embedded TX header
2923 */
2924 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
2925 if (m == NULL) {
2926 if_printf(&ic->ic_if, "prepend TX header failed\n");
2927 return ENOBUFS;
2928 }
2929 hdr = mtod(m, struct bwi_txbuf_hdr *);
2930
2931 bzero(hdr, sizeof(*hdr));
2932
2933 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
2934 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
2935
2936 if (!mcast_pkt) {
2937 uint16_t dur;
2938 uint8_t ack_rate;
2939
2940 ack_rate = ieee80211_ack_rate(ni, rate_fb);
2941 dur = ieee80211_txtime(ni,
2942 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
2943 ack_rate, ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
2944
2945 hdr->txh_fb_duration = htole16(dur);
2946 }
2947
2948 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
2949 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
2950
2951 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
2952 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
2953
2954 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
2955 BWI_TXH_PHY_C_ANTMODE_MASK);
2956 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
2957 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
2958 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
2959 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
2960
2961 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
2962 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
2963 mac_ctrl |= BWI_TXH_MAC_C_ACK;
2964 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
2965 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
2966
2967 hdr->txh_mac_ctrl = htole32(mac_ctrl);
2968 hdr->txh_phy_ctrl = htole16(phy_ctrl);
2969
2970 /* Catch any further usage */
2971 hdr = NULL;
2972 wh = NULL;
2973
2974 /* DMA load */
2975 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
2976 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2977 if (error && error != EFBIG) {
2978 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
2979 goto back;
2980 }
2981
2982 if (error) { /* error == EFBIG */
2983 struct mbuf *m_new;
2984
2985 m_new = m_defrag(m, MB_DONTWAIT);
2986 if (m_new == NULL) {
2987 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
2988 error = ENOBUFS;
2989 goto back;
2990 } else {
2991 m = m_new;
2992 }
2993
2994 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
2995 bwi_dma_buf_addr, &paddr,
2996 BUS_DMA_NOWAIT);
2997 if (error) {
2998 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
2999 error);
3000 goto back;
3001 }
3002 }
3003 error = 0;
3004
3005 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3006
3007 if (mgt_pkt || mcast_pkt) {
3008 /* Don't involve mcast/mgt packets into TX rate control */
3009 ieee80211_free_node(ni);
3010 *ni0 = ni = NULL;
3011 }
3012 tb->tb_mbuf = m;
3013 tb->tb_ni = ni;
3014
3015 #if 0
3016 p = mtod(m, const uint8_t *);
3017 for (i = 0; i < m->m_pkthdr.len; ++i) {
3018 if (i != 0 && i % 8 == 0)
3019 kprintf("\n");
3020 kprintf("%02x ", p[i]);
3021 }
3022 kprintf("\n");
3023 #endif
3024
3025 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3026 idx, pkt_len, m->m_pkthdr.len);
3027
3028 /* Setup TX descriptor */
3029 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3030 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3031 BUS_DMASYNC_PREWRITE);
3032
3033 /* Kick start */
3034 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3035
3036 back:
3037 if (error)
3038 m_freem(m);
3039 return error;
3040 }
3041
3042 static void
3043 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3044 {
3045 idx = (idx + 1) % BWI_TX_NDESC;
3046 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3047 idx * sizeof(struct bwi_desc32));
3048 }
3049
3050 static void
3051 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3052 {
3053 /* TODO:64 */
3054 }
3055
3056 static void
3057 bwi_txeof_status32(struct bwi_softc *sc)
3058 {
3059 struct ifnet *ifp = &sc->sc_ic.ic_if;
3060 uint32_t val, ctrl_base;
3061 int end_idx;
3062
3063 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3064
3065 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3066 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3067 sizeof(struct bwi_desc32);
3068
3069 bwi_txeof_status(sc, end_idx);
3070
3071 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3072 end_idx * sizeof(struct bwi_desc32));
3073
3074 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3075 ifp->if_start(ifp);
3076 }
3077
3078 static void
3079 bwi_txeof_status64(struct bwi_softc *sc)
3080 {
3081 /* TODO:64 */
3082 }
3083
3084 static void
3085 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3086 {
3087 struct ifnet *ifp = &sc->sc_ic.ic_if;
3088 struct bwi_txbuf_data *tbd;
3089 struct bwi_txbuf *tb;
3090 int ring_idx, buf_idx;
3091
3092 if (tx_id == 0) {
3093 if_printf(ifp, "zero tx id\n");
3094 return;
3095 }
3096
3097 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3098 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3099
3100 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3101 KKASSERT(buf_idx < BWI_TX_NDESC);
3102
3103 tbd = &sc->sc_tx_bdata[ring_idx];
3104 KKASSERT(tbd->tbd_used > 0);
3105 tbd->tbd_used--;
3106
3107 tb = &tbd->tbd_buf[buf_idx];
3108
3109 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3110 "acked %d, data_txcnt %d, ni %p\n",
3111 buf_idx, acked, data_txcnt, tb->tb_ni);
3112
3113 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3114 m_freem(tb->tb_mbuf);
3115 tb->tb_mbuf = NULL;
3116
3117 if (tb->tb_ni != NULL) {
3118 /* Feed back 'acked and data_txcnt' */
3119 ieee80211_free_node(tb->tb_ni);
3120 tb->tb_ni = NULL;
3121 }
3122
3123 if (tbd->tbd_used == 0)
3124 sc->sc_tx_timer = 0;
3125
3126 ifp->if_flags &= ~IFF_OACTIVE;
3127 }
3128
3129 static void
3130 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3131 {
3132 struct bwi_txstats_data *st = sc->sc_txstats;
3133 int idx;
3134
3135 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3136
3137 idx = st->stats_idx;
3138 while (idx != end_idx) {
3139 const struct bwi_txstats *stats = &st->stats[idx];
3140
3141 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3142 int data_txcnt;
3143
3144 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3145 BWI_TXS_TXCNT_DATA);
3146 _bwi_txeof(sc, le16toh(stats->txs_id),
3147 stats->txs_flags & BWI_TXS_F_ACKED,
3148 data_txcnt);
3149 }
3150 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3151 }
3152 st->stats_idx = idx;
3153 }
3154
3155 static void
3156 bwi_txeof(struct bwi_softc *sc)
3157 {
3158 struct ifnet *ifp = &sc->sc_ic.ic_if;
3159
3160 for (;;) {
3161 uint32_t tx_status0, tx_status1;
3162 uint16_t tx_id;
3163 int data_txcnt;
3164
3165 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3166 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3167 break;
3168 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3169
3170 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3171 data_txcnt = __SHIFTOUT(tx_status0,
3172 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3173
3174 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3175 continue;
3176
3177 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3178 data_txcnt);
3179 }
3180
3181 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3182 ifp->if_start(ifp);
3183 }
3184
3185 static int
3186 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3187 {
3188 bwi_power_on(sc, 1);
3189 return bwi_set_clock_mode(sc, clk_mode);
3190 }
3191
3192 static void
3193 bwi_bbp_power_off(struct bwi_softc *sc)
3194 {
3195 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3196 bwi_power_off(sc, 1);
3197 }
3198
3199 static int
3200 bwi_get_pwron_delay(struct bwi_softc *sc)
3201 {
3202 struct bwi_regwin *com, *old;
3203 struct bwi_clock_freq freq;
3204 uint32_t val;
3205 int error;
3206
3207 com = &sc->sc_com_regwin;
3208 KKASSERT(BWI_REGWIN_EXIST(com));
3209
3210 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3211 return 0;
3212
3213 error = bwi_regwin_switch(sc, com, &old);
3214 if (error)
3215 return error;
3216
3217 bwi_get_clock_freq(sc, &freq);
3218
3219 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3220 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3221 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3222
3223 return bwi_regwin_switch(sc, old, NULL);
3224 }
3225
3226 static int
3227 bwi_bus_attach(struct bwi_softc *sc)
3228 {
3229 struct bwi_regwin *bus, *old;
3230 int error;
3231
3232 bus = &sc->sc_bus_regwin;
3233
3234 error = bwi_regwin_switch(sc, bus, &old);
3235 if (error)
3236 return error;
3237
3238 if (!bwi_regwin_is_enabled(sc, bus))
3239 bwi_regwin_enable(sc, bus, 0);
3240
3241 /* Disable interripts */
3242 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3243
3244 return bwi_regwin_switch(sc, old, NULL);
3245 }
3246
3247 static const char *
3248 bwi_regwin_name(const struct bwi_regwin *rw)
3249 {
3250 switch (rw->rw_type) {
3251 case BWI_REGWIN_T_COM:
3252 return "COM";
3253 case BWI_REGWIN_T_BUSPCI:
3254 return "PCI";
3255 case BWI_REGWIN_T_MAC:
3256 return "MAC";
3257 case BWI_REGWIN_T_BUSPCIE:
3258 return "PCIE";
3259 }
3260 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3261 return NULL;
3262 }
3263
3264 static uint32_t
3265 bwi_regwin_disable_bits(struct bwi_softc *sc)
3266 {
3267 uint32_t busrev;
3268
3269 /* XXX cache this */
3270 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3271 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3272 "bus rev %u\n", busrev);
3273
3274 if (busrev == BWI_BUSREV_0)
3275 return BWI_STATE_LO_DISABLE1;
3276 else if (busrev == BWI_BUSREV_1)
3277 return BWI_STATE_LO_DISABLE2;
3278 else
3279 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3280 }
3281
3282 int
3283 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3284 {
3285 uint32_t val, disable_bits;
3286
3287 disable_bits = bwi_regwin_disable_bits(sc);
3288 val = CSR_READ_4(sc, BWI_STATE_LO);
3289
3290 if ((val & (BWI_STATE_LO_CLOCK |
3291 BWI_STATE_LO_RESET |
3292 disable_bits)) == BWI_STATE_LO_CLOCK) {
3293 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3294 bwi_regwin_name(rw));
3295 return 1;
3296 } else {
3297 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3298 bwi_regwin_name(rw));
3299 return 0;
3300 }
3301 }
3302
3303 void
3304 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3305 {
3306 uint32_t state_lo, disable_bits;
3307 int i;
3308
3309 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3310
3311 /*
3312 * If current regwin is in 'reset' state, it was already disabled.
3313 */
3314 if (state_lo & BWI_STATE_LO_RESET) {
3315 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3316 "%s was already disabled\n", bwi_regwin_name(rw));
3317 return;
3318 }
3319
3320 disable_bits = bwi_regwin_disable_bits(sc);
3321
3322 /*
3323 * Disable normal clock
3324 */
3325 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3326 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3327
3328 /*
3329 * Wait until normal clock is disabled
3330 */
3331 #define NRETRY 1000
3332 for (i = 0; i < NRETRY; ++i) {
3333 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3334 if (state_lo & disable_bits)
3335 break;
3336 DELAY(10);
3337 }
3338 if (i == NRETRY) {
3339 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3340 bwi_regwin_name(rw));
3341 }
3342
3343 for (i = 0; i < NRETRY; ++i) {
3344 uint32_t state_hi;
3345
3346 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3347 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3348 break;
3349 DELAY(10);
3350 }
3351 if (i == NRETRY) {
3352 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3353 bwi_regwin_name(rw));
3354 }
3355 #undef NRETRY
3356
3357 /*
3358 * Reset and disable regwin with gated clock
3359 */
3360 state_lo = BWI_STATE_LO_RESET | disable_bits |
3361 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3362 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3363 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3364
3365 /* Flush pending bus write */
3366 CSR_READ_4(sc, BWI_STATE_LO);
3367 DELAY(1);
3368
3369 /* Reset and disable regwin */
3370 state_lo = BWI_STATE_LO_RESET | disable_bits |
3371 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3372 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3373
3374 /* Flush pending bus write */
3375 CSR_READ_4(sc, BWI_STATE_LO);
3376 DELAY(1);
3377 }
3378
3379 void
3380 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3381 {
3382 uint32_t state_lo, state_hi, imstate;
3383
3384 bwi_regwin_disable(sc, rw, flags);
3385
3386 /* Reset regwin with gated clock */
3387 state_lo = BWI_STATE_LO_RESET |
3388 BWI_STATE_LO_CLOCK |
3389 BWI_STATE_LO_GATED_CLOCK |
3390 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3391 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3392
3393 /* Flush pending bus write */
3394 CSR_READ_4(sc, BWI_STATE_LO);
3395 DELAY(1);
3396
3397 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3398 if (state_hi & BWI_STATE_HI_SERROR)
3399 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3400
3401 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3402 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3403 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3404 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3405 }
3406
3407 /* Enable regwin with gated clock */
3408 state_lo = BWI_STATE_LO_CLOCK |
3409 BWI_STATE_LO_GATED_CLOCK |
3410 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3411 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3412
3413 /* Flush pending bus write */
3414 CSR_READ_4(sc, BWI_STATE_LO);
3415 DELAY(1);
3416
3417 /* Enable regwin with normal clock */
3418 state_lo = BWI_STATE_LO_CLOCK |
3419 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3420 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3421
3422 /* Flush pending bus write */
3423 CSR_READ_4(sc, BWI_STATE_LO);
3424 DELAY(1);
3425 }
3426
3427 static void
3428 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3429 {
3430 struct ieee80211com *ic = &sc->sc_ic;
3431 struct bwi_mac *mac;
3432 struct bwi_myaddr_bssid buf;
3433 const uint8_t *p;
3434 uint32_t val;
3435 int n, i;
3436
3437 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3438 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3439
3440 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3441
3442 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3443 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3444
3445 n = sizeof(buf) / sizeof(val);
3446 p = (const uint8_t *)&buf;
3447 for (i = 0; i < n; ++i) {
3448 int j;
3449
3450 val = 0;
3451 for (j = 0; j < sizeof(val); ++j)
3452 val |= ((uint32_t)(*p++)) << (j * 8);
3453
3454 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3455 }
3456 }
3457
3458 static void
3459 bwi_updateslot(struct ifnet *ifp)
3460 {
3461 struct bwi_softc *sc = ifp->if_softc;
3462 struct ieee80211com *ic = &sc->sc_ic;
3463 struct bwi_mac *mac;
3464
3465 if ((ifp->if_flags & IFF_RUNNING) == 0)
3466 return;
3467
3468 ASSERT_SERIALIZED(ifp->if_serializer);
3469
3470 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3471
3472 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3473 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3474
3475 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3476 }
3477
3478 static void
3479 bwi_calibrate(void *xsc)
3480 {
3481 struct bwi_softc *sc = xsc;
3482 struct ieee80211com *ic = &sc->sc_ic;
3483 struct ifnet *ifp = &ic->ic_if;
3484
3485 lwkt_serialize_enter(ifp->if_serializer);
3486
3487 if (ic->ic_state == IEEE80211_S_RUN) {
3488 struct bwi_mac *mac;
3489
3490 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3491 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3492
3493 if (ic->ic_opmode != IEEE80211_M_MONITOR)
3494 bwi_mac_calibrate_txpower(mac);
3495
3496 /* XXX 15 seconds */
3497 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3498 }
3499
3500 lwkt_serialize_exit(ifp->if_serializer);
3501 }
3502
3503 static int
3504 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3505 {
3506 struct bwi_mac *mac;
3507
3508 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3509 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3510
3511 return bwi_rf_calc_rssi(mac, hdr);
3512 }
3513
3514 static __inline uint8_t
3515 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
3516 {
3517 uint32_t plcp;
3518 uint8_t plcp_rate;
3519
3520 plcp = le32toh(*plcp0);
3521 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
3522 return ieee80211_plcp2rate(plcp_rate, 1);
3523 }
3524
3525 static __inline uint8_t
3526 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
3527 {
3528 return ieee80211_plcp2rate(hdr->i_signal, 0);
3529 }
3530
3531 static void
3532 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3533 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rssi)
3534 {
3535 const struct ieee80211_frame_min *wh;
3536 uint16_t flags1;
3537 uint8_t rate;
3538
3539 KKASSERT(sc->sc_drvbpf != NULL);
3540
3541 flags1 = htole16(hdr->rxh_flags1);
3542 if (flags1 & BWI_RXH_F1_OFDM)
3543 rate = bwi_ofdm_plcp2rate(plcp);
3544 else
3545 rate = bwi_ds_plcp2rate(plcp);
3546
3547 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3548 if (flags1 & BWI_RXH_F1_SHPREAMBLE)
3549 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3550
3551 wh = mtod(m, const struct ieee80211_frame_min *);
3552 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3553 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3554
3555 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3556 sc->sc_rx_th.wr_rate = rate;
3557 sc->sc_rx_th.wr_antsignal = rssi;
3558 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3559
3560 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3561 }
A repo for keeping AMD64 port code before merging with the master