2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/amd64/amd64/initcpu.c,v 1.50 2006/06/19 22:59:28 davidxu Exp $
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
47 static int hw_instruction_sse
;
48 SYSCTL_INT(_hw
, OID_AUTO
, instruction_sse
, CTLFLAG_RD
,
49 &hw_instruction_sse
, 0, "SIMD/MMX2 instructions available in CPU");
51 int cpu
; /* Are we 386, 386sx, 486, etc? */
52 u_int cpu_feature
; /* Feature flags */
53 u_int cpu_feature2
; /* Feature flags */
54 u_int amd_feature
; /* AMD feature flags */
55 u_int amd_feature2
; /* AMD feature flags */
56 u_int cpu_high
; /* Highest arg to CPUID */
57 u_int cpu_exthigh
; /* Highest arg to extended CPUID */
58 u_int cpu_id
; /* Stepping ID */
59 u_int cpu_procinfo
; /* HyperThreading Info / Brand Index / CLFUSH */
60 u_int cpu_procinfo2
; /* Multicore info */
61 char cpu_vendor
[20]; /* CPU Origin code */
62 u_int cpu_fxsr
; /* SSE enabled */
63 u_int cpu_mxcsr_mask
; /* Valid bits in mxcsr */
66 * Initialize CPU control registers
73 if ((cpu_feature
& CPUID_XMM
) && (cpu_feature
& CPUID_FXSR
)) {
74 load_cr4(rcr4() | CR4_FXSR
| CR4_XMM
);
75 cpu_fxsr
= hw_instruction_sse
= 1;
77 if ((amd_feature
& AMDID_NX
) != 0) {
78 msr
= rdmsr(MSR_EFER
) | EFER_NXE
;