sys/dev/powermng/ichsmb/ichsmb_pci.c

   1
   2 /*
   3  * ichsmb_pci.c
   4  *
   5  * Copyright (c) 2000 Whistle Communications, Inc.
   6  * All rights reserved.
   7  *
   8  * Subject to the following obligations and disclaimer of warranty, use and
   9  * redistribution of this software, in source or object code forms, with or
  10  * without modifications are expressly permitted by Whistle Communications;
  11  * provided, however, that:
  12  * 1. Any and all reproductions of the source or object code must include the
  13  *    copyright notice above and the following disclaimer of warranties; and
  14  * 2. No rights are granted, in any manner or form, to use Whistle
  15  *    Communications, Inc. trademarks, including the mark "WHISTLE
  16  *    COMMUNICATIONS" on advertising, endorsements, or otherwise except as
  17  *    such appears in the above copyright notice or in the software.
  18  *
  19  * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
  20  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
  21  * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
  22  * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  24  * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
  25  * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
  26  * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
  27  * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
  28  * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
  29  * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  30  * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
  31  * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
  32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  34  * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
  35  * OF SUCH DAMAGE.
  36  *
  37  * Author: Archie Cobbs <archie@freebsd.org>
  38  *
  39  * $FreeBSD: src/sys/dev/ichsmb/ichsmb_pci.c,v 1.1.2.3 2002/10/20 14:57:19 nyan Exp $
  40  * $DragonFly: src/sys/dev/powermng/ichsmb/ichsmb_pci.c,v 1.9 2007/09/23 22:06:10 hasso Exp $
  41  */
  42
  43 /*
  44  * Support for the SMBus controller logical device which is part of the
  45  * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips.
  46  */
  47
  48 #include <sys/param.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/errno.h>
  52 #include <sys/syslog.h>
  53 #include <sys/bus.h>
  54 #include <sys/rman.h>
  55
  56 #include <bus/pci/pcivar.h>
  57 #include <bus/pci/pcireg.h>
  58
  59 #include <bus/smbus/smbconf.h>
  60
  61 #include "ichsmb_var.h"
  62 #include "ichsmb_reg.h"
  63
  64 /* PCI unique identifiers */
  65 #define ID_6300ESB                      0x25A48086
  66 #define ID_63xxESB                      0x269B8086
  67 #define ID_82801AA                      0x24138086
  68 #define ID_82801AB                      0x24238086
  69 #define ID_82801BA                      0x24438086
  70 #define ID_82801E                       0x24538086
  71 #define ID_82801CA                      0x24838086
  72 #define ID_82801DB                      0x24C38086
  73 #define ID_82801EB                      0x24D38086
  74 #define ID_82801FB                      0x266A8086
  75 #define ID_82801G                       0x27DA8086
  76 #define ID_82801H                       0x283E8086
  77 #define ID_82801I                       0x29308086
  78
  79 #define PCIS_SERIALBUS_SMBUS_PROGIF     0x00
  80
  81 /* Internal functions */
  82 static int      ichsmb_pci_probe(device_t dev);
  83 static int      ichsmb_pci_attach(device_t dev);
  84
  85 /* Device methods */
  86 static device_method_t ichsmb_pci_methods[] = {
  87         /* Device interface */
  88         DEVMETHOD(device_probe, ichsmb_pci_probe),
  89         DEVMETHOD(device_attach, ichsmb_pci_attach),
  90
  91         /* Bus methods */
  92         DEVMETHOD(bus_print_child, bus_generic_print_child),
  93
  94         /* SMBus methods */
  95         DEVMETHOD(smbus_callback, ichsmb_callback),
  96         DEVMETHOD(smbus_quick, ichsmb_quick),
  97         DEVMETHOD(smbus_sendb, ichsmb_sendb),
  98         DEVMETHOD(smbus_recvb, ichsmb_recvb),
  99         DEVMETHOD(smbus_writeb, ichsmb_writeb),
 100         DEVMETHOD(smbus_writew, ichsmb_writew),
 101         DEVMETHOD(smbus_readb, ichsmb_readb),
 102         DEVMETHOD(smbus_readw, ichsmb_readw),
 103         DEVMETHOD(smbus_pcall, ichsmb_pcall),
 104         DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
 105         DEVMETHOD(smbus_bread, ichsmb_bread),
 106         { 0, 0 }
 107 };
 108
 109 static driver_t ichsmb_pci_driver = {
 110         "ichsmb",
 111         ichsmb_pci_methods,
 112         sizeof(struct ichsmb_softc)
 113 };
 114
 115 static devclass_t ichsmb_pci_devclass;
 116
 117 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0);
 118
 119 static int
 120 ichsmb_pci_probe(device_t dev)
 121 {
 122         /* Check PCI identifier */
 123         switch (pci_get_devid(dev)) {
 124         case ID_6300ESB:
 125                 device_set_desc(dev, "Intel 6300ESB (ESB) SMBus controller");
 126                 break;
 127         case ID_63xxESB:
 128                 device_set_desc(dev, "Intel 63xxESB (ESB2) SMBus controller");
 129                 break;
 130         case ID_82801AA:
 131                 device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller");
 132                 break;
 133         case ID_82801AB:
 134                 device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller");
 135                 break;
 136         case ID_82801BA:
 137                 device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller");
 138                 break;
 139         case ID_82801CA:
 140                 device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller");
 141                 break;
 142         case ID_82801DB:
 143                 device_set_desc(dev, "Intel 82801DB (ICH4) SMBus controller");
 144                 break;
 145         case ID_82801E:
 146                 device_set_desc(dev, "Intel 82801E (C-ICH) SMBus controller");
 147                 break;
 148         case ID_82801EB:
 149                 device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller");
 150                 break;
 151         case ID_82801FB:
 152                 device_set_desc(dev, "Intel 82801FB (ICH6) SMBus controller");
 153                 break;
 154         case ID_82801G:
 155                 device_set_desc(dev, "Intel 82801G (ICH7) SMBus controller");
 156                 break;
 157         case ID_82801H:
 158                 device_set_desc(dev, "Intel 82801H (ICH8) SMBus controller");
 159                 break;
 160         case ID_82801I:
 161                 device_set_desc(dev, "Intel 82801I (ICH9) SMBus controller");
 162                 break;
 163         default:
 164                 if (pci_get_class(dev) == PCIC_SERIALBUS
 165                     && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS
 166                     && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) {
 167                         device_set_desc(dev, "SMBus controller");
 168                         return (-2);            /* XXX */
 169                 }
 170                 return (ENXIO);
 171         }
 172
 173         /* Done */
 174         return (ichsmb_probe(dev));
 175 }
 176
 177 static int
 178 ichsmb_pci_attach(device_t dev)
 179 {
 180         const sc_p sc = device_get_softc(dev);
 181         u_int32_t cmd;
 182         int error;
 183
 184         /* Initialize private state */
 185         bzero(sc, sizeof(*sc));
 186         sc->ich_cmd = -1;
 187         sc->dev = dev;
 188
 189         /* Allocate an I/O range */
 190         sc->io_rid = ICH_SMB_BASE;
 191         sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
 192             &sc->io_rid, 0, ~0, 16, RF_ACTIVE);
 193         if (sc->io_res == NULL) {
 194                 log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev));
 195                 error = ENXIO;
 196                 goto fail;
 197         }
 198         sc->io_bst = rman_get_bustag(sc->io_res);
 199         sc->io_bsh = rman_get_bushandle(sc->io_res);
 200
 201         /* Allocate interrupt */
 202         sc->irq_rid = 0;
 203         sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 204             &sc->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
 205         if (sc->irq_res == NULL) {
 206                 log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev));
 207                 error = ENXIO;
 208                 goto fail;
 209         }
 210
 211         /* Set up interrupt handler */
 212         error = bus_setup_intr(dev, sc->irq_res, 0, ichsmb_device_intr, sc,
 213                                &sc->irq_handle, NULL);
 214         if (error != 0) {
 215                 log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev));
 216                 goto fail;
 217         }
 218
 219         /* Enable I/O mapping */
 220         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 221         cmd |= PCIM_CMD_PORTEN;
 222         pci_write_config(dev, PCIR_COMMAND, cmd, 4);
 223         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 224         if ((cmd & PCIM_CMD_PORTEN) == 0) {
 225                 log(LOG_ERR, "%s: can't enable memory map\n",
 226                     device_get_nameunit(dev));
 227                 error = ENXIO;
 228                 goto fail;
 229         }
 230
 231         /* Enable device */
 232         pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
 233
 234         /* Done */
 235         return (ichsmb_attach(dev));
 236
 237 fail:
 238         /* Attach failed, release resources */
 239         ichsmb_release_resources(sc);
 240         return (error);
 241 }
 242