sys/cpu/amd64/include/specialreg.h

   1 /*-
   2  * Copyright (c) 1991 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 4. Neither the name of the University nor the names of its contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  *      from: @(#)specialreg.h  7.1 (Berkeley) 5/9/91
  30  * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $
  31  * $DragonFly: src/sys/cpu/amd64/include/specialreg.h,v 1.1 2007/09/23 04:29:30 yanyh Exp $
  32  */
  33
  34 #ifndef _CPU_SPECIALREG_H_
  35 #define _CPU_SPECIALREG_H_
  36
  37 /*
  38  * Bits in 386 special registers:
  39  */
  40 #define CR0_PE  0x00000001      /* Protected mode Enable */
  41 #define CR0_MP  0x00000002      /* "Math" (fpu) Present */
  42 #define CR0_EM  0x00000004      /* EMulate FPU instructions. (trap ESC only) */
  43 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
  44 #define CR0_PG  0x80000000      /* PaGing enable */
  45
  46 /*
  47  * Bits in 486 special registers:
  48  */
  49 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
  50 #define CR0_WP  0x00010000      /* Write Protect (honor page protect in
  51                                                            all modes) */
  52 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
  53 #define CR0_NW  0x20000000      /* Not Write-through */
  54 #define CR0_CD  0x40000000      /* Cache Disable */
  55
  56 /*
  57  * Bits in PPro special registers
  58  */
  59 #define CR4_VME 0x00000001      /* Virtual 8086 mode extensions */
  60 #define CR4_PVI 0x00000002      /* Protected-mode virtual interrupts */
  61 #define CR4_TSD 0x00000004      /* Time stamp disable */
  62 #define CR4_DE  0x00000008      /* Debugging extensions */
  63 #define CR4_PSE 0x00000010      /* Page size extensions */
  64 #define CR4_PAE 0x00000020      /* Physical address extension */
  65 #define CR4_MCE 0x00000040      /* Machine check enable */
  66 #define CR4_PGE 0x00000080      /* Page global enable */
  67 #define CR4_PCE 0x00000100      /* Performance monitoring counter enable */
  68 #define CR4_FXSR 0x00000200     /* Fast FPU save/restore used by OS */
  69 #define CR4_XMM 0x00000400      /* enable SIMD/MMX2 to use except 16 */
  70
  71 /*
  72  * Bits in AMD64 special registers.  EFER is 64 bits wide.
  73  */
  74 #define EFER_SCE 0x000000001    /* System Call Extensions (R/W) */
  75 #define EFER_LME 0x000000100    /* Long mode enable (R/W) */
  76 #define EFER_LMA 0x000000400    /* Long mode active (R) */
  77 #define EFER_NXE 0x000000800    /* PTE No-Execute bit enable (R/W) */
  78
  79 /*
  80  * CPUID instruction features register
  81  */
  82 #define CPUID_FPU       0x00000001
  83 #define CPUID_VME       0x00000002
  84 #define CPUID_DE        0x00000004
  85 #define CPUID_PSE       0x00000008
  86 #define CPUID_TSC       0x00000010
  87 #define CPUID_MSR       0x00000020
  88 #define CPUID_PAE       0x00000040
  89 #define CPUID_MCE       0x00000080
  90 #define CPUID_CX8       0x00000100
  91 #define CPUID_APIC      0x00000200
  92 #define CPUID_B10       0x00000400
  93 #define CPUID_SEP       0x00000800
  94 #define CPUID_MTRR      0x00001000
  95 #define CPUID_PGE       0x00002000
  96 #define CPUID_MCA       0x00004000
  97 #define CPUID_CMOV      0x00008000
  98 #define CPUID_PAT       0x00010000
  99 #define CPUID_PSE36     0x00020000
 100 #define CPUID_PSN       0x00040000
 101 #define CPUID_CLFSH     0x00080000
 102 #define CPUID_B20       0x00100000
 103 #define CPUID_DS        0x00200000
 104 #define CPUID_ACPI      0x00400000
 105 #define CPUID_MMX       0x00800000
 106 #define CPUID_FXSR      0x01000000
 107 #define CPUID_SSE       0x02000000
 108 #define CPUID_XMM       0x02000000
 109 #define CPUID_SSE2      0x04000000
 110 #define CPUID_SS        0x08000000
 111 #define CPUID_HTT       0x10000000
 112 #define CPUID_TM        0x20000000
 113 #define CPUID_IA64      0x40000000
 114 #define CPUID_PBE       0x80000000
 115
 116 #define CPUID2_SSE3     0x00000001
 117 #define CPUID2_MON      0x00000008
 118 #define CPUID2_DS_CPL   0x00000010
 119 #define CPUID2_VMX      0x00000020
 120 #define CPUID2_SMX      0x00000040
 121 #define CPUID2_EST      0x00000080
 122 #define CPUID2_TM2      0x00000100
 123 #define CPUID2_SSSE3    0x00000200
 124 #define CPUID2_CNXTID   0x00000400
 125 #define CPUID2_CX16     0x00002000
 126 #define CPUID2_XTPR     0x00004000
 127 #define CPUID2_PDCM     0x00008000
 128 #define CPUID2_DCA      0x00040000
 129
 130 /*
 131  * Important bits in the AMD extended cpuid flags
 132  */
 133 #define AMDID_SYSCALL   0x00000800
 134 #define AMDID_MP        0x00080000
 135 #define AMDID_NX        0x00100000
 136 #define AMDID_EXT_MMX   0x00400000
 137 #define AMDID_FFXSR     0x01000000
 138 #define AMDID_RDTSCP    0x08000000
 139 #define AMDID_LM        0x20000000
 140 #define AMDID_EXT_3DNOW 0x40000000
 141 #define AMDID_3DNOW     0x80000000
 142
 143 #define AMDID2_LAHF     0x00000001
 144 #define AMDID2_CMP      0x00000002
 145 #define AMDID2_SVM      0x00000004
 146 #define AMDID2_EXT_APIC 0x00000008
 147 #define AMDID2_CR8      0x00000010
 148 #define AMDID2_PREFETCH 0x00000100
 149
 150 /*
 151  * CPUID instruction 1 ebx info
 152  */
 153 #define CPUID_BRAND_INDEX       0x000000ff
 154 #define CPUID_CLFUSH_SIZE       0x0000ff00
 155 #define CPUID_HTT_CORES         0x00ff0000
 156 #define CPUID_LOCAL_APIC_ID     0xff000000
 157
 158 /*
 159  * AMD extended function 8000_0008h ecx info
 160  */
 161 #define AMDID_CMP_CORES         0x000000ff
 162
 163 /*
 164  * Model-specific registers for the i386 family
 165  */
 166 #define MSR_P5_MC_ADDR          0x000
 167 #define MSR_P5_MC_TYPE          0x001
 168 #define MSR_TSC                 0x010
 169 #define MSR_P5_CESR             0x011
 170 #define MSR_P5_CTR0             0x012
 171 #define MSR_P5_CTR1             0x013
 172 #define MSR_IA32_PLATFORM_ID    0x017
 173 #define MSR_APICBASE            0x01b
 174 #define MSR_EBL_CR_POWERON      0x02a
 175 #define MSR_TEST_CTL            0x033
 176 #define MSR_BIOS_UPDT_TRIG      0x079
 177 #define MSR_BBL_CR_D0           0x088
 178 #define MSR_BBL_CR_D1           0x089
 179 #define MSR_BBL_CR_D2           0x08a
 180 #define MSR_BIOS_SIGN           0x08b
 181 #define MSR_PERFCTR0            0x0c1
 182 #define MSR_PERFCTR1            0x0c2
 183 #define MSR_MTRRcap             0x0fe
 184 #define MSR_BBL_CR_ADDR         0x116
 185 #define MSR_BBL_CR_DECC         0x118
 186 #define MSR_BBL_CR_CTL          0x119
 187 #define MSR_BBL_CR_TRIG         0x11a
 188 #define MSR_BBL_CR_BUSY         0x11b
 189 #define MSR_BBL_CR_CTL3         0x11e
 190 #define MSR_SYSENTER_CS_MSR     0x174
 191 #define MSR_SYSENTER_ESP_MSR    0x175
 192 #define MSR_SYSENTER_EIP_MSR    0x176
 193 #define MSR_MCG_CAP             0x179
 194 #define MSR_MCG_STATUS          0x17a
 195 #define MSR_MCG_CTL             0x17b
 196 #define MSR_EVNTSEL0            0x186
 197 #define MSR_EVNTSEL1            0x187
 198 #define MSR_THERM_CONTROL       0x19a
 199 #define MSR_THERM_INTERRUPT     0x19b
 200 #define MSR_THERM_STATUS        0x19c
 201 #define MSR_IA32_MISC_ENABLE    0x1a0
 202 #define MSR_DEBUGCTLMSR         0x1d9
 203 #define MSR_LASTBRANCHFROMIP    0x1db
 204 #define MSR_LASTBRANCHTOIP      0x1dc
 205 #define MSR_LASTINTFROMIP       0x1dd
 206 #define MSR_LASTINTTOIP         0x1de
 207 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
 208 #define MSR_MTRRVarBase         0x200
 209 #define MSR_MTRR64kBase         0x250
 210 #define MSR_MTRR16kBase         0x258
 211 #define MSR_MTRR4kBase          0x268
 212 #define MSR_PAT                 0x277
 213 #define MSR_MTRRdefType         0x2ff
 214 #define MSR_MC0_CTL             0x400
 215 #define MSR_MC0_STATUS          0x401
 216 #define MSR_MC0_ADDR            0x402
 217 #define MSR_MC0_MISC            0x403
 218 #define MSR_MC1_CTL             0x404
 219 #define MSR_MC1_STATUS          0x405
 220 #define MSR_MC1_ADDR            0x406
 221 #define MSR_MC1_MISC            0x407
 222 #define MSR_MC2_CTL             0x408
 223 #define MSR_MC2_STATUS          0x409
 224 #define MSR_MC2_ADDR            0x40a
 225 #define MSR_MC2_MISC            0x40b
 226 #define MSR_MC3_CTL             0x40c
 227 #define MSR_MC3_STATUS          0x40d
 228 #define MSR_MC3_ADDR            0x40e
 229 #define MSR_MC3_MISC            0x40f
 230 #define MSR_MC4_CTL             0x410
 231 #define MSR_MC4_STATUS          0x411
 232 #define MSR_MC4_ADDR            0x412
 233 #define MSR_MC4_MISC            0x413
 234
 235 /*
 236  * Constants related to MSR's.
 237  */
 238 #define APICBASE_RESERVED       0x000006ff
 239 #define APICBASE_BSP            0x00000100
 240 #define APICBASE_ENABLED        0x00000800
 241 #define APICBASE_ADDRESS        0xfffff000
 242
 243 /*
 244  * PAT modes.
 245  */
 246 #define PAT_UNCACHEABLE         0x00
 247 #define PAT_WRITE_COMBINING     0x01
 248 #define PAT_WRITE_THROUGH       0x04
 249 #define PAT_WRITE_PROTECTED     0x05
 250 #define PAT_WRITE_BACK          0x06
 251 #define PAT_UNCACHED            0x07
 252 #define PAT_VALUE(i, m)         ((long)(m) << (8 * (i)))
 253 #define PAT_MASK(i)             PAT_VALUE(i, 0xff)
 254
 255 /*
 256  * Constants related to MTRRs
 257  */
 258 #define MTRR_N64K               8       /* numbers of fixed-size entries */
 259 #define MTRR_N16K               16
 260 #define MTRR_N4K                64
 261
 262 /* Performance Control Register (5x86 only). */
 263 #define PCR0                    0x20
 264 #define PCR0_RSTK               0x01    /* Enables return stack */
 265 #define PCR0_BTB                0x02    /* Enables branch target buffer */
 266 #define PCR0_LOOP               0x04    /* Enables loop */
 267 #define PCR0_AIS                0x08    /* Enables all instrcutions stalled to
 268                                                                    serialize pipe. */
 269 #define PCR0_MLR                0x10    /* Enables reordering of misaligned loads */
 270 #define PCR0_BTBRT              0x40    /* Enables BTB test register. */
 271 #define PCR0_LSSER              0x80    /* Disable reorder */
 272
 273 /* Device Identification Registers */
 274 #define DIR0                    0xfe
 275 #define DIR1                    0xff
 276
 277 /*
 278  * The following four 3-byte registers control the non-cacheable regions.
 279  * These registers must be written as three separate bytes.
 280  *
 281  * NCRx+0: A31-A24 of starting address
 282  * NCRx+1: A23-A16 of starting address
 283  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
 284  *
 285  * The non-cacheable region's starting address must be aligned to the
 286  * size indicated by the NCR_SIZE_xx field.
 287  */
 288 #define NCR1    0xc4
 289 #define NCR2    0xc7
 290 #define NCR3    0xca
 291 #define NCR4    0xcd
 292
 293 #define NCR_SIZE_0K     0
 294 #define NCR_SIZE_4K     1
 295 #define NCR_SIZE_8K     2
 296 #define NCR_SIZE_16K    3
 297 #define NCR_SIZE_32K    4
 298 #define NCR_SIZE_64K    5
 299 #define NCR_SIZE_128K   6
 300 #define NCR_SIZE_256K   7
 301 #define NCR_SIZE_512K   8
 302 #define NCR_SIZE_1M     9
 303 #define NCR_SIZE_2M     10
 304 #define NCR_SIZE_4M     11
 305 #define NCR_SIZE_8M     12
 306 #define NCR_SIZE_16M    13
 307 #define NCR_SIZE_32M    14
 308 #define NCR_SIZE_4G     15
 309
 310 /*
 311  * The address region registers are used to specify the location and
 312  * size for the eight address regions.
 313  *
 314  * ARRx + 0: A31-A24 of start address
 315  * ARRx + 1: A23-A16 of start address
 316  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
 317  */
 318 #define ARR0    0xc4
 319 #define ARR1    0xc7
 320 #define ARR2    0xca
 321 #define ARR3    0xcd
 322 #define ARR4    0xd0
 323 #define ARR5    0xd3
 324 #define ARR6    0xd6
 325 #define ARR7    0xd9
 326
 327 #define ARR_SIZE_0K             0
 328 #define ARR_SIZE_4K             1
 329 #define ARR_SIZE_8K             2
 330 #define ARR_SIZE_16K    3
 331 #define ARR_SIZE_32K    4
 332 #define ARR_SIZE_64K    5
 333 #define ARR_SIZE_128K   6
 334 #define ARR_SIZE_256K   7
 335 #define ARR_SIZE_512K   8
 336 #define ARR_SIZE_1M             9
 337 #define ARR_SIZE_2M             10
 338 #define ARR_SIZE_4M             11
 339 #define ARR_SIZE_8M             12
 340 #define ARR_SIZE_16M    13
 341 #define ARR_SIZE_32M    14
 342 #define ARR_SIZE_4G             15
 343
 344 /*
 345  * The region control registers specify the attributes associated with
 346  * the ARRx addres regions.
 347  */
 348 #define RCR0    0xdc
 349 #define RCR1    0xdd
 350 #define RCR2    0xde
 351 #define RCR3    0xdf
 352 #define RCR4    0xe0
 353 #define RCR5    0xe1
 354 #define RCR6    0xe2
 355 #define RCR7    0xe3
 356
 357 #define RCR_RCD 0x01    /* Disables caching for ARRx (x = 0-6). */
 358 #define RCR_RCE 0x01    /* Enables caching for ARR7. */
 359 #define RCR_WWO 0x02    /* Weak write ordering. */
 360 #define RCR_WL  0x04    /* Weak locking. */
 361 #define RCR_WG  0x08    /* Write gathering. */
 362 #define RCR_WT  0x10    /* Write-through. */
 363 #define RCR_NLB 0x20    /* LBA# pin is not asserted. */
 364
 365 /* AMD Write Allocate Top-Of-Memory and Control Register */
 366 #define AMD_WT_ALLOC_TME        0x40000 /* top-of-memory enable */
 367 #define AMD_WT_ALLOC_PRE        0x20000 /* programmable range enable */
 368 #define AMD_WT_ALLOC_FRE        0x10000 /* fixed (A0000-FFFFF) range enable */
 369
 370 /* AMD64 MSR's */
 371 #define MSR_EFER        0xc0000080      /* extended features */
 372 #define MSR_STAR        0xc0000081      /* legacy mode SYSCALL target/cs/ss */
 373 #define MSR_LSTAR       0xc0000082      /* long mode SYSCALL target rip */
 374 #define MSR_CSTAR       0xc0000083      /* compat mode SYSCALL target rip */
 375 #define MSR_SF_MASK     0xc0000084      /* syscall flags mask */
 376 #define MSR_FSBASE      0xc0000100      /* base address of the %fs "segment" */
 377 #define MSR_GSBASE      0xc0000101      /* base address of the %gs "segment" */
 378 #define MSR_KGSBASE     0xc0000102      /* base address of the kernel %gs */
 379 #define MSR_PERFEVSEL0  0xc0010000
 380 #define MSR_PERFEVSEL1  0xc0010001
 381 #define MSR_PERFEVSEL2  0xc0010002
 382 #define MSR_PERFEVSEL3  0xc0010003
 383 #undef MSR_PERFCTR0
 384 #undef MSR_PERFCTR1
 385 #define MSR_PERFCTR0    0xc0010004
 386 #define MSR_PERFCTR1    0xc0010005
 387 #define MSR_PERFCTR2    0xc0010006
 388 #define MSR_PERFCTR3    0xc0010007
 389 #define MSR_SYSCFG      0xc0010010
 390 #define MSR_IORRBASE0   0xc0010016
 391 #define MSR_IORRMASK0   0xc0010017
 392 #define MSR_IORRBASE1   0xc0010018
 393 #define MSR_IORRMASK1   0xc0010019
 394 #define MSR_TOP_MEM     0xc001001a      /* boundary for ram below 4G */
 395 #define MSR_TOP_MEM2    0xc001001d      /* boundary for ram above 4G */
 396
 397 #endif /* !_CPU_SPECIALREG_H_ */