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- Rename NFE_RXTX_V[32]MAGIC to NFE_RXTX_DESC_V[32].
[dragonfly.git] / sys / dev / netif / nfe / if_nfe.c
blob2b0941cc31d87a700d83524f9ba987db203c7ea7
1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.27 2008/06/27 16:30:53 sephe Exp $ */
3
4 /*
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 /*
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
42 *
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
46 *
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
54 */
55
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
57
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
60
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
64 #include <sys/bus.h>
65 #include <sys/interrupt.h>
66 #include <sys/proc.h>
67 #include <sys/rman.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
72
73 #include <net/ethernet.h>
74 #include <net/if.h>
75 #include <net/bpf.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
84
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
88
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
91
92 #include "miibus_if.h"
93
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
96
97 #define NFE_CSUM
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
106
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
110
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
113 #endif
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static void nfe_rxeof(struct nfe_softc *);
117 static void nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 struct mbuf *);
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_powerup(device_t);
143 static void nfe_mac_reset(struct nfe_softc *);
144 static void nfe_tick(void *);
145 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
146 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
147 int);
148 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
149 int, bus_addr_t);
150 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
151 int);
152 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
153 int);
154 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
155 int);
156
157 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
158
159 #define NFE_DEBUG
160 #ifdef NFE_DEBUG
161
162 static int nfe_debug = 0;
163 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
164 static int nfe_imtime = -1;
165
166 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
167 TUNABLE_INT("hw.nfe.imtime", &nfe_imtime);
168 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
169
170 #define DPRINTF(sc, fmt, ...) do { \
171 if ((sc)->sc_debug) { \
172 if_printf(&(sc)->arpcom.ac_if, \
173 fmt, __VA_ARGS__); \
174 } \
175 } while (0)
176
177 #define DPRINTFN(sc, lv, fmt, ...) do { \
178 if ((sc)->sc_debug >= (lv)) { \
179 if_printf(&(sc)->arpcom.ac_if, \
180 fmt, __VA_ARGS__); \
181 } \
182 } while (0)
183
184 #else /* !NFE_DEBUG */
185
186 #define DPRINTF(sc, fmt, ...)
187 #define DPRINTFN(sc, lv, fmt, ...)
188
189 #endif /* NFE_DEBUG */
190
191 struct nfe_dma_ctx {
192 int nsegs;
193 bus_dma_segment_t *segs;
194 };
195
196 static const struct nfe_dev {
197 uint16_t vid;
198 uint16_t did;
199 const char *desc;
200 } nfe_devices[] = {
201 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
202 "NVIDIA nForce Fast Ethernet" },
203
204 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
205 "NVIDIA nForce2 Fast Ethernet" },
206
207 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
208 "NVIDIA nForce3 Gigabit Ethernet" },
209
210 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
211 chipset, and possibly also the 400R; it might be both nForce2- and
212 nForce3-based boards can use the same MCPs (= southbridges) */
213 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
214 "NVIDIA nForce3 Gigabit Ethernet" },
215
216 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
217 "NVIDIA nForce3 Gigabit Ethernet" },
218
219 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
220 "NVIDIA nForce3 Gigabit Ethernet" },
221
222 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
223 "NVIDIA nForce3 Gigabit Ethernet" },
224
225 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
226 "NVIDIA CK804 Gigabit Ethernet" },
227
228 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
229 "NVIDIA CK804 Gigabit Ethernet" },
230
231 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
232 "NVIDIA MCP04 Gigabit Ethernet" },
233
234 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
235 "NVIDIA MCP04 Gigabit Ethernet" },
236
237 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
238 "NVIDIA MCP51 Gigabit Ethernet" },
239
240 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
241 "NVIDIA MCP51 Gigabit Ethernet" },
242
243 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
244 "NVIDIA MCP55 Gigabit Ethernet" },
245
246 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
247 "NVIDIA MCP55 Gigabit Ethernet" },
248
249 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
250 "NVIDIA MCP61 Gigabit Ethernet" },
251
252 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
253 "NVIDIA MCP61 Gigabit Ethernet" },
254
255 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
256 "NVIDIA MCP61 Gigabit Ethernet" },
257
258 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
259 "NVIDIA MCP61 Gigabit Ethernet" },
260
261 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
262 "NVIDIA MCP65 Gigabit Ethernet" },
263
264 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
265 "NVIDIA MCP65 Gigabit Ethernet" },
266
267 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
268 "NVIDIA MCP65 Gigabit Ethernet" },
269
270 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
271 "NVIDIA MCP65 Gigabit Ethernet" },
272
273 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
274 "NVIDIA MCP67 Gigabit Ethernet" },
275
276 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
277 "NVIDIA MCP67 Gigabit Ethernet" },
278
279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
280 "NVIDIA MCP67 Gigabit Ethernet" },
281
282 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
283 "NVIDIA MCP67 Gigabit Ethernet" },
284
285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
286 "NVIDIA MCP73 Gigabit Ethernet" },
287
288 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
289 "NVIDIA MCP73 Gigabit Ethernet" },
290
291 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
292 "NVIDIA MCP73 Gigabit Ethernet" },
293
294 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
295 "NVIDIA MCP73 Gigabit Ethernet" },
296
297 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
298 "NVIDIA MCP77 Gigabit Ethernet" },
299
300 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
301 "NVIDIA MCP77 Gigabit Ethernet" },
302
303 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
304 "NVIDIA MCP77 Gigabit Ethernet" },
305
306 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
307 "NVIDIA MCP77 Gigabit Ethernet" },
308
309 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
310 "NVIDIA MCP79 Gigabit Ethernet" },
311
312 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
313 "NVIDIA MCP79 Gigabit Ethernet" },
314
315 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
316 "NVIDIA MCP79 Gigabit Ethernet" },
317
318 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
319 "NVIDIA MCP79 Gigabit Ethernet" },
320
321 { 0, 0, NULL }
322 };
323
324 static device_method_t nfe_methods[] = {
325 /* Device interface */
326 DEVMETHOD(device_probe, nfe_probe),
327 DEVMETHOD(device_attach, nfe_attach),
328 DEVMETHOD(device_detach, nfe_detach),
329 DEVMETHOD(device_suspend, nfe_suspend),
330 DEVMETHOD(device_resume, nfe_resume),
331 DEVMETHOD(device_shutdown, nfe_shutdown),
332
333 /* Bus interface */
334 DEVMETHOD(bus_print_child, bus_generic_print_child),
335 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
336
337 /* MII interface */
338 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
339 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
340 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
341
342 { 0, 0 }
343 };
344
345 static driver_t nfe_driver = {
346 "nfe",
347 nfe_methods,
348 sizeof(struct nfe_softc)
349 };
350
351 static devclass_t nfe_devclass;
352
353 DECLARE_DUMMY_MODULE(if_nfe);
354 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
355 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
356 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
357
358 static int
359 nfe_probe(device_t dev)
360 {
361 const struct nfe_dev *n;
362 uint16_t vid, did;
363
364 vid = pci_get_vendor(dev);
365 did = pci_get_device(dev);
366 for (n = nfe_devices; n->desc != NULL; ++n) {
367 if (vid == n->vid && did == n->did) {
368 struct nfe_softc *sc = device_get_softc(dev);
369
370 switch (did) {
371 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
372 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
373 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
374 sc->sc_flags = NFE_NO_PWRCTL;
375 break;
376 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
377 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
378 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
379 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
380 sc->sc_flags = NFE_JUMBO_SUP |
381 NFE_HW_CSUM |
382 NFE_NO_PWRCTL;
383 break;
384 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
385 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
386 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
387 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
388 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
389 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
390 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
391 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
392 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
393 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
394 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
395 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
396 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
397 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
398 sc->sc_flags = NFE_40BIT_ADDR;
399 break;
400 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
401 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
403 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
404 sc->sc_flags = NFE_JUMBO_SUP |
405 NFE_40BIT_ADDR |
406 NFE_HW_CSUM |
407 NFE_NO_PWRCTL;
408 break;
409 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
410 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
411 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
412 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
413 sc->sc_flags = NFE_JUMBO_SUP |
414 NFE_40BIT_ADDR;
415 break;
416 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
417 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
418 sc->sc_flags = NFE_JUMBO_SUP |
419 NFE_40BIT_ADDR |
420 NFE_HW_CSUM |
421 NFE_HW_VLAN;
422 break;
423 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
424 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
425 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
426 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
427 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
428 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
429 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
430 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
431 sc->sc_flags = NFE_40BIT_ADDR |
432 NFE_HW_CSUM;
433 break;
434 }
435
436 device_set_desc(dev, n->desc);
437 device_set_async_attach(dev, TRUE);
438 return 0;
439 }
440 }
441 return ENXIO;
442 }
443
444 static int
445 nfe_attach(device_t dev)
446 {
447 struct nfe_softc *sc = device_get_softc(dev);
448 struct ifnet *ifp = &sc->arpcom.ac_if;
449 uint8_t eaddr[ETHER_ADDR_LEN];
450 int error;
451
452 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
453 lwkt_serialize_init(&sc->sc_jbuf_serializer);
454
455 /*
456 * Initialize sysctl variables
457 */
458 sc->sc_imtime = nfe_imtime;
459 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
460 sc->sc_rx_ring_count = nfe_rx_ring_count;
461 sc->sc_debug = nfe_debug;
462
463 sc->sc_mem_rid = PCIR_BAR(0);
464
465 if (sc->sc_flags & NFE_40BIT_ADDR)
466 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
467 else if (sc->sc_flags & NFE_JUMBO_SUP)
468 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
469
470 #ifndef BURN_BRIDGES
471 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
472 uint32_t mem, irq;
473
474 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
475 irq = pci_read_config(dev, PCIR_INTLINE, 4);
476
477 device_printf(dev, "chip is in D%d power mode "
478 "-- setting to D0\n", pci_get_powerstate(dev));
479
480 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
481
482 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
483 pci_write_config(dev, PCIR_INTLINE, irq, 4);
484 }
485 #endif /* !BURN_BRIDGE */
486
487 /* Enable bus mastering */
488 pci_enable_busmaster(dev);
489
490 /* Allocate IO memory */
491 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
492 &sc->sc_mem_rid, RF_ACTIVE);
493 if (sc->sc_mem_res == NULL) {
494 device_printf(dev, "cound not allocate io memory\n");
495 return ENXIO;
496 }
497 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
498 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
499
500 /* Allocate IRQ */
501 sc->sc_irq_rid = 0;
502 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
503 &sc->sc_irq_rid,
504 RF_SHAREABLE | RF_ACTIVE);
505 if (sc->sc_irq_res == NULL) {
506 device_printf(dev, "could not allocate irq\n");
507 error = ENXIO;
508 goto fail;
509 }
510
511 /* Disable WOL */
512 NFE_WRITE(sc, NFE_WOL_CTL, 0);
513
514 if ((sc->sc_flags & NFE_NO_PWRCTL) == 0)
515 nfe_powerup(dev);
516
517 nfe_get_macaddr(sc, eaddr);
518
519 /*
520 * Allocate Tx and Rx rings.
521 */
522 error = nfe_alloc_tx_ring(sc, &sc->txq);
523 if (error) {
524 device_printf(dev, "could not allocate Tx ring\n");
525 goto fail;
526 }
527
528 error = nfe_alloc_rx_ring(sc, &sc->rxq);
529 if (error) {
530 device_printf(dev, "could not allocate Rx ring\n");
531 goto fail;
532 }
533
534 /*
535 * Create sysctl tree
536 */
537 sysctl_ctx_init(&sc->sc_sysctl_ctx);
538 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
539 SYSCTL_STATIC_CHILDREN(_hw),
540 OID_AUTO,
541 device_get_nameunit(dev),
542 CTLFLAG_RD, 0, "");
543 if (sc->sc_sysctl_tree == NULL) {
544 device_printf(dev, "can't add sysctl node\n");
545 error = ENXIO;
546 goto fail;
547 }
548 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
549 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
550 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
551 sc, 0, nfe_sysctl_imtime, "I",
552 "Interrupt moderation time (usec). "
553 "-1 to disable interrupt moderation.");
554 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
555 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
556 0, "RX ring count");
557 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
558 "debug", CTLFLAG_RW, &sc->sc_debug,
559 0, "control debugging printfs");
560
561 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
562 nfe_ifmedia_sts);
563 if (error) {
564 device_printf(dev, "MII without any phy\n");
565 goto fail;
566 }
567
568 ifp->if_softc = sc;
569 ifp->if_mtu = ETHERMTU;
570 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
571 ifp->if_ioctl = nfe_ioctl;
572 ifp->if_start = nfe_start;
573 #ifdef DEVICE_POLLING
574 ifp->if_poll = nfe_poll;
575 #endif
576 ifp->if_watchdog = nfe_watchdog;
577 ifp->if_init = nfe_init;
578 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
579 ifq_set_ready(&ifp->if_snd);
580
581 ifp->if_capabilities = IFCAP_VLAN_MTU;
582
583 if (sc->sc_flags & NFE_HW_VLAN)
584 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
585
586 #ifdef NFE_CSUM
587 if (sc->sc_flags & NFE_HW_CSUM) {
588 ifp->if_capabilities |= IFCAP_HWCSUM;
589 ifp->if_hwassist = NFE_CSUM_FEATURES;
590 }
591 #else
592 sc->sc_flags &= ~NFE_HW_CSUM;
593 #endif
594 ifp->if_capenable = ifp->if_capabilities;
595
596 callout_init(&sc->sc_tick_ch);
597
598 ether_ifattach(ifp, eaddr, NULL);
599
600 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
601 &sc->sc_ih, ifp->if_serializer);
602 if (error) {
603 device_printf(dev, "could not setup intr\n");
604 ether_ifdetach(ifp);
605 goto fail;
606 }
607
608 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
609 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
610
611 return 0;
612 fail:
613 nfe_detach(dev);
614 return error;
615 }
616
617 static int
618 nfe_detach(device_t dev)
619 {
620 struct nfe_softc *sc = device_get_softc(dev);
621
622 if (device_is_attached(dev)) {
623 struct ifnet *ifp = &sc->arpcom.ac_if;
624
625 lwkt_serialize_enter(ifp->if_serializer);
626 nfe_stop(sc);
627 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
628 lwkt_serialize_exit(ifp->if_serializer);
629
630 ether_ifdetach(ifp);
631 }
632
633 if (sc->sc_miibus != NULL)
634 device_delete_child(dev, sc->sc_miibus);
635 bus_generic_detach(dev);
636
637 if (sc->sc_sysctl_tree != NULL)
638 sysctl_ctx_free(&sc->sc_sysctl_ctx);
639
640 if (sc->sc_irq_res != NULL) {
641 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
642 sc->sc_irq_res);
643 }
644
645 if (sc->sc_mem_res != NULL) {
646 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
647 sc->sc_mem_res);
648 }
649
650 nfe_free_tx_ring(sc, &sc->txq);
651 nfe_free_rx_ring(sc, &sc->rxq);
652
653 return 0;
654 }
655
656 static void
657 nfe_shutdown(device_t dev)
658 {
659 struct nfe_softc *sc = device_get_softc(dev);
660 struct ifnet *ifp = &sc->arpcom.ac_if;
661
662 lwkt_serialize_enter(ifp->if_serializer);
663 nfe_stop(sc);
664 lwkt_serialize_exit(ifp->if_serializer);
665 }
666
667 static int
668 nfe_suspend(device_t dev)
669 {
670 struct nfe_softc *sc = device_get_softc(dev);
671 struct ifnet *ifp = &sc->arpcom.ac_if;
672
673 lwkt_serialize_enter(ifp->if_serializer);
674 nfe_stop(sc);
675 lwkt_serialize_exit(ifp->if_serializer);
676
677 return 0;
678 }
679
680 static int
681 nfe_resume(device_t dev)
682 {
683 struct nfe_softc *sc = device_get_softc(dev);
684 struct ifnet *ifp = &sc->arpcom.ac_if;
685
686 lwkt_serialize_enter(ifp->if_serializer);
687 if (ifp->if_flags & IFF_UP)
688 nfe_init(sc);
689 lwkt_serialize_exit(ifp->if_serializer);
690
691 return 0;
692 }
693
694 static void
695 nfe_miibus_statchg(device_t dev)
696 {
697 struct nfe_softc *sc = device_get_softc(dev);
698 struct mii_data *mii = device_get_softc(sc->sc_miibus);
699 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
700
701 phy = NFE_READ(sc, NFE_PHY_IFACE);
702 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
703
704 seed = NFE_READ(sc, NFE_RNDSEED);
705 seed &= ~NFE_SEED_MASK;
706
707 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
708 phy |= NFE_PHY_HDX; /* half-duplex */
709 misc |= NFE_MISC1_HDX;
710 }
711
712 switch (IFM_SUBTYPE(mii->mii_media_active)) {
713 case IFM_1000_T: /* full-duplex only */
714 link |= NFE_MEDIA_1000T;
715 seed |= NFE_SEED_1000T;
716 phy |= NFE_PHY_1000T;
717 break;
718 case IFM_100_TX:
719 link |= NFE_MEDIA_100TX;
720 seed |= NFE_SEED_100TX;
721 phy |= NFE_PHY_100TX;
722 break;
723 case IFM_10_T:
724 link |= NFE_MEDIA_10T;
725 seed |= NFE_SEED_10T;
726 break;
727 }
728
729 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
730
731 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
732 NFE_WRITE(sc, NFE_MISC1, misc);
733 NFE_WRITE(sc, NFE_LINKSPEED, link);
734 }
735
736 static int
737 nfe_miibus_readreg(device_t dev, int phy, int reg)
738 {
739 struct nfe_softc *sc = device_get_softc(dev);
740 uint32_t val;
741 int ntries;
742
743 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
744
745 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
746 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
747 DELAY(100);
748 }
749
750 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
751
752 for (ntries = 0; ntries < 1000; ntries++) {
753 DELAY(100);
754 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
755 break;
756 }
757 if (ntries == 1000) {
758 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
759 return 0;
760 }
761
762 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
763 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
764 return 0;
765 }
766
767 val = NFE_READ(sc, NFE_PHY_DATA);
768 if (val != 0xffffffff && val != 0)
769 sc->mii_phyaddr = phy;
770
771 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
772
773 return val;
774 }
775
776 static void
777 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
778 {
779 struct nfe_softc *sc = device_get_softc(dev);
780 uint32_t ctl;
781 int ntries;
782
783 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
784
785 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
786 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
787 DELAY(100);
788 }
789
790 NFE_WRITE(sc, NFE_PHY_DATA, val);
791 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
792 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
793
794 for (ntries = 0; ntries < 1000; ntries++) {
795 DELAY(100);
796 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
797 break;
798 }
799
800 #ifdef NFE_DEBUG
801 if (ntries == 1000)
802 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
803 #endif
804 }
805
806 #ifdef DEVICE_POLLING
807
808 static void
809 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
810 {
811 struct nfe_softc *sc = ifp->if_softc;
812
813 ASSERT_SERIALIZED(ifp->if_serializer);
814
815 switch(cmd) {
816 case POLL_REGISTER:
817 /* Disable interrupts */
818 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
819 break;
820 case POLL_DEREGISTER:
821 /* enable interrupts */
822 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
823 break;
824 case POLL_AND_CHECK_STATUS:
825 /* fall through */
826 case POLL_ONLY:
827 if (ifp->if_flags & IFF_RUNNING) {
828 nfe_rxeof(sc);
829 nfe_txeof(sc);
830 }
831 break;
832 }
833 }
834
835 #endif
836
837 static void
838 nfe_intr(void *arg)
839 {
840 struct nfe_softc *sc = arg;
841 struct ifnet *ifp = &sc->arpcom.ac_if;
842 uint32_t r;
843
844 r = NFE_READ(sc, NFE_IRQ_STATUS);
845 if (r == 0)
846 return; /* not for us */
847 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
848
849 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
850
851 if (r & NFE_IRQ_LINK) {
852 NFE_READ(sc, NFE_PHY_STATUS);
853 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
854 DPRINTF(sc, "link state changed %s\n", "");
855 }
856
857 if (ifp->if_flags & IFF_RUNNING) {
858 /* check Rx ring */
859 nfe_rxeof(sc);
860
861 /* check Tx ring */
862 nfe_txeof(sc);
863 }
864 }
865
866 static int
867 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
868 {
869 struct nfe_softc *sc = ifp->if_softc;
870 struct ifreq *ifr = (struct ifreq *)data;
871 struct mii_data *mii;
872 int error = 0, mask;
873
874 switch (cmd) {
875 case SIOCSIFMTU:
876 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
877 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
878 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
879 ifr->ifr_mtu > ETHERMTU)) {
880 return EINVAL;
881 } else if (ifp->if_mtu != ifr->ifr_mtu) {
882 ifp->if_mtu = ifr->ifr_mtu;
883 nfe_init(sc);
884 }
885 break;
886 case SIOCSIFFLAGS:
887 if (ifp->if_flags & IFF_UP) {
888 /*
889 * If only the PROMISC or ALLMULTI flag changes, then
890 * don't do a full re-init of the chip, just update
891 * the Rx filter.
892 */
893 if ((ifp->if_flags & IFF_RUNNING) &&
894 ((ifp->if_flags ^ sc->sc_if_flags) &
895 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
896 nfe_setmulti(sc);
897 } else {
898 if (!(ifp->if_flags & IFF_RUNNING))
899 nfe_init(sc);
900 }
901 } else {
902 if (ifp->if_flags & IFF_RUNNING)
903 nfe_stop(sc);
904 }
905 sc->sc_if_flags = ifp->if_flags;
906 break;
907 case SIOCADDMULTI:
908 case SIOCDELMULTI:
909 if (ifp->if_flags & IFF_RUNNING)
910 nfe_setmulti(sc);
911 break;
912 case SIOCSIFMEDIA:
913 case SIOCGIFMEDIA:
914 mii = device_get_softc(sc->sc_miibus);
915 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
916 break;
917 case SIOCSIFCAP:
918 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
919 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
920 ifp->if_capenable ^= mask;
921 if (IFCAP_TXCSUM & ifp->if_capenable)
922 ifp->if_hwassist = NFE_CSUM_FEATURES;
923 else
924 ifp->if_hwassist = 0;
925
926 if (ifp->if_flags & IFF_RUNNING)
927 nfe_init(sc);
928 }
929 break;
930 default:
931 error = ether_ioctl(ifp, cmd, data);
932 break;
933 }
934 return error;
935 }
936
937 static void
938 nfe_rxeof(struct nfe_softc *sc)
939 {
940 struct ifnet *ifp = &sc->arpcom.ac_if;
941 struct nfe_rx_ring *ring = &sc->rxq;
942 int reap;
943 #ifdef ETHER_INPUT_CHAIN
944 struct mbuf_chain chain[MAXCPU];
945 #endif
946
947 reap = 0;
948 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
949
950 #ifdef ETHER_INPUT_CHAIN
951 ether_input_chain_init(chain);
952 #endif
953
954 for (;;) {
955 struct nfe_rx_data *data = &ring->data[ring->cur];
956 struct mbuf *m;
957 uint16_t flags;
958 int len, error;
959
960 if (sc->sc_flags & NFE_40BIT_ADDR) {
961 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
962
963 flags = le16toh(desc64->flags);
964 len = le16toh(desc64->length) & 0x3fff;
965 } else {
966 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
967
968 flags = le16toh(desc32->flags);
969 len = le16toh(desc32->length) & 0x3fff;
970 }
971
972 if (flags & NFE_RX_READY)
973 break;
974
975 reap = 1;
976
977 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
978 if (!(flags & NFE_RX_VALID_V1))
979 goto skip;
980
981 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
982 flags &= ~NFE_RX_ERROR;
983 len--; /* fix buffer length */
984 }
985 } else {
986 if (!(flags & NFE_RX_VALID_V2))
987 goto skip;
988
989 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
990 flags &= ~NFE_RX_ERROR;
991 len--; /* fix buffer length */
992 }
993 }
994
995 if (flags & NFE_RX_ERROR) {
996 ifp->if_ierrors++;
997 goto skip;
998 }
999
1000 m = data->m;
1001
1002 if (sc->sc_flags & NFE_USE_JUMBO)
1003 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1004 else
1005 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1006 if (error) {
1007 ifp->if_ierrors++;
1008 goto skip;
1009 }
1010
1011 /* finalize mbuf */
1012 m->m_pkthdr.len = m->m_len = len;
1013 m->m_pkthdr.rcvif = ifp;
1014
1015 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1016 (flags & NFE_RX_CSUMOK)) {
1017 if (flags & NFE_RX_IP_CSUMOK_V2) {
1018 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1019 CSUM_IP_VALID;
1020 }
1021
1022 if (flags &
1023 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1024 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1025 CSUM_PSEUDO_HDR |
1026 CSUM_FRAG_NOT_CHECKED;
1027 m->m_pkthdr.csum_data = 0xffff;
1028 }
1029 }
1030
1031 ifp->if_ipackets++;
1032 #ifdef ETHER_INPUT_CHAIN
1033 #ifdef ETHER_INPUT2
1034 ether_input_chain2(ifp, m, chain);
1035 #else
1036 ether_input_chain(ifp, m, chain);
1037 #endif
1038 #else
1039 ifp->if_input(ifp, m);
1040 #endif
1041 skip:
1042 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1043 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1044 }
1045
1046 if (reap) {
1047 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1048 #ifdef ETHER_INPUT_CHAIN
1049 ether_input_dispatch(chain);
1050 #endif
1051 }
1052 }
1053
1054 static void
1055 nfe_txeof(struct nfe_softc *sc)
1056 {
1057 struct ifnet *ifp = &sc->arpcom.ac_if;
1058 struct nfe_tx_ring *ring = &sc->txq;
1059 struct nfe_tx_data *data = NULL;
1060
1061 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1062 while (ring->next != ring->cur) {
1063 uint16_t flags;
1064
1065 if (sc->sc_flags & NFE_40BIT_ADDR)
1066 flags = le16toh(ring->desc64[ring->next].flags);
1067 else
1068 flags = le16toh(ring->desc32[ring->next].flags);
1069
1070 if (flags & NFE_TX_VALID)
1071 break;
1072
1073 data = &ring->data[ring->next];
1074
1075 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1076 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1077 goto skip;
1078
1079 if ((flags & NFE_TX_ERROR_V1) != 0) {
1080 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1081 NFE_V1_TXERR);
1082 ifp->if_oerrors++;
1083 } else {
1084 ifp->if_opackets++;
1085 }
1086 } else {
1087 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1088 goto skip;
1089
1090 if ((flags & NFE_TX_ERROR_V2) != 0) {
1091 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1092 NFE_V2_TXERR);
1093 ifp->if_oerrors++;
1094 } else {
1095 ifp->if_opackets++;
1096 }
1097 }
1098
1099 if (data->m == NULL) { /* should not get there */
1100 if_printf(ifp,
1101 "last fragment bit w/o associated mbuf!\n");
1102 goto skip;
1103 }
1104
1105 /* last fragment of the mbuf chain transmitted */
1106 bus_dmamap_sync(ring->data_tag, data->map,
1107 BUS_DMASYNC_POSTWRITE);
1108 bus_dmamap_unload(ring->data_tag, data->map);
1109 m_freem(data->m);
1110 data->m = NULL;
1111
1112 ifp->if_timer = 0;
1113 skip:
1114 ring->queued--;
1115 KKASSERT(ring->queued >= 0);
1116 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1117 }
1118
1119 if (data != NULL) { /* at least one slot freed */
1120 ifp->if_flags &= ~IFF_OACTIVE;
1121 if_devstart(ifp);
1122 }
1123 }
1124
1125 static int
1126 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1127 {
1128 struct nfe_dma_ctx ctx;
1129 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1130 struct nfe_tx_data *data, *data_map;
1131 bus_dmamap_t map;
1132 struct nfe_desc64 *desc64 = NULL;
1133 struct nfe_desc32 *desc32 = NULL;
1134 uint16_t flags = 0;
1135 uint32_t vtag = 0;
1136 int error, i, j;
1137
1138 data = &ring->data[ring->cur];
1139 map = data->map;
1140 data_map = data; /* Remember who owns the DMA map */
1141
1142 ctx.nsegs = NFE_MAX_SCATTER;
1143 ctx.segs = segs;
1144 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1145 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1146 if (error && error != EFBIG) {
1147 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1148 goto back;
1149 }
1150
1151 if (error) { /* error == EFBIG */
1152 struct mbuf *m_new;
1153
1154 m_new = m_defrag(m0, MB_DONTWAIT);
1155 if (m_new == NULL) {
1156 if_printf(&sc->arpcom.ac_if,
1157 "could not defrag TX mbuf\n");
1158 error = ENOBUFS;
1159 goto back;
1160 } else {
1161 m0 = m_new;
1162 }
1163
1164 ctx.nsegs = NFE_MAX_SCATTER;
1165 ctx.segs = segs;
1166 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1167 nfe_buf_dma_addr, &ctx,
1168 BUS_DMA_NOWAIT);
1169 if (error) {
1170 if_printf(&sc->arpcom.ac_if,
1171 "could not map defraged TX mbuf\n");
1172 goto back;
1173 }
1174 }
1175
1176 error = 0;
1177
1178 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1179 bus_dmamap_unload(ring->data_tag, map);
1180 error = ENOBUFS;
1181 goto back;
1182 }
1183
1184 /* setup h/w VLAN tagging */
1185 if (m0->m_flags & M_VLANTAG)
1186 vtag = m0->m_pkthdr.ether_vlantag;
1187
1188 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1189 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1190 flags |= NFE_TX_IP_CSUM;
1191 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1192 flags |= NFE_TX_TCP_CSUM;
1193 }
1194
1195 /*
1196 * XXX urm. somebody is unaware of how hardware works. You
1197 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1198 * the ring until the entire chain is actually *VALID*. Otherwise
1199 * the hardware may encounter a partially initialized chain that
1200 * is marked as being ready to go when it in fact is not ready to
1201 * go.
1202 */
1203
1204 for (i = 0; i < ctx.nsegs; i++) {
1205 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1206 data = &ring->data[j];
1207
1208 if (sc->sc_flags & NFE_40BIT_ADDR) {
1209 desc64 = &ring->desc64[j];
1210 #if defined(__LP64__)
1211 desc64->physaddr[0] =
1212 htole32(segs[i].ds_addr >> 32);
1213 #endif
1214 desc64->physaddr[1] =
1215 htole32(segs[i].ds_addr & 0xffffffff);
1216 desc64->length = htole16(segs[i].ds_len - 1);
1217 desc64->vtag = htole32(vtag);
1218 desc64->flags = htole16(flags);
1219 } else {
1220 desc32 = &ring->desc32[j];
1221 desc32->physaddr = htole32(segs[i].ds_addr);
1222 desc32->length = htole16(segs[i].ds_len - 1);
1223 desc32->flags = htole16(flags);
1224 }
1225
1226 /* csum flags and vtag belong to the first fragment only */
1227 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1228 vtag = 0;
1229
1230 ring->queued++;
1231 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1232 }
1233
1234 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1235 if (sc->sc_flags & NFE_40BIT_ADDR) {
1236 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1237 } else {
1238 if (sc->sc_flags & NFE_JUMBO_SUP)
1239 flags = NFE_TX_LASTFRAG_V2;
1240 else
1241 flags = NFE_TX_LASTFRAG_V1;
1242 desc32->flags |= htole16(flags);
1243 }
1244
1245 /*
1246 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1247 * whole mess until the first descriptor in the map is flagged.
1248 */
1249 for (i = ctx.nsegs - 1; i >= 0; --i) {
1250 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1251 if (sc->sc_flags & NFE_40BIT_ADDR) {
1252 desc64 = &ring->desc64[j];
1253 desc64->flags |= htole16(NFE_TX_VALID);
1254 } else {
1255 desc32 = &ring->desc32[j];
1256 desc32->flags |= htole16(NFE_TX_VALID);
1257 }
1258 }
1259 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1260
1261 /* Exchange DMA map */
1262 data_map->map = data->map;
1263 data->map = map;
1264 data->m = m0;
1265
1266 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1267 back:
1268 if (error)
1269 m_freem(m0);
1270 return error;
1271 }
1272
1273 static void
1274 nfe_start(struct ifnet *ifp)
1275 {
1276 struct nfe_softc *sc = ifp->if_softc;
1277 struct nfe_tx_ring *ring = &sc->txq;
1278 int count = 0;
1279 struct mbuf *m0;
1280
1281 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1282 return;
1283
1284 for (;;) {
1285 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1286 if (m0 == NULL)
1287 break;
1288
1289 ETHER_BPF_MTAP(ifp, m0);
1290
1291 if (nfe_encap(sc, ring, m0) != 0) {
1292 ifp->if_flags |= IFF_OACTIVE;
1293 break;
1294 }
1295 ++count;
1296
1297 /*
1298 * NOTE:
1299 * `m0' may be freed in nfe_encap(), so
1300 * it should not be touched any more.
1301 */
1302 }
1303 if (count == 0) /* nothing sent */
1304 return;
1305
1306 /* Sync TX descriptor ring */
1307 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1308
1309 /* Kick Tx */
1310 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1311
1312 /*
1313 * Set a timeout in case the chip goes out to lunch.
1314 */
1315 ifp->if_timer = 5;
1316 }
1317
1318 static void
1319 nfe_watchdog(struct ifnet *ifp)
1320 {
1321 struct nfe_softc *sc = ifp->if_softc;
1322
1323 if (ifp->if_flags & IFF_RUNNING) {
1324 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1325 nfe_txeof(sc);
1326 return;
1327 }
1328
1329 if_printf(ifp, "watchdog timeout\n");
1330
1331 nfe_init(ifp->if_softc);
1332
1333 ifp->if_oerrors++;
1334 }
1335
1336 static void
1337 nfe_init(void *xsc)
1338 {
1339 struct nfe_softc *sc = xsc;
1340 struct ifnet *ifp = &sc->arpcom.ac_if;
1341 uint32_t tmp;
1342 int error;
1343
1344 nfe_stop(sc);
1345
1346 if ((sc->sc_flags & NFE_NO_PWRCTL) == 0)
1347 nfe_mac_reset(sc);
1348
1349 /*
1350 * NOTE:
1351 * Switching between jumbo frames and normal frames should
1352 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1353 */
1354 if (ifp->if_mtu > ETHERMTU) {
1355 sc->sc_flags |= NFE_USE_JUMBO;
1356 sc->rxq.bufsz = NFE_JBYTES;
1357 if (bootverbose)
1358 if_printf(ifp, "use jumbo frames\n");
1359 } else {
1360 sc->sc_flags &= ~NFE_USE_JUMBO;
1361 sc->rxq.bufsz = MCLBYTES;
1362 if (bootverbose)
1363 if_printf(ifp, "use non-jumbo frames\n");
1364 }
1365
1366 error = nfe_init_tx_ring(sc, &sc->txq);
1367 if (error) {
1368 nfe_stop(sc);
1369 return;
1370 }
1371
1372 error = nfe_init_rx_ring(sc, &sc->rxq);
1373 if (error) {
1374 nfe_stop(sc);
1375 return;
1376 }
1377
1378 NFE_WRITE(sc, NFE_TX_POLL, 0);
1379 NFE_WRITE(sc, NFE_STATUS, 0);
1380
1381 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1382
1383 if (ifp->if_capenable & IFCAP_RXCSUM)
1384 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1385
1386 /*
1387 * Although the adapter is capable of stripping VLAN tags from received
1388 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1389 * purpose. This will be done in software by our network stack.
1390 */
1391 if (sc->sc_flags & NFE_HW_VLAN)
1392 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1393
1394 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1395 DELAY(10);
1396 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1397
1398 if (sc->sc_flags & NFE_HW_VLAN)
1399 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1400
1401 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1402
1403 /* set MAC address */
1404 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1405
1406 /* tell MAC where rings are in memory */
1407 #ifdef __LP64__
1408 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1409 #endif
1410 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1411 #ifdef __LP64__
1412 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1413 #endif
1414 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1415
1416 NFE_WRITE(sc, NFE_RING_SIZE,
1417 (sc->sc_rx_ring_count - 1) << 16 |
1418 (NFE_TX_RING_COUNT - 1));
1419
1420 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1421
1422 /* force MAC to wakeup */
1423 tmp = NFE_READ(sc, NFE_PWR_STATE);
1424 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1425 DELAY(10);
1426 tmp = NFE_READ(sc, NFE_PWR_STATE);
1427 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1428
1429 /*
1430 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1431 * It is unclear how wide the timer is. Base programming does
1432 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1433 * we don't get any interrupt moderation. TX moderation is
1434 * possible by using the timer interrupt instead of TX_DONE.
1435 *
1436 * It is unclear whether there are other bits that can be
1437 * set to make the NFE device actually do interrupt moderation
1438 * on the RX side.
1439 *
1440 * For now set a 128uS interval as a placemark, but don't use
1441 * the timer.
1442 */
1443 if (sc->sc_imtime < 0)
1444 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
1445 else
1446 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
1447
1448 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1449 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1450 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1451
1452 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1453 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1454
1455 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1456
1457 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1458 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1459 DELAY(10);
1460 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1461
1462 /* set Rx filter */
1463 nfe_setmulti(sc);
1464
1465 nfe_ifmedia_upd(ifp);
1466
1467 /* enable Rx */
1468 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1469
1470 /* enable Tx */
1471 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1472
1473 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1474
1475 #ifdef DEVICE_POLLING
1476 if ((ifp->if_flags & IFF_POLLING) == 0)
1477 #endif
1478 /* enable interrupts */
1479 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
1480
1481 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1482
1483 ifp->if_flags |= IFF_RUNNING;
1484 ifp->if_flags &= ~IFF_OACTIVE;
1485
1486 /*
1487 * If we had stuff in the tx ring before its all cleaned out now
1488 * so we are not going to get an interrupt, jump-start any pending
1489 * output.
1490 */
1491 if_devstart(ifp);
1492 }
1493
1494 static void
1495 nfe_stop(struct nfe_softc *sc)
1496 {
1497 struct ifnet *ifp = &sc->arpcom.ac_if;
1498
1499 callout_stop(&sc->sc_tick_ch);
1500
1501 ifp->if_timer = 0;
1502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1503
1504 /*
1505 * Are NFE_TX_CTL and NFE_RX_CTL polled by the chip microcontroller
1506 * or do they directly reset/terminate the DMA hardware? Nobody
1507 * knows.
1508 *
1509 * Add two delays:
1510 *
1511 * (1) Delay before zeroing out NFE_TX_CTL. This seems to help a
1512 * watchdog timeout that occurs after a stop/init sequence. I am
1513 * theorizing that a TX KICK occuring just prior to a reinit (e.g.
1514 * due to dhclient) is queueing an interrupt to the microcontroller
1515 * which gets delayed until after we clear the control registers
1516 * down below, resulting in mass confusion. TX KICK is clearly
1517 * hardware aided whereas the other bits in the control register
1518 * are more likely to be polled by the microcontroller.
1519 *
1520 * (2) Delay after zeroing out TX and RX CTL registers, under the
1521 * assumption that primary DMA is initiated and terminated by
1522 * the microcontroller and not hardware (and anyway, one can hardly
1523 * expect the DMA engine to just instantly stop!). We don't want
1524 * to rip the rings out from under it before it has had a chance to
1525 * actually stop!
1526 */
1527 DELAY(1000);
1528
1529 /* Abort Tx */
1530 NFE_WRITE(sc, NFE_TX_CTL, 0);
1531
1532 /* Disable Rx */
1533 NFE_WRITE(sc, NFE_RX_CTL, 0);
1534
1535 /* Disable interrupts */
1536 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1537
1538 DELAY(1000);
1539
1540 /* Reset Tx and Rx rings */
1541 nfe_reset_tx_ring(sc, &sc->txq);
1542 nfe_reset_rx_ring(sc, &sc->rxq);
1543 }
1544
1545 static int
1546 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1547 {
1548 int i, j, error, descsize;
1549 void **desc;
1550
1551 if (sc->sc_flags & NFE_40BIT_ADDR) {
1552 desc = (void **)&ring->desc64;
1553 descsize = sizeof(struct nfe_desc64);
1554 } else {
1555 desc = (void **)&ring->desc32;
1556 descsize = sizeof(struct nfe_desc32);
1557 }
1558
1559 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1560 M_DEVBUF, M_WAITOK | M_ZERO);
1561 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1562 M_DEVBUF, M_WAITOK | M_ZERO);
1563
1564 ring->bufsz = MCLBYTES;
1565 ring->cur = ring->next = 0;
1566
1567 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1568 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1569 NULL, NULL,
1570 sc->sc_rx_ring_count * descsize, 1,
1571 sc->sc_rx_ring_count * descsize,
1572 0, &ring->tag);
1573 if (error) {
1574 if_printf(&sc->arpcom.ac_if,
1575 "could not create desc RX DMA tag\n");
1576 return error;
1577 }
1578
1579 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1580 &ring->map);
1581 if (error) {
1582 if_printf(&sc->arpcom.ac_if,
1583 "could not allocate RX desc DMA memory\n");
1584 bus_dma_tag_destroy(ring->tag);
1585 ring->tag = NULL;
1586 return error;
1587 }
1588
1589 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1590 sc->sc_rx_ring_count * descsize,
1591 nfe_ring_dma_addr, &ring->physaddr,
1592 BUS_DMA_WAITOK);
1593 if (error) {
1594 if_printf(&sc->arpcom.ac_if,
1595 "could not load RX desc DMA map\n");
1596 bus_dmamem_free(ring->tag, *desc, ring->map);
1597 bus_dma_tag_destroy(ring->tag);
1598 ring->tag = NULL;
1599 return error;
1600 }
1601
1602 if (sc->sc_flags & NFE_JUMBO_SUP) {
1603 error = nfe_jpool_alloc(sc, ring);
1604 if (error) {
1605 if_printf(&sc->arpcom.ac_if,
1606 "could not allocate jumbo frames\n");
1607 return error;
1608 }
1609 }
1610
1611 error = bus_dma_tag_create(NULL, 1, 0,
1612 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1613 NULL, NULL,
1614 MCLBYTES, 1, MCLBYTES,
1615 0, &ring->data_tag);
1616 if (error) {
1617 if_printf(&sc->arpcom.ac_if,
1618 "could not create RX mbuf DMA tag\n");
1619 return error;
1620 }
1621
1622 /* Create a spare RX mbuf DMA map */
1623 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1624 if (error) {
1625 if_printf(&sc->arpcom.ac_if,
1626 "could not create spare RX mbuf DMA map\n");
1627 bus_dma_tag_destroy(ring->data_tag);
1628 ring->data_tag = NULL;
1629 return error;
1630 }
1631
1632 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1633 error = bus_dmamap_create(ring->data_tag, 0,
1634 &ring->data[i].map);
1635 if (error) {
1636 if_printf(&sc->arpcom.ac_if,
1637 "could not create %dth RX mbuf DMA mapn", i);
1638 goto fail;
1639 }
1640 }
1641 return 0;
1642 fail:
1643 for (j = 0; j < i; ++j)
1644 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1645 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1646 bus_dma_tag_destroy(ring->data_tag);
1647 ring->data_tag = NULL;
1648 return error;
1649 }
1650
1651 static void
1652 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1653 {
1654 int i;
1655
1656 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1657 struct nfe_rx_data *data = &ring->data[i];
1658
1659 if (data->m != NULL) {
1660 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1661 bus_dmamap_unload(ring->data_tag, data->map);
1662 m_freem(data->m);
1663 data->m = NULL;
1664 }
1665 }
1666 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1667
1668 ring->cur = ring->next = 0;
1669 }
1670
1671 static int
1672 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1673 {
1674 int i;
1675
1676 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1677 int error;
1678
1679 /* XXX should use a function pointer */
1680 if (sc->sc_flags & NFE_USE_JUMBO)
1681 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1682 else
1683 error = nfe_newbuf_std(sc, ring, i, 1);
1684 if (error) {
1685 if_printf(&sc->arpcom.ac_if,
1686 "could not allocate RX buffer\n");
1687 return error;
1688 }
1689
1690 nfe_set_ready_rxdesc(sc, ring, i);
1691 }
1692 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1693
1694 return 0;
1695 }
1696
1697 static void
1698 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1699 {
1700 if (ring->data_tag != NULL) {
1701 struct nfe_rx_data *data;
1702 int i;
1703
1704 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1705 data = &ring->data[i];
1706
1707 if (data->m != NULL) {
1708 bus_dmamap_unload(ring->data_tag, data->map);
1709 m_freem(data->m);
1710 }
1711 bus_dmamap_destroy(ring->data_tag, data->map);
1712 }
1713 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1714 bus_dma_tag_destroy(ring->data_tag);
1715 }
1716
1717 nfe_jpool_free(sc, ring);
1718
1719 if (ring->jbuf != NULL)
1720 kfree(ring->jbuf, M_DEVBUF);
1721 if (ring->data != NULL)
1722 kfree(ring->data, M_DEVBUF);
1723
1724 if (ring->tag != NULL) {
1725 void *desc;
1726
1727 if (sc->sc_flags & NFE_40BIT_ADDR)
1728 desc = ring->desc64;
1729 else
1730 desc = ring->desc32;
1731
1732 bus_dmamap_unload(ring->tag, ring->map);
1733 bus_dmamem_free(ring->tag, desc, ring->map);
1734 bus_dma_tag_destroy(ring->tag);
1735 }
1736 }
1737
1738 static struct nfe_jbuf *
1739 nfe_jalloc(struct nfe_softc *sc)
1740 {
1741 struct ifnet *ifp = &sc->arpcom.ac_if;
1742 struct nfe_jbuf *jbuf;
1743
1744 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1745
1746 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1747 if (jbuf != NULL) {
1748 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1749 jbuf->inuse = 1;
1750 } else {
1751 if_printf(ifp, "no free jumbo buffer\n");
1752 }
1753
1754 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1755
1756 return jbuf;
1757 }
1758
1759 static void
1760 nfe_jfree(void *arg)
1761 {
1762 struct nfe_jbuf *jbuf = arg;
1763 struct nfe_softc *sc = jbuf->sc;
1764 struct nfe_rx_ring *ring = jbuf->ring;
1765
1766 if (&ring->jbuf[jbuf->slot] != jbuf)
1767 panic("%s: free wrong jumbo buffer\n", __func__);
1768 else if (jbuf->inuse == 0)
1769 panic("%s: jumbo buffer already freed\n", __func__);
1770
1771 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1772 atomic_subtract_int(&jbuf->inuse, 1);
1773 if (jbuf->inuse == 0)
1774 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1775 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1776 }
1777
1778 static void
1779 nfe_jref(void *arg)
1780 {
1781 struct nfe_jbuf *jbuf = arg;
1782 struct nfe_rx_ring *ring = jbuf->ring;
1783
1784 if (&ring->jbuf[jbuf->slot] != jbuf)
1785 panic("%s: ref wrong jumbo buffer\n", __func__);
1786 else if (jbuf->inuse == 0)
1787 panic("%s: jumbo buffer already freed\n", __func__);
1788
1789 atomic_add_int(&jbuf->inuse, 1);
1790 }
1791
1792 static int
1793 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1794 {
1795 struct nfe_jbuf *jbuf;
1796 bus_addr_t physaddr;
1797 caddr_t buf;
1798 int i, error;
1799
1800 /*
1801 * Allocate a big chunk of DMA'able memory.
1802 */
1803 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1804 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1805 NULL, NULL,
1806 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1807 0, &ring->jtag);
1808 if (error) {
1809 if_printf(&sc->arpcom.ac_if,
1810 "could not create jumbo DMA tag\n");
1811 return error;
1812 }
1813
1814 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1815 BUS_DMA_WAITOK, &ring->jmap);
1816 if (error) {
1817 if_printf(&sc->arpcom.ac_if,
1818 "could not allocate jumbo DMA memory\n");
1819 bus_dma_tag_destroy(ring->jtag);
1820 ring->jtag = NULL;
1821 return error;
1822 }
1823
1824 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1825 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1826 BUS_DMA_WAITOK);
1827 if (error) {
1828 if_printf(&sc->arpcom.ac_if,
1829 "could not load jumbo DMA map\n");
1830 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1831 bus_dma_tag_destroy(ring->jtag);
1832 ring->jtag = NULL;
1833 return error;
1834 }
1835
1836 /* ..and split it into 9KB chunks */
1837 SLIST_INIT(&ring->jfreelist);
1838
1839 buf = ring->jpool;
1840 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1841 jbuf = &ring->jbuf[i];
1842
1843 jbuf->sc = sc;
1844 jbuf->ring = ring;
1845 jbuf->inuse = 0;
1846 jbuf->slot = i;
1847 jbuf->buf = buf;
1848 jbuf->physaddr = physaddr;
1849
1850 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1851
1852 buf += NFE_JBYTES;
1853 physaddr += NFE_JBYTES;
1854 }
1855
1856 return 0;
1857 }
1858
1859 static void
1860 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1861 {
1862 if (ring->jtag != NULL) {
1863 bus_dmamap_unload(ring->jtag, ring->jmap);
1864 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1865 bus_dma_tag_destroy(ring->jtag);
1866 }
1867 }
1868
1869 static int
1870 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1871 {
1872 int i, j, error, descsize;
1873 void **desc;
1874
1875 if (sc->sc_flags & NFE_40BIT_ADDR) {
1876 desc = (void **)&ring->desc64;
1877 descsize = sizeof(struct nfe_desc64);
1878 } else {
1879 desc = (void **)&ring->desc32;
1880 descsize = sizeof(struct nfe_desc32);
1881 }
1882
1883 ring->queued = 0;
1884 ring->cur = ring->next = 0;
1885
1886 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1887 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1888 NULL, NULL,
1889 NFE_TX_RING_COUNT * descsize, 1,
1890 NFE_TX_RING_COUNT * descsize,
1891 0, &ring->tag);
1892 if (error) {
1893 if_printf(&sc->arpcom.ac_if,
1894 "could not create TX desc DMA map\n");
1895 return error;
1896 }
1897
1898 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1899 &ring->map);
1900 if (error) {
1901 if_printf(&sc->arpcom.ac_if,
1902 "could not allocate TX desc DMA memory\n");
1903 bus_dma_tag_destroy(ring->tag);
1904 ring->tag = NULL;
1905 return error;
1906 }
1907
1908 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1909 NFE_TX_RING_COUNT * descsize,
1910 nfe_ring_dma_addr, &ring->physaddr,
1911 BUS_DMA_WAITOK);
1912 if (error) {
1913 if_printf(&sc->arpcom.ac_if,
1914 "could not load TX desc DMA map\n");
1915 bus_dmamem_free(ring->tag, *desc, ring->map);
1916 bus_dma_tag_destroy(ring->tag);
1917 ring->tag = NULL;
1918 return error;
1919 }
1920
1921 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1922 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1923 NULL, NULL,
1924 NFE_JBYTES * NFE_MAX_SCATTER,
1925 NFE_MAX_SCATTER, NFE_JBYTES,
1926 0, &ring->data_tag);
1927 if (error) {
1928 if_printf(&sc->arpcom.ac_if,
1929 "could not create TX buf DMA tag\n");
1930 return error;
1931 }
1932
1933 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1934 error = bus_dmamap_create(ring->data_tag, 0,
1935 &ring->data[i].map);
1936 if (error) {
1937 if_printf(&sc->arpcom.ac_if,
1938 "could not create %dth TX buf DMA map\n", i);
1939 goto fail;
1940 }
1941 }
1942
1943 return 0;
1944 fail:
1945 for (j = 0; j < i; ++j)
1946 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1947 bus_dma_tag_destroy(ring->data_tag);
1948 ring->data_tag = NULL;
1949 return error;
1950 }
1951
1952 static void
1953 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1954 {
1955 int i;
1956
1957 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1958 struct nfe_tx_data *data = &ring->data[i];
1959
1960 if (sc->sc_flags & NFE_40BIT_ADDR)
1961 ring->desc64[i].flags = 0;
1962 else
1963 ring->desc32[i].flags = 0;
1964
1965 if (data->m != NULL) {
1966 bus_dmamap_sync(ring->data_tag, data->map,
1967 BUS_DMASYNC_POSTWRITE);
1968 bus_dmamap_unload(ring->data_tag, data->map);
1969 m_freem(data->m);
1970 data->m = NULL;
1971 }
1972 }
1973 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1974
1975 ring->queued = 0;
1976 ring->cur = ring->next = 0;
1977 }
1978
1979 static int
1980 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1981 struct nfe_tx_ring *ring __unused)
1982 {
1983 return 0;
1984 }
1985
1986 static void
1987 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1988 {
1989 if (ring->data_tag != NULL) {
1990 struct nfe_tx_data *data;
1991 int i;
1992
1993 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1994 data = &ring->data[i];
1995
1996 if (data->m != NULL) {
1997 bus_dmamap_unload(ring->data_tag, data->map);
1998 m_freem(data->m);
1999 }
2000 bus_dmamap_destroy(ring->data_tag, data->map);
2001 }
2002
2003 bus_dma_tag_destroy(ring->data_tag);
2004 }
2005
2006 if (ring->tag != NULL) {
2007 void *desc;
2008
2009 if (sc->sc_flags & NFE_40BIT_ADDR)
2010 desc = ring->desc64;
2011 else
2012 desc = ring->desc32;
2013
2014 bus_dmamap_unload(ring->tag, ring->map);
2015 bus_dmamem_free(ring->tag, desc, ring->map);
2016 bus_dma_tag_destroy(ring->tag);
2017 }
2018 }
2019
2020 static int
2021 nfe_ifmedia_upd(struct ifnet *ifp)
2022 {
2023 struct nfe_softc *sc = ifp->if_softc;
2024 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2025
2026 if (mii->mii_instance != 0) {
2027 struct mii_softc *miisc;
2028
2029 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2030 mii_phy_reset(miisc);
2031 }
2032 mii_mediachg(mii);
2033
2034 return 0;
2035 }
2036
2037 static void
2038 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2039 {
2040 struct nfe_softc *sc = ifp->if_softc;
2041 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2042
2043 mii_pollstat(mii);
2044 ifmr->ifm_status = mii->mii_media_status;
2045 ifmr->ifm_active = mii->mii_media_active;
2046 }
2047
2048 static void
2049 nfe_setmulti(struct nfe_softc *sc)
2050 {
2051 struct ifnet *ifp = &sc->arpcom.ac_if;
2052 struct ifmultiaddr *ifma;
2053 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2054 uint32_t filter = NFE_RXFILTER_MAGIC;
2055 int i;
2056
2057 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2058 bzero(addr, ETHER_ADDR_LEN);
2059 bzero(mask, ETHER_ADDR_LEN);
2060 goto done;
2061 }
2062
2063 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2064 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2065
2066 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2067 caddr_t maddr;
2068
2069 if (ifma->ifma_addr->sa_family != AF_LINK)
2070 continue;
2071
2072 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2073 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2074 addr[i] &= maddr[i];
2075 mask[i] &= ~maddr[i];
2076 }
2077 }
2078
2079 for (i = 0; i < ETHER_ADDR_LEN; i++)
2080 mask[i] |= addr[i];
2081
2082 done:
2083 addr[0] |= 0x01; /* make sure multicast bit is set */
2084
2085 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2086 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2087 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2088 addr[5] << 8 | addr[4]);
2089 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2090 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2091 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2092 mask[5] << 8 | mask[4]);
2093
2094 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2095 NFE_WRITE(sc, NFE_RXFILTER, filter);
2096 }
2097
2098 static void
2099 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2100 {
2101 uint32_t tmp;
2102
2103 tmp = NFE_READ(sc, NFE_MACADDR_LO);
2104 addr[0] = (tmp >> 8) & 0xff;
2105 addr[1] = (tmp & 0xff);
2106
2107 tmp = NFE_READ(sc, NFE_MACADDR_HI);
2108 addr[2] = (tmp >> 24) & 0xff;
2109 addr[3] = (tmp >> 16) & 0xff;
2110 addr[4] = (tmp >> 8) & 0xff;
2111 addr[5] = (tmp & 0xff);
2112 }
2113
2114 static void
2115 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2116 {
2117 NFE_WRITE(sc, NFE_MACADDR_LO,
2118 addr[5] << 8 | addr[4]);
2119 NFE_WRITE(sc, NFE_MACADDR_HI,
2120 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2121 }
2122
2123 static void
2124 nfe_tick(void *arg)
2125 {
2126 struct nfe_softc *sc = arg;
2127 struct ifnet *ifp = &sc->arpcom.ac_if;
2128 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2129
2130 lwkt_serialize_enter(ifp->if_serializer);
2131
2132 mii_tick(mii);
2133 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2134
2135 lwkt_serialize_exit(ifp->if_serializer);
2136 }
2137
2138 static void
2139 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2140 {
2141 if (error)
2142 return;
2143
2144 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2145
2146 *((uint32_t *)arg) = seg->ds_addr;
2147 }
2148
2149 static void
2150 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2151 bus_size_t mapsz __unused, int error)
2152 {
2153 struct nfe_dma_ctx *ctx = arg;
2154 int i;
2155
2156 if (error)
2157 return;
2158
2159 KASSERT(nsegs <= ctx->nsegs,
2160 ("too many segments(%d), should be <= %d\n",
2161 nsegs, ctx->nsegs));
2162
2163 ctx->nsegs = nsegs;
2164 for (i = 0; i < nsegs; ++i)
2165 ctx->segs[i] = segs[i];
2166 }
2167
2168 static int
2169 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2170 int wait)
2171 {
2172 struct nfe_rx_data *data = &ring->data[idx];
2173 struct nfe_dma_ctx ctx;
2174 bus_dma_segment_t seg;
2175 bus_dmamap_t map;
2176 struct mbuf *m;
2177 int error;
2178
2179 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2180 if (m == NULL)
2181 return ENOBUFS;
2182 m->m_len = m->m_pkthdr.len = MCLBYTES;
2183
2184 ctx.nsegs = 1;
2185 ctx.segs = &seg;
2186 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2187 m, nfe_buf_dma_addr, &ctx,
2188 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2189 if (error) {
2190 m_freem(m);
2191 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2192 return error;
2193 }
2194
2195 /* Unload originally mapped mbuf */
2196 bus_dmamap_unload(ring->data_tag, data->map);
2197
2198 /* Swap this DMA map with tmp DMA map */
2199 map = data->map;
2200 data->map = ring->data_tmpmap;
2201 ring->data_tmpmap = map;
2202
2203 /* Caller is assumed to have collected the old mbuf */
2204 data->m = m;
2205
2206 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2207
2208 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2209 return 0;
2210 }
2211
2212 static int
2213 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2214 int wait)
2215 {
2216 struct nfe_rx_data *data = &ring->data[idx];
2217 struct nfe_jbuf *jbuf;
2218 struct mbuf *m;
2219
2220 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2221 if (m == NULL)
2222 return ENOBUFS;
2223
2224 jbuf = nfe_jalloc(sc);
2225 if (jbuf == NULL) {
2226 m_freem(m);
2227 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2228 "-- packet dropped!\n");
2229 return ENOBUFS;
2230 }
2231
2232 m->m_ext.ext_arg = jbuf;
2233 m->m_ext.ext_buf = jbuf->buf;
2234 m->m_ext.ext_free = nfe_jfree;
2235 m->m_ext.ext_ref = nfe_jref;
2236 m->m_ext.ext_size = NFE_JBYTES;
2237
2238 m->m_data = m->m_ext.ext_buf;
2239 m->m_flags |= M_EXT;
2240 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2241
2242 /* Caller is assumed to have collected the old mbuf */
2243 data->m = m;
2244
2245 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2246
2247 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2248 return 0;
2249 }
2250
2251 static void
2252 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2253 bus_addr_t physaddr)
2254 {
2255 if (sc->sc_flags & NFE_40BIT_ADDR) {
2256 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2257
2258 #if defined(__LP64__)
2259 desc64->physaddr[0] = htole32(physaddr >> 32);
2260 #endif
2261 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2262 } else {
2263 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2264
2265 desc32->physaddr = htole32(physaddr);
2266 }
2267 }
2268
2269 static void
2270 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2271 {
2272 if (sc->sc_flags & NFE_40BIT_ADDR) {
2273 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2274
2275 desc64->length = htole16(ring->bufsz);
2276 desc64->flags = htole16(NFE_RX_READY);
2277 } else {
2278 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2279
2280 desc32->length = htole16(ring->bufsz);
2281 desc32->flags = htole16(NFE_RX_READY);
2282 }
2283 }
2284
2285 static int
2286 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2287 {
2288 struct nfe_softc *sc = arg1;
2289 struct ifnet *ifp = &sc->arpcom.ac_if;
2290 int error, v;
2291
2292 lwkt_serialize_enter(ifp->if_serializer);
2293
2294 v = sc->sc_imtime;
2295 error = sysctl_handle_int(oidp, &v, 0, req);
2296 if (error || req->newptr == NULL)
2297 goto back;
2298 if (v == 0) {
2299 error = EINVAL;
2300 goto back;
2301 }
2302
2303 if (sc->sc_imtime != v) {
2304 int old_imtime = sc->sc_imtime;
2305
2306 sc->sc_imtime = v;
2307 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2308
2309 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2310 == IFF_RUNNING) {
2311 if (old_imtime > 0 && sc->sc_imtime > 0) {
2312 NFE_WRITE(sc, NFE_IMTIMER,
2313 NFE_IMTIME(sc->sc_imtime));
2314 } else if ((old_imtime * sc->sc_imtime) < 0) {
2315 ifp->if_init(sc);
2316 }
2317 }
2318 }
2319 back:
2320 lwkt_serialize_exit(ifp->if_serializer);
2321 return error;
2322 }
2323
2324 static void
2325 nfe_powerup(device_t dev)
2326 {
2327 struct nfe_softc *sc = device_get_softc(dev);
2328 uint32_t pwr_state;
2329 uint16_t did;
2330
2331 /*
2332 * Bring MAC and PHY out of low power state
2333 */
2334
2335 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2336
2337 did = pci_get_device(dev);
2338 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2339 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2340 pci_get_revid(dev) >= 0xa3)
2341 pwr_state |= NFE_PWRUP_REV_A3;
2342
2343 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2344 }
2345
2346 static void
2347 nfe_mac_reset(struct nfe_softc *sc)
2348 {
2349 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2350 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2351
2352 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2353
2354 /* Save several registers for later restoration */
2355 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2356 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2357 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2358
2359 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2360 DELAY(100);
2361
2362 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2363 DELAY(100);
2364
2365 /* Restore saved registers */
2366 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2367 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2368 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2369
2370 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2371 }
DragonFly BSD