sys/dev/netif/re/if_rereg.h

   1 /*
   2  * Copyright (c) 2004
   3  *      Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
   4  *
   5  * Copyright (c) 1997, 1998-2003
   6  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Bill Paul.
  19  * 4. Neither the name of the author nor the names of any co-contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  33  * THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
  36  */
  37
  38 #define RE_TXLIST_ADDR_LO       0x0020  /* 64 bits, 256 byte alignment */
  39 #define RE_TXLIST_ADDR_HI       0x0024  /* 64 bits, 256 byte alignment */
  40
  41 #define RE_RXLIST_ADDR_LO       0x00E4  /* 64 bits, 256 byte alignment */
  42 #define RE_RXLIST_ADDR_HI       0x00E8  /* 64 bits, 256 byte alignment */
  43
  44 #define RE_TIMERINT             0x0058  /* 32 bits */
  45
  46 /*
  47  * Config 2 register bits
  48  */
  49 #define RE_CFG2_PCICLK_MASK     0x07
  50 #define RE_CFG2_PCICLK_33MHZ    0x00
  51 #define RE_CFG2_PCICLK_66MHZ    0x01
  52 #define RE_CFG2_PCI64           0x08
  53
  54 #define RE_TX_LIST_CNT          4
  55 #define RE_MIN_FRAMELEN         60
  56
  57 #define RE_IM_MAGIC             0x5050
  58 #define RE_IM_RXTIME(t)         ((t) & 0xf)
  59 #define RE_IM_TXTIME(t)         (((t) & 0xf) << 8)
  60
  61 /*
  62  * The 8169/8168 gigE chips support descriptor-based TX and RX.
  63  * In fact, they even support TCP large send.  Descriptors
  64  * must be allocated in contiguous blocks that are aligned on a
  65  * 256-byte boundary.
  66  */
  67
  68 /*
  69  * RX/TX descriptor definition.  When large send mode is enabled, the
  70  * lower 11 bits of the TX re_cmd word are used to hold the MSS, and
  71  * the checksum offload bits are disabled.  The structure layout is
  72  * the same for RX and TX descriptors.
  73  */
  74
  75 struct re_desc {
  76         uint32_t                re_cmdstat;
  77         uint32_t                re_control;
  78         uint32_t                re_bufaddr_lo;
  79         uint32_t                re_bufaddr_hi;
  80 };
  81
  82 #define RE_TDESC_CMD_FRAGLEN    0x0000FFFF
  83 #define RE_TDESC_CMD_TCPCSUM    0x00010000      /* TCP checksum enable */
  84 #define RE_TDESC_CMD_UDPCSUM    0x00020000      /* UDP checksum enable */
  85 #define RE_TDESC_CMD_IPCSUM     0x00040000      /* IP header checksum enable */
  86 #define RE_TDESC_CMD_MSSVAL     0x07FF0000      /* Large send MSS value */
  87 #define RE_TDESC_CMD_LGSEND     0x08000000      /* TCP large send enb */
  88 #define RE_TDESC_CMD_EOF        0x10000000      /* end of frame marker */
  89 #define RE_TDESC_CMD_SOF        0x20000000      /* start of frame marker */
  90 #define RE_TDESC_CMD_EOR        0x40000000      /* end of ring marker */
  91 #define RE_TDESC_CMD_OWN        0x80000000      /* chip owns descriptor */
  92
  93 #define RE_TDESC_CTL_INSTAG     0x00020000      /* Insert VLAN tag */
  94 #define RE_TDESC_CTL_TAGDATA    0x0000FFFF      /* TAG data */
  95 #define RE_TDESC_CTL_IPCSUM     0x20000000      /* IP header csum, MAC2 only */
  96 #define RE_TDESC_CTL_TCPCSUM    0x60000000      /* TCP csum, MAC2 only */
  97 #define RE_TDESC_CTL_UDPCSUM    0xa0000000      /* UDP csum, MAC2 only */
  98
  99 /*
 100  * Error bits are valid only on the last descriptor of a frame
 101  * (i.e. RE_TDESC_CMD_EOF == 1)
 102  */
 103
 104 #define RE_TDESC_STAT_COLCNT    0x000F0000      /* collision count */
 105 #define RE_TDESC_STAT_EXCESSCOL 0x00100000      /* excessive collisions */
 106 #define RE_TDESC_STAT_LINKFAIL  0x00200000      /* link faulure */
 107 #define RE_TDESC_STAT_OWINCOL   0x00400000      /* out-of-window collision */
 108 #define RE_TDESC_STAT_TXERRSUM  0x00800000      /* transmit error summary */
 109 #define RE_TDESC_STAT_UNDERRUN  0x02000000      /* TX underrun occured */
 110 #define RE_TDESC_STAT_OWN       0x80000000
 111
 112 /*
 113  * RX descriptor cmd/vlan definitions
 114  */
 115
 116 #define RE_RDESC_CMD_EOR        0x40000000
 117 #define RE_RDESC_CMD_OWN        0x80000000
 118 #define RE_RDESC_CMD_BUFLEN     0x00001FFF
 119
 120 #define RE_RDESC_STAT_OWN       0x80000000
 121 #define RE_RDESC_STAT_EOR       0x40000000
 122 #define RE_RDESC_STAT_SOF       0x20000000
 123 #define RE_RDESC_STAT_EOF       0x10000000
 124 #define RE_RDESC_STAT_FRALIGN   0x08000000      /* frame alignment error */
 125 #define RE_RDESC_STAT_MCAST     0x04000000      /* multicast pkt received */
 126 #define RE_RDESC_STAT_UCAST     0x02000000      /* unicast pkt received */
 127 #define RE_RDESC_STAT_BCAST     0x01000000      /* broadcast pkt received */
 128 #define RE_RDESC_STAT_BUFOFLOW  0x00800000      /* out of buffer space */
 129 #define RE_RDESC_STAT_FIFOOFLOW 0x00400000      /* FIFO overrun */
 130 #define RE_RDESC_STAT_GIANT     0x00200000      /* pkt > 4096 bytes */
 131 #define RE_RDESC_STAT_RXERRSUM  0x00100000      /* RX error summary */
 132 #define RE_RDESC_STAT_RUNT      0x00080000      /* runt packet received */
 133 #define RE_RDESC_STAT_CRCERR    0x00040000      /* CRC error */
 134 #define RE_RDESC_STAT_PROTOID   0x00030000      /* Protocol type */
 135 #define RE_RDESC_STAT_IPSUMBAD  0x00008000      /* IP header checksum bad */
 136 #define RE_RDESC_STAT_UDPSUMBAD 0x00004000      /* UDP checksum bad */
 137 #define RE_RDESC_STAT_TCPSUMBAD 0x00002000      /* TCP checksum bad */
 138 #define RE_RDESC_STAT_FRAGLEN   0x00001FFF      /* RX'ed frame/frag len */
 139 #define RE_RDESC_STAT_GFRAGLEN  0x00003FFF      /* RX'ed frame/frag len */
 140
 141 #define RE_RDESC_CTL_HASTAG     0x00010000      /* VLAN tag available
 142                                                    (TAG data valid) */
 143 #define RE_RDESC_CTL_TAGDATA    0x0000FFFF      /* TAG data */
 144 #define RE_RDESC_CTL_PROTOIP4   0x40000000      /* IPv4 packet, MAC2 only */
 145 #define RE_RDESC_CTL_PROTOIP6   0x80000000      /* IPv6 packet, MAC2 only */
 146
 147 #define RE_PROTOID_NONIP        0x00000000
 148 #define RE_PROTOID_TCPIP        0x00010000
 149 #define RE_PROTOID_UDPIP        0x00020000
 150 #define RE_PROTOID_IP           0x00030000
 151 #define RE_TCPPKT(x)            (((x) & RE_RDESC_STAT_PROTOID) == \
 152                                  RE_PROTOID_TCPIP)
 153 #define RE_UDPPKT(x)            (((x) & RE_RDESC_STAT_PROTOID) == \
 154                                  RE_PROTOID_UDPIP)
 155
 156 /*
 157  * Statistics counter structure.
 158  */
 159 struct re_stats {
 160         uint32_t                re_tx_pkts_lo;
 161         uint32_t                re_tx_pkts_hi;
 162         uint32_t                re_tx_errs_lo;
 163         uint32_t                re_tx_errs_hi;
 164         uint32_t                re_tx_errs;
 165         uint16_t                re_missed_pkts;
 166         uint16_t                re_rx_framealign_errs;
 167         uint32_t                re_tx_onecoll;
 168         uint32_t                re_tx_multicolls;
 169         uint32_t                re_rx_ucasts_hi;
 170         uint32_t                re_rx_ucasts_lo;
 171         uint32_t                re_rx_bcasts_lo;
 172         uint32_t                re_rx_bcasts_hi;
 173         uint32_t                re_rx_mcasts;
 174         uint16_t                re_tx_aborts;
 175         uint16_t                re_rx_underruns;
 176 };
 177
 178 /*
 179  * General constants that are fun to know.
 180  *
 181  * PCI low memory base and low I/O base register, and
 182  * other PCI registers.
 183  */
 184
 185 #define RE_PCI_LOMEM            0x14
 186 #define RE_PCI_LOIO             0x10
 187
 188 #define PCI_SUBDEVICE_LINKSYS_EG1032_REV3       0x0024