sys/dev/netif/mii_layer/rgephy.c

   1 /*      $OpenBSD: rgephy.c,v 1.12 2006/06/27 05:36:58 brad Exp $        */
   2
   3 /*
   4  * Copyright (c) 2003
   5  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $
  35  */
  36
  37 /*
  38  * Driver for the RealTek 8211B/8169S/8110S internal 10/100/1000 PHY.
  39  */
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/kernel.h>
  44 #include <sys/module.h>
  45 #include <sys/socket.h>
  46 #include <sys/bus.h>
  47
  48 #include <machine/clock.h>
  49
  50 #include <net/if.h>
  51 #include <net/if_arp.h>
  52 #include <net/if_media.h>
  53
  54 #include <dev/netif/mii_layer/mii.h>
  55 #include <dev/netif/mii_layer/miivar.h>
  56 #include <dev/netif/mii_layer/rgephyreg.h>
  57
  58 #include "miibus_if.h"
  59 #include "miidevs.h"
  60
  61 static int rgephy_probe(device_t);
  62 static int rgephy_attach(device_t);
  63
  64 static device_method_t rgephy_methods[] = {
  65         /* device interface */
  66         DEVMETHOD(device_probe,         rgephy_probe),
  67         DEVMETHOD(device_attach,        rgephy_attach),
  68         DEVMETHOD(device_detach,        ukphy_detach),
  69         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  70         DEVMETHOD_END
  71 };
  72
  73 static const struct mii_phydesc rgephys[] = {
  74         MII_PHYDESC(REALTEK2,   RTL8169S),
  75         MII_PHYDESC(xxREALTEK,  RTL8169S),
  76         MII_PHYDESC(xxREALTEK,  RTL8251),
  77         MII_PHYDESC_NULL
  78 };
  79
  80 static devclass_t rgephy_devclass;
  81
  82 static driver_t rgephy_driver = {
  83         "rgephy",
  84         rgephy_methods,
  85         sizeof(struct mii_softc)
  86 };
  87
  88 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, NULL, NULL);
  89
  90 static int      rgephy_service(struct mii_softc *, struct mii_data *, int);
  91 static void     rgephy_status(struct mii_softc *);
  92 static int      rgephy_mii_phy_auto(struct mii_softc *);
  93 static void     rgephy_reset(struct mii_softc *);
  94 static void     rgephy_loop(struct mii_softc *);
  95 static void     rgephy_load_dspcode(struct mii_softc *);
  96
  97 static int
  98 rgephy_probe(device_t dev)
  99 {
 100         struct mii_attach_args *ma = device_get_ivars(dev);
 101         const struct mii_phydesc *mpd;
 102
 103         mpd = mii_phy_match(ma, rgephys);
 104         if (mpd != NULL) {
 105                 device_set_desc(dev, mpd->mpd_name);
 106                 if (bootverbose)
 107                         device_printf(dev, "rev: %d\n", MII_REV(ma->mii_id2));
 108                 return (0);
 109         }
 110         return(ENXIO);
 111 }
 112
 113 static int
 114 rgephy_attach(device_t dev)
 115 {
 116         struct mii_softc *sc;
 117         struct mii_attach_args *ma;
 118         struct mii_data *mii;
 119
 120         sc = device_get_softc(dev);
 121         ma = device_get_ivars(dev);
 122         mii_softc_init(sc, ma);
 123         sc->mii_dev = device_get_parent(dev);
 124
 125         mii = device_get_softc(sc->mii_dev);
 126         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 127
 128         sc->mii_inst = mii->mii_instance;
 129         sc->mii_service = rgephy_service;
 130         sc->mii_reset = rgephy_reset;
 131         sc->mii_pdata = mii;
 132
 133         sc->mii_flags |= MIIF_NOISOLATE;
 134         mii->mii_instance++;
 135
 136         rgephy_reset(sc);
 137
 138         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 139         if (sc->mii_capabilities & BMSR_EXTSTAT)
 140                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 141
 142         device_printf(dev, " ");
 143         if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
 144             (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
 145                 kprintf("no media present");
 146         else
 147                 mii_phy_add_media(sc);
 148         kprintf("\n");
 149
 150         MIIBUS_MEDIAINIT(sc->mii_dev);
 151         return(0);
 152 }
 153
 154 static int
 155 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 156 {
 157         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 158         int reg, speed, gig;
 159         uint16_t id2;
 160
 161         switch (cmd) {
 162         case MII_POLLSTAT:
 163                 /*
 164                  * If we're not polling our PHY instance, just return.
 165                  */
 166                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 167                         return (0);
 168                 break;
 169
 170         case MII_MEDIACHG:
 171                 /*
 172                  * If the media indicates a different PHY instance,
 173                  * isolate ourselves.
 174                  */
 175                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 176                         reg = PHY_READ(sc, MII_BMCR);
 177                         PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
 178                         return (0);
 179                 }
 180
 181                 /*
 182                  * If the interface is not up, don't do anything.
 183                  */
 184                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 185                         break;
 186
 187                 rgephy_reset(sc);       /* XXX hardware bug work-around */
 188
 189                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 190                 case IFM_AUTO:
 191 #ifdef foo
 192                         /*
 193                          * If we're already in auto mode, just return.
 194                          */
 195                         if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
 196                                 return (0);
 197 #endif
 198                         rgephy_mii_phy_auto(sc);
 199                         break;
 200                 case IFM_1000_T:
 201                         speed = RGEPHY_S1000;
 202                         goto setit;
 203                 case IFM_100_TX:
 204                         speed = RGEPHY_S100;
 205                         goto setit;
 206                 case IFM_10_T:
 207                         speed = RGEPHY_S10;
 208 setit:
 209                         rgephy_loop(sc);
 210                         if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
 211                                 speed |= RGEPHY_BMCR_FDX;
 212                                 gig = RGEPHY_1000CTL_AFD;
 213                         } else {
 214                                 gig = RGEPHY_1000CTL_AHD;
 215                         }
 216
 217                         PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
 218                         PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
 219                         PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
 220
 221                         if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
 222                                 break;
 223
 224                         PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
 225                         PHY_WRITE(sc, RGEPHY_MII_BMCR,
 226                             speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
 227
 228                         /*
 229                          * When settning the link manually, one side must
 230                          * be the master and the other the slave. However
 231                          * ifmedia doesn't give us a good way to specify
 232                          * this, so we fake it by using one of the LINK
 233                          * flags. If LINK0 is set, we program the PHY to
 234                          * be a master, otherwise it's a slave.
 235                          */
 236                         if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
 237                                 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 238                                     gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
 239                         } else {
 240                                 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 241                                     gig|RGEPHY_1000CTL_MSE);
 242                         }
 243                         break;
 244 #ifdef foo
 245                 case IFM_NONE:
 246                         PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
 247                         break;
 248 #endif
 249                 case IFM_100_T4:
 250                 default:
 251                         return (EINVAL);
 252                 }
 253                 break;
 254
 255         case MII_TICK:
 256                 /*
 257                  * If we're not currently selected, just return.
 258                  */
 259                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 260                         return (0);
 261
 262                 /*
 263                  * Is the interface even up?
 264                  */
 265                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 266                         return (0);
 267
 268                 /*
 269                  * Only used for autonegotiation.
 270                  */
 271                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
 272                         break;
 273
 274                 /*
 275                  * Check to see if we have link.  If we do, we don't
 276                  * need to restart the autonegotiation process.
 277                  *
 278                  * XXX Read the BMSR twice in case it's latched?
 279                  */
 280                 id2 = PHY_READ(sc, MII_PHYIDR2);
 281
 282                 if (MII_REV(id2) < 2) {
 283                         reg = PHY_READ(sc, RE_GMEDIASTAT);
 284                         if (reg & RE_GMEDIASTAT_LINK) {
 285                                 sc->mii_ticks = 0;
 286                                 break;
 287                         }
 288                 } else {
 289                         reg = PHY_READ(sc, RGEPHY_SR);
 290                         if (reg & RGEPHY_SR_LINK) {
 291                                 sc->mii_ticks = 0;
 292                                 break;
 293                         }
 294                 }
 295
 296                 /*
 297                  * Only retry autonegotiation every mii_anegticks seconds.
 298                  */
 299                 if (++sc->mii_ticks <= sc->mii_anegticks)
 300                         break;
 301
 302                 sc->mii_ticks = 0;
 303
 304                 /*
 305                  * Although rgephy_mii_phy_auto() always returns EJUSTRETURN,
 306                  * we should not rely on that.
 307                  */
 308                 if (rgephy_mii_phy_auto(sc) == EJUSTRETURN)
 309                         return (0);
 310                 break;
 311         }
 312
 313         /* Update the media status. */
 314         rgephy_status(sc);
 315
 316         /*
 317          * Callback if something changed. Note that we need to poke
 318          * the DSP on the RealTek PHYs if the media changes.
 319          */
 320         if (sc->mii_media_active != mii->mii_media_active ||
 321             sc->mii_media_status != mii->mii_media_status ||
 322             cmd == MII_MEDIACHG)
 323                 rgephy_load_dspcode(sc);
 324         mii_phy_update(sc, cmd);
 325         return (0);
 326 }
 327
 328 static void
 329 rgephy_status(struct mii_softc *sc)
 330 {
 331         struct mii_data *mii = sc->mii_pdata;
 332         int bmsr, bmcr;
 333         uint16_t id2;
 334
 335         mii->mii_media_status = IFM_AVALID;
 336         mii->mii_media_active = IFM_ETHER;
 337
 338         id2 = PHY_READ(sc, MII_PHYIDR2);
 339
 340         if (MII_REV(id2) < 2) {
 341                 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
 342                 if (bmsr & RE_GMEDIASTAT_LINK)
 343                         mii->mii_media_status |= IFM_ACTIVE;
 344         } else {
 345                 bmsr = PHY_READ(sc, RGEPHY_SR);
 346                 if (bmsr & RGEPHY_SR_LINK)
 347                         mii->mii_media_status |= IFM_ACTIVE;
 348         }
 349
 350         bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
 351
 352         bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
 353
 354         if (bmcr & RGEPHY_BMCR_LOOP)
 355                 mii->mii_media_active |= IFM_LOOP;
 356
 357         if (bmcr & RGEPHY_BMCR_AUTOEN) {
 358                 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
 359                         /* Erg, still trying, I guess... */
 360                         mii->mii_media_active |= IFM_NONE;
 361                         return;
 362                 }
 363         }
 364
 365         if (MII_REV(id2) < 2) {
 366                 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
 367                 if (bmsr & RE_GMEDIASTAT_1000MBPS)
 368                         mii->mii_media_active |= IFM_1000_T;
 369                 else if (bmsr & RE_GMEDIASTAT_100MBPS)
 370                         mii->mii_media_active |= IFM_100_TX;
 371                 else if (bmsr & RE_GMEDIASTAT_10MBPS)
 372                         mii->mii_media_active |= IFM_10_T;
 373                 else
 374                         mii->mii_media_active |= IFM_NONE;
 375                 if (bmsr & RE_GMEDIASTAT_FDX)
 376                         mii->mii_media_active |= IFM_FDX;
 377         } else {
 378                 bmsr = PHY_READ(sc, RGEPHY_SR);
 379                 if (RGEPHY_SR_SPEED(bmsr) == 2)
 380                         mii->mii_media_active |= IFM_1000_T;
 381                 else if (RGEPHY_SR_SPEED(bmsr) == 1)
 382                         mii->mii_media_active |= IFM_100_TX;
 383                 else if (RGEPHY_SR_SPEED(bmsr) == 0)
 384                         mii->mii_media_active |= IFM_10_T;
 385                 else
 386                         mii->mii_media_active |= IFM_NONE;
 387                 if (bmsr & RGEPHY_SR_FDX)
 388                         mii->mii_media_active |= IFM_FDX;
 389         }
 390 }
 391
 392 static int
 393 rgephy_mii_phy_auto(struct mii_softc *sc)
 394 {
 395         uint16_t id2;
 396
 397         id2 = PHY_READ(sc, MII_PHYIDR2);
 398         if (MII_REV(id2) < 2) {
 399                 rgephy_loop(sc);
 400                 rgephy_reset(sc);
 401         }
 402
 403         PHY_WRITE(sc, RGEPHY_MII_ANAR,
 404                   BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
 405         DELAY(1000);
 406         PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 407             RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
 408         DELAY(1000);
 409         PHY_WRITE(sc, RGEPHY_MII_BMCR,
 410             RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
 411         DELAY(100);
 412
 413         return (EJUSTRETURN);
 414 }
 415
 416 static void
 417 rgephy_loop(struct mii_softc *sc)
 418 {
 419         uint32_t bmsr;
 420         int i;
 421         uint16_t id2;
 422
 423         id2 = PHY_READ(sc, MII_PHYIDR2);
 424         if (MII_MODEL(id2) != MII_MODEL_xxREALTEK_RTL8251 &&
 425             MII_REV(id2) < 2) {
 426                 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
 427                 DELAY(1000);
 428         }
 429
 430         for (i = 0; i < 15000; i++) {
 431                 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
 432                 if (!(bmsr & RGEPHY_BMSR_LINK)) {
 433 #if 0
 434                         device_printf(sc->mii_dev, "looped %d\n", i);
 435 #endif
 436                         break;
 437                 }
 438                 DELAY(10);
 439         }
 440 }
 441
 442 #define PHY_SETBIT(x, y, z) \
 443         PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
 444 #define PHY_CLRBIT(x, y, z) \
 445         PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
 446
 447 /*
 448  * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
 449  * existing revisions of the 8169S/8110S chips need to be tuned in
 450  * order to reliably negotiate a 1000Mbps link. This is only needed
 451  * for rev 0 and rev 1 of the PHY. Later versions work without
 452  * any fixups.
 453  */
 454 static void
 455 rgephy_load_dspcode(struct mii_softc *sc)
 456 {
 457         int val;
 458
 459         if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8251 || sc->mii_rev > 1)
 460                 return;
 461
 462         PHY_WRITE(sc, 31, 0x0001);
 463         PHY_WRITE(sc, 21, 0x1000);
 464         PHY_WRITE(sc, 24, 0x65C7);
 465         PHY_CLRBIT(sc, 4, 0x0800);
 466         val = PHY_READ(sc, 4) & 0xFFF;
 467         PHY_WRITE(sc, 4, val);
 468         PHY_WRITE(sc, 3, 0x00A1);
 469         PHY_WRITE(sc, 2, 0x0008);
 470         PHY_WRITE(sc, 1, 0x1020);
 471         PHY_WRITE(sc, 0, 0x1000);
 472         PHY_SETBIT(sc, 4, 0x0800);
 473         PHY_CLRBIT(sc, 4, 0x0800);
 474         val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
 475         PHY_WRITE(sc, 4, val);
 476         PHY_WRITE(sc, 3, 0xFF41);
 477         PHY_WRITE(sc, 2, 0xDE60);
 478         PHY_WRITE(sc, 1, 0x0140);
 479         PHY_WRITE(sc, 0, 0x0077);
 480         val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
 481         PHY_WRITE(sc, 4, val);
 482         PHY_WRITE(sc, 3, 0xDF01);
 483         PHY_WRITE(sc, 2, 0xDF20);
 484         PHY_WRITE(sc, 1, 0xFF95);
 485         PHY_WRITE(sc, 0, 0xFA00);
 486         val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
 487         PHY_WRITE(sc, 4, val);
 488         PHY_WRITE(sc, 3, 0xFF41);
 489         PHY_WRITE(sc, 2, 0xDE20);
 490         PHY_WRITE(sc, 1, 0x0140);
 491         PHY_WRITE(sc, 0, 0x00BB);
 492         val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
 493         PHY_WRITE(sc, 4, val);
 494         PHY_WRITE(sc, 3, 0xDF01);
 495         PHY_WRITE(sc, 2, 0xDF20);
 496         PHY_WRITE(sc, 1, 0xFF95);
 497         PHY_WRITE(sc, 0, 0xBF00);
 498         PHY_SETBIT(sc, 4, 0x0800);
 499         PHY_CLRBIT(sc, 4, 0x0800);
 500         PHY_WRITE(sc, 31, 0x0000);
 501
 502         DELAY(40);
 503 }
 504
 505 static void
 506 rgephy_reset(struct mii_softc *sc)
 507 {
 508         uint16_t id2;
 509
 510         mii_phy_reset(sc);
 511
 512         id2 = PHY_READ(sc, MII_PHYIDR2);
 513         if (MII_REV(id2) < 2) {
 514                 DELAY(1000);
 515                 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN);
 516                 DELAY(1000);
 517         }
 518         rgephy_load_dspcode(sc);
 519 }