sys/dev/netif/e1000/e1000_ich8lan.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
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  10       this list of conditions and the following disclaimer.
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  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
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  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_ICH8LAN_H_
  36 #define _E1000_ICH8LAN_H_
  37
  38 #define ICH_FLASH_GFPREG                 0x0000
  39 #define ICH_FLASH_HSFSTS                 0x0004
  40 #define ICH_FLASH_HSFCTL                 0x0006
  41 #define ICH_FLASH_FADDR                  0x0008
  42 #define ICH_FLASH_FDATA0                 0x0010
  43
  44 /* Requires up to 10 seconds when MNG might be accessing part. */
  45 #define ICH_FLASH_READ_COMMAND_TIMEOUT   10000000
  46 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT  10000000
  47 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT  10000000
  48 #define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
  49 #define ICH_FLASH_CYCLE_REPEAT_COUNT     10
  50
  51 #define ICH_CYCLE_READ                   0
  52 #define ICH_CYCLE_WRITE                  2
  53 #define ICH_CYCLE_ERASE                  3
  54
  55 #define FLASH_GFPREG_BASE_MASK           0x1FFF
  56 #define FLASH_SECTOR_ADDR_SHIFT          12
  57
  58 #define ICH_FLASH_SEG_SIZE_256           256
  59 #define ICH_FLASH_SEG_SIZE_4K            4096
  60 #define ICH_FLASH_SEG_SIZE_8K            8192
  61 #define ICH_FLASH_SEG_SIZE_64K           65536
  62 #define ICH_FLASH_SECTOR_SIZE            4096
  63
  64 #define ICH_FLASH_REG_MAPSIZE            0x00A0
  65
  66 #define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
  67 #define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
  68 /* FW established a valid mode */
  69 #define E1000_ICH_FWSM_FW_VALID          0x00008000
  70
  71 #define E1000_ICH_MNG_IAMT_MODE          0x2
  72
  73 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  74                                  (ID_LED_OFF1_OFF2 <<  8) | \
  75                                  (ID_LED_OFF1_ON2  <<  4) | \
  76                                  (ID_LED_DEF1_DEF2))
  77
  78 #define E1000_ICH_NVM_SIG_WORD           0x13
  79 #define E1000_ICH_NVM_SIG_MASK           0xC000
  80 #define E1000_ICH_NVM_VALID_SIG_MASK     0xC0
  81 #define E1000_ICH_NVM_SIG_VALUE          0x80
  82
  83 #define E1000_ICH8_LAN_INIT_TIMEOUT      1500
  84
  85 #define E1000_FEXTNVM_SW_CONFIG        1
  86 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
  87
  88 #define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
  89
  90 #define E1000_ICH_RAR_ENTRIES            7
  91
  92 #define PHY_PAGE_SHIFT 5
  93 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
  94                            ((reg) & MAX_PHY_REG_ADDRESS))
  95 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
  96 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
  97 #define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
  98 #define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
  99
 100 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
 101 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 102 #define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
 103 #define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
 104
 105 /* PHY Wakeup Registers and defines */
 106 #define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
 107 #define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
 108 #define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
 109 #define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
 110 #define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
 111 #define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
 112 #define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
 113 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
 114 #define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
 115
 116 #define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
 117 #define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
 118 #define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
 119 #define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
 120 #define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
 121 #define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
 122 #define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
 123
 124 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 125 #define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
 126 #define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
 127 #define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
 128 #define HV_SCC_UPPER            PHY_REG(778, 16) /* Single Collision Count */
 129 #define HV_SCC_LOWER            PHY_REG(778, 17)
 130 #define HV_ECOL_UPPER           PHY_REG(778, 18) /* Excessive Collision Count */
 131 #define HV_ECOL_LOWER           PHY_REG(778, 19)
 132 #define HV_MCC_UPPER            PHY_REG(778, 20) /* Multiple Collision Count */
 133 #define HV_MCC_LOWER            PHY_REG(778, 21)
 134 #define HV_LATECOL_UPPER        PHY_REG(778, 23) /* Late Collision Count */
 135 #define HV_LATECOL_LOWER        PHY_REG(778, 24)
 136 #define HV_COLC_UPPER           PHY_REG(778, 25) /* Collision Count */
 137 #define HV_COLC_LOWER           PHY_REG(778, 26)
 138 #define HV_DC_UPPER             PHY_REG(778, 27) /* Defer Count */
 139 #define HV_DC_LOWER             PHY_REG(778, 28)
 140 #define HV_TNCRS_UPPER          PHY_REG(778, 29) /* Transmit with no CRS */
 141 #define HV_TNCRS_LOWER          PHY_REG(778, 30)
 142
 143 #define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
 144
 145 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 146 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 147
 148 /* SMBus Address Phy Register */
 149 #define HV_SMB_ADDR            PHY_REG(768, 26)
 150 #define HV_SMB_ADDR_PEC_EN     0x0200
 151 #define HV_SMB_ADDR_VALID      0x0080
 152
 153 /* Strapping Option Register - RO */
 154 #define E1000_STRAP                     0x0000C
 155 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 156 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 157
 158 /* OEM Bits Phy Register */
 159 #define HV_OEM_BITS            PHY_REG(768, 25)
 160 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 161 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 162 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 163
 164 #define LCD_CFG_PHY_ADDR_BIT   0x0020 /* Phy address bit from LCD Config word */
 165
 166 /* KMRN Mode Control */
 167 #define HV_KMRN_MODE_CTRL       PHY_REG(769, 16)
 168 #define HV_KMRN_MDIO_SLOW       0x0400
 169
 170 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 171
 172 /*
 173  * Additional interrupts need to be handled for ICH family:
 174  *  DSW = The FW changed the status of the DISSW bit in FWSM
 175  *  PHYINT = The LAN connected device generates an interrupt
 176  *  EPRST = Manageability reset event
 177  */
 178 #define IMS_ICH_ENABLE_MASK (\
 179     E1000_IMS_DSW   | \
 180     E1000_IMS_PHYINT | \
 181     E1000_IMS_EPRST)
 182
 183 /* Additional interrupt register bit definitions */
 184 #define E1000_ICR_LSECPNC       0x00004000          /* PN threshold - client */
 185 #define E1000_IMS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
 186 #define E1000_ICS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
 187
 188 /* Security Processing bit Indication */
 189 #define E1000_RXDEXT_LINKSEC_STATUS_LSECH       0x01000000
 190 #define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK     0x60000000
 191 #define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH  0x20000000
 192 #define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
 193 #define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG      0x60000000
 194
 195
 196 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
 197                                                  bool state);
 198 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 199 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
 200 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);
 201 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
 202 s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
 203 s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 204 #endif