sys/dev/disk/aic/aic6360reg.h

   1 /*-
   2  * Copyright (c) 1994 Charles Hannum.
   3  * Copyright (c) 1994 Jarle Greipsland.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Jarle Greipsland
  17  * 4. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  22  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  23  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  24  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  25  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  26  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  28  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  29  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * $FreeBSD: src/sys/dev/aic/aic6360reg.h,v 1.1 1999/10/21 08:56:52 luoqi Exp $
  33  * $DragonFly: src/sys/dev/disk/aic/aic6360reg.h,v 1.3 2008/01/05 07:27:09 pavalos Exp $
  34  */
  35
  36 #define SCSISEQ         0x00    /* SCSI sequence control */
  37 #define SXFRCTL0        0x01    /* SCSI transfer control 0 */
  38 #define SXFRCTL1        0x02    /* SCSI transfer control 1 */
  39 #define SCSISIGI        0x03    /* SCSI signal in */
  40 #define SCSISIGO        0x03    /* SCSI signal out */
  41 #define SCSIRATE        0x04    /* SCSI rate control */
  42 #define SCSIID          0x05    /* SCSI ID */
  43 #define SELID           0x05    /* Selection/Reselection ID */
  44 #define SCSIDAT         0x06    /* SCSI Latched Data */
  45 #define SCSIBUS         0x07    /* SCSI Data Bus*/
  46 #define STCNT0          0x08    /* SCSI transfer count */
  47 #define STCNT1          0x09
  48 #define STCNT2          0x0a
  49 #define CLRSINT0        0x0b    /* Clear SCSI interrupts 0 */
  50 #define SSTAT0          0x0b    /* SCSI interrupt status 0 */
  51 #define CLRSINT1        0x0c    /* Clear SCSI interrupts 1 */
  52 #define SSTAT1          0x0c    /* SCSI status 1 */
  53 #define SSTAT2          0x0d    /* SCSI status 2 */
  54 #define SCSITEST        0x0e    /* SCSI test control */
  55 #define SSTAT3          0x0e    /* SCSI status 3 */
  56 #define CLRSERR         0x0f    /* Clear SCSI errors */
  57 #define SSTAT4          0x0f    /* SCSI status 4 */
  58 #define SIMODE0         0x10    /* SCSI interrupt mode 0 */
  59 #define SIMODE1         0x11    /* SCSI interrupt mode 1 */
  60 #define DMACNTRL0       0x12    /* DMA control 0 */
  61 #define DMACNTRL1       0x13    /* DMA control 1 */
  62 #define DMASTAT         0x14    /* DMA status */
  63 #define FIFOSTAT        0x15    /* FIFO status */
  64 #define DMADATA         0x16    /* DMA data */
  65 #define DMADATAL        0x16    /* DMA data low byte */
  66 #define DMADATAH        0x17    /* DMA data high byte */
  67 #define BRSTCNTRL       0x18    /* Burst Control */
  68 #define DMADATALONG     0x18
  69 #define PORTA           0x1a    /* Port A */
  70 #define PORTB           0x1b    /* Port B */
  71 #define REV             0x1c    /* Revision (001 for 6360) */
  72 #define STACK           0x1d    /* Stack */
  73 #define TEST            0x1e    /* Test register */
  74 #define ID              0x1f    /* ID register */
  75
  76 #define IDSTRING_AIC6360  "(C)1991ADAPTECAIC6360           "
  77 #define IDSTRING_AIC6370  "(C)1994ADAPTECAIC6370"
  78 #define IDSTRING_GM82C700 "(C)1993 GoldStarGM82C700        "
  79
  80 /* What all the bits do */
  81
  82 /* SCSISEQ */
  83 #define TEMODEO         0x80
  84 #define ENSELO          0x40
  85 #define ENSELI          0x20
  86 #define ENRESELI        0x10
  87 #define ENAUTOATNO      0x08
  88 #define ENAUTOATNI      0x04
  89 #define ENAUTOATNP      0x02
  90 #define SCSIRSTO        0x01
  91
  92 /* SXFRCTL0 */
  93 #define SCSIEN          0x80
  94 #define DMAEN           0x40
  95 #define CHEN            0x20
  96 #define CLRSTCNT        0x10
  97 #define SPIOEN          0x08
  98 #define CLRCH           0x02
  99
 100 /* SXFRCTL1 */
 101 #define BITBUCKET       0x80
 102 #define SWRAPEN         0x40
 103 #define ENSPCHK         0x20
 104 #define STIMESEL1       0x10
 105 #define STIMESEL0       0x08
 106 #define STIMO_256ms     0x00
 107 #define STIMO_128ms     0x08
 108 #define STIMO_64ms      0x10
 109 #define STIMO_32ms      0x18
 110 #define ENSTIMER        0x04
 111 #define BYTEALIGN       0x02
 112
 113 /* SCSISIGI */
 114 #define CDI             0x80
 115 #define IOI             0x40
 116 #define MSGI            0x20
 117 #define ATNI            0x10
 118 #define SELI            0x08
 119 #define BSYI            0x04
 120 #define REQI            0x02
 121 #define ACKI            0x01
 122
 123 /* Important! The 3 most significant bits of this register, in initiator mode,
 124  * represents the "expected" SCSI bus phase and can be used to trigger phase
 125  * mismatch and phase change interrupts.  But more important:  If there is a
 126  * phase mismatch the chip will not transfer any data!  This is actually a nice
 127  * feature as it gives us a bit more control over what is happening when we are
 128  * bursting data (in) through the FIFOs and the phase suddenly changes from
 129  * DATA IN to STATUS or MESSAGE IN.  The transfer will stop and wait for the
 130  * proper phase to be set in this register instead of dumping the bits into the
 131  * FIFOs.
 132  */
 133 /* SCSISIGO */
 134 #define CDO             0x80
 135 #define IOO             0x40
 136 #define MSGO            0x20
 137 #define ATNO            0x10
 138 #define SELO            0x08
 139 #define BSYO            0x04
 140 #define REQO            0x02
 141 #define ACKO            0x01
 142
 143 /* Information transfer phases */
 144 #define PH_DATAOUT      (0)
 145 #define PH_DATAIN       (IOI)
 146 #define PH_CMD          (CDI)
 147 #define PH_STAT         (CDI|IOI)
 148 #define PH_MSGOUT       (MSGI|CDI)
 149 #define PH_MSGIN        (MSGI|CDI|IOI)
 150 #define PH_MASK         (MSGI|CDI|IOI)
 151
 152 /* SCSIRATE */
 153 #define SXFR2           0x40
 154 #define SXFR1           0x20
 155 #define SXFR0           0x10
 156 #define SOFS3           0x08
 157 #define SOFS2           0x04
 158 #define SOFS1           0x02
 159 #define SOFS0           0x01
 160
 161 /* SCSI ID */
 162 #define OID2            0x40
 163 #define OID1            0x20
 164 #define OID0            0x10
 165 #define OID_S           4       /* shift value */
 166 #define TID2            0x04
 167 #define TID1            0x02
 168 #define TID0            0x01
 169 #define SCSI_ID_MASK    0x7
 170
 171 /* SCSI selection/reselection ID (both target *and* initiator) */
 172 #define SELID7          0x80
 173 #define SELID6          0x40
 174 #define SELID5          0x20
 175 #define SELID4          0x10
 176 #define SELID3          0x08
 177 #define SELID2          0x04
 178 #define SELID1          0x02
 179 #define SELID0          0x01
 180
 181 /* CLRSINT0                      Clears what? (interrupt and/or status bit) */
 182 #define SETSDONE        0x80
 183 #define CLRSELDO        0x40    /* I */
 184 #define CLRSELDI        0x20    /* I+ */
 185 #define CLRSELINGO      0x10    /* I */
 186 #define CLRSWRAP        0x08    /* I+S */
 187 #define CLRSDONE        0x04    /* I+S */
 188 #define CLRSPIORDY      0x02    /* I */
 189 #define CLRDMADONE      0x01    /* I */
 190
 191 /* SSTAT0                          Howto clear */
 192 #define TARGET          0x80
 193 #define SELDO           0x40    /* Selfclearing */
 194 #define SELDI           0x20    /* Selfclearing when CLRSELDI is set */
 195 #define SELINGO         0x10    /* Selfclearing */
 196 #define SWRAP           0x08    /* CLRSWAP */
 197 #define SDONE           0x04    /* Not used in initiator mode */
 198 #define SPIORDY         0x02    /* Selfclearing (op on SCSIDAT) */
 199 #define DMADONE         0x01    /* Selfclearing (all FIFOs empty & T/C */
 200
 201 /* CLRSINT1                      Clears what? */
 202 #define CLRSELTIMO      0x80    /* I+S */
 203 #define CLRATNO         0x40
 204 #define CLRSCSIRSTI     0x20    /* I+S */
 205 #define CLRBUSFREE      0x08    /* I+S */
 206 #define CLRSCSIPERR     0x04    /* I+S */
 207 #define CLRPHASECHG     0x02    /* I+S */
 208 #define CLRREQINIT      0x01    /* I+S */
 209
 210 /* SSTAT1                       How to clear?  When set?*/
 211 #define SELTO           0x80    /* C            select out timeout */
 212 #define ATNTARG         0x40    /* Not used in initiator mode */
 213 #define SCSIRSTI        0x20    /* C            RST asserted */
 214 #define PHASEMIS        0x10    /* Selfclearing */
 215 #define BUSFREE         0x08    /* C            bus free condition */
 216 #define SCSIPERR        0x04    /* C            parity error on inbound data */
 217 #define PHASECHG        0x02    /* C         phase in SCSISIGI doesn't match */
 218 #define REQINIT         0x01    /* C or ACK     asserting edge of REQ */
 219
 220 /* SSTAT2 */
 221 #define SOFFSET         0x20
 222 #define SEMPTY          0x10
 223 #define SFULL           0x08
 224 #define SFCNT2          0x04
 225 #define SFCNT1          0x02
 226 #define SFCNT0          0x01
 227
 228 /* SCSITEST */
 229 #define SCTESTU         0x08
 230 #define SCTESTD         0x04
 231 #define STCTEST         0x01
 232
 233 /* SSTAT3 */
 234 #define SCSICNT3        0x80
 235 #define SCSICNT2        0x40
 236 #define SCSICNT1        0x20
 237 #define SCSICNT0        0x10
 238 #define OFFCNT3         0x08
 239 #define OFFCNT2         0x04
 240 #define OFFCNT1         0x02
 241 #define OFFCNT0         0x01
 242
 243 /* CLRSERR */
 244 #define CLRSYNCERR      0x04
 245 #define CLRFWERR        0x02
 246 #define CLRFRERR        0x01
 247
 248 /* SSTAT4 */
 249 #define SYNCERR         0x04
 250 #define FWERR           0x02
 251 #define FRERR           0x01
 252
 253 /* SIMODE0 */
 254 #define ENSELDO         0x40
 255 #define ENSELDI         0x20
 256 #define ENSELINGO       0x10
 257 #define ENSWRAP         0x08
 258 #define ENSDONE         0x04
 259 #define ENSPIORDY       0x02
 260 #define ENDMADONE       0x01
 261
 262 /* SIMODE1 */
 263 #define ENSELTIMO       0x80
 264 #define ENATNTARG       0x40
 265 #define ENSCSIRST       0x20
 266 #define ENPHASEMIS      0x10
 267 #define ENBUSFREE       0x08
 268 #define ENSCSIPERR      0x04
 269 #define ENPHASECHG      0x02
 270 #define ENREQINIT       0x01
 271
 272 /* DMACNTRL0 */
 273 #define ENDMA           0x80
 274 #define B8MODE          0x40
 275 #define DMA             0x20
 276 #define DWORDPIO        0x10
 277 #define WRITE           0x08
 278 #define INTEN           0x04
 279 #define RSTFIFO         0x02
 280 #define SWINT           0x01
 281
 282 /* DMACNTRL1 */
 283 #define PWRDWN          0x80
 284 #define ENSTK32         0x40
 285 #define STK4            0x10
 286 #define STK3            0x08
 287 #define STK2            0x04
 288 #define STK1            0x02
 289 #define STK0            0x01
 290
 291 /* DMASTAT */
 292 #define ATDONE          0x80
 293 #define WORDRDY         0x40
 294 #define INTSTAT         0x20
 295 #define DFIFOFULL       0x10
 296 #define DFIFOEMP        0x08
 297 #define DFIFOHF         0x04
 298 #define DWORDRDY        0x02
 299
 300 /* BRSTCNTRL */
 301 #define BON3            0x80
 302 #define BON2            0x40
 303 #define BON1            0x20
 304 #define BON0            0x10
 305 #define BOFF3           0x08
 306 #define BOFF2           0x04
 307 #define BOFF1           0x02
 308 #define BOFF0           0x01
 309
 310 /* TEST */
 311 #define BOFFTMR         0x40
 312 #define BONTMR          0x20
 313 #define STCNTH          0x10
 314 #define STCNTM          0x08
 315 #define STCNTL          0x04
 316 #define SCSIBLK         0x02
 317 #define DMABLK          0x01
 318
 319 /* PORTA */
 320 #define PORTA_ID(a)     ((a) & 7)
 321 #define PORTA_IRQ(a)    ((((a) >> 3) & 3) + 9)
 322 #define PORTA_DRQ(a)    ((((a) >> 5) & 3) ? (((a) >> 5) & 3) + 4 : 0)
 323 #define PORTA_PARITY(a) ((a) & 0x80)
 324
 325 /* PORTB */
 326 #define PORTB_EXTTRAN(b)((b) & 1)
 327 #define PORTB_DISC(b)   ((b) & 4)
 328 #define PORTB_SYNC(b)   ((b) & 8)
 329 #define PORTB_FSYNC(b)  ((b) & 0x10)
 330 #define PORTB_BOOT(b)   ((b) & 0x40)
 331 #define PORTB_DMA(b)    ((b) & 0x80)
 332
 333 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */
 334 #define EISA_BRST_TIM   ((15<<4) + 1)   /* 15us on, 1us off */
 335
 336 #define FIFOSIZE        128