2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
28 * $DragonFly: src/sys/dev/agp/agp_i810.c,v 1.17 2008/01/08 04:25:07 hasso Exp $
32 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
33 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
46 #include <bus/pci/pcivar.h>
47 #include <bus/pci/pcireg.h>
52 #include <vm/vm_object.h>
53 #include <vm/vm_page.h>
54 #include <vm/vm_pageout.h>
57 #include <machine/md_var.h>
59 #define bus_read_1(r, o) \
60 bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
61 #define bus_read_4(r, o) \
62 bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
63 #define bus_write_4(r, o, v) \
64 bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
66 MALLOC_DECLARE(M_AGP
);
69 CHIP_I810
, /* i810/i815 */
70 CHIP_I830
, /* 830M/845G */
71 CHIP_I855
, /* 852GM/855GM/865G */
72 CHIP_I915
, /* 915G/915GM */
74 CHIP_G33
, /* G33/Q33/Q35 */
77 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
78 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
79 * start of the stolen memory, and should only be accessed by the OS through
80 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
81 * is registers, second 512KB is GATT.
83 static struct resource_spec agp_i810_res_spec
[] = {
84 { SYS_RES_MEMORY
, AGP_I810_MMADR
, RF_ACTIVE
| RF_SHAREABLE
},
88 static struct resource_spec agp_i915_res_spec
[] = {
89 { SYS_RES_MEMORY
, AGP_I915_MMADR
, RF_ACTIVE
| RF_SHAREABLE
},
90 { SYS_RES_MEMORY
, AGP_I915_GTTADR
, RF_ACTIVE
| RF_SHAREABLE
},
94 static struct resource_spec agp_i965_res_spec
[] = {
95 { SYS_RES_MEMORY
, AGP_I965_GTTMMADR
, RF_ACTIVE
| RF_SHAREABLE
},
99 struct agp_i810_softc
{
100 struct agp_softc agp
;
101 u_int32_t initial_aperture
; /* aperture size at startup */
102 struct agp_gatt
*gatt
;
103 int chiptype
; /* i810-like or i830 */
104 u_int32_t dcache_size
; /* i810 only */
105 u_int32_t stolen
; /* number of i830/845 gtt entries for stolen memory */
106 device_t bdev
; /* bridge device */
108 void *argb_cursor
; /* contigmalloc area for ARGB cursor */
110 struct resource_spec
* sc_res_spec
;
111 struct resource
*sc_res
[2];
114 /* For adding new devices, devid is the id of the graphics controller
115 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
116 * second head should never be added. The bridge_offset is the offset to
117 * subtract from devid to get the id of the hostb that the device is on.
119 static const struct agp_i810_match
{
124 } agp_i810_matches
[] = {
125 {0x71218086, CHIP_I810
, 0x00010000,
126 "Intel 82810 (i810 GMCH) SVGA controller"},
127 {0x71238086, CHIP_I810
, 0x00010000,
128 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
129 {0x71258086, CHIP_I810
, 0x00010000,
130 "Intel 82810E (i810E GMCH) SVGA controller"},
131 {0x11328086, CHIP_I810
, 0x00020000,
132 "Intel 82815 (i815 GMCH) SVGA controller"},
133 {0x35778086, CHIP_I830
, 0x00020000,
134 "Intel 82830M (830M GMCH) SVGA controller"},
135 {0x25628086, CHIP_I830
, 0x00020000,
136 "Intel 82845M (845M GMCH) SVGA controller"},
137 {0x35828086, CHIP_I855
, 0x00020000,
139 {0x25728086, CHIP_I855
, 0x00020000,
140 "Intel 82865G (865G GMCH) SVGA controller"},
141 {0x25828086, CHIP_I915
, 0x00020000,
142 "Intel 82915G (915G GMCH) SVGA controller"},
143 {0x258A8086, CHIP_I915
, 0x00020000,
144 "Intel E7221 SVGA controller"},
145 {0x25928086, CHIP_I915
, 0x00020000,
146 "Intel 82915GM (915GM GMCH) SVGA controller"},
147 {0x27728086, CHIP_I915
, 0x00020000,
148 "Intel 82945G (945G GMCH) SVGA controller"},
149 {0x27A28086, CHIP_I915
, 0x00020000,
150 "Intel 82945GM (945GM GMCH) SVGA controller"},
151 {0x27AE8086, CHIP_I915
, 0x00020000,
152 "Intel 945GME SVGA controller"},
153 {0x29728086, CHIP_I965
, 0x00020000,
154 "Intel 946GZ SVGA controller"},
155 {0x29828086, CHIP_I965
, 0x00020000,
156 "Intel G965 SVGA controller"},
157 {0x29928086, CHIP_I965
, 0x00020000,
158 "Intel Q965 SVGA controller"},
159 {0x29a28086, CHIP_I965
, 0x00020000,
160 "Intel G965 SVGA controller"},
162 {0x29b28086, CHIP_G33, 0x00020000,
163 "Intel Q35 SVGA controller"},
164 {0x29c28086, CHIP_G33, 0x00020000,
165 "Intel G33 SVGA controller"},
166 {0x29d28086, CHIP_G33, 0x00020000,
167 "Intel Q33 SVGA controller"},
169 {0x2a028086, CHIP_I965
, 0x00020000,
170 "Intel GM965 SVGA controller"},
171 {0x2a128086, CHIP_I965
, 0x00020000,
172 "Intel GME965 SVGA controller"},
176 static const struct agp_i810_match
*
177 agp_i810_match(device_t dev
)
181 if (pci_get_class(dev
) != PCIC_DISPLAY
182 || pci_get_subclass(dev
) != PCIS_DISPLAY_VGA
)
185 devid
= pci_get_devid(dev
);
186 for (i
= 0; agp_i810_matches
[i
].devid
!= 0; i
++) {
187 if (agp_i810_matches
[i
].devid
== devid
)
190 if (agp_i810_matches
[i
].devid
== 0)
193 return &agp_i810_matches
[i
];
197 * Find bridge device.
200 agp_i810_find_bridge(device_t dev
)
202 device_t
*children
, child
;
205 const struct agp_i810_match
*match
;
207 match
= agp_i810_match(dev
);
208 devid
= match
->devid
- match
->bridge_offset
;
210 if (device_get_children(device_get_parent(dev
), &children
, &nchildren
))
213 for (i
= 0; i
< nchildren
; i
++) {
216 if (pci_get_devid(child
) == devid
) {
217 kfree(children
, M_TEMP
);
221 kfree(children
, M_TEMP
);
226 agp_i810_identify(driver_t
*driver
, device_t parent
)
229 if (device_find_child(parent
, "agp", -1) == NULL
&&
230 agp_i810_match(parent
))
231 device_add_child(parent
, "agp", -1);
235 agp_i810_probe(device_t dev
)
238 const struct agp_i810_match
*match
;
242 if (resource_disabled("agp", device_get_unit(dev
)))
244 match
= agp_i810_match(dev
);
248 bdev
= agp_i810_find_bridge(dev
);
251 kprintf("I810: can't find bridge device\n");
256 * checking whether internal graphics device has been activated.
258 switch (match
->chiptype
) {
260 smram
= pci_read_config(bdev
, AGP_I810_SMRAM
, 1);
261 if ((smram
& AGP_I810_SMRAM_GMS
) ==
262 AGP_I810_SMRAM_GMS_DISABLED
) {
264 kprintf("I810: disabled, not probing\n");
270 gcc1
= pci_read_config(bdev
, AGP_I830_GCC1
, 1);
271 if ((gcc1
& AGP_I830_GCC1_DEV2
) ==
272 AGP_I830_GCC1_DEV2_DISABLED
) {
274 kprintf("I830: disabled, not probing\n");
281 deven
= pci_read_config(bdev
, AGP_I915_DEVEN
, 4);
282 if ((deven
& AGP_I915_DEVEN_D2F0
) ==
283 AGP_I915_DEVEN_D2F0_DISABLED
) {
285 kprintf("I915: disabled, not probing\n");
292 if (match
->devid
== 0x35828086) {
293 switch (pci_read_config(dev
, AGP_I85X_CAPID
, 1)) {
296 "Intel 82855GME (855GME GMCH) SVGA controller");
300 "Intel 82855GM (855GM GMCH) SVGA controller");
304 "Intel 82852GME (852GME GMCH) SVGA controller");
308 "Intel 82852GM (852GM GMCH) SVGA controller");
312 "Intel 8285xM (85xGM GMCH) SVGA controller");
316 device_set_desc(dev
, match
->name
);
319 return BUS_PROBE_DEFAULT
;
323 agp_i810_dump_regs(device_t dev
)
325 struct agp_i810_softc
*sc
= device_get_softc(dev
);
327 device_printf(dev
, "AGP_I810_PGTBL_CTL: %08x\n",
328 bus_read_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
));
330 switch (sc
->chiptype
) {
332 device_printf(dev
, "AGP_I810_MISCC: 0x%04x\n",
333 pci_read_config(sc
->bdev
, AGP_I810_MISCC
, 2));
336 device_printf(dev
, "AGP_I830_GCC1: 0x%02x\n",
337 pci_read_config(sc
->bdev
, AGP_I830_GCC1
, 1));
340 device_printf(dev
, "AGP_I855_GCC1: 0x%02x\n",
341 pci_read_config(sc
->bdev
, AGP_I855_GCC1
, 1));
346 device_printf(dev
, "AGP_I855_GCC1: 0x%02x\n",
347 pci_read_config(sc
->bdev
, AGP_I855_GCC1
, 1));
348 device_printf(dev
, "AGP_I915_MSAC: 0x%02x\n",
349 pci_read_config(sc
->bdev
, AGP_I915_MSAC
, 1));
352 device_printf(dev
, "Aperture resource size: %d bytes\n",
353 AGP_GET_APERTURE(dev
));
357 agp_i810_attach(device_t dev
)
359 struct agp_i810_softc
*sc
= device_get_softc(dev
);
360 struct agp_gatt
*gatt
;
361 const struct agp_i810_match
*match
;
364 sc
->bdev
= agp_i810_find_bridge(dev
);
368 match
= agp_i810_match(dev
);
369 sc
->chiptype
= match
->chiptype
;
371 switch (sc
->chiptype
) {
375 sc
->sc_res_spec
= agp_i810_res_spec
;
376 agp_set_aperture_resource(dev
, AGP_APBASE
);
380 sc
->sc_res_spec
= agp_i915_res_spec
;
381 agp_set_aperture_resource(dev
, AGP_I915_GMADR
);
384 sc
->sc_res_spec
= agp_i965_res_spec
;
385 agp_set_aperture_resource(dev
, AGP_I915_GMADR
);
389 error
= agp_generic_attach(dev
);
393 if (sc
->chiptype
!= CHIP_I965
&& sc
->chiptype
!= CHIP_G33
&&
394 ptoa((vm_paddr_t
)Maxmem
) > 0xfffffffful
)
396 device_printf(dev
, "agp_i810.c does not support physical "
397 "memory above 4GB.\n");
401 if (bus_alloc_resources(dev
, sc
->sc_res_spec
, sc
->sc_res
)) {
402 agp_generic_detach(dev
);
406 sc
->initial_aperture
= AGP_GET_APERTURE(dev
);
407 if (sc
->initial_aperture
== 0) {
408 device_printf(dev
, "bad initial aperture size, disabling\n");
412 gatt
= kmalloc( sizeof(struct agp_gatt
), M_AGP
, M_INTWAIT
);
415 gatt
->ag_entries
= AGP_GET_APERTURE(dev
) >> AGP_PAGE_SHIFT
;
417 if ( sc
->chiptype
== CHIP_I810
) {
418 /* Some i810s have on-chip memory called dcache */
419 if (bus_read_1(sc
->sc_res
[0], AGP_I810_DRT
) &
420 AGP_I810_DRT_POPULATED
)
421 sc
->dcache_size
= 4 * 1024 * 1024;
425 /* According to the specs the gatt on the i810 must be 64k */
426 gatt
->ag_virtual
= contigmalloc( 64 * 1024, M_AGP
, 0,
427 0, ~0, PAGE_SIZE
, 0);
428 if (!gatt
->ag_virtual
) {
430 device_printf(dev
, "contiguous allocation failed\n");
431 bus_release_resources(dev
, sc
->sc_res_spec
,
434 agp_generic_detach(dev
);
437 bzero(gatt
->ag_virtual
, gatt
->ag_entries
* sizeof(u_int32_t
));
439 gatt
->ag_physical
= vtophys((vm_offset_t
) gatt
->ag_virtual
);
441 /* Install the GATT. */
442 bus_write_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
,
443 gatt
->ag_physical
| 1);
444 } else if ( sc
->chiptype
== CHIP_I830
) {
445 /* The i830 automatically initializes the 128k gatt on boot. */
446 unsigned int gcc1
, pgtblctl
;
448 gcc1
= pci_read_config(sc
->bdev
, AGP_I830_GCC1
, 1);
449 switch (gcc1
& AGP_I830_GCC1_GMS
) {
450 case AGP_I830_GCC1_GMS_STOLEN_512
:
451 sc
->stolen
= (512 - 132) * 1024 / 4096;
453 case AGP_I830_GCC1_GMS_STOLEN_1024
:
454 sc
->stolen
= (1024 - 132) * 1024 / 4096;
456 case AGP_I830_GCC1_GMS_STOLEN_8192
:
457 sc
->stolen
= (8192 - 132) * 1024 / 4096;
461 device_printf(dev
, "unknown memory configuration, disabling\n");
462 bus_release_resources(dev
, sc
->sc_res_spec
,
465 agp_generic_detach(dev
);
468 if (sc
->stolen
> 0) {
469 device_printf(dev
, "detected %dk stolen memory\n",
472 device_printf(dev
, "aperture size is %dM\n",
473 sc
->initial_aperture
/ 1024 / 1024);
475 /* GATT address is already in there, make sure it's enabled */
476 pgtblctl
= bus_read_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
);
478 bus_write_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
, pgtblctl
);
480 gatt
->ag_physical
= pgtblctl
& ~1;
481 } else if (sc
->chiptype
== CHIP_I855
|| sc
->chiptype
== CHIP_I915
||
482 sc
->chiptype
== CHIP_I965
|| sc
->chiptype
== CHIP_G33
) {
483 unsigned int gcc1
, pgtblctl
, stolen
, gtt_size
;
485 /* Stolen memory is set up at the beginning of the aperture by
486 * the BIOS, consisting of the GATT followed by 4kb for the
489 switch (sc
->chiptype
) {
498 switch (bus_read_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
) &
499 AGP_I810_PGTBL_SIZE_MASK
) {
500 case AGP_I810_PGTBL_SIZE_128KB
:
503 case AGP_I810_PGTBL_SIZE_256KB
:
506 case AGP_I810_PGTBL_SIZE_512KB
:
510 device_printf(dev
, "Bad PGTBL size\n");
511 bus_release_resources(dev
, sc
->sc_res_spec
,
514 agp_generic_detach(dev
);
519 device_printf(dev
, "Bad chiptype\n");
520 bus_release_resources(dev
, sc
->sc_res_spec
,
523 agp_generic_detach(dev
);
527 /* GCC1 is called MGGC on i915+ */
528 gcc1
= pci_read_config(sc
->bdev
, AGP_I855_GCC1
, 1);
529 switch (gcc1
& AGP_I855_GCC1_GMS
) {
530 case AGP_I855_GCC1_GMS_STOLEN_1M
:
533 case AGP_I855_GCC1_GMS_STOLEN_4M
:
536 case AGP_I855_GCC1_GMS_STOLEN_8M
:
539 case AGP_I855_GCC1_GMS_STOLEN_16M
:
542 case AGP_I855_GCC1_GMS_STOLEN_32M
:
545 case AGP_I915_GCC1_GMS_STOLEN_48M
:
548 case AGP_I915_GCC1_GMS_STOLEN_64M
:
551 case AGP_G33_GCC1_GMS_STOLEN_128M
:
554 case AGP_G33_GCC1_GMS_STOLEN_256M
:
558 device_printf(dev
, "unknown memory configuration, "
560 bus_release_resources(dev
, sc
->sc_res_spec
,
563 agp_generic_detach(dev
);
566 sc
->stolen
= (stolen
- gtt_size
- 4) * 1024 / 4096;
568 device_printf(dev
, "detected %dk stolen memory\n", sc
->stolen
* 4);
569 device_printf(dev
, "aperture size is %dM\n", sc
->initial_aperture
/ 1024 / 1024);
571 /* GATT address is already in there, make sure it's enabled */
572 pgtblctl
= bus_read_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
);
574 bus_write_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
, pgtblctl
);
576 gatt
->ag_physical
= pgtblctl
& ~1;
579 /* Add a device for the drm to attach to */
580 /* XXX This will go away once we have vgapci */
581 if (!device_add_child(dev
, "drmsub", -1))
582 device_printf(dev
, "could not add drm subdevice\n");
585 agp_i810_dump_regs(dev
);
591 agp_i810_detach(device_t dev
)
593 struct agp_i810_softc
*sc
= device_get_softc(dev
);
598 /* Clear the GATT base. */
599 if ( sc
->chiptype
== CHIP_I810
) {
600 bus_write_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
, 0);
602 unsigned int pgtblctl
;
603 pgtblctl
= bus_read_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
);
605 bus_write_4(sc
->sc_res
[0], AGP_I810_PGTBL_CTL
, pgtblctl
);
608 /* Put the aperture back the way it started. */
609 AGP_SET_APERTURE(dev
, sc
->initial_aperture
);
611 if ( sc
->chiptype
== CHIP_I810
) {
612 contigfree(sc
->gatt
->ag_virtual
, 64 * 1024, M_AGP
);
614 kfree(sc
->gatt
, M_AGP
);
616 bus_release_resources(dev
, sc
->sc_res_spec
, sc
->sc_res
);
619 /* XXX This will go away once we have vgapci */
620 child
= device_find_child(dev
, "drmsub", 0);
622 device_delete_child(dev
, child
);
628 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
629 * while returning failure on later chipsets when an actual change is
632 * This whole function is likely bogus, as the kernel would probably need to
633 * reconfigure the placement of the AGP aperture if a larger size is requested,
634 * which doesn't happen currently.
637 agp_i810_set_aperture(device_t dev
, u_int32_t aperture
)
639 struct agp_i810_softc
*sc
= device_get_softc(dev
);
640 u_int16_t miscc
, gcc1
;
642 switch (sc
->chiptype
) {
645 * Double check for sanity.
647 if (aperture
!= 32 * 1024 * 1024 && aperture
!= 64 * 1024 * 1024) {
648 device_printf(dev
, "bad aperture size %d\n", aperture
);
652 miscc
= pci_read_config(sc
->bdev
, AGP_I810_MISCC
, 2);
653 miscc
&= ~AGP_I810_MISCC_WINSIZE
;
654 if (aperture
== 32 * 1024 * 1024)
655 miscc
|= AGP_I810_MISCC_WINSIZE_32
;
657 miscc
|= AGP_I810_MISCC_WINSIZE_64
;
659 pci_write_config(sc
->bdev
, AGP_I810_MISCC
, miscc
, 2);
662 if (aperture
!= 64 * 1024 * 1024 &&
663 aperture
!= 128 * 1024 * 1024) {
664 device_printf(dev
, "bad aperture size %d\n", aperture
);
667 gcc1
= pci_read_config(sc
->bdev
, AGP_I830_GCC1
, 2);
668 gcc1
&= ~AGP_I830_GCC1_GMASIZE
;
669 if (aperture
== 64 * 1024 * 1024)
670 gcc1
|= AGP_I830_GCC1_GMASIZE_64
;
672 gcc1
|= AGP_I830_GCC1_GMASIZE_128
;
674 pci_write_config(sc
->bdev
, AGP_I830_GCC1
, gcc1
, 2);
680 return agp_generic_set_aperture(dev
, aperture
);
687 * Writes a GTT entry mapping the page at the given offset from the beginning
688 * of the aperture to the given physical address.
691 agp_i810_write_gtt_entry(device_t dev
, int offset
, vm_offset_t physical
,
694 struct agp_i810_softc
*sc
= device_get_softc(dev
);
697 pte
= (u_int32_t
)physical
| 1;
698 if (sc
->chiptype
== CHIP_I965
|| sc
->chiptype
== CHIP_G33
) {
699 pte
|= (physical
& 0x0000000f00000000ull
) >> 28;
701 /* If we do actually have memory above 4GB on an older system,
702 * crash cleanly rather than scribble on system memory,
703 * so we know we need to fix it.
705 KASSERT((pte
& 0x0000000f00000000ull
) == 0,
706 (">4GB physical address in agp"));
709 switch (sc
->chiptype
) {
713 bus_write_4(sc
->sc_res
[0],
714 AGP_I810_GTT
+ (offset
>> AGP_PAGE_SHIFT
) * 4, pte
);
718 bus_write_4(sc
->sc_res
[1],
719 (offset
>> AGP_PAGE_SHIFT
) * 4, pte
);
722 bus_write_4(sc
->sc_res
[0],
723 (offset
>> AGP_PAGE_SHIFT
) * 4 + (512 * 1024), pte
);
729 agp_i810_bind_page(device_t dev
, int offset
, vm_offset_t physical
)
731 struct agp_i810_softc
*sc
= device_get_softc(dev
);
733 if (offset
< 0 || offset
>= (sc
->gatt
->ag_entries
<< AGP_PAGE_SHIFT
)) {
734 device_printf(dev
, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset
, AGP_PAGE_SHIFT
, sc
->gatt
->ag_entries
);
738 if ( sc
->chiptype
!= CHIP_I810
) {
739 if ( (offset
>> AGP_PAGE_SHIFT
) < sc
->stolen
) {
740 device_printf(dev
, "trying to bind into stolen memory");
745 agp_i810_write_gtt_entry(dev
, offset
, physical
, 1);
751 agp_i810_unbind_page(device_t dev
, int offset
)
753 struct agp_i810_softc
*sc
= device_get_softc(dev
);
755 if (offset
< 0 || offset
>= (sc
->gatt
->ag_entries
<< AGP_PAGE_SHIFT
))
758 if ( sc
->chiptype
!= CHIP_I810
) {
759 if ( (offset
>> AGP_PAGE_SHIFT
) < sc
->stolen
) {
760 device_printf(dev
, "trying to unbind from stolen memory");
765 agp_i810_write_gtt_entry(dev
, offset
, 0, 0);
771 * Writing via memory mapped registers already flushes all TLBs.
774 agp_i810_flush_tlb(device_t dev
)
779 agp_i810_enable(device_t dev
, u_int32_t mode
)
785 static struct agp_memory
*
786 agp_i810_alloc_memory(device_t dev
, int type
, vm_size_t size
)
788 struct agp_i810_softc
*sc
= device_get_softc(dev
);
789 struct agp_memory
*mem
;
791 if ((size
& (AGP_PAGE_SIZE
- 1)) != 0)
794 if (sc
->agp
.as_allocated
+ size
> sc
->agp
.as_maxmem
)
799 * Mapping local DRAM into GATT.
801 if ( sc
->chiptype
!= CHIP_I810
)
803 if (size
!= sc
->dcache_size
)
805 } else if (type
== 2) {
807 * Type 2 is the contiguous physical memory type, that hands
808 * back a physical address. This is used for cursors on i810.
809 * Hand back as many single pages with physical as the user
810 * wants, but only allow one larger allocation (ARGB cursor)
813 if (size
!= AGP_PAGE_SIZE
) {
814 if (sc
->argb_cursor
!= NULL
)
817 /* Allocate memory for ARGB cursor, if we can. */
818 sc
->argb_cursor
= contigmalloc(size
, M_AGP
,
819 0, 0, ~0, PAGE_SIZE
, 0);
820 if (sc
->argb_cursor
== NULL
)
825 mem
= kmalloc(sizeof *mem
, M_AGP
, M_INTWAIT
);
826 mem
->am_id
= sc
->agp
.as_nextid
++;
829 if (type
!= 1 && (type
!= 2 || size
== AGP_PAGE_SIZE
))
830 mem
->am_obj
= vm_object_allocate(OBJT_DEFAULT
,
831 atop(round_page(size
)));
836 if (size
== AGP_PAGE_SIZE
) {
838 * Allocate and wire down the page now so that we can
839 * get its physical address.
843 m
= vm_page_grab(mem
->am_obj
, 0,
844 VM_ALLOC_NORMAL
|VM_ALLOC_ZERO
|VM_ALLOC_RETRY
);
845 if ((m
->flags
& PG_ZERO
) == 0)
846 vm_page_zero_fill(m
);
848 mem
->am_physical
= VM_PAGE_TO_PHYS(m
);
851 /* Our allocation is already nicely wired down for us.
852 * Just grab the physical address.
854 mem
->am_physical
= vtophys(sc
->argb_cursor
);
857 mem
->am_physical
= 0;
861 mem
->am_is_bound
= 0;
862 TAILQ_INSERT_TAIL(&sc
->agp
.as_memory
, mem
, am_link
);
863 sc
->agp
.as_allocated
+= size
;
869 agp_i810_free_memory(device_t dev
, struct agp_memory
*mem
)
871 struct agp_i810_softc
*sc
= device_get_softc(dev
);
873 if (mem
->am_is_bound
)
876 if (mem
->am_type
== 2) {
877 if (mem
->am_size
== AGP_PAGE_SIZE
) {
879 * Unwire the page which we wired in alloc_memory.
881 vm_page_t m
= vm_page_lookup(mem
->am_obj
, 0);
882 vm_page_unwire(m
, 0);
884 contigfree(sc
->argb_cursor
, mem
->am_size
, M_AGP
);
885 sc
->argb_cursor
= NULL
;
889 sc
->agp
.as_allocated
-= mem
->am_size
;
890 TAILQ_REMOVE(&sc
->agp
.as_memory
, mem
, am_link
);
892 vm_object_deallocate(mem
->am_obj
);
898 agp_i810_bind_memory(device_t dev
, struct agp_memory
*mem
,
901 struct agp_i810_softc
*sc
= device_get_softc(dev
);
904 /* Do some sanity checks first. */
905 if (offset
< 0 || (offset
& (AGP_PAGE_SIZE
- 1)) != 0 ||
906 offset
+ mem
->am_size
> AGP_GET_APERTURE(dev
)) {
907 device_printf(dev
, "binding memory at bad offset %#x\n",
912 if (mem
->am_type
== 2 && mem
->am_size
!= AGP_PAGE_SIZE
) {
913 lockmgr(&sc
->agp
.as_lock
, LK_EXCLUSIVE
);
914 if (mem
->am_is_bound
) {
915 lockmgr(&sc
->agp
.as_lock
, LK_RELEASE
);
918 /* The memory's already wired down, just stick it in the GTT. */
919 for (i
= 0; i
< mem
->am_size
; i
+= AGP_PAGE_SIZE
) {
920 agp_i810_write_gtt_entry(dev
, offset
+ i
,
921 mem
->am_physical
+ i
, 1);
924 mem
->am_offset
= offset
;
925 mem
->am_is_bound
= 1;
926 lockmgr(&sc
->agp
.as_lock
, LK_RELEASE
);
930 if (mem
->am_type
!= 1)
931 return agp_generic_bind_memory(dev
, mem
, offset
);
933 if ( sc
->chiptype
!= CHIP_I810
)
936 for (i
= 0; i
< mem
->am_size
; i
+= AGP_PAGE_SIZE
) {
937 bus_write_4(sc
->sc_res
[0],
938 AGP_I810_GTT
+ (i
>> AGP_PAGE_SHIFT
) * 4, i
| 3);
945 agp_i810_unbind_memory(device_t dev
, struct agp_memory
*mem
)
947 struct agp_i810_softc
*sc
= device_get_softc(dev
);
950 if (mem
->am_type
== 2 && mem
->am_size
!= AGP_PAGE_SIZE
) {
951 lockmgr(&sc
->agp
.as_lock
, LK_EXCLUSIVE
);
952 if (!mem
->am_is_bound
) {
953 lockmgr(&sc
->agp
.as_lock
, LK_RELEASE
);
957 for (i
= 0; i
< mem
->am_size
; i
+= AGP_PAGE_SIZE
) {
958 agp_i810_write_gtt_entry(dev
, mem
->am_offset
+ i
,
962 mem
->am_is_bound
= 0;
963 lockmgr(&sc
->agp
.as_lock
, LK_RELEASE
);
967 if (mem
->am_type
!= 1)
968 return agp_generic_unbind_memory(dev
, mem
);
970 if ( sc
->chiptype
!= CHIP_I810
)
973 for (i
= 0; i
< mem
->am_size
; i
+= AGP_PAGE_SIZE
) {
974 bus_write_4(sc
->sc_res
[0],
975 AGP_I810_GTT
+ (i
>> AGP_PAGE_SHIFT
) * 4, 0);
981 static device_method_t agp_i810_methods
[] = {
982 /* Device interface */
983 DEVMETHOD(device_identify
, agp_i810_identify
),
984 DEVMETHOD(device_probe
, agp_i810_probe
),
985 DEVMETHOD(device_attach
, agp_i810_attach
),
986 DEVMETHOD(device_detach
, agp_i810_detach
),
989 DEVMETHOD(agp_get_aperture
, agp_generic_get_aperture
),
990 DEVMETHOD(agp_set_aperture
, agp_i810_set_aperture
),
991 DEVMETHOD(agp_bind_page
, agp_i810_bind_page
),
992 DEVMETHOD(agp_unbind_page
, agp_i810_unbind_page
),
993 DEVMETHOD(agp_flush_tlb
, agp_i810_flush_tlb
),
994 DEVMETHOD(agp_enable
, agp_i810_enable
),
995 DEVMETHOD(agp_alloc_memory
, agp_i810_alloc_memory
),
996 DEVMETHOD(agp_free_memory
, agp_i810_free_memory
),
997 DEVMETHOD(agp_bind_memory
, agp_i810_bind_memory
),
998 DEVMETHOD(agp_unbind_memory
, agp_i810_unbind_memory
),
1003 static driver_t agp_i810_driver
= {
1006 sizeof(struct agp_i810_softc
),
1009 static devclass_t agp_devclass
;
1011 DRIVER_MODULE(agp_i810
, pci
, agp_i810_driver
, agp_devclass
, 0, 0);
1012 MODULE_DEPEND(agp_i810
, agp
, 1, 1, 1);
1013 MODULE_DEPEND(agp_i810
, pci
, 1, 1, 1);