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netif - alc driver port - Initial work by Samuel J. Greear
[dragonfly.git] / sys / dev / netif / alc / if_alc.c
blob66a5a2e0af04408e84ce9d0a18fae60e663253e5
1 /*-
2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $
28 * $DragonFly$
29 */
30
31 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */
32
33 #include <sys/cdefs.h>
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/mbuf.h>
43 #include <sys/module.h>
44 #include <sys/spinlock.h>
45 #include <sys/rman.h>
46 #include <sys/queue.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
51
52 #include <net/bpf.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_llc.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/ifq_var.h>
61 #include <net/vlan/if_vlan_var.h>
62 #include <net/vlan/if_vlan_ether.h>
63
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68
69 #include <dev/netif/mii_layer/mii.h>
70 #include <dev/netif/mii_layer/miivar.h>
71
72 #include <bus/pci/pcireg.h>
73 #include <bus/pci/pcivar.h>
74
75 #include <machine/atomic.h>
76 /*
77 XXX
78 #include <machine/bus.h>
79 #include <machine/in_cksum.h>
80 */
81
82 #include "if_alcreg.h"
83 #include "if_alcvar.h"
84
85 /* "device miibus" required. See GENERIC if you get errors here. */
86 #include "miibus_if.h"
87 #undef ALC_USE_CUSTOM_CSUM
88
89 #ifdef ALC_USE_CUSTOM_CSUM
90 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
91 #else
92 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
93 #endif
94 #ifndef IFCAP_VLAN_HWTSO
95 #define IFCAP_VLAN_HWTSO 0
96 #endif
97
98 MODULE_DEPEND(alc, pci, 1, 1, 1);
99 MODULE_DEPEND(alc, ether, 1, 1, 1);
100 MODULE_DEPEND(alc, miibus, 1, 1, 1);
101
102 /* Tunables. */
103 static int msi_disable = 0;
104 static int msix_disable = 0;
105 TUNABLE_INT("hw.alc.msi_disable", &msi_disable);
106 TUNABLE_INT("hw.alc.msix_disable", &msix_disable);
107
108 /*
109 * Devices supported by this driver.
110 */
111 static struct alc_dev {
112 uint16_t alc_vendorid;
113 uint16_t alc_deviceid;
114 const char *alc_name;
115 } alc_devs[] = {
116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131,
117 "Atheros AR8131 PCIe Gigabit Ethernet" },
118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132,
119 "Atheros AR8132 PCIe Fast Ethernet" }
120 };
121
122 static void alc_aspm(struct alc_softc *);
123 static int alc_attach(device_t);
124 static int alc_check_boundary(struct alc_softc *);
125 static int alc_detach(device_t);
126 static void alc_disable_l0s_l1(struct alc_softc *);
127 static int alc_dma_alloc(struct alc_softc *);
128 static void alc_dma_free(struct alc_softc *);
129 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
130 static int alc_encap(struct alc_softc *, struct mbuf **);
131 #ifndef __NO_STRICT_ALIGNMENT
132 static struct mbuf *
133 alc_fixup_rx(struct ifnet *, struct mbuf *);
134 #endif
135 static void alc_get_macaddr(struct alc_softc *);
136 static void alc_init(void *);
137 static void alc_init_cmb(struct alc_softc *);
138 static void alc_init_locked(struct alc_softc *);
139 static void alc_init_rr_ring(struct alc_softc *);
140 static int alc_init_rx_ring(struct alc_softc *);
141 static void alc_init_smb(struct alc_softc *);
142 static void alc_init_tx_ring(struct alc_softc *);
143 static void alc_int_task(void *, int);
144 static void alc_intr(void *);
145 static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
146 static void alc_mac_config(struct alc_softc *);
147 static int alc_miibus_readreg(device_t, int, int);
148 static void alc_miibus_statchg(device_t);
149 static int alc_miibus_writereg(device_t, int, int, int);
150 static int alc_mediachange(struct ifnet *);
151 static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
152 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *);
153 static void alc_phy_down(struct alc_softc *);
154 static void alc_phy_reset(struct alc_softc *);
155 static int alc_probe(device_t);
156 static void alc_reset(struct alc_softc *);
157 static int alc_resume(device_t);
158 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
159 static int alc_rxintr(struct alc_softc *, int);
160 static void alc_rxfilter(struct alc_softc *);
161 static void alc_rxvlan(struct alc_softc *);
162 static void alc_setlinkspeed(struct alc_softc *);
163 #if 0
164 /* XXX: WOL */
165 static void alc_setwol(struct alc_softc *);
166 #endif
167 static int alc_shutdown(device_t);
168 static void alc_start(struct ifnet *);
169 static void alc_start_queue(struct alc_softc *);
170 static void alc_stats_clear(struct alc_softc *);
171 static void alc_stats_update(struct alc_softc *);
172 static void alc_stop(struct alc_softc *);
173 static void alc_stop_mac(struct alc_softc *);
174 static void alc_stop_queue(struct alc_softc *);
175 static int alc_suspend(device_t);
176 static void alc_sysctl_node(struct alc_softc *);
177 static void alc_tick(void *);
178 static void alc_tx_task(void *, int);
179 static void alc_txeof(struct alc_softc *);
180 static void alc_watchdog(struct alc_softc *);
181 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS);
182 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS);
183
184 static device_method_t alc_methods[] = {
185 /* Device interface. */
186 DEVMETHOD(device_probe, alc_probe),
187 DEVMETHOD(device_attach, alc_attach),
188 DEVMETHOD(device_detach, alc_detach),
189 DEVMETHOD(device_shutdown, alc_shutdown),
190 DEVMETHOD(device_suspend, alc_suspend),
191 DEVMETHOD(device_resume, alc_resume),
192
193 /* MII interface. */
194 DEVMETHOD(miibus_readreg, alc_miibus_readreg),
195 DEVMETHOD(miibus_writereg, alc_miibus_writereg),
196 DEVMETHOD(miibus_statchg, alc_miibus_statchg),
197
198 { NULL, NULL }
199 };
200
201 static driver_t alc_driver = {
202 "alc",
203 alc_methods,
204 sizeof(struct alc_softc)
205 };
206
207 static devclass_t alc_devclass;
208
209 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0);
210 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0);
211
212 static struct resource_spec alc_res_spec_mem[] = {
213 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
214 { -1, 0, 0 }
215 };
216
217 static struct resource_spec alc_irq_spec_legacy[] = {
218 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
219 { -1, 0, 0 }
220 };
221
222 static struct resource_spec alc_irq_spec_msi[] = {
223 { SYS_RES_IRQ, 1, RF_ACTIVE },
224 { -1, 0, 0 }
225 };
226
227 static struct resource_spec alc_irq_spec_msix[] = {
228 { SYS_RES_IRQ, 1, RF_ACTIVE },
229 { -1, 0, 0 }
230 };
231
232 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
233
234 static int
235 alc_miibus_readreg(device_t dev, int phy, int reg)
236 {
237 struct alc_softc *sc;
238 uint32_t v;
239 int i;
240
241 sc = device_get_softc(dev);
242
243 if (phy != sc->alc_phyaddr)
244 return (0);
245
246 /*
247 * For AR8132 fast ethernet controller, do not report 1000baseT
248 * capability to mii(4). Even though AR8132 uses the same
249 * model/revision number of F1 gigabit PHY, the PHY has no
250 * ability to establish 1000baseT link.
251 */
252 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
253 reg == MII_EXTSR)
254 return (0);
255
256 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
257 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
258 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
259 DELAY(5);
260 v = CSR_READ_4(sc, ALC_MDIO);
261 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
262 break;
263 }
264
265 if (i == 0) {
266 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
267 return (0);
268 }
269
270 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
271 }
272
273 static int
274 alc_miibus_writereg(device_t dev, int phy, int reg, int val)
275 {
276 struct alc_softc *sc;
277 uint32_t v;
278 int i;
279
280 sc = device_get_softc(dev);
281
282 if (phy != sc->alc_phyaddr)
283 return (0);
284
285 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
286 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
287 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
288 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
289 DELAY(5);
290 v = CSR_READ_4(sc, ALC_MDIO);
291 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
292 break;
293 }
294
295 if (i == 0)
296 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
297
298 return (0);
299 }
300
301 static void
302 alc_miibus_statchg(device_t dev)
303 {
304 struct alc_softc *sc;
305 struct mii_data *mii;
306 struct ifnet *ifp;
307 uint32_t reg;
308
309 sc = device_get_softc(dev);
310
311 mii = device_get_softc(sc->alc_miibus);
312 ifp = sc->alc_ifp;
313 if (mii == NULL || ifp == NULL ||
314 (ifp->if_flags & IFF_RUNNING) == 0)
315 return;
316
317 sc->alc_flags &= ~ALC_FLAG_LINK;
318 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
319 (IFM_ACTIVE | IFM_AVALID)) {
320 switch (IFM_SUBTYPE(mii->mii_media_active)) {
321 case IFM_10_T:
322 case IFM_100_TX:
323 sc->alc_flags |= ALC_FLAG_LINK;
324 break;
325 case IFM_1000_T:
326 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
327 sc->alc_flags |= ALC_FLAG_LINK;
328 break;
329 default:
330 break;
331 }
332 }
333 alc_stop_queue(sc);
334 /* Stop Rx/Tx MACs. */
335 alc_stop_mac(sc);
336
337 /* Program MACs with resolved speed/duplex/flow-control. */
338 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
339 alc_start_queue(sc);
340 alc_mac_config(sc);
341 /* Re-enable Tx/Rx MACs. */
342 reg = CSR_READ_4(sc, ALC_MAC_CFG);
343 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
344 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
345 }
346 alc_aspm(sc);
347 }
348
349 static void
350 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
351 {
352 struct alc_softc *sc;
353 struct mii_data *mii;
354
355 sc = ifp->if_softc;
356 ALC_LOCK(sc);
357 if ((ifp->if_flags & IFF_UP) == 0) {
358 ALC_UNLOCK(sc);
359 return;
360 }
361 mii = device_get_softc(sc->alc_miibus);
362
363 mii_pollstat(mii);
364 ALC_UNLOCK(sc);
365 ifmr->ifm_status = mii->mii_media_status;
366 ifmr->ifm_active = mii->mii_media_active;
367 }
368
369 static int
370 alc_mediachange(struct ifnet *ifp)
371 {
372 struct alc_softc *sc;
373 struct mii_data *mii;
374 struct mii_softc *miisc;
375 int error;
376
377 sc = ifp->if_softc;
378 ALC_LOCK(sc);
379 mii = device_get_softc(sc->alc_miibus);
380 if (mii->mii_instance != 0) {
381 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
382 mii_phy_reset(miisc);
383 }
384 error = mii_mediachg(mii);
385 ALC_UNLOCK(sc);
386
387 return (error);
388 }
389
390 static int
391 alc_probe(device_t dev)
392 {
393 struct alc_dev *sp;
394 int i;
395 uint16_t vendor, devid;
396
397 vendor = pci_get_vendor(dev);
398 devid = pci_get_device(dev);
399 sp = alc_devs;
400 for (i = 0; i < sizeof(alc_devs) / sizeof(alc_devs[0]); i++) {
401 if (vendor == sp->alc_vendorid &&
402 devid == sp->alc_deviceid) {
403 device_set_desc(dev, sp->alc_name);
404 return (BUS_PROBE_DEFAULT);
405 }
406 sp++;
407 }
408
409 return (ENXIO);
410 }
411
412 static void
413 alc_get_macaddr(struct alc_softc *sc)
414 {
415 uint32_t ea[2], opt;
416 int i;
417
418 opt = CSR_READ_4(sc, ALC_OPT_CFG);
419 if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
420 /*
421 * EEPROM found, let TWSI reload EEPROM configuration.
422 * This will set ethernet address of controller.
423 */
424 if ((opt & OPT_CFG_CLK_ENB) == 0) {
425 opt |= OPT_CFG_CLK_ENB;
426 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
427 CSR_READ_4(sc, ALC_OPT_CFG);
428 DELAY(1000);
429 }
430 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
431 TWSI_CFG_SW_LD_START);
432 for (i = 100; i > 0; i--) {
433 DELAY(1000);
434 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
435 TWSI_CFG_SW_LD_START) == 0)
436 break;
437 }
438 if (i == 0)
439 device_printf(sc->alc_dev,
440 "reloading EEPROM timeout!\n");
441 } else {
442 if (bootverbose)
443 device_printf(sc->alc_dev, "EEPROM not found!\n");
444 }
445 if ((opt & OPT_CFG_CLK_ENB) != 0) {
446 opt &= ~OPT_CFG_CLK_ENB;
447 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
448 CSR_READ_4(sc, ALC_OPT_CFG);
449 DELAY(1000);
450 }
451
452 ea[0] = CSR_READ_4(sc, ALC_PAR0);
453 ea[1] = CSR_READ_4(sc, ALC_PAR1);
454 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
455 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
456 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
457 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
458 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
459 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
460 }
461
462 static void
463 alc_disable_l0s_l1(struct alc_softc *sc)
464 {
465 uint32_t pmcfg;
466
467 /* Another magic from vendor. */
468 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
469 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
470 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK |
471 PM_CFG_SERDES_PD_EX_L1);
472 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
473 PM_CFG_SERDES_L1_ENB;
474 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
475 }
476
477 static void
478 alc_phy_reset(struct alc_softc *sc)
479 {
480 uint16_t data;
481
482 /* Reset magic from Linux. */
483 CSR_WRITE_2(sc, ALC_GPHY_CFG,
484 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET);
485 CSR_READ_2(sc, ALC_GPHY_CFG);
486 DELAY(10 * 1000);
487
488 CSR_WRITE_2(sc, ALC_GPHY_CFG,
489 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
490 GPHY_CFG_SEL_ANA_RESET);
491 CSR_READ_2(sc, ALC_GPHY_CFG);
492 DELAY(10 * 1000);
493
494 /* Load DSP codes, vendor magic. */
495 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
496 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
497 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
498 ALC_MII_DBG_ADDR, MII_ANA_CFG18);
499 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
500 ALC_MII_DBG_DATA, data);
501
502 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
503 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
504 ANA_SERDES_EN_LCKDT;
505 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
506 ALC_MII_DBG_ADDR, MII_ANA_CFG5);
507 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
508 ALC_MII_DBG_DATA, data);
509
510 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
511 ANA_LONG_CABLE_TH_100_MASK) |
512 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
513 ANA_SHORT_CABLE_TH_100_SHIFT) |
514 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
515 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
516 ALC_MII_DBG_ADDR, MII_ANA_CFG54);
517 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
518 ALC_MII_DBG_DATA, data);
519
520 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
521 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
522 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
523 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
524 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
525 ALC_MII_DBG_ADDR, MII_ANA_CFG4);
526 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
527 ALC_MII_DBG_DATA, data);
528
529 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
530 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
531 ANA_OEN_125M;
532 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
533 ALC_MII_DBG_ADDR, MII_ANA_CFG0);
534 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
535 ALC_MII_DBG_DATA, data);
536 DELAY(1000);
537 }
538
539 static void
540 alc_phy_down(struct alc_softc *sc)
541 {
542
543 /* Force PHY down. */
544 CSR_WRITE_2(sc, ALC_GPHY_CFG,
545 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
546 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW);
547 DELAY(1000);
548 }
549
550 static void
551 alc_aspm(struct alc_softc *sc)
552 {
553 uint32_t pmcfg;
554
555 ALC_LOCK_ASSERT(sc);
556
557 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
558 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
559 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
560 pmcfg |= PM_CFG_SERDES_L1_ENB;
561 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
562 pmcfg |= PM_CFG_MAC_ASPM_CHK;
563 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
564 pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
565 pmcfg &= ~PM_CFG_CLK_SWH_L1;
566 pmcfg &= ~PM_CFG_ASPM_L1_ENB;
567 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
568 } else {
569 pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
570 pmcfg |= PM_CFG_CLK_SWH_L1;
571 pmcfg &= ~PM_CFG_ASPM_L1_ENB;
572 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
573 }
574 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
575 }
576
577 static int
578 alc_attach(device_t dev)
579 {
580 struct alc_softc *sc;
581 struct ifnet *ifp;
582 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
583 uint16_t burst;
584 int base, error, i, msic, msixc, pmc, state;
585 uint32_t cap, ctl, val;
586
587 error = 0;
588 sc = device_get_softc(dev);
589 sc->alc_dev = dev;
590
591 lockinit(&sc->alc_lock, "alc_lock", 0, LK_CANRECURSE);
592 // XXX callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
593 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
594
595 /* Map the device. */
596 pci_enable_busmaster(dev);
597 sc->alc_res_spec = alc_res_spec_mem;
598 sc->alc_irq_spec = alc_irq_spec_legacy;
599 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
600 if (error != 0) {
601 device_printf(dev, "cannot allocate memory resources.\n");
602 goto fail;
603 }
604
605 /* Set PHY address. */
606 sc->alc_phyaddr = ALC_PHY_ADDR;
607
608 /* Initialize DMA parameters. */
609 sc->alc_dma_rd_burst = 0;
610 sc->alc_dma_wr_burst = 0;
611 sc->alc_rcb = DMA_CFG_RCB_64;
612 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) {
613 sc->alc_flags |= ALC_FLAG_PCIE;
614 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL);
615 sc->alc_dma_rd_burst =
616 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12;
617 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5;
618 if (bootverbose) {
619 device_printf(dev, "Read request size : %u bytes.\n",
620 alc_dma_burst[sc->alc_dma_rd_burst]);
621 device_printf(dev, "TLP payload size : %u bytes.\n",
622 alc_dma_burst[sc->alc_dma_wr_burst]);
623 }
624 /* Clear data link and flow-control protocol error. */
625 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
626 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
627 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
628 /* Disable ASPM L0S and L1. */
629 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP);
630 if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
631 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL);
632 if ((ctl & 0x08) != 0)
633 sc->alc_rcb = DMA_CFG_RCB_128;
634 if (bootverbose)
635 device_printf(dev, "RCB %u bytes\n",
636 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
637 state = ctl & 0x03;
638 if (bootverbose)
639 device_printf(sc->alc_dev, "ASPM %s %s\n",
640 aspm_state[state],
641 state == 0 ? "disabled" : "enabled");
642 if (state != 0)
643 alc_disable_l0s_l1(sc);
644 }
645 }
646
647 /* Reset PHY. */
648 alc_phy_reset(sc);
649
650 /* Reset the ethernet controller. */
651 alc_reset(sc);
652
653 /*
654 * One odd thing is AR8132 uses the same PHY hardware(F1
655 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
656 * the PHY supports 1000Mbps but that's not true. The PHY
657 * used in AR8132 can't establish gigabit link even if it
658 * shows the same PHY model/revision number of AR8131.
659 */
660 if (pci_get_device(dev) == DEVICEID_ATHEROS_AR8132)
661 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
662 else
663 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
664 /*
665 * It seems that AR8131/AR8132 has silicon bug for SMB. In
666 * addition, Atheros said that enabling SMB wouldn't improve
667 * performance. However I think it's bad to access lots of
668 * registers to extract MAC statistics.
669 */
670 sc->alc_flags |= ALC_FLAG_SMB_BUG;
671 /*
672 * Don't use Tx CMB. It is known to have silicon bug.
673 */
674 sc->alc_flags |= ALC_FLAG_CMB_BUG;
675 sc->alc_rev = pci_get_revid(dev);
676 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
677 MASTER_CHIP_REV_SHIFT;
678 if (bootverbose) {
679 device_printf(dev, "PCI device revision : 0x%04x\n",
680 sc->alc_rev);
681 device_printf(dev, "Chip id/revision : 0x%04x\n",
682 sc->alc_chip_rev);
683 }
684 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
685 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
686 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
687
688 /* Allocate IRQ resources. */
689 msixc = pci_msix_count(dev);
690 msic = pci_msi_count(dev);
691 if (bootverbose) {
692 device_printf(dev, "MSIX count : %d\n", msixc);
693 device_printf(dev, "MSI count : %d\n", msic);
694 }
695 /* Prefer MSIX over MSI. */
696 if (msix_disable == 0 || msi_disable == 0) {
697 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES &&
698 pci_alloc_msix(dev, &msixc) == 0) {
699 if (msic == ALC_MSIX_MESSAGES) {
700 device_printf(dev,
701 "Using %d MSIX message(s).\n", msixc);
702 sc->alc_flags |= ALC_FLAG_MSIX;
703 sc->alc_irq_spec = alc_irq_spec_msix;
704 } else
705 pci_release_msi(dev);
706 }
707 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
708 msic == ALC_MSI_MESSAGES &&
709 pci_alloc_msi(dev, &msic) == 0) {
710 if (msic == ALC_MSI_MESSAGES) {
711 device_printf(dev,
712 "Using %d MSI message(s).\n", msic);
713 sc->alc_flags |= ALC_FLAG_MSI;
714 sc->alc_irq_spec = alc_irq_spec_msi;
715 } else
716 pci_release_msi(dev);
717 }
718 }
719
720 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq);
721 if (error != 0) {
722 device_printf(dev, "cannot allocate IRQ resources.\n");
723 goto fail;
724 }
725
726 /* Create device sysctl node. */
727 alc_sysctl_node(sc);
728
729 if ((error = alc_dma_alloc(sc) != 0))
730 goto fail;
731
732 /* Load station address. */
733 alc_get_macaddr(sc);
734
735 ifp = sc->alc_ifp = &sc->arpcom.ac_if;
736 ifp->if_softc = sc;
737 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
738 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
739 ifp->if_ioctl = alc_ioctl;
740 ifp->if_start = alc_start;
741 ifp->if_init = alc_init;
742 ifp->if_snd.ifq_maxlen = ALC_TX_RING_CNT - 1;
743 ifq_set_maxlen(&ifp->if_snd, ifp->if_snd.ifq_maxlen);
744 ifq_set_ready(&ifp->if_snd);
745 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
746 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
747 #if 0
748 /* XXX: WOL */
749 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
750 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
751 #endif
752 ifp->if_capenable = ifp->if_capabilities;
753
754 /* Set up MII bus. */
755 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange,
756 alc_mediastatus)) != 0) {
757 device_printf(dev, "no PHY found!\n");
758 goto fail;
759 }
760
761 ether_ifattach(ifp, sc->alc_eaddr, NULL);
762
763 /* VLAN capability setup. */
764 ifp->if_capabilities |= IFCAP_VLAN_MTU;
765 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
766 ifp->if_capenable = ifp->if_capabilities;
767 /*
768 * XXX
769 * It seems enabling Tx checksum offloading makes more trouble.
770 * Sometimes the controller does not receive any frames when
771 * Tx checksum offloading is enabled. I'm not sure whether this
772 * is a bug in Tx checksum offloading logic or I got broken
773 * sample boards. To safety, don't enable Tx checksum offloading
774 * by default but give chance to users to toggle it if they know
775 * their controllers work without problems.
776 */
777 ifp->if_capenable &= ~IFCAP_TXCSUM;
778 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
779
780 /* Tell the upper layer(s) we support long frames. */
781 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
782
783 /* Create local taskq. */
784 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp);
785 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK,
786 taskqueue_thread_enqueue, &sc->alc_tq);
787 if (sc->alc_tq == NULL) {
788 device_printf(dev, "could not create taskqueue.\n");
789 ether_ifdetach(ifp);
790 error = ENXIO;
791 goto fail;
792 }
793 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq",
794 device_get_nameunit(sc->alc_dev));
795
796 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
797 msic = ALC_MSIX_MESSAGES;
798 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
799 msic = ALC_MSI_MESSAGES;
800 else
801 msic = 1;
802 for (i = 0; i < msic; i++) {
803 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE,
804 alc_intr, NULL, sc, &sc->alc_intrhand[i]);
805 if (error != 0)
806 break;
807 }
808 if (error != 0) {
809 device_printf(dev, "could not set up interrupt handler.\n");
810 taskqueue_free(sc->alc_tq);
811 sc->alc_tq = NULL;
812 ether_ifdetach(ifp);
813 goto fail;
814 }
815
816 fail:
817 if (error != 0)
818 alc_detach(dev);
819
820 return (error);
821 }
822
823 static int
824 alc_detach(device_t dev)
825 {
826 struct alc_softc *sc;
827 struct ifnet *ifp;
828 int i, msic;
829
830 sc = device_get_softc(dev);
831
832 ifp = sc->alc_ifp;
833 if (device_is_attached(dev)) {
834 ALC_LOCK(sc);
835 sc->alc_flags |= ALC_FLAG_DETACH;
836 alc_stop(sc);
837 ALC_UNLOCK(sc);
838 #if 0
839 /* XXX */
840 callout_drain(&sc->alc_tick_ch);
841 #endif
842 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
843 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task);
844 ether_ifdetach(ifp);
845 }
846
847 if (sc->alc_tq != NULL) {
848 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
849 taskqueue_free(sc->alc_tq);
850 sc->alc_tq = NULL;
851 }
852
853 if (sc->alc_miibus != NULL) {
854 device_delete_child(dev, sc->alc_miibus);
855 sc->alc_miibus = NULL;
856 }
857 bus_generic_detach(dev);
858 alc_dma_free(sc);
859
860 if (ifp != NULL) {
861 // XXX? if_free(ifp);
862 sc->alc_ifp = NULL;
863 }
864
865 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
866 msic = ALC_MSIX_MESSAGES;
867 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
868 msic = ALC_MSI_MESSAGES;
869 else
870 msic = 1;
871 for (i = 0; i < msic; i++) {
872 if (sc->alc_intrhand[i] != NULL) {
873 bus_teardown_intr(dev, sc->alc_irq[i],
874 sc->alc_intrhand[i]);
875 sc->alc_intrhand[i] = NULL;
876 }
877 }
878 if (sc->alc_res[0] != NULL)
879 alc_phy_down(sc);
880 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq);
881 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0)
882 pci_release_msi(dev);
883 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res);
884 lockuninit(&sc->alc_lock);
885
886 return (0);
887 }
888
889 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \
890 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
891 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \
892 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
893
894 static void
895 alc_sysctl_node(struct alc_softc *sc)
896 {
897 struct sysctl_ctx_list *ctx;
898 struct sysctl_oid *tree;
899 struct sysctl_oid_list *child, *parent;
900 struct alc_hw_stats *stats;
901 int error;
902
903 stats = &sc->alc_stats;
904 ctx = &sc->alc_sysctl_ctx;
905 sysctl_ctx_init(ctx);
906
907 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw),
908 OID_AUTO,
909 device_get_nameunit(sc->alc_dev),
910 CTLFLAG_RD, 0, "");
911 if (tree == NULL) {
912 device_printf(sc->alc_dev, "can't add sysctl node\n");
913 return;
914 }
915 child = SYSCTL_CHILDREN(tree);
916
917 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
918 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0,
919 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
920 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
921 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0,
922 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
923 /* Pull in device tunables. */
924 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
925 error = resource_int_value(device_get_name(sc->alc_dev),
926 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod);
927 if (error == 0) {
928 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN ||
929 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) {
930 device_printf(sc->alc_dev, "int_rx_mod value out of "
931 "range; using default: %d\n",
932 ALC_IM_RX_TIMER_DEFAULT);
933 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
934 }
935 }
936 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
937 error = resource_int_value(device_get_name(sc->alc_dev),
938 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod);
939 if (error == 0) {
940 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN ||
941 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) {
942 device_printf(sc->alc_dev, "int_tx_mod value out of "
943 "range; using default: %d\n",
944 ALC_IM_TX_TIMER_DEFAULT);
945 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
946 }
947 }
948 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
949 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0,
950 sysctl_hw_alc_proc_limit, "I",
951 "max number of Rx events to process");
952 /* Pull in device tunables. */
953 sc->alc_process_limit = ALC_PROC_DEFAULT;
954 error = resource_int_value(device_get_name(sc->alc_dev),
955 device_get_unit(sc->alc_dev), "process_limit",
956 &sc->alc_process_limit);
957 if (error == 0) {
958 if (sc->alc_process_limit < ALC_PROC_MIN ||
959 sc->alc_process_limit > ALC_PROC_MAX) {
960 device_printf(sc->alc_dev,
961 "process_limit value out of range; "
962 "using default: %d\n", ALC_PROC_DEFAULT);
963 sc->alc_process_limit = ALC_PROC_DEFAULT;
964 }
965 }
966
967 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
968 NULL, "ALC statistics");
969 parent = SYSCTL_CHILDREN(tree);
970
971 /* Rx statistics. */
972 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
973 NULL, "Rx MAC statistics");
974 child = SYSCTL_CHILDREN(tree);
975 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
976 &stats->rx_frames, "Good frames");
977 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
978 &stats->rx_bcast_frames, "Good broadcast frames");
979 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
980 &stats->rx_mcast_frames, "Good multicast frames");
981 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
982 &stats->rx_pause_frames, "Pause control frames");
983 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
984 &stats->rx_control_frames, "Control frames");
985 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
986 &stats->rx_crcerrs, "CRC errors");
987 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
988 &stats->rx_lenerrs, "Frames with length mismatched");
989 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
990 &stats->rx_bytes, "Good octets");
991 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
992 &stats->rx_bcast_bytes, "Good broadcast octets");
993 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
994 &stats->rx_mcast_bytes, "Good multicast octets");
995 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts",
996 &stats->rx_runts, "Too short frames");
997 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments",
998 &stats->rx_fragments, "Fragmented frames");
999 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1000 &stats->rx_pkts_64, "64 bytes frames");
1001 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1002 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
1003 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1004 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
1005 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1006 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
1007 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1008 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
1009 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1010 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
1011 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1012 &stats->rx_pkts_1519_max, "1519 to max frames");
1013 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1014 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
1015 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1016 &stats->rx_fifo_oflows, "FIFO overflows");
1017 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
1018 &stats->rx_rrs_errs, "Return status write-back errors");
1019 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
1020 &stats->rx_alignerrs, "Alignment errors");
1021 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered",
1022 &stats->rx_pkts_filtered,
1023 "Frames dropped due to address filtering");
1024
1025 /* Tx statistics. */
1026 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1027 NULL, "Tx MAC statistics");
1028 child = SYSCTL_CHILDREN(tree);
1029 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1030 &stats->tx_frames, "Good frames");
1031 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1032 &stats->tx_bcast_frames, "Good broadcast frames");
1033 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1034 &stats->tx_mcast_frames, "Good multicast frames");
1035 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1036 &stats->tx_pause_frames, "Pause control frames");
1037 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1038 &stats->tx_control_frames, "Control frames");
1039 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
1040 &stats->tx_excess_defer, "Frames with excessive derferrals");
1041 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers",
1042 &stats->tx_excess_defer, "Frames with derferrals");
1043 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1044 &stats->tx_bytes, "Good octets");
1045 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1046 &stats->tx_bcast_bytes, "Good broadcast octets");
1047 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1048 &stats->tx_mcast_bytes, "Good multicast octets");
1049 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1050 &stats->tx_pkts_64, "64 bytes frames");
1051 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1052 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
1053 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1054 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
1055 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1056 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
1057 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1058 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
1059 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1060 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
1061 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1062 &stats->tx_pkts_1519_max, "1519 to max frames");
1063 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
1064 &stats->tx_single_colls, "Single collisions");
1065 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
1066 &stats->tx_multi_colls, "Multiple collisions");
1067 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
1068 &stats->tx_late_colls, "Late collisions");
1069 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
1070 &stats->tx_excess_colls, "Excessive collisions");
1071 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort",
1072 &stats->tx_abort, "Aborted frames due to Excessive collisions");
1073 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
1074 &stats->tx_underrun, "FIFO underruns");
1075 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
1076 &stats->tx_desc_underrun, "Descriptor write-back errors");
1077 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1078 &stats->tx_lenerrs, "Frames with length mismatched");
1079 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1080 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
1081 }
1082
1083 #undef ALC_SYSCTL_STAT_ADD32
1084 #undef ALC_SYSCTL_STAT_ADD64
1085
1086 struct alc_dmamap_arg {
1087 bus_addr_t alc_busaddr;
1088 };
1089
1090 static void
1091 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1092 {
1093 struct alc_dmamap_arg *ctx;
1094
1095 if (error != 0)
1096 return;
1097
1098 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1099
1100 ctx = (struct alc_dmamap_arg *)arg;
1101 ctx->alc_busaddr = segs[0].ds_addr;
1102 }
1103
1104 /*
1105 * Normal and high Tx descriptors shares single Tx high address.
1106 * Four Rx descriptor/return rings and CMB shares the same Rx
1107 * high address.
1108 */
1109 static int
1110 alc_check_boundary(struct alc_softc *sc)
1111 {
1112 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end;
1113
1114 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ;
1115 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ;
1116 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ;
1117 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ;
1118
1119 /* 4GB boundary crossing is not allowed. */
1120 if ((ALC_ADDR_HI(rx_ring_end) !=
1121 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) ||
1122 (ALC_ADDR_HI(rr_ring_end) !=
1123 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) ||
1124 (ALC_ADDR_HI(cmb_end) !=
1125 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) ||
1126 (ALC_ADDR_HI(tx_ring_end) !=
1127 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr)))
1128 return (EFBIG);
1129 /*
1130 * Make sure Rx return descriptor/Rx descriptor/CMB use
1131 * the same high address.
1132 */
1133 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) ||
1134 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end)))
1135 return (EFBIG);
1136
1137 return (0);
1138 }
1139
1140 static int
1141 alc_dma_alloc(struct alc_softc *sc)
1142 {
1143 struct alc_txdesc *txd;
1144 struct alc_rxdesc *rxd;
1145 bus_addr_t lowaddr;
1146 struct alc_dmamap_arg ctx;
1147 int error, i;
1148
1149 lowaddr = BUS_SPACE_MAXADDR;
1150 again:
1151 /* Create parent DMA tag. */
1152 error = bus_dma_tag_create(
1153 sc->alc_cdata.alc_parent_tag, /* parent */
1154 1, 0, /* alignment, boundary */
1155 lowaddr, /* lowaddr */
1156 BUS_SPACE_MAXADDR, /* highaddr */
1157 NULL, NULL, /* filter, filterarg */
1158 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1159 0, /* nsegments */
1160 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1161 0, /* flags */
1162 &sc->alc_cdata.alc_parent_tag);
1163 if (error != 0) {
1164 device_printf(sc->alc_dev,
1165 "could not create parent DMA tag.\n");
1166 goto fail;
1167 }
1168
1169 /* Create DMA tag for Tx descriptor ring. */
1170 error = bus_dma_tag_create(
1171 sc->alc_cdata.alc_parent_tag, /* parent */
1172 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */
1173 BUS_SPACE_MAXADDR, /* lowaddr */
1174 BUS_SPACE_MAXADDR, /* highaddr */
1175 NULL, NULL, /* filter, filterarg */
1176 ALC_TX_RING_SZ, /* maxsize */
1177 1, /* nsegments */
1178 ALC_TX_RING_SZ, /* maxsegsize */
1179 0, /* flags */
1180 &sc->alc_cdata.alc_tx_ring_tag);
1181 if (error != 0) {
1182 device_printf(sc->alc_dev,
1183 "could not create Tx ring DMA tag.\n");
1184 goto fail;
1185 }
1186
1187 /* Create DMA tag for Rx free descriptor ring. */
1188 error = bus_dma_tag_create(
1189 sc->alc_cdata.alc_parent_tag, /* parent */
1190 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */
1191 BUS_SPACE_MAXADDR, /* lowaddr */
1192 BUS_SPACE_MAXADDR, /* highaddr */
1193 NULL, NULL, /* filter, filterarg */
1194 ALC_RX_RING_SZ, /* maxsize */
1195 1, /* nsegments */
1196 ALC_RX_RING_SZ, /* maxsegsize */
1197 0, /* flags */
1198 &sc->alc_cdata.alc_rx_ring_tag);
1199 if (error != 0) {
1200 device_printf(sc->alc_dev,
1201 "could not create Rx ring DMA tag.\n");
1202 goto fail;
1203 }
1204 /* Create DMA tag for Rx return descriptor ring. */
1205 error = bus_dma_tag_create(
1206 sc->alc_cdata.alc_parent_tag, /* parent */
1207 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */
1208 BUS_SPACE_MAXADDR, /* lowaddr */
1209 BUS_SPACE_MAXADDR, /* highaddr */
1210 NULL, NULL, /* filter, filterarg */
1211 ALC_RR_RING_SZ, /* maxsize */
1212 1, /* nsegments */
1213 ALC_RR_RING_SZ, /* maxsegsize */
1214 0, /* flags */
1215 &sc->alc_cdata.alc_rr_ring_tag);
1216 if (error != 0) {
1217 device_printf(sc->alc_dev,
1218 "could not create Rx return ring DMA tag.\n");
1219 goto fail;
1220 }
1221
1222 /* Create DMA tag for coalescing message block. */
1223 error = bus_dma_tag_create(
1224 sc->alc_cdata.alc_parent_tag, /* parent */
1225 ALC_CMB_ALIGN, 0, /* alignment, boundary */
1226 BUS_SPACE_MAXADDR, /* lowaddr */
1227 BUS_SPACE_MAXADDR, /* highaddr */
1228 NULL, NULL, /* filter, filterarg */
1229 ALC_CMB_SZ, /* maxsize */
1230 1, /* nsegments */
1231 ALC_CMB_SZ, /* maxsegsize */
1232 0, /* flags */
1233 &sc->alc_cdata.alc_cmb_tag);
1234 if (error != 0) {
1235 device_printf(sc->alc_dev,
1236 "could not create CMB DMA tag.\n");
1237 goto fail;
1238 }
1239 /* Create DMA tag for status message block. */
1240 error = bus_dma_tag_create(
1241 sc->alc_cdata.alc_parent_tag, /* parent */
1242 ALC_SMB_ALIGN, 0, /* alignment, boundary */
1243 BUS_SPACE_MAXADDR, /* lowaddr */
1244 BUS_SPACE_MAXADDR, /* highaddr */
1245 NULL, NULL, /* filter, filterarg */
1246 ALC_SMB_SZ, /* maxsize */
1247 1, /* nsegments */
1248 ALC_SMB_SZ, /* maxsegsize */
1249 0, /* flags */
1250 &sc->alc_cdata.alc_smb_tag);
1251 if (error != 0) {
1252 device_printf(sc->alc_dev,
1253 "could not create SMB DMA tag.\n");
1254 goto fail;
1255 }
1256
1257 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1258 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag,
1259 (void **)&sc->alc_rdata.alc_tx_ring,
1260 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1261 &sc->alc_cdata.alc_tx_ring_map);
1262 if (error != 0) {
1263 device_printf(sc->alc_dev,
1264 "could not allocate DMA'able memory for Tx ring.\n");
1265 goto fail;
1266 }
1267 ctx.alc_busaddr = 0;
1268 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag,
1269 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring,
1270 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1271 if (error != 0 || ctx.alc_busaddr == 0) {
1272 device_printf(sc->alc_dev,
1273 "could not load DMA'able memory for Tx ring.\n");
1274 goto fail;
1275 }
1276 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr;
1277
1278 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1279 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag,
1280 (void **)&sc->alc_rdata.alc_rx_ring,
1281 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1282 &sc->alc_cdata.alc_rx_ring_map);
1283 if (error != 0) {
1284 device_printf(sc->alc_dev,
1285 "could not allocate DMA'able memory for Rx ring.\n");
1286 goto fail;
1287 }
1288 ctx.alc_busaddr = 0;
1289 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag,
1290 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring,
1291 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1292 if (error != 0 || ctx.alc_busaddr == 0) {
1293 device_printf(sc->alc_dev,
1294 "could not load DMA'able memory for Rx ring.\n");
1295 goto fail;
1296 }
1297 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr;
1298
1299 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */
1300 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag,
1301 (void **)&sc->alc_rdata.alc_rr_ring,
1302 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1303 &sc->alc_cdata.alc_rr_ring_map);
1304 if (error != 0) {
1305 device_printf(sc->alc_dev,
1306 "could not allocate DMA'able memory for Rx return ring.\n");
1307 goto fail;
1308 }
1309 ctx.alc_busaddr = 0;
1310 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag,
1311 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring,
1312 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
1313 if (error != 0 || ctx.alc_busaddr == 0) {
1314 device_printf(sc->alc_dev,
1315 "could not load DMA'able memory for Tx ring.\n");
1316 goto fail;
1317 }
1318 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr;
1319
1320 /* Allocate DMA'able memory and load the DMA map for CMB. */
1321 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag,
1322 (void **)&sc->alc_rdata.alc_cmb,
1323 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1324 &sc->alc_cdata.alc_cmb_map);
1325 if (error != 0) {
1326 device_printf(sc->alc_dev,
1327 "could not allocate DMA'able memory for CMB.\n");
1328 goto fail;
1329 }
1330 ctx.alc_busaddr = 0;
1331 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag,
1332 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb,
1333 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
1334 if (error != 0 || ctx.alc_busaddr == 0) {
1335 device_printf(sc->alc_dev,
1336 "could not load DMA'able memory for CMB.\n");
1337 goto fail;
1338 }
1339 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr;
1340
1341 /* Allocate DMA'able memory and load the DMA map for SMB. */
1342 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag,
1343 (void **)&sc->alc_rdata.alc_smb,
1344 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1345 &sc->alc_cdata.alc_smb_map);
1346 if (error != 0) {
1347 device_printf(sc->alc_dev,
1348 "could not allocate DMA'able memory for SMB.\n");
1349 goto fail;
1350 }
1351 ctx.alc_busaddr = 0;
1352 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag,
1353 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb,
1354 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
1355 if (error != 0 || ctx.alc_busaddr == 0) {
1356 device_printf(sc->alc_dev,
1357 "could not load DMA'able memory for CMB.\n");
1358 goto fail;
1359 }
1360 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr;
1361
1362 /* Make sure we've not crossed 4GB boundary. */
1363 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1364 (error = alc_check_boundary(sc)) != 0) {
1365 device_printf(sc->alc_dev, "4GB boundary crossed, "
1366 "switching to 32bit DMA addressing mode.\n");
1367 alc_dma_free(sc);
1368 /*
1369 * Limit max allowable DMA address space to 32bit
1370 * and try again.
1371 */
1372 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1373 goto again;
1374 }
1375
1376 /*
1377 * Create Tx buffer parent tag.
1378 * AR8131/AR8132 allows 64bit DMA addressing of Tx/Rx buffers
1379 * so it needs separate parent DMA tag as parent DMA address
1380 * space could be restricted to be within 32bit address space
1381 * by 4GB boundary crossing.
1382 */
1383 error = bus_dma_tag_create(
1384 sc->alc_cdata.alc_parent_tag, /* parent */
1385 1, 0, /* alignment, boundary */
1386 BUS_SPACE_MAXADDR, /* lowaddr */
1387 BUS_SPACE_MAXADDR, /* highaddr */
1388 NULL, NULL, /* filter, filterarg */
1389 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1390 0, /* nsegments */
1391 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1392 0, /* flags */
1393 &sc->alc_cdata.alc_buffer_tag);
1394 if (error != 0) {
1395 device_printf(sc->alc_dev,
1396 "could not create parent buffer DMA tag.\n");
1397 goto fail;
1398 }
1399
1400 /* Create DMA tag for Tx buffers. */
1401 error = bus_dma_tag_create(
1402 sc->alc_cdata.alc_buffer_tag, /* parent */
1403 1, 0, /* alignment, boundary */
1404 BUS_SPACE_MAXADDR, /* lowaddr */
1405 BUS_SPACE_MAXADDR, /* highaddr */
1406 NULL, NULL, /* filter, filterarg */
1407 ALC_TSO_MAXSIZE, /* maxsize */
1408 ALC_MAXTXSEGS, /* nsegments */
1409 ALC_TSO_MAXSEGSIZE, /* maxsegsize */
1410 0, /* flags */
1411 &sc->alc_cdata.alc_tx_tag);
1412 if (error != 0) {
1413 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n");
1414 goto fail;
1415 }
1416
1417 /* Create DMA tag for Rx buffers. */
1418 error = bus_dma_tag_create(
1419 sc->alc_cdata.alc_buffer_tag, /* parent */
1420 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */
1421 BUS_SPACE_MAXADDR, /* lowaddr */
1422 BUS_SPACE_MAXADDR, /* highaddr */
1423 NULL, NULL, /* filter, filterarg */
1424 MCLBYTES, /* maxsize */
1425 1, /* nsegments */
1426 MCLBYTES, /* maxsegsize */
1427 0, /* flags */
1428 &sc->alc_cdata.alc_rx_tag);
1429 if (error != 0) {
1430 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n");
1431 goto fail;
1432 }
1433 /* Create DMA maps for Tx buffers. */
1434 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1435 txd = &sc->alc_cdata.alc_txdesc[i];
1436 txd->tx_m = NULL;
1437 txd->tx_dmamap = NULL;
1438 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0,
1439 &txd->tx_dmamap);
1440 if (error != 0) {
1441 device_printf(sc->alc_dev,
1442 "could not create Tx dmamap.\n");
1443 goto fail;
1444 }
1445 }
1446 /* Create DMA maps for Rx buffers. */
1447 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
1448 &sc->alc_cdata.alc_rx_sparemap)) != 0) {
1449 device_printf(sc->alc_dev,
1450 "could not create spare Rx dmamap.\n");
1451 goto fail;
1452 }
1453 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1454 rxd = &sc->alc_cdata.alc_rxdesc[i];
1455 rxd->rx_m = NULL;
1456 rxd->rx_dmamap = NULL;
1457 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
1458 &rxd->rx_dmamap);
1459 if (error != 0) {
1460 device_printf(sc->alc_dev,
1461 "could not create Rx dmamap.\n");
1462 goto fail;
1463 }
1464 }
1465
1466 fail:
1467 return (error);
1468 }
1469
1470 static void
1471 alc_dma_free(struct alc_softc *sc)
1472 {
1473 struct alc_txdesc *txd;
1474 struct alc_rxdesc *rxd;
1475 int i;
1476
1477 /* Tx buffers. */
1478 if (sc->alc_cdata.alc_tx_tag != NULL) {
1479 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1480 txd = &sc->alc_cdata.alc_txdesc[i];
1481 if (txd->tx_dmamap != NULL) {
1482 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag,
1483 txd->tx_dmamap);
1484 txd->tx_dmamap = NULL;
1485 }
1486 }
1487 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag);
1488 sc->alc_cdata.alc_tx_tag = NULL;
1489 }
1490 /* Rx buffers */
1491 if (sc->alc_cdata.alc_rx_tag != NULL) {
1492 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1493 rxd = &sc->alc_cdata.alc_rxdesc[i];
1494 if (rxd->rx_dmamap != NULL) {
1495 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1496 rxd->rx_dmamap);
1497 rxd->rx_dmamap = NULL;
1498 }
1499 }
1500 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
1501 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1502 sc->alc_cdata.alc_rx_sparemap);
1503 sc->alc_cdata.alc_rx_sparemap = NULL;
1504 }
1505 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag);
1506 sc->alc_cdata.alc_rx_tag = NULL;
1507 }
1508 /* Tx descriptor ring. */
1509 if (sc->alc_cdata.alc_tx_ring_tag != NULL) {
1510 if (sc->alc_cdata.alc_tx_ring_map != NULL)
1511 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag,
1512 sc->alc_cdata.alc_tx_ring_map);
1513 if (sc->alc_cdata.alc_tx_ring_map != NULL &&
1514 sc->alc_rdata.alc_tx_ring != NULL)
1515 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag,
1516 sc->alc_rdata.alc_tx_ring,
1517 sc->alc_cdata.alc_tx_ring_map);
1518 sc->alc_rdata.alc_tx_ring = NULL;
1519 sc->alc_cdata.alc_tx_ring_map = NULL;
1520 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag);
1521 sc->alc_cdata.alc_tx_ring_tag = NULL;
1522 }
1523 /* Rx ring. */
1524 if (sc->alc_cdata.alc_rx_ring_tag != NULL) {
1525 if (sc->alc_cdata.alc_rx_ring_map != NULL)
1526 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag,
1527 sc->alc_cdata.alc_rx_ring_map);
1528 if (sc->alc_cdata.alc_rx_ring_map != NULL &&
1529 sc->alc_rdata.alc_rx_ring != NULL)
1530 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag,
1531 sc->alc_rdata.alc_rx_ring,
1532 sc->alc_cdata.alc_rx_ring_map);
1533 sc->alc_rdata.alc_rx_ring = NULL;
1534 sc->alc_cdata.alc_rx_ring_map = NULL;
1535 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag);
1536 sc->alc_cdata.alc_rx_ring_tag = NULL;
1537 }
1538 /* Rx return ring. */
1539 if (sc->alc_cdata.alc_rr_ring_tag != NULL) {
1540 if (sc->alc_cdata.alc_rr_ring_map != NULL)
1541 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag,
1542 sc->alc_cdata.alc_rr_ring_map);
1543 if (sc->alc_cdata.alc_rr_ring_map != NULL &&
1544 sc->alc_rdata.alc_rr_ring != NULL)
1545 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag,
1546 sc->alc_rdata.alc_rr_ring,
1547 sc->alc_cdata.alc_rr_ring_map);
1548 sc->alc_rdata.alc_rr_ring = NULL;
1549 sc->alc_cdata.alc_rr_ring_map = NULL;
1550 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag);
1551 sc->alc_cdata.alc_rr_ring_tag = NULL;
1552 }
1553 /* CMB block */
1554 if (sc->alc_cdata.alc_cmb_tag != NULL) {
1555 if (sc->alc_cdata.alc_cmb_map != NULL)
1556 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag,
1557 sc->alc_cdata.alc_cmb_map);
1558 if (sc->alc_cdata.alc_cmb_map != NULL &&
1559 sc->alc_rdata.alc_cmb != NULL)
1560 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag,
1561 sc->alc_rdata.alc_cmb,
1562 sc->alc_cdata.alc_cmb_map);
1563 sc->alc_rdata.alc_cmb = NULL;
1564 sc->alc_cdata.alc_cmb_map = NULL;
1565 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag);
1566 sc->alc_cdata.alc_cmb_tag = NULL;
1567 }
1568 /* SMB block */
1569 if (sc->alc_cdata.alc_smb_tag != NULL) {
1570 if (sc->alc_cdata.alc_smb_map != NULL)
1571 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag,
1572 sc->alc_cdata.alc_smb_map);
1573 if (sc->alc_cdata.alc_smb_map != NULL &&
1574 sc->alc_rdata.alc_smb != NULL)
1575 bus_dmamem_free(sc->alc_cdata.alc_smb_tag,
1576 sc->alc_rdata.alc_smb,
1577 sc->alc_cdata.alc_smb_map);
1578 sc->alc_rdata.alc_smb = NULL;
1579 sc->alc_cdata.alc_smb_map = NULL;
1580 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag);
1581 sc->alc_cdata.alc_smb_tag = NULL;
1582 }
1583 if (sc->alc_cdata.alc_buffer_tag != NULL) {
1584 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag);
1585 sc->alc_cdata.alc_buffer_tag = NULL;
1586 }
1587 if (sc->alc_cdata.alc_parent_tag != NULL) {
1588 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag);
1589 sc->alc_cdata.alc_parent_tag = NULL;
1590 }
1591 }
1592
1593 static int
1594 alc_shutdown(device_t dev)
1595 {
1596
1597 return (alc_suspend(dev));
1598 }
1599
1600 #if 0
1601 /* XXX: LINK SPEED */
1602 /*
1603 * Note, this driver resets the link speed to 10/100Mbps by
1604 * restarting auto-negotiation in suspend/shutdown phase but we
1605 * don't know whether that auto-negotiation would succeed or not
1606 * as driver has no control after powering off/suspend operation.
1607 * If the renegotiation fail WOL may not work. Running at 1Gbps
1608 * will draw more power than 375mA at 3.3V which is specified in
1609 * PCI specification and that would result in complete
1610 * shutdowning power to ethernet controller.
1611 *
1612 * TODO
1613 * Save current negotiated media speed/duplex/flow-control to
1614 * softc and restore the same link again after resuming. PHY
1615 * handling such as power down/resetting to 100Mbps may be better
1616 * handled in suspend method in phy driver.
1617 */
1618 static void
1619 alc_setlinkspeed(struct alc_softc *sc)
1620 {
1621 struct mii_data *mii;
1622 int aneg, i;
1623
1624 mii = device_get_softc(sc->alc_miibus);
1625 mii_pollstat(mii);
1626 aneg = 0;
1627 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1628 (IFM_ACTIVE | IFM_AVALID)) {
1629 switch IFM_SUBTYPE(mii->mii_media_active) {
1630 case IFM_10_T:
1631 case IFM_100_TX:
1632 return;
1633 case IFM_1000_T:
1634 aneg++;
1635 break;
1636 default:
1637 break;
1638 }
1639 }
1640 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
1641 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1642 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1643 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1644 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1645 DELAY(1000);
1646 if (aneg != 0) {
1647 /*
1648 * Poll link state until alc(4) get a 10/100Mbps link.
1649 */
1650 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1651 mii_pollstat(mii);
1652 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1653 == (IFM_ACTIVE | IFM_AVALID)) {
1654 switch (IFM_SUBTYPE(
1655 mii->mii_media_active)) {
1656 case IFM_10_T:
1657 case IFM_100_TX:
1658 alc_mac_config(sc);
1659 return;
1660 default:
1661 break;
1662 }
1663 }
1664 ALC_UNLOCK(sc);
1665 pause("alclnk", hz);
1666 ALC_LOCK(sc);
1667 }
1668 if (i == MII_ANEGTICKS_GIGE)
1669 device_printf(sc->alc_dev,
1670 "establishing a link failed, WOL may not work!");
1671 }
1672 /*
1673 * No link, force MAC to have 100Mbps, full-duplex link.
1674 * This is the last resort and may/may not work.
1675 */
1676 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1677 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1678 alc_mac_config(sc);
1679 }
1680 #endif
1681
1682 #if 0
1683 /* XXX: WOL */
1684 static void
1685 alc_setwol(struct alc_softc *sc)
1686 {
1687 struct ifnet *ifp;
1688 uint32_t cap, reg, pmcs;
1689 uint16_t pmstat;
1690 int base, pmc;
1691
1692 ALC_LOCK_ASSERT(sc);
1693
1694 if (pci_find_extcap(sc->alc_dev, PCIY_EXPRESS, &base) == 0) {
1695 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP);
1696 if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
1697 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL);
1698 alc_disable_l0s_l1(sc);
1699 }
1700 }
1701 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) != 0) {
1702 /* Disable WOL. */
1703 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
1704 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1705 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1706 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1707 /* Force PHY power down. */
1708 alc_phy_down(sc);
1709 return;
1710 }
1711
1712 ifp = sc->alc_ifp;
1713 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1714 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
1715 alc_setlinkspeed(sc);
1716 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
1717 reg &= ~MASTER_CLK_SEL_DIS;
1718 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
1719 }
1720
1721 pmcs = 0;
1722 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1723 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1724 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
1725 reg = CSR_READ_4(sc, ALC_MAC_CFG);
1726 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1727 MAC_CFG_BCAST);
1728 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1729 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1730 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1731 reg |= MAC_CFG_RX_ENB;
1732 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
1733
1734 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1735 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1736 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1737 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1738 /* WOL disabled, PHY power down. */
1739 alc_phy_down(sc);
1740 }
1741 /* Request PME. */
1742 pmstat = pci_read_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, 2);
1743 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1744 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1745 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1746 pci_write_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1747 }
1748 #endif
1749
1750 static int
1751 alc_suspend(device_t dev)
1752 {
1753 struct alc_softc *sc;
1754
1755 sc = device_get_softc(dev);
1756
1757 ALC_LOCK(sc);
1758 alc_stop(sc);
1759 #if 0
1760 /* XXX: WOL */
1761 alc_setwol(sc);
1762 #endif
1763 ALC_UNLOCK(sc);
1764
1765 return (0);
1766 }
1767
1768 static int
1769 alc_resume(device_t dev)
1770 {
1771 struct alc_softc *sc;
1772 struct ifnet *ifp;
1773 int pmc;
1774 uint16_t pmstat;
1775
1776 sc = device_get_softc(dev);
1777
1778 ALC_LOCK(sc);
1779 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) == 0) {
1780 /* Disable PME and clear PME status. */
1781 pmstat = pci_read_config(sc->alc_dev,
1782 pmc + PCIR_POWER_STATUS, 2);
1783 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1784 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1785 pci_write_config(sc->alc_dev,
1786 pmc + PCIR_POWER_STATUS, pmstat, 2);
1787 }
1788 }
1789 /* Reset PHY. */
1790 alc_phy_reset(sc);
1791 ifp = sc->alc_ifp;
1792 if ((ifp->if_flags & IFF_UP) != 0) {
1793 ifp->if_flags &= ~IFF_RUNNING;
1794 alc_init_locked(sc);
1795 }
1796 ALC_UNLOCK(sc);
1797
1798 return (0);
1799 }
1800
1801 static int
1802 alc_encap(struct alc_softc *sc, struct mbuf **m_head)
1803 {
1804 struct alc_txdesc *txd, *txd_last;
1805 struct tx_desc *desc;
1806 struct mbuf *m;
1807 struct ip *ip;
1808 struct tcphdr *tcp;
1809 bus_dma_segment_t txsegs[ALC_MAXTXSEGS];
1810 bus_dmamap_t map;
1811 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1812 int error, idx, nsegs, prod;
1813
1814 ALC_LOCK_ASSERT(sc);
1815
1816 M_ASSERTPKTHDR((*m_head));
1817
1818 m = *m_head;
1819 ip = NULL;
1820 tcp = NULL;
1821 ip_off = poff = 0;
1822 #if 0
1823 /* XXX: TSO */
1824 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
1825 /*
1826 * AR8131/AR8132 requires offset of TCP/UDP header in its
1827 * Tx descriptor to perform Tx checksum offloading. TSO
1828 * also requires TCP header offset and modification of
1829 * IP/TCP header. This kind of operation takes many CPU
1830 * cycles on FreeBSD so fast host CPU is required to get
1831 * smooth TSO performance.
1832 */
1833 struct ether_header *eh;
1834
1835 if (M_WRITABLE(m) == 0) {
1836 /* Get a writable copy. */
1837 m = m_dup(*m_head, MB_DONTWAIT);
1838 /* Release original mbufs. */
1839 m_freem(*m_head);
1840 if (m == NULL) {
1841 *m_head = NULL;
1842 return (ENOBUFS);
1843 }
1844 *m_head = m;
1845 }
1846
1847 ip_off = sizeof(struct ether_header);
1848 m = m_pullup(m, ip_off);
1849 if (m == NULL) {
1850 *m_head = NULL;
1851 return (ENOBUFS);
1852 }
1853 eh = mtod(m, struct ether_header *);
1854 /*
1855 * Check if hardware VLAN insertion is off.
1856 * Additional check for LLC/SNAP frame?
1857 */
1858 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1859 ip_off = sizeof(struct ether_vlan_header);
1860 m = m_pullup(m, ip_off);
1861 if (m == NULL) {
1862 *m_head = NULL;
1863 return (ENOBUFS);
1864 }
1865 }
1866 m = m_pullup(m, ip_off + sizeof(struct ip));
1867 if (m == NULL) {
1868 *m_head = NULL;
1869 return (ENOBUFS);
1870 }
1871 ip = (struct ip *)(mtod(m, char *) + ip_off);
1872 poff = ip_off + (ip->ip_hl << 2);
1873
1874 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1875 m = m_pullup(m, poff + sizeof(struct tcphdr));
1876 if (m == NULL) {
1877 *m_head = NULL;
1878 return (ENOBUFS);
1879 }
1880 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1881 m = m_pullup(m, poff + (tcp->th_off << 2));
1882 if (m == NULL) {
1883 *m_head = NULL;
1884 return (ENOBUFS);
1885 }
1886 /*
1887 * Due to strict adherence of Microsoft NDIS
1888 * Large Send specification, hardware expects
1889 * a pseudo TCP checksum inserted by upper
1890 * stack. Unfortunately the pseudo TCP
1891 * checksum that NDIS refers to does not include
1892 * TCP payload length so driver should recompute
1893 * the pseudo checksum here. Hopefully this
1894 * wouldn't be much burden on modern CPUs.
1895 *
1896 * Reset IP checksum and recompute TCP pseudo
1897 * checksum as NDIS specification said.
1898 */
1899 ip->ip_sum = 0;
1900 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1901 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1902 }
1903 *m_head = m;
1904 }
1905 #endif /* TSO */
1906
1907 prod = sc->alc_cdata.alc_tx_prod;
1908 txd = &sc->alc_cdata.alc_txdesc[prod];
1909 txd_last = txd;
1910 map = txd->tx_dmamap;
1911
1912 error = bus_dmamap_load_mbuf_segment(sc->alc_cdata.alc_tx_tag, map,
1913 *m_head, txsegs, 1, &nsegs, 0);
1914 if (error == EFBIG) {
1915 m = m_defrag(*m_head, M_NOWAIT); /* XXX: ALC_MAXTXSEGS */
1916 if (m == NULL) {
1917 m_freem(*m_head);
1918 *m_head = NULL;
1919 return (ENOMEM);
1920 }
1921 *m_head = m;
1922 error = bus_dmamap_load_mbuf_segment(sc->alc_cdata.alc_tx_tag,
1923 map, *m_head, txsegs, 1, &nsegs, 0);
1924 if (error != 0) {
1925 m_freem(*m_head);
1926 *m_head = NULL;
1927 return (error);
1928 }
1929 } else if (error != 0)
1930 return (error);
1931 if (nsegs == 0) {
1932 m_freem(*m_head);
1933 *m_head = NULL;
1934 return (EIO);
1935 }
1936
1937 /* Check descriptor overrun. */
1938 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
1939 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map);
1940 return (ENOBUFS);
1941 }
1942 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE);
1943
1944 m = *m_head;
1945 cflags = TD_ETHERNET;
1946 vtag = 0;
1947 desc = NULL;
1948 idx = 0;
1949 /* Configure VLAN hardware tag insertion. */
1950 if ((m->m_flags & M_VLANTAG) != 0) {
1951 vtag = htons(m->m_pkthdr.ether_vlantag);
1952 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
1953 cflags |= TD_INS_VLAN_TAG;
1954 }
1955 /* Configure Tx checksum offload. */
1956 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
1957 #ifdef ALC_USE_CUSTOM_CSUM
1958 cflags |= TD_CUSTOM_CSUM;
1959 /* Set checksum start offset. */
1960 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
1961 TD_PLOAD_OFFSET_MASK;
1962 /* Set checksum insertion position of TCP/UDP. */
1963 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) <<
1964 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK;
1965 #else
1966 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1967 cflags |= TD_IPCSUM;
1968 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1969 cflags |= TD_TCPCSUM;
1970 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1971 cflags |= TD_UDPCSUM;
1972 /* Set TCP/UDP header offset. */
1973 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) &
1974 TD_L4HDR_OFFSET_MASK;
1975 #endif
1976 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1977 /* Request TSO and set MSS. */
1978 cflags |= TD_TSO | TD_TSO_DESCV1;
1979 #if 0
1980 /* XXX: TSO */
1981 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) &
1982 TD_MSS_MASK;
1983 /* Set TCP header offset. */
1984 #endif
1985 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
1986 TD_TCPHDR_OFFSET_MASK;
1987 /*
1988 * AR8131/AR8132 requires the first buffer should
1989 * only hold IP/TCP header data. Payload should
1990 * be handled in other descriptors.
1991 */
1992 hdrlen = poff + (tcp->th_off << 2);
1993 desc = &sc->alc_rdata.alc_tx_ring[prod];
1994 desc->len = htole32(TX_BYTES(hdrlen | vtag));
1995 desc->flags = htole32(cflags);
1996 desc->addr = htole64(txsegs[0].ds_addr);
1997 sc->alc_cdata.alc_tx_cnt++;
1998 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
1999 if (m->m_len - hdrlen > 0) {
2000 /* Handle remaining payload of the first fragment. */
2001 desc = &sc->alc_rdata.alc_tx_ring[prod];
2002 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) |
2003 vtag));
2004 desc->flags = htole32(cflags);
2005 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
2006 sc->alc_cdata.alc_tx_cnt++;
2007 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2008 }
2009 /* Handle remaining fragments. */
2010 idx = 1;
2011 }
2012 for (; idx < nsegs; idx++) {
2013 desc = &sc->alc_rdata.alc_tx_ring[prod];
2014 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag);
2015 desc->flags = htole32(cflags);
2016 desc->addr = htole64(txsegs[idx].ds_addr);
2017 sc->alc_cdata.alc_tx_cnt++;
2018 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2019 }
2020 /* Update producer index. */
2021 sc->alc_cdata.alc_tx_prod = prod;
2022
2023 /* Finally set EOP on the last descriptor. */
2024 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
2025 desc = &sc->alc_rdata.alc_tx_ring[prod];
2026 desc->flags |= htole32(TD_EOP);
2027
2028 /* Swap dmamap of the first and the last. */
2029 txd = &sc->alc_cdata.alc_txdesc[prod];
2030 map = txd_last->tx_dmamap;
2031 txd_last->tx_dmamap = txd->tx_dmamap;
2032 txd->tx_dmamap = map;
2033 txd->tx_m = m;
2034
2035 return (0);
2036 }
2037
2038 static void
2039 alc_tx_task(void *arg, int pending)
2040 {
2041 struct ifnet *ifp;
2042
2043 ifp = (struct ifnet *)arg;
2044 alc_start(ifp);
2045 }
2046
2047 static void
2048 alc_start(struct ifnet *ifp)
2049 {
2050 struct alc_softc *sc;
2051 struct mbuf *m_head;
2052 int enq;
2053
2054 sc = ifp->if_softc;
2055
2056 ALC_LOCK(sc);
2057
2058 /* Reclaim transmitted frames. */
2059 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
2060 alc_txeof(sc);
2061
2062 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) !=
2063 IFF_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) {
2064 ALC_UNLOCK(sc);
2065 return;
2066 }
2067
2068 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) {
2069 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2070 if (m_head == NULL)
2071 break;
2072 /*
2073 * Pack the data into the transmit ring. If we
2074 * don't have room, set the OACTIVE flag and wait
2075 * for the NIC to drain the ring.
2076 */
2077 if (alc_encap(sc, &m_head)) {
2078 if (m_head == NULL)
2079 break;
2080 ifq_prepend(&ifp->if_snd, m_head);
2081 ifp->if_flags |= IFF_OACTIVE;
2082 break;
2083 }
2084
2085 enq++;
2086 /*
2087 * If there's a BPF listener, bounce a copy of this frame
2088 * to him.
2089 */
2090 ETHER_BPF_MTAP(ifp, m_head);
2091 }
2092
2093 if (enq > 0) {
2094 /* Sync descriptors. */
2095 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2096 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
2097 /* Kick. Assume we're using normal Tx priority queue. */
2098 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
2099 (sc->alc_cdata.alc_tx_prod <<
2100 MBOX_TD_PROD_LO_IDX_SHIFT) &
2101 MBOX_TD_PROD_LO_IDX_MASK);
2102 /* Set a timeout in case the chip goes out to lunch. */
2103 sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
2104 }
2105
2106 ALC_UNLOCK(sc);
2107 }
2108
2109 static void
2110 alc_watchdog(struct alc_softc *sc)
2111 {
2112 struct ifnet *ifp;
2113
2114 ALC_LOCK_ASSERT(sc);
2115
2116 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
2117 return;
2118
2119 ifp = sc->alc_ifp;
2120 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
2121 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n");
2122 ifp->if_oerrors++;
2123 ifp->if_flags &= ~IFF_RUNNING;
2124 alc_init_locked(sc);
2125 return;
2126 }
2127 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n");
2128 ifp->if_oerrors++;
2129 ifp->if_flags &= ~IFF_RUNNING;
2130 alc_init_locked(sc);
2131 if (!ifq_is_empty(&ifp->if_snd))
2132 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task);
2133 }
2134
2135 static int
2136 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
2137 {
2138 struct alc_softc *sc;
2139 struct ifreq *ifr;
2140 struct mii_data *mii;
2141 int error, mask;
2142
2143 (void)cr;
2144 sc = ifp->if_softc;
2145 ifr = (struct ifreq *)data;
2146 error = 0;
2147 switch (cmd) {
2148 case SIOCSIFMTU:
2149 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALC_JUMBO_MTU ||
2150 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
2151 ifr->ifr_mtu > ETHERMTU))
2152 error = EINVAL;
2153 else if (ifp->if_mtu != ifr->ifr_mtu) {
2154 ALC_LOCK(sc);
2155 ifp->if_mtu = ifr->ifr_mtu;
2156 /* AR8131/AR8132 has 13 bits MSS field. */
2157 if (ifp->if_mtu > ALC_TSO_MTU &&
2158 (ifp->if_capenable & IFCAP_TSO4) != 0) {
2159 ifp->if_capenable &= ~IFCAP_TSO4;
2160 ifp->if_hwassist &= ~CSUM_TSO;
2161 }
2162 ALC_UNLOCK(sc);
2163 }
2164 break;
2165 case SIOCSIFFLAGS:
2166 ALC_LOCK(sc);
2167 if ((ifp->if_flags & IFF_UP) != 0) {
2168 if ((ifp->if_flags & IFF_RUNNING) != 0 &&
2169 ((ifp->if_flags ^ sc->alc_if_flags) &
2170 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2171 alc_rxfilter(sc);
2172 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0)
2173 alc_init_locked(sc);
2174 } else if ((ifp->if_flags & IFF_RUNNING) != 0)
2175 alc_stop(sc);
2176 sc->alc_if_flags = ifp->if_flags;
2177 ALC_UNLOCK(sc);
2178 break;
2179 case SIOCADDMULTI:
2180 case SIOCDELMULTI:
2181 ALC_LOCK(sc);
2182 if ((ifp->if_flags & IFF_RUNNING) != 0)
2183 alc_rxfilter(sc);
2184 ALC_UNLOCK(sc);
2185 break;
2186 case SIOCSIFMEDIA:
2187 case SIOCGIFMEDIA:
2188 mii = device_get_softc(sc->alc_miibus);
2189 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2190 break;
2191 case SIOCSIFCAP:
2192 ALC_LOCK(sc);
2193 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2194 if ((mask & IFCAP_TXCSUM) != 0 &&
2195 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2196 ifp->if_capenable ^= IFCAP_TXCSUM;
2197 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2198 ifp->if_hwassist |= ALC_CSUM_FEATURES;
2199 else
2200 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
2201 }
2202 if ((mask & IFCAP_TSO4) != 0 &&
2203 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2204 ifp->if_capenable ^= IFCAP_TSO4;
2205 if ((ifp->if_capenable & IFCAP_TSO4) != 0) {
2206 /* AR8131/AR8132 has 13 bits MSS field. */
2207 if (ifp->if_mtu > ALC_TSO_MTU) {
2208 ifp->if_capenable &= ~IFCAP_TSO4;
2209 ifp->if_hwassist &= ~CSUM_TSO;
2210 } else
2211 ifp->if_hwassist |= CSUM_TSO;
2212 } else
2213 ifp->if_hwassist &= ~CSUM_TSO;
2214 }
2215 #if 0
2216 /* XXX: WOL */
2217 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2218 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2219 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2220 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2221 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2222 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2223 #endif
2224 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2225 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2226 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2227 alc_rxvlan(sc);
2228 }
2229 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2230 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2231 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2232 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2233 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2234 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2235 /*
2236 * VLAN hardware tagging is required to do checksum
2237 * offload or TSO on VLAN interface. Checksum offload
2238 * on VLAN interface also requires hardware checksum
2239 * offload of parent interface.
2240 */
2241 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0)
2242 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
2243 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2244 ifp->if_capenable &=
2245 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2246 ALC_UNLOCK(sc);
2247 // XXX VLAN_CAPABILITIES(ifp);
2248 break;
2249 default:
2250 error = ether_ioctl(ifp, cmd, data);
2251 break;
2252 }
2253
2254 return (error);
2255 }
2256
2257 static void
2258 alc_mac_config(struct alc_softc *sc)
2259 {
2260 struct mii_data *mii;
2261 uint32_t reg;
2262
2263 ALC_LOCK_ASSERT(sc);
2264
2265 mii = device_get_softc(sc->alc_miibus);
2266 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2267 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2268 MAC_CFG_SPEED_MASK);
2269 /* Reprogram MAC with resolved speed/duplex. */
2270 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2271 case IFM_10_T:
2272 case IFM_100_TX:
2273 reg |= MAC_CFG_SPEED_10_100;
2274 break;
2275 case IFM_1000_T:
2276 reg |= MAC_CFG_SPEED_1000;
2277 break;
2278 }
2279 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2280 reg |= MAC_CFG_FULL_DUPLEX;
2281 #ifdef notyet
2282 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2283 reg |= MAC_CFG_TX_FC;
2284 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2285 reg |= MAC_CFG_RX_FC;
2286 #endif
2287 }
2288 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2289 }
2290
2291 static void
2292 alc_stats_clear(struct alc_softc *sc)
2293 {
2294 struct smb sb, *smb;
2295 uint32_t *reg;
2296 int i;
2297
2298 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2299 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2300 sc->alc_cdata.alc_smb_map,
2301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2302 smb = sc->alc_rdata.alc_smb;
2303 /* Update done, clear. */
2304 smb->updated = 0;
2305 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2306 sc->alc_cdata.alc_smb_map,
2307 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2308 } else {
2309 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2310 reg++) {
2311 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2312 i += sizeof(uint32_t);
2313 }
2314 /* Read Tx statistics. */
2315 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2316 reg++) {
2317 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2318 i += sizeof(uint32_t);
2319 }
2320 }
2321 }
2322
2323 static void
2324 alc_stats_update(struct alc_softc *sc)
2325 {
2326 struct alc_hw_stats *stat;
2327 struct smb sb, *smb;
2328 struct ifnet *ifp;
2329 uint32_t *reg;
2330 int i;
2331
2332 ALC_LOCK_ASSERT(sc);
2333
2334 ifp = sc->alc_ifp;
2335 stat = &sc->alc_stats;
2336 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2337 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2338 sc->alc_cdata.alc_smb_map,
2339 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2340 smb = sc->alc_rdata.alc_smb;
2341 if (smb->updated == 0)
2342 return;
2343 } else {
2344 smb = &sb;
2345 /* Read Rx statistics. */
2346 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2347 reg++) {
2348 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2349 i += sizeof(uint32_t);
2350 }
2351 /* Read Tx statistics. */
2352 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2353 reg++) {
2354 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2355 i += sizeof(uint32_t);
2356 }
2357 }
2358
2359 /* Rx stats. */
2360 stat->rx_frames += smb->rx_frames;
2361 stat->rx_bcast_frames += smb->rx_bcast_frames;
2362 stat->rx_mcast_frames += smb->rx_mcast_frames;
2363 stat->rx_pause_frames += smb->rx_pause_frames;
2364 stat->rx_control_frames += smb->rx_control_frames;
2365 stat->rx_crcerrs += smb->rx_crcerrs;
2366 stat->rx_lenerrs += smb->rx_lenerrs;
2367 stat->rx_bytes += smb->rx_bytes;
2368 stat->rx_runts += smb->rx_runts;
2369 stat->rx_fragments += smb->rx_fragments;
2370 stat->rx_pkts_64 += smb->rx_pkts_64;
2371 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2372 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2373 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2374 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2375 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2376 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2377 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2378 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2379 stat->rx_rrs_errs += smb->rx_rrs_errs;
2380 stat->rx_alignerrs += smb->rx_alignerrs;
2381 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2382 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2383 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2384
2385 /* Tx stats. */
2386 stat->tx_frames += smb->tx_frames;
2387 stat->tx_bcast_frames += smb->tx_bcast_frames;
2388 stat->tx_mcast_frames += smb->tx_mcast_frames;
2389 stat->tx_pause_frames += smb->tx_pause_frames;
2390 stat->tx_excess_defer += smb->tx_excess_defer;
2391 stat->tx_control_frames += smb->tx_control_frames;
2392 stat->tx_deferred += smb->tx_deferred;
2393 stat->tx_bytes += smb->tx_bytes;
2394 stat->tx_pkts_64 += smb->tx_pkts_64;
2395 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2396 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2397 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2398 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2399 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2400 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2401 stat->tx_single_colls += smb->tx_single_colls;
2402 stat->tx_multi_colls += smb->tx_multi_colls;
2403 stat->tx_late_colls += smb->tx_late_colls;
2404 stat->tx_excess_colls += smb->tx_excess_colls;
2405 stat->tx_abort += smb->tx_abort;
2406 stat->tx_underrun += smb->tx_underrun;
2407 stat->tx_desc_underrun += smb->tx_desc_underrun;
2408 stat->tx_lenerrs += smb->tx_lenerrs;
2409 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2410 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2411 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2412
2413 /* Update counters in ifnet. */
2414 ifp->if_opackets += smb->tx_frames;
2415
2416 ifp->if_collisions += smb->tx_single_colls +
2417 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2418 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2419
2420 /*
2421 * XXX
2422 * tx_pkts_truncated counter looks suspicious. It constantly
2423 * increments with no sign of Tx errors. This may indicate
2424 * the counter name is not correct one so I've removed the
2425 * counter in output errors.
2426 */
2427 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2428 smb->tx_underrun;
2429
2430 ifp->if_ipackets += smb->rx_frames;
2431
2432 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2433 smb->rx_runts + smb->rx_pkts_truncated +
2434 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2435 smb->rx_alignerrs;
2436
2437 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2438 /* Update done, clear. */
2439 smb->updated = 0;
2440 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2441 sc->alc_cdata.alc_smb_map,
2442 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2443 }
2444 }
2445
2446 static void
2447 alc_intr(void *arg)
2448 {
2449 struct alc_softc *sc;
2450 uint32_t status;
2451
2452 sc = (struct alc_softc *)arg;
2453
2454 status = CSR_READ_4(sc, ALC_INTR_STATUS);
2455 if ((status & ALC_INTRS) == 0)
2456 return;
2457 /* Disable interrupts. */
2458 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
2459 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
2460
2461 return;
2462 }
2463
2464 static void
2465 alc_int_task(void *arg, int pending)
2466 {
2467 struct alc_softc *sc;
2468 struct ifnet *ifp;
2469 uint32_t status;
2470 int more;
2471
2472 sc = (struct alc_softc *)arg;
2473 ifp = sc->alc_ifp;
2474
2475 status = CSR_READ_4(sc, ALC_INTR_STATUS);
2476 more = atomic_readandclear_int(&sc->alc_morework);
2477 if (more != 0)
2478 status |= INTR_RX_PKT;
2479 if ((status & ALC_INTRS) == 0)
2480 goto done;
2481
2482 /* Acknowledge interrupts but still disable interrupts. */
2483 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
2484
2485 more = 0;
2486 if ((ifp->if_flags & IFF_RUNNING) != 0) {
2487 if ((status & INTR_RX_PKT) != 0) {
2488 more = alc_rxintr(sc, sc->alc_process_limit);
2489 if (more == EAGAIN)
2490 atomic_set_int(&sc->alc_morework, 1);
2491 else if (more == EIO) {
2492 ALC_LOCK(sc);
2493 ifp->if_flags &= ~IFF_RUNNING;
2494 alc_init_locked(sc);
2495 ALC_UNLOCK(sc);
2496 return;
2497 }
2498 }
2499 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
2500 INTR_TXQ_TO_RST)) != 0) {
2501 if ((status & INTR_DMA_RD_TO_RST) != 0)
2502 device_printf(sc->alc_dev,
2503 "DMA read error! -- resetting\n");
2504 if ((status & INTR_DMA_WR_TO_RST) != 0)
2505 device_printf(sc->alc_dev,
2506 "DMA write error! -- resetting\n");
2507 if ((status & INTR_TXQ_TO_RST) != 0)
2508 device_printf(sc->alc_dev,
2509 "TxQ reset! -- resetting\n");
2510 ALC_LOCK(sc);
2511 ifp->if_flags &= ~IFF_RUNNING;
2512 alc_init_locked(sc);
2513 ALC_UNLOCK(sc);
2514 return;
2515 }
2516 if ((ifp->if_flags & IFF_RUNNING) != 0 &&
2517 !ifq_is_empty(&ifp->if_snd))
2518 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task);
2519 }
2520
2521 if (more == EAGAIN ||
2522 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {
2523 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
2524 return;
2525 }
2526
2527 done:
2528 if ((ifp->if_flags & IFF_RUNNING) != 0) {
2529 /* Re-enable interrupts if we're running. */
2530 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
2531 }
2532 }
2533
2534 static void
2535 alc_txeof(struct alc_softc *sc)
2536 {
2537 struct ifnet *ifp;
2538 struct alc_txdesc *txd;
2539 uint32_t cons, prod;
2540 int prog;
2541
2542 ALC_LOCK_ASSERT(sc);
2543
2544 ifp = sc->alc_ifp;
2545
2546 if (sc->alc_cdata.alc_tx_cnt == 0)
2547 return;
2548 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2549 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2550 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2551 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2552 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
2553 prod = sc->alc_rdata.alc_cmb->cons;
2554 } else
2555 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
2556 /* Assume we're using normal Tx priority queue. */
2557 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
2558 MBOX_TD_CONS_LO_IDX_SHIFT;
2559 cons = sc->alc_cdata.alc_tx_cons;
2560 /*
2561 * Go through our Tx list and free mbufs for those
2562 * frames which have been transmitted.
2563 */
2564 for (prog = 0; cons != prod; prog++,
2565 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
2566 if (sc->alc_cdata.alc_tx_cnt <= 0)
2567 break;
2568 prog++;
2569 ifp->if_flags &= ~IFF_OACTIVE;
2570 sc->alc_cdata.alc_tx_cnt--;
2571 txd = &sc->alc_cdata.alc_txdesc[cons];
2572 if (txd->tx_m != NULL) {
2573 /* Reclaim transmitted mbufs. */
2574 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
2575 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2576 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
2577 txd->tx_dmamap);
2578 m_freem(txd->tx_m);
2579 txd->tx_m = NULL;
2580 }
2581 }
2582
2583 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
2584 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2585 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD);
2586 sc->alc_cdata.alc_tx_cons = cons;
2587 /*
2588 * Unarm watchdog timer only when there is no pending
2589 * frames in Tx queue.
2590 */
2591 if (sc->alc_cdata.alc_tx_cnt == 0)
2592 sc->alc_watchdog_timer = 0;
2593 }
2594
2595 static int
2596 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd)
2597 {
2598 struct mbuf *m;
2599 bus_dma_segment_t segs[1];
2600 bus_dmamap_t map;
2601 int nsegs;
2602
2603 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2604 if (m == NULL)
2605 return (ENOBUFS);
2606 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
2607 #ifndef __NO_STRICT_ALIGNMENT
2608 m_adj(m, sizeof(uint64_t));
2609 #endif
2610
2611 if (bus_dmamap_load_mbuf_segment(sc->alc_cdata.alc_rx_tag,
2612 sc->alc_cdata.alc_rx_sparemap, m, segs, 1, &nsegs, 0) != 0) {
2613 m_freem(m);
2614 return (ENOBUFS);
2615 }
2616 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2617
2618 if (rxd->rx_m != NULL) {
2619 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2620 BUS_DMASYNC_POSTREAD);
2621 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap);
2622 }
2623 map = rxd->rx_dmamap;
2624 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
2625 sc->alc_cdata.alc_rx_sparemap = map;
2626 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2627 BUS_DMASYNC_PREREAD);
2628 rxd->rx_m = m;
2629 rxd->rx_desc->addr = htole64(segs[0].ds_addr);
2630 return (0);
2631 }
2632
2633 static int
2634 alc_rxintr(struct alc_softc *sc, int count)
2635 {
2636 struct ifnet *ifp;
2637 struct rx_rdesc *rrd;
2638 uint32_t nsegs, status;
2639 int rr_cons, prog;
2640
2641 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2642 sc->alc_cdata.alc_rr_ring_map,
2643 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2644 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2645 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2646 rr_cons = sc->alc_cdata.alc_rr_cons;
2647 ifp = sc->alc_ifp;
2648 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) {
2649 if (count-- <= 0)
2650 break;
2651 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
2652 status = le32toh(rrd->status);
2653 if ((status & RRD_VALID) == 0)
2654 break;
2655 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
2656 if (nsegs == 0) {
2657 /* This should not happen! */
2658 device_printf(sc->alc_dev,
2659 "unexpected segment count -- resetting\n");
2660 return (EIO);
2661 }
2662 alc_rxeof(sc, rrd);
2663 /* Clear Rx return status. */
2664 rrd->status = 0;
2665 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
2666 sc->alc_cdata.alc_rx_cons += nsegs;
2667 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
2668 prog += nsegs;
2669 }
2670
2671 if (prog > 0) {
2672 /* Update the consumer index. */
2673 sc->alc_cdata.alc_rr_cons = rr_cons;
2674 /* Sync Rx return descriptors. */
2675 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2676 sc->alc_cdata.alc_rr_ring_map,
2677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2678 /*
2679 * Sync updated Rx descriptors such that controller see
2680 * modified buffer addresses.
2681 */
2682 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2683 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
2684 /*
2685 * Let controller know availability of new Rx buffers.
2686 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
2687 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
2688 * only when Rx buffer pre-fetching is required. In
2689 * addition we already set ALC_RX_RD_FREE_THRESH to
2690 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
2691 * it still seems that pre-fetching needs more
2692 * experimentation.
2693 */
2694 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2695 sc->alc_cdata.alc_rx_cons);
2696 }
2697
2698 return (count > 0 ? 0 : EAGAIN);
2699 }
2700
2701 #ifndef __NO_STRICT_ALIGNMENT
2702 static struct mbuf *
2703 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m)
2704 {
2705 struct mbuf *n;
2706 int i;
2707 uint16_t *src, *dst;
2708
2709 src = mtod(m, uint16_t *);
2710 dst = src - 3;
2711
2712 if (m->m_next == NULL) {
2713 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2714 *dst++ = *src++;
2715 m->m_data -= 6;
2716 return (m);
2717 }
2718 /*
2719 * Append a new mbuf to received mbuf chain and copy ethernet
2720 * header from the mbuf chain. This can save lots of CPU
2721 * cycles for jumbo frame.
2722 */
2723 MGETHDR(n, MB_DONTWAIT, MT_DATA);
2724 if (n == NULL) {
2725 ifp->if_iqdrops++;
2726 m_freem(m);
2727 return (NULL);
2728 }
2729 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2730 m->m_data += ETHER_HDR_LEN;
2731 m->m_len -= ETHER_HDR_LEN;
2732 n->m_len = ETHER_HDR_LEN;
2733 M_MOVE_PKTHDR(n, m);
2734 n->m_next = m;
2735 return (n);
2736 }
2737 #endif
2738
2739 /* Receive a frame. */
2740 static void
2741 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
2742 {
2743 struct alc_rxdesc *rxd;
2744 struct ifnet *ifp;
2745 struct mbuf *mp, *m;
2746 uint32_t rdinfo, status, vtag;
2747 int count, nsegs, rx_cons;
2748
2749 ifp = sc->alc_ifp;
2750 status = le32toh(rrd->status);
2751 rdinfo = le32toh(rrd->rdinfo);
2752 rx_cons = RRD_RD_IDX(rdinfo);
2753 nsegs = RRD_RD_CNT(rdinfo);
2754
2755 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
2756 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
2757 /*
2758 * We want to pass the following frames to upper
2759 * layer regardless of error status of Rx return
2760 * ring.
2761 *
2762 * o IP/TCP/UDP checksum is bad.
2763 * o frame length and protocol specific length
2764 * does not match.
2765 *
2766 * Force network stack compute checksum for
2767 * errored frames.
2768 */
2769 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
2770 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
2771 RRD_ERR_RUNT) != 0)
2772 return;
2773 }
2774
2775 for (count = 0; count < nsegs; count++,
2776 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
2777 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
2778 mp = rxd->rx_m;
2779 /* Add a new receive buffer to the ring. */
2780 if (alc_newbuf(sc, rxd) != 0) {
2781 ifp->if_iqdrops++;
2782 /* Reuse Rx buffers. */
2783 if (sc->alc_cdata.alc_rxhead != NULL)
2784 m_freem(sc->alc_cdata.alc_rxhead);
2785 break;
2786 }
2787
2788 /*
2789 * Assume we've received a full sized frame.
2790 * Actual size is fixed when we encounter the end of
2791 * multi-segmented frame.
2792 */
2793 mp->m_len = sc->alc_buf_size;
2794
2795 /* Chain received mbufs. */
2796 if (sc->alc_cdata.alc_rxhead == NULL) {
2797 sc->alc_cdata.alc_rxhead = mp;
2798 sc->alc_cdata.alc_rxtail = mp;
2799 } else {
2800 mp->m_flags &= ~M_PKTHDR;
2801 sc->alc_cdata.alc_rxprev_tail =
2802 sc->alc_cdata.alc_rxtail;
2803 sc->alc_cdata.alc_rxtail->m_next = mp;
2804 sc->alc_cdata.alc_rxtail = mp;
2805 }
2806
2807 if (count == nsegs - 1) {
2808 /* Last desc. for this frame. */
2809 m = sc->alc_cdata.alc_rxhead;
2810 m->m_flags |= M_PKTHDR;
2811 /*
2812 * It seems that L1C/L2C controller has no way
2813 * to tell hardware to strip CRC bytes.
2814 */
2815 m->m_pkthdr.len =
2816 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
2817 if (nsegs > 1) {
2818 /* Set last mbuf size. */
2819 mp->m_len = sc->alc_cdata.alc_rxlen -
2820 (nsegs - 1) * sc->alc_buf_size;
2821 /* Remove the CRC bytes in chained mbufs. */
2822 if (mp->m_len <= ETHER_CRC_LEN) {
2823 sc->alc_cdata.alc_rxtail =
2824 sc->alc_cdata.alc_rxprev_tail;
2825 sc->alc_cdata.alc_rxtail->m_len -=
2826 (ETHER_CRC_LEN - mp->m_len);
2827 sc->alc_cdata.alc_rxtail->m_next = NULL;
2828 m_freem(mp);
2829 } else {
2830 mp->m_len -= ETHER_CRC_LEN;
2831 }
2832 } else
2833 m->m_len = m->m_pkthdr.len;
2834 m->m_pkthdr.rcvif = ifp;
2835 /*
2836 * Due to hardware bugs, Rx checksum offloading
2837 * was intentionally disabled.
2838 */
2839 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2840 (status & RRD_VLAN_TAG) != 0) {
2841 vtag = RRD_VLAN(le32toh(rrd->vtag));
2842 m->m_pkthdr.ether_vlantag = ntohs(vtag);
2843 m->m_flags |= M_VLANTAG;
2844 }
2845 #ifndef __NO_STRICT_ALIGNMENT
2846 m = alc_fixup_rx(ifp, m);
2847 if (m != NULL)
2848 #endif
2849 {
2850 /* Pass it on. */
2851 (*ifp->if_input)(ifp, m);
2852 }
2853 }
2854 }
2855 /* Reset mbuf chains. */
2856 ALC_RXCHAIN_RESET(sc);
2857 }
2858
2859 static void
2860 alc_tick(void *arg)
2861 {
2862 struct alc_softc *sc;
2863 struct mii_data *mii;
2864
2865 sc = (struct alc_softc *)arg;
2866
2867 ALC_LOCK_ASSERT(sc);
2868
2869 mii = device_get_softc(sc->alc_miibus);
2870 mii_tick(mii);
2871 alc_stats_update(sc);
2872 /*
2873 * alc(4) does not rely on Tx completion interrupts to reclaim
2874 * transferred buffers. Instead Tx completion interrupts are
2875 * used to hint for scheduling Tx task. So it's necessary to
2876 * release transmitted buffers by kicking Tx completion
2877 * handler. This limits the maximum reclamation delay to a hz.
2878 */
2879 alc_txeof(sc);
2880 alc_watchdog(sc);
2881 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
2882 }
2883
2884 static void
2885 alc_reset(struct alc_softc *sc)
2886 {
2887 uint32_t reg;
2888 int i;
2889
2890 CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET);
2891 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2892 DELAY(10);
2893 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
2894 break;
2895 }
2896 if (i == 0)
2897 device_printf(sc->alc_dev, "master reset timeout!\n");
2898
2899 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2900 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0)
2901 break;
2902 DELAY(10);
2903 }
2904
2905 if (i == 0)
2906 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
2907 }
2908
2909 static void
2910 alc_init(void *xsc)
2911 {
2912 struct alc_softc *sc;
2913
2914 sc = (struct alc_softc *)xsc;
2915 ALC_LOCK(sc);
2916 alc_init_locked(sc);
2917 ALC_UNLOCK(sc);
2918 }
2919
2920 static void
2921 alc_init_locked(struct alc_softc *sc)
2922 {
2923 struct ifnet *ifp;
2924 struct mii_data *mii;
2925 uint8_t eaddr[ETHER_ADDR_LEN];
2926 bus_addr_t paddr;
2927 uint32_t reg, rxf_hi, rxf_lo;
2928
2929 ALC_LOCK_ASSERT(sc);
2930
2931 ifp = sc->alc_ifp;
2932 mii = device_get_softc(sc->alc_miibus);
2933
2934 if ((ifp->if_flags & IFF_RUNNING) != 0)
2935 return;
2936 /*
2937 * Cancel any pending I/O.
2938 */
2939 alc_stop(sc);
2940 /*
2941 * Reset the chip to a known state.
2942 */
2943 alc_reset(sc);
2944
2945 /* Initialize Rx descriptors. */
2946 if (alc_init_rx_ring(sc) != 0) {
2947 device_printf(sc->alc_dev, "no memory for Rx buffers.\n");
2948 alc_stop(sc);
2949 return;
2950 }
2951 alc_init_rr_ring(sc);
2952 alc_init_tx_ring(sc);
2953 alc_init_cmb(sc);
2954 alc_init_smb(sc);
2955
2956 /* Reprogram the station address. */
2957 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2958 CSR_WRITE_4(sc, ALC_PAR0,
2959 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2960 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
2961 /*
2962 * Clear WOL status and disable all WOL feature as WOL
2963 * would interfere Rx operation under normal environments.
2964 */
2965 CSR_READ_4(sc, ALC_WOL_CFG);
2966 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2967 /* Set Tx descriptor base addresses. */
2968 paddr = sc->alc_rdata.alc_tx_ring_paddr;
2969 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2970 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2971 /* We don't use high priority ring. */
2972 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
2973 /* Set Tx descriptor counter. */
2974 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
2975 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
2976 /* Set Rx descriptor base addresses. */
2977 paddr = sc->alc_rdata.alc_rx_ring_paddr;
2978 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2979 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2980 /* We use one Rx ring. */
2981 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
2982 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
2983 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
2984 /* Set Rx descriptor counter. */
2985 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
2986 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
2987
2988 /*
2989 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
2990 * if it do not fit the buffer size. Rx return descriptor holds
2991 * a counter that indicates how many fragments were made by the
2992 * hardware. The buffer size should be multiple of 8 bytes.
2993 * Since hardware has limit on the size of buffer size, always
2994 * use the maximum value.
2995 * For strict-alignment architectures make sure to reduce buffer
2996 * size by 8 bytes to make room for alignment fixup.
2997 */
2998 #ifndef __NO_STRICT_ALIGNMENT
2999 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t);
3000 #else
3001 sc->alc_buf_size = RX_BUF_SIZE_MAX;
3002 #endif
3003 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
3004
3005 paddr = sc->alc_rdata.alc_rr_ring_paddr;
3006 /* Set Rx return descriptor base addresses. */
3007 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3008 /* We use one Rx return ring. */
3009 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
3010 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
3011 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
3012 /* Set Rx return descriptor counter. */
3013 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
3014 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
3015 paddr = sc->alc_rdata.alc_cmb_paddr;
3016 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
3017 paddr = sc->alc_rdata.alc_smb_paddr;
3018 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3019 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
3020
3021 /* Tell hardware that we're ready to load DMA blocks. */
3022 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
3023
3024 /* Configure interrupt moderation timer. */
3025 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
3026 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
3027 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
3028 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3029 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
3030 /*
3031 * We don't want to automatic interrupt clear as task queue
3032 * for the interrupt should know interrupt status.
3033 */
3034 reg &= ~MASTER_INTR_RD_CLR;
3035 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
3036 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
3037 reg |= MASTER_IM_RX_TIMER_ENB;
3038 if (ALC_USECS(sc->alc_int_tx_mod) != 0)
3039 reg |= MASTER_IM_TX_TIMER_ENB;
3040 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3041 /*
3042 * Disable interrupt re-trigger timer. We don't want automatic
3043 * re-triggering of un-ACKed interrupts.
3044 */
3045 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
3046 /* Configure CMB. */
3047 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
3048 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3049 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
3050 else
3051 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
3052 /*
3053 * Hardware can be configured to issue SMB interrupt based
3054 * on programmed interval. Since there is a callout that is
3055 * invoked for every hz in driver we use that instead of
3056 * relying on periodic SMB interrupt.
3057 */
3058 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
3059 /* Clear MAC statistics. */
3060 alc_stats_clear(sc);
3061
3062 /*
3063 * Always use maximum frame size that controller can support.
3064 * Otherwise received frames that has larger frame length
3065 * than alc(4) MTU would be silently dropped in hardware. This
3066 * would make path-MTU discovery hard as sender wouldn't get
3067 * any responses from receiver. alc(4) supports
3068 * multi-fragmented frames on Rx path so it has no issue on
3069 * assembling fragmented frames. Using maximum frame size also
3070 * removes the need to reinitialize hardware when interface
3071 * MTU configuration was changed.
3072 *
3073 * Be conservative in what you do, be liberal in what you
3074 * accept from others - RFC 793.
3075 */
3076 CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN);
3077
3078 /* Disable header split(?) */
3079 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
3080
3081 /* Configure IPG/IFG parameters. */
3082 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
3083 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
3084 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
3085 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
3086 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
3087 /* Set parameters for half-duplex media. */
3088 CSR_WRITE_4(sc, ALC_HDPX_CFG,
3089 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
3090 HDPX_CFG_LCOL_MASK) |
3091 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
3092 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
3093 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
3094 HDPX_CFG_ABEBT_MASK) |
3095 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
3096 HDPX_CFG_JAMIPG_MASK));
3097 /*
3098 * Set TSO/checksum offload threshold. For frames that is
3099 * larger than this threshold, hardware wouldn't do
3100 * TSO/checksum offloading.
3101 */
3102 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
3103 (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
3104 TSO_OFFLOAD_THRESH_MASK);
3105 /* Configure TxQ. */
3106 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
3107 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
3108 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
3109 TXQ_CFG_TD_BURST_MASK;
3110 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
3111
3112 /* Configure Rx free descriptor pre-fetching. */
3113 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
3114 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) &
3115 RX_RD_FREE_THRESH_HI_MASK) |
3116 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) &
3117 RX_RD_FREE_THRESH_LO_MASK));
3118
3119 /*
3120 * Configure flow control parameters.
3121 * XON : 80% of Rx FIFO
3122 * XOFF : 30% of Rx FIFO
3123 */
3124 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3125 rxf_hi = (reg * 8) / 10;
3126 rxf_lo = (reg * 3)/ 10;
3127 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3128 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
3129 RX_FIFO_PAUSE_THRESH_LO_MASK) |
3130 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
3131 RX_FIFO_PAUSE_THRESH_HI_MASK));
3132
3133 /* Disable RSS until I understand L1C/L2C's RSS logic. */
3134 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
3135 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
3136
3137 /* Configure RxQ. */
3138 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
3139 RXQ_CFG_RD_BURST_MASK;
3140 reg |= RXQ_CFG_RSS_MODE_DIS;
3141 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
3142 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
3143 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3144
3145 /* Configure Rx DMAW request thresold. */
3146 CSR_WRITE_4(sc, ALC_RD_DMA_CFG,
3147 ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) &
3148 RD_DMA_CFG_THRESH_MASK) |
3149 ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) &
3150 RD_DMA_CFG_TIMER_MASK));
3151 /* Configure DMA parameters. */
3152 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
3153 reg |= sc->alc_rcb;
3154 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3155 reg |= DMA_CFG_CMB_ENB;
3156 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
3157 reg |= DMA_CFG_SMB_ENB;
3158 else
3159 reg |= DMA_CFG_SMB_DIS;
3160 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
3161 DMA_CFG_RD_BURST_SHIFT;
3162 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
3163 DMA_CFG_WR_BURST_SHIFT;
3164 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
3165 DMA_CFG_RD_DELAY_CNT_MASK;
3166 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
3167 DMA_CFG_WR_DELAY_CNT_MASK;
3168 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3169
3170 /*
3171 * Configure Tx/Rx MACs.
3172 * - Auto-padding for short frames.
3173 * - Enable CRC generation.
3174 * Actual reconfiguration of MAC for resolved speed/duplex
3175 * is followed after detection of link establishment.
3176 * AR8131/AR8132 always does checksum computation regardless
3177 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
3178 * have bug in protocol field in Rx return structure so
3179 * these controllers can't handle fragmented frames. Disable
3180 * Rx checksum offloading until there is a newer controller
3181 * that has sane implementation.
3182 */
3183 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
3184 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
3185 MAC_CFG_PREAMBLE_MASK);
3186 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
3187 reg |= MAC_CFG_SPEED_10_100;
3188 else
3189 reg |= MAC_CFG_SPEED_1000;
3190 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3191
3192 /* Set up the receive filter. */
3193 alc_rxfilter(sc);
3194 alc_rxvlan(sc);
3195
3196 /* Acknowledge all pending interrupts and clear it. */
3197 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
3198 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3199 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3200
3201 sc->alc_flags &= ~ALC_FLAG_LINK;
3202 /* Switch to the current media. */
3203 mii_mediachg(mii);
3204
3205 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3206
3207 ifp->if_flags |= IFF_RUNNING;
3208 ifp->if_flags &= ~IFF_OACTIVE;
3209 }
3210
3211 static void
3212 alc_stop(struct alc_softc *sc)
3213 {
3214 struct ifnet *ifp;
3215 struct alc_txdesc *txd;
3216 struct alc_rxdesc *rxd;
3217 uint32_t reg;
3218 int i;
3219
3220 ALC_LOCK_ASSERT(sc);
3221 /*
3222 * Mark the interface down and cancel the watchdog timer.
3223 */
3224 ifp = sc->alc_ifp;
3225 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3226 sc->alc_flags &= ~ALC_FLAG_LINK;
3227 callout_stop(&sc->alc_tick_ch);
3228 sc->alc_watchdog_timer = 0;
3229 alc_stats_update(sc);
3230 /* Disable interrupts. */
3231 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
3232 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3233 alc_stop_queue(sc);
3234 /* Disable DMA. */
3235 reg = CSR_READ_4(sc, ALC_DMA_CFG);
3236 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
3237 reg |= DMA_CFG_SMB_DIS;
3238 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3239 DELAY(1000);
3240 /* Stop Rx/Tx MACs. */
3241 alc_stop_mac(sc);
3242 /* Disable interrupts which might be touched in taskq handler. */
3243 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3244
3245 /* Reclaim Rx buffers that have been processed. */
3246 if (sc->alc_cdata.alc_rxhead != NULL)
3247 m_freem(sc->alc_cdata.alc_rxhead);
3248 ALC_RXCHAIN_RESET(sc);
3249 /*
3250 * Free Tx/Rx mbufs still in the queues.
3251 */
3252 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3253 rxd = &sc->alc_cdata.alc_rxdesc[i];
3254 if (rxd->rx_m != NULL) {
3255 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag,
3256 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3257 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag,
3258 rxd->rx_dmamap);
3259 m_freem(rxd->rx_m);
3260 rxd->rx_m = NULL;
3261 }
3262 }
3263 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3264 txd = &sc->alc_cdata.alc_txdesc[i];
3265 if (txd->tx_m != NULL) {
3266 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
3267 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3268 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
3269 txd->tx_dmamap);
3270 m_freem(txd->tx_m);
3271 txd->tx_m = NULL;
3272 }
3273 }
3274 }
3275
3276 static void
3277 alc_stop_mac(struct alc_softc *sc)
3278 {
3279 uint32_t reg;
3280 int i;
3281
3282 ALC_LOCK_ASSERT(sc);
3283
3284 /* Disable Rx/Tx MAC. */
3285 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3286 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
3287 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
3288 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3289 }
3290 for (i = ALC_TIMEOUT; i > 0; i--) {
3291 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3292 if (reg == 0)
3293 break;
3294 DELAY(10);
3295 }
3296 if (i == 0)
3297 device_printf(sc->alc_dev,
3298 "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
3299 }
3300
3301 static void
3302 alc_start_queue(struct alc_softc *sc)
3303 {
3304 uint32_t qcfg[] = {
3305 0,
3306 RXQ_CFG_QUEUE0_ENB,
3307 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
3308 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
3309 RXQ_CFG_ENB
3310 };
3311 uint32_t cfg;
3312
3313 ALC_LOCK_ASSERT(sc);
3314
3315 /* Enable RxQ. */
3316 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
3317 cfg &= ~RXQ_CFG_ENB;
3318 cfg |= qcfg[1];
3319 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
3320 /* Enable TxQ. */
3321 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
3322 cfg |= TXQ_CFG_ENB;
3323 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
3324 }
3325
3326 static void
3327 alc_stop_queue(struct alc_softc *sc)
3328 {
3329 uint32_t reg;
3330 int i;
3331
3332 ALC_LOCK_ASSERT(sc);
3333
3334 /* Disable RxQ. */
3335 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
3336 if ((reg & RXQ_CFG_ENB) != 0) {
3337 reg &= ~RXQ_CFG_ENB;
3338 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3339 }
3340 /* Disable TxQ. */
3341 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
3342 if ((reg & TXQ_CFG_ENB) == 0) {
3343 reg &= ~TXQ_CFG_ENB;
3344 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
3345 }
3346 for (i = ALC_TIMEOUT; i > 0; i--) {
3347 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3348 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3349 break;
3350 DELAY(10);
3351 }
3352 if (i == 0)
3353 device_printf(sc->alc_dev,
3354 "could not disable RxQ/TxQ (0x%08x)!\n", reg);
3355 }
3356
3357 static void
3358 alc_init_tx_ring(struct alc_softc *sc)
3359 {
3360 struct alc_ring_data *rd;
3361 struct alc_txdesc *txd;
3362 int i;
3363
3364 ALC_LOCK_ASSERT(sc);
3365
3366 sc->alc_cdata.alc_tx_prod = 0;
3367 sc->alc_cdata.alc_tx_cons = 0;
3368 sc->alc_cdata.alc_tx_cnt = 0;
3369
3370 rd = &sc->alc_rdata;
3371 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ);
3372 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3373 txd = &sc->alc_cdata.alc_txdesc[i];
3374 txd->tx_m = NULL;
3375 }
3376
3377 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3378 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
3379 }
3380
3381 static int
3382 alc_init_rx_ring(struct alc_softc *sc)
3383 {
3384 struct alc_ring_data *rd;
3385 struct alc_rxdesc *rxd;
3386 int i;
3387
3388 ALC_LOCK_ASSERT(sc);
3389
3390 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
3391 sc->alc_morework = 0;
3392 rd = &sc->alc_rdata;
3393 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ);
3394 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3395 rxd = &sc->alc_cdata.alc_rxdesc[i];
3396 rxd->rx_m = NULL;
3397 rxd->rx_desc = &rd->alc_rx_ring[i];
3398 if (alc_newbuf(sc, rxd) != 0)
3399 return (ENOBUFS);
3400 }
3401
3402 /*
3403 * Since controller does not update Rx descriptors, driver
3404 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
3405 * is enough to ensure coherence.
3406 */
3407 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3408 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
3409 /* Let controller know availability of new Rx buffers. */
3410 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
3411
3412 return (0);
3413 }
3414
3415 static void
3416 alc_init_rr_ring(struct alc_softc *sc)
3417 {
3418 struct alc_ring_data *rd;
3419
3420 ALC_LOCK_ASSERT(sc);
3421
3422 sc->alc_cdata.alc_rr_cons = 0;
3423 ALC_RXCHAIN_RESET(sc);
3424
3425 rd = &sc->alc_rdata;
3426 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ);
3427 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3428 sc->alc_cdata.alc_rr_ring_map,
3429 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3430 }
3431
3432 static void
3433 alc_init_cmb(struct alc_softc *sc)
3434 {
3435 struct alc_ring_data *rd;
3436
3437 ALC_LOCK_ASSERT(sc);
3438
3439 rd = &sc->alc_rdata;
3440 bzero(rd->alc_cmb, ALC_CMB_SZ);
3441 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map,
3442 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3443 }
3444
3445 static void
3446 alc_init_smb(struct alc_softc *sc)
3447 {
3448 struct alc_ring_data *rd;
3449
3450 ALC_LOCK_ASSERT(sc);
3451
3452 rd = &sc->alc_rdata;
3453 bzero(rd->alc_smb, ALC_SMB_SZ);
3454 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map,
3455 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3456 }
3457
3458 static void
3459 alc_rxvlan(struct alc_softc *sc)
3460 {
3461 struct ifnet *ifp;
3462 uint32_t reg;
3463
3464 ALC_LOCK_ASSERT(sc);
3465
3466 ifp = sc->alc_ifp;
3467 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3468 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3469 reg |= MAC_CFG_VLAN_TAG_STRIP;
3470 else
3471 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3472 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3473 }
3474
3475 static void
3476 alc_rxfilter(struct alc_softc *sc)
3477 {
3478 struct ifnet *ifp;
3479 struct ifmultiaddr *ifma;
3480 uint32_t crc;
3481 uint32_t mchash[2];
3482 uint32_t rxcfg;
3483
3484 ALC_LOCK_ASSERT(sc);
3485
3486 ifp = sc->alc_ifp;
3487
3488 bzero(mchash, sizeof(mchash));
3489 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
3490 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3491 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3492 rxcfg |= MAC_CFG_BCAST;
3493 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3494 if ((ifp->if_flags & IFF_PROMISC) != 0)
3495 rxcfg |= MAC_CFG_PROMISC;
3496 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3497 rxcfg |= MAC_CFG_ALLMULTI;
3498 mchash[0] = 0xFFFFFFFF;
3499 mchash[1] = 0xFFFFFFFF;
3500 goto chipit;
3501 }
3502
3503 #if 0
3504 /* XXX */
3505 if_maddr_rlock(ifp);
3506 #endif
3507 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) {
3508 if (ifma->ifma_addr->sa_family != AF_LINK)
3509 continue;
3510 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3511 ifma->ifma_addr), ETHER_ADDR_LEN);
3512 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3513 }
3514 #if 0
3515 /* XXX */
3516 if_maddr_runlock(ifp);
3517 #endif
3518
3519 chipit:
3520 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
3521 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
3522 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
3523 }
3524
3525 static int
3526 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)
3527 {
3528 return (sysctl_int_range(oidp, arg1, arg2, req,
3529 ALC_PROC_MIN, ALC_PROC_MAX));
3530 }
3531
3532 static int
3533 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)
3534 {
3535
3536 return (sysctl_int_range(oidp, arg1, arg2, req,
3537 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX));
3538 }
DragonFly BSD