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Add support for network devices found on Intel ICH9 hardware. I have one
[dragonfly.git] / sys / dev / netif / em / if_em_hw.c
blob4e969d38a50a588d22ce3220925a39084f07f67e
1 /*******************************************************************************
2 Copyright (c) 2001-2005, Intel Corporation
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 1. Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10
11 2. Redistributions in binary form must reproduce the above copyright
12 notice, this list of conditions and the following disclaimer in the
13 documentation and/or other materials provided with the distribution.
14
15 3. Neither the name of the Intel Corporation nor the names of its
16 contributors may be used to endorse or promote products derived from
17 this software without specific prior written permission.
18
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE.
30 *******************************************************************************/
31
32 /*$FreeBSD: src/sys/dev/em/if_em_hw.c,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/
33 /*$DragonFly: src/sys/dev/netif/em/if_em_hw.c,v 1.12 2008/01/10 10:44:28 matthias Exp $*/
34
35 /* if_em_hw.c
36 * Shared functions for accessing and configuring the MAC
37 */
38
39 #define STATIC static
40
41 #ifdef LM
42 #include "if_em_hw.h"
43 #else
44 #include <dev/netif/em/if_em_hw.h>
45 #endif
46
47 static int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);
48 static void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);
49 static int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data);
50 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
51 static int32_t em_get_software_semaphore(struct em_hw *hw);
52 static void em_release_software_semaphore(struct em_hw *hw);
53
54 static uint8_t em_arc_subsystem_valid(struct em_hw *hw);
55 static int32_t em_check_downshift(struct em_hw *hw);
56 static int32_t em_check_polarity(struct em_hw *hw, em_rev_polarity *polarity);
57 static void em_clear_vfta(struct em_hw *hw);
58 static int32_t em_commit_shadow_ram(struct em_hw *hw);
59 static int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
60 static int32_t em_config_fc_after_link_up(struct em_hw *hw);
61 static int32_t em_detect_gig_phy(struct em_hw *hw);
62 static int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank);
63 static int32_t em_get_auto_rd_done(struct em_hw *hw);
64 static int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length);
65 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw);
66 static int32_t em_get_phy_cfg_done(struct em_hw *hw);
67 static int32_t em_get_software_flag(struct em_hw *hw);
68 static int32_t em_ich8_cycle_init(struct em_hw *hw);
69 static int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout);
70 static int32_t em_id_led_init(struct em_hw *hw);
71 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
72 static int32_t em_init_lcd_from_nvm(struct em_hw *hw);
73 static void em_init_rx_addrs(struct em_hw *hw);
74 static void em_initialize_hardware_bits(struct em_hw *hw);
75 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw);
76 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw);
77 static int32_t em_mng_enable_host_if(struct em_hw *hw);
78 static int32_t em_mng_host_if_write(struct em_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
79 static int32_t em_mng_write_cmd_header(struct em_hw* hw, struct em_host_mng_command_header* hdr);
80 static int32_t em_mng_write_commit(struct em_hw *hw);
81 static int32_t em_phy_ife_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
82 static int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
83 static int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
84 static int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd);
86 static int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
87 static void em_put_hw_eeprom_semaphore(struct em_hw *hw);
88 static int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data);
89 static int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
90 static int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
91 static int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data);
92 static int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
93 static int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t data);
94 static int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
95 static int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
96 static void em_release_software_flag(struct em_hw *hw);
97 static int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
98 static int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active);
99 static int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);
100 static void em_set_pci_express_master_disable(struct em_hw *hw);
101 static int32_t em_wait_autoneg(struct em_hw *hw);
102 static void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
103 static int32_t em_set_phy_type(struct em_hw *hw);
104 static void em_phy_init_script(struct em_hw *hw);
105 static int32_t em_setup_copper_link(struct em_hw *hw);
106 static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
107 static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
108 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
109 static int32_t em_config_mac_to_phy(struct em_hw *hw);
110 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
111 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
112 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
113 uint16_t count);
114 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
115 static int32_t em_phy_reset_dsp(struct em_hw *hw);
116 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
117 uint16_t words, uint16_t *data);
118 static int32_t em_write_eeprom_microwire(struct em_hw *hw,
119 uint16_t offset, uint16_t words,
120 uint16_t *data);
121 static int32_t em_spi_eeprom_ready(struct em_hw *hw);
122 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
123 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
124 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
125 uint16_t count);
126 static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
127 uint16_t phy_data);
128 static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
129 uint16_t *phy_data);
130 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
131 static int32_t em_acquire_eeprom(struct em_hw *hw);
132 static void em_release_eeprom(struct em_hw *hw);
133 static void em_standby_eeprom(struct em_hw *hw);
134 static int32_t em_set_vco_speed(struct em_hw *hw);
135 static int32_t em_polarity_reversal_workaround(struct em_hw *hw);
136 static int32_t em_set_phy_mode(struct em_hw *hw);
137 static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer);
138 static uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length);
139 static int32_t em_configure_kmrn_for_10_100(struct em_hw *hw,
140 uint16_t duplex);
141 static int32_t em_configure_kmrn_for_1000(struct em_hw *hw);
142
143 /* IGP cable length table */
144 static const
145 uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
146 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
147 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
148 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
149 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
150 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
151 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
152 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
153 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
154
155 static const
156 uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
157 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
158 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
159 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
160 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
161 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
162 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
163 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
164 104, 109, 114, 118, 121, 124};
165
166 /******************************************************************************
167 * Set the phy type member in the hw struct.
168 *
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
171 STATIC int32_t
172 em_set_phy_type(struct em_hw *hw)
173 {
174 DEBUGFUNC("em_set_phy_type");
175
176 if (hw->mac_type == em_undefined)
177 return -E1000_ERR_PHY_TYPE;
178
179 switch (hw->phy_id) {
180 case M88E1000_E_PHY_ID:
181 case M88E1000_I_PHY_ID:
182 case M88E1011_I_PHY_ID:
183 case M88E1111_I_PHY_ID:
184 hw->phy_type = em_phy_m88;
185 break;
186 case IGP01E1000_I_PHY_ID:
187 if (hw->mac_type == em_82541 ||
188 hw->mac_type == em_82541_rev_2 ||
189 hw->mac_type == em_82547 ||
190 hw->mac_type == em_82547_rev_2) {
191 hw->phy_type = em_phy_igp;
192 break;
193 }
194 case IGP03E1000_E_PHY_ID:
195 hw->phy_type = em_phy_igp_3;
196 break;
197 case IFE_E_PHY_ID:
198 case IFE_PLUS_E_PHY_ID:
199 case IFE_C_E_PHY_ID:
200 hw->phy_type = em_phy_ife;
201 break;
202 case GG82563_E_PHY_ID:
203 if (hw->mac_type == em_80003es2lan) {
204 hw->phy_type = em_phy_gg82563;
205 break;
206 }
207 /* Fall Through */
208 default:
209 /* Should never have loaded on this device */
210 hw->phy_type = em_phy_undefined;
211 return -E1000_ERR_PHY_TYPE;
212 }
213
214 return E1000_SUCCESS;
215 }
216
217 /******************************************************************************
218 * IGP phy init script - initializes the GbE PHY
219 *
220 * hw - Struct containing variables accessed by shared code
221 *****************************************************************************/
222 static void
223 em_phy_init_script(struct em_hw *hw)
224 {
225 uint32_t ret_val;
226 uint16_t phy_saved_data;
227
228 DEBUGFUNC("em_phy_init_script");
229
230 if (hw->phy_init_script) {
231 msec_delay(20);
232
233 /* Save off the current value of register 0x2F5B to be restored at
234 * the end of this routine. */
235 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
236
237 /* Disabled the PHY transmitter */
238 em_write_phy_reg(hw, 0x2F5B, 0x0003);
239
240 msec_delay(20);
241
242 em_write_phy_reg(hw,0x0000,0x0140);
243
244 msec_delay(5);
245
246 switch (hw->mac_type) {
247 case em_82541:
248 case em_82547:
249 em_write_phy_reg(hw, 0x1F95, 0x0001);
250
251 em_write_phy_reg(hw, 0x1F71, 0xBD21);
252
253 em_write_phy_reg(hw, 0x1F79, 0x0018);
254
255 em_write_phy_reg(hw, 0x1F30, 0x1600);
256
257 em_write_phy_reg(hw, 0x1F31, 0x0014);
258
259 em_write_phy_reg(hw, 0x1F32, 0x161C);
260
261 em_write_phy_reg(hw, 0x1F94, 0x0003);
262
263 em_write_phy_reg(hw, 0x1F96, 0x003F);
264
265 em_write_phy_reg(hw, 0x2010, 0x0008);
266 break;
267
268 case em_82541_rev_2:
269 case em_82547_rev_2:
270 em_write_phy_reg(hw, 0x1F73, 0x0099);
271 break;
272 default:
273 break;
274 }
275
276 em_write_phy_reg(hw, 0x0000, 0x3300);
277
278 msec_delay(20);
279
280 /* Now enable the transmitter */
281 em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
282
283 if (hw->mac_type == em_82547) {
284 uint16_t fused, fine, coarse;
285
286 /* Move to analog registers page */
287 em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
288
289 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
290 em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
291
292 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
293 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
294
295 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
296 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
297 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
298 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
299 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
300
301 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
302 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
303 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
304
305 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
306 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
307 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
308 }
309 }
310 }
311 }
312
313 /******************************************************************************
314 * Set the mac type member in the hw struct.
315 *
316 * hw - Struct containing variables accessed by shared code
317 *****************************************************************************/
318 int32_t
319 em_set_mac_type(struct em_hw *hw)
320 {
321 DEBUGFUNC("em_set_mac_type");
322
323 switch (hw->device_id) {
324 case E1000_DEV_ID_82542:
325 switch (hw->revision_id) {
326 case E1000_82542_2_0_REV_ID:
327 hw->mac_type = em_82542_rev2_0;
328 break;
329 case E1000_82542_2_1_REV_ID:
330 hw->mac_type = em_82542_rev2_1;
331 break;
332 default:
333 /* Invalid 82542 revision ID */
334 return -E1000_ERR_MAC_TYPE;
335 }
336 break;
337 case E1000_DEV_ID_82543GC_FIBER:
338 case E1000_DEV_ID_82543GC_COPPER:
339 hw->mac_type = em_82543;
340 break;
341 case E1000_DEV_ID_82544EI_COPPER:
342 case E1000_DEV_ID_82544EI_FIBER:
343 case E1000_DEV_ID_82544GC_COPPER:
344 case E1000_DEV_ID_82544GC_LOM:
345 hw->mac_type = em_82544;
346 break;
347 case E1000_DEV_ID_82540EM:
348 case E1000_DEV_ID_82540EM_LOM:
349 case E1000_DEV_ID_82540EP:
350 case E1000_DEV_ID_82540EP_LOM:
351 case E1000_DEV_ID_82540EP_LP:
352 hw->mac_type = em_82540;
353 break;
354 case E1000_DEV_ID_82545EM_COPPER:
355 case E1000_DEV_ID_82545EM_FIBER:
356 hw->mac_type = em_82545;
357 break;
358 case E1000_DEV_ID_82545GM_COPPER:
359 case E1000_DEV_ID_82545GM_FIBER:
360 case E1000_DEV_ID_82545GM_SERDES:
361 hw->mac_type = em_82545_rev_3;
362 break;
363 case E1000_DEV_ID_82546EB_COPPER:
364 case E1000_DEV_ID_82546EB_FIBER:
365 case E1000_DEV_ID_82546EB_QUAD_COPPER:
366 hw->mac_type = em_82546;
367 break;
368 case E1000_DEV_ID_82546GB_COPPER:
369 case E1000_DEV_ID_82546GB_FIBER:
370 case E1000_DEV_ID_82546GB_SERDES:
371 case E1000_DEV_ID_82546GB_PCIE:
372 case E1000_DEV_ID_82546GB_QUAD_COPPER:
373 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
374 hw->mac_type = em_82546_rev_3;
375 break;
376 case E1000_DEV_ID_82541EI:
377 case E1000_DEV_ID_82541EI_MOBILE:
378 case E1000_DEV_ID_82541ER_LOM:
379 hw->mac_type = em_82541;
380 break;
381 case E1000_DEV_ID_82541ER:
382 case E1000_DEV_ID_82541GI:
383 case E1000_DEV_ID_82541GI_LF:
384 case E1000_DEV_ID_82541GI_MOBILE:
385 hw->mac_type = em_82541_rev_2;
386 break;
387 case E1000_DEV_ID_82547EI:
388 case E1000_DEV_ID_82547EI_MOBILE:
389 hw->mac_type = em_82547;
390 break;
391 case E1000_DEV_ID_82547GI:
392 hw->mac_type = em_82547_rev_2;
393 break;
394 case E1000_DEV_ID_82571EB_COPPER:
395 case E1000_DEV_ID_82571EB_FIBER:
396 case E1000_DEV_ID_82571EB_SERDES:
397 case E1000_DEV_ID_82571EB_QUAD_COPPER:
398 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
399 hw->mac_type = em_82571;
400 break;
401 case E1000_DEV_ID_82572EI_COPPER:
402 case E1000_DEV_ID_82572EI_FIBER:
403 case E1000_DEV_ID_82572EI_SERDES:
404 case E1000_DEV_ID_82572EI:
405 hw->mac_type = em_82572;
406 break;
407 case E1000_DEV_ID_82573E:
408 case E1000_DEV_ID_82573E_IAMT:
409 case E1000_DEV_ID_82573L:
410 hw->mac_type = em_82573;
411 break;
412 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
413 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
414 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
415 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
416 hw->mac_type = em_80003es2lan;
417 break;
418 case E1000_DEV_ID_ICH8_IGP_M_AMT:
419 case E1000_DEV_ID_ICH8_IGP_AMT:
420 case E1000_DEV_ID_ICH8_IGP_C:
421 case E1000_DEV_ID_ICH8_IFE:
422 case E1000_DEV_ID_ICH8_IFE_GT:
423 case E1000_DEV_ID_ICH8_IFE_G:
424 case E1000_DEV_ID_ICH8_IGP_M:
425 hw->mac_type = em_ich8lan;
426 break;
427 case E1000_DEV_ID_ICH9_IGP_AMT:
428 case E1000_DEV_ID_ICH9_IGP_C:
429 case E1000_DEV_ID_ICH9_IFE:
430 case E1000_DEV_ID_ICH9_IFE_GT:
431 case E1000_DEV_ID_ICH9_IFE_G:
432 hw->mac_type = em_ich9lan;
433 break;
434 default:
435 /* Should never have loaded on this device */
436 return -E1000_ERR_MAC_TYPE;
437 }
438
439 switch (hw->mac_type) {
440 case em_ich8lan:
441 case em_ich9lan:
442 hw->swfwhw_semaphore_present = TRUE;
443 hw->asf_firmware_present = TRUE;
444 break;
445 case em_80003es2lan:
446 hw->swfw_sync_present = TRUE;
447 /* fall through */
448 case em_82571:
449 case em_82572:
450 case em_82573:
451 hw->eeprom_semaphore_present = TRUE;
452 /* fall through */
453 case em_82541:
454 case em_82547:
455 case em_82541_rev_2:
456 case em_82547_rev_2:
457 hw->asf_firmware_present = TRUE;
458 break;
459 default:
460 break;
461 }
462
463 return E1000_SUCCESS;
464 }
465
466 /*****************************************************************************
467 * Set media type and TBI compatibility.
468 *
469 * hw - Struct containing variables accessed by shared code
470 * **************************************************************************/
471 void
472 em_set_media_type(struct em_hw *hw)
473 {
474 uint32_t status;
475
476 DEBUGFUNC("em_set_media_type");
477
478 if (hw->mac_type != em_82543) {
479 /* tbi_compatibility is only valid on 82543 */
480 hw->tbi_compatibility_en = FALSE;
481 }
482
483 switch (hw->device_id) {
484 case E1000_DEV_ID_82545GM_SERDES:
485 case E1000_DEV_ID_82546GB_SERDES:
486 case E1000_DEV_ID_82571EB_SERDES:
487 case E1000_DEV_ID_82572EI_SERDES:
488 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
489 hw->media_type = em_media_type_internal_serdes;
490 break;
491 default:
492 switch (hw->mac_type) {
493 case em_82542_rev2_0:
494 case em_82542_rev2_1:
495 hw->media_type = em_media_type_fiber;
496 break;
497 case em_ich8lan:
498 case em_ich9lan:
499 case em_82573:
500 /* The STATUS_TBIMODE bit is reserved or reused for the this
501 * device.
502 */
503 hw->media_type = em_media_type_copper;
504 break;
505 default:
506 status = E1000_READ_REG(hw, STATUS);
507 if (status & E1000_STATUS_TBIMODE) {
508 hw->media_type = em_media_type_fiber;
509 /* tbi_compatibility not valid on fiber */
510 hw->tbi_compatibility_en = FALSE;
511 } else {
512 hw->media_type = em_media_type_copper;
513 }
514 break;
515 }
516 }
517 }
518
519 /******************************************************************************
520 * Reset the transmit and receive units; mask and clear all interrupts.
521 *
522 * hw - Struct containing variables accessed by shared code
523 *****************************************************************************/
524 int32_t
525 em_reset_hw(struct em_hw *hw)
526 {
527 uint32_t ctrl;
528 uint32_t ctrl_ext;
529 uint32_t icr;
530 uint32_t manc;
531 uint32_t led_ctrl;
532 uint32_t timeout;
533 uint32_t extcnf_ctrl;
534 int32_t ret_val;
535
536 DEBUGFUNC("em_reset_hw");
537
538 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
539 if (hw->mac_type == em_82542_rev2_0) {
540 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
541 em_pci_clear_mwi(hw);
542 }
543
544 if (hw->bus_type == em_bus_type_pci_express) {
545 /* Prevent the PCI-E bus from sticking if there is no TLP connection
546 * on the last TLP read/write transaction when MAC is reset.
547 */
548 if (em_disable_pciex_master(hw) != E1000_SUCCESS) {
549 DEBUGOUT("PCI-E Master disable polling has failed.\n");
550 }
551 }
552
553 /* Clear interrupt mask to stop board from generating interrupts */
554 DEBUGOUT("Masking off all interrupts\n");
555 E1000_WRITE_REG(hw, IMC, 0xffffffff);
556
557 /* Disable the Transmit and Receive units. Then delay to allow
558 * any pending transactions to complete before we hit the MAC with
559 * the global reset.
560 */
561 E1000_WRITE_REG(hw, RCTL, 0);
562 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
563 E1000_WRITE_FLUSH(hw);
564
565 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
566 hw->tbi_compatibility_on = FALSE;
567
568 /* Delay to allow any outstanding PCI transactions to complete before
569 * resetting the device
570 */
571 msec_delay(10);
572
573 ctrl = E1000_READ_REG(hw, CTRL);
574
575 /* Must reset the PHY before resetting the MAC */
576 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
577 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
578 msec_delay(5);
579 }
580
581 /* Must acquire the MDIO ownership before MAC reset.
582 * Ownership defaults to firmware after a reset. */
583 if (hw->mac_type == em_82573) {
584 timeout = 10;
585
586 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
587 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
588
589 do {
590 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
591 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
592
593 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
594 break;
595 else
596 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
597
598 msec_delay(2);
599 timeout--;
600 } while (timeout);
601 }
602
603 /* Workaround for ICH8 bit corruption issue in FIFO memory */
604 if (hw->mac_type == em_ich8lan) {
605 /* Set Tx and Rx buffer allocation to 8k apiece. */
606 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
607 /* Set Packet Buffer Size to 16k. */
608 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
609 }
610
611 /* Issue a global reset to the MAC. This will reset the chip's
612 * transmit, receive, DMA, and link units. It will not effect
613 * the current PCI configuration. The global reset bit is self-
614 * clearing, and should clear within a microsecond.
615 */
616 DEBUGOUT("Issuing a global reset to MAC\n");
617
618 switch (hw->mac_type) {
619 case em_82544:
620 case em_82540:
621 case em_82545:
622 case em_82546:
623 case em_82541:
624 case em_82541_rev_2:
625 /* These controllers can't ack the 64-bit write when issuing the
626 * reset, so use IO-mapping as a workaround to issue the reset */
627 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
628 break;
629 case em_82545_rev_3:
630 case em_82546_rev_3:
631 /* Reset is performed on a shadow of the control register */
632 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
633 break;
634 case em_ich8lan:
635 case em_ich9lan:
636 if (!hw->phy_reset_disable &&
637 em_check_phy_reset_block(hw) == E1000_SUCCESS) {
638 /* em_ich8lan PHY HW reset requires MAC CORE reset
639 * at the same time to make sure the interface between
640 * MAC and the external PHY is reset.
641 */
642 ctrl |= E1000_CTRL_PHY_RST;
643 }
644
645 em_get_software_flag(hw);
646 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
647 msec_delay(5);
648 break;
649 default:
650 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
651 break;
652 }
653
654 /* After MAC reset, force reload of EEPROM to restore power-on settings to
655 * device. Later controllers reload the EEPROM automatically, so just wait
656 * for reload to complete.
657 */
658 switch (hw->mac_type) {
659 case em_82542_rev2_0:
660 case em_82542_rev2_1:
661 case em_82543:
662 case em_82544:
663 /* Wait for reset to complete */
664 usec_delay(10);
665 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
666 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
667 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
668 E1000_WRITE_FLUSH(hw);
669 /* Wait for EEPROM reload */
670 msec_delay(2);
671 break;
672 case em_82541:
673 case em_82541_rev_2:
674 case em_82547:
675 case em_82547_rev_2:
676 /* Wait for EEPROM reload */
677 msec_delay(20);
678 break;
679 case em_82573:
680 if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
681 usec_delay(10);
682 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
683 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
684 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
685 E1000_WRITE_FLUSH(hw);
686 }
687 /* fall through */
688 default:
689 /* Auto read done will delay 5ms or poll based on mac type */
690 ret_val = em_get_auto_rd_done(hw);
691 if (ret_val)
692 return ret_val;
693 break;
694 }
695
696 /* Disable HW ARPs on ASF enabled adapters */
697 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) {
698 manc = E1000_READ_REG(hw, MANC);
699 manc &= ~(E1000_MANC_ARP_EN);
700 E1000_WRITE_REG(hw, MANC, manc);
701 }
702
703 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
704 em_phy_init_script(hw);
705
706 /* Configure activity LED after PHY reset */
707 led_ctrl = E1000_READ_REG(hw, LEDCTL);
708 led_ctrl &= IGP_ACTIVITY_LED_MASK;
709 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
710 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
711 }
712
713 /* Clear interrupt mask to stop board from generating interrupts */
714 DEBUGOUT("Masking off all interrupts\n");
715 E1000_WRITE_REG(hw, IMC, 0xffffffff);
716
717 /* Clear any pending interrupt events. */
718 icr = E1000_READ_REG(hw, ICR);
719
720 /* If MWI was previously enabled, reenable it. */
721 if (hw->mac_type == em_82542_rev2_0) {
722 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
723 em_pci_set_mwi(hw);
724 }
725
726 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
727 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
728 kab |= E1000_KABGTXD_BGSQLBIAS;
729 E1000_WRITE_REG(hw, KABGTXD, kab);
730 }
731
732 return E1000_SUCCESS;
733 }
734
735 /******************************************************************************
736 *
737 * Initialize a number of hardware-dependent bits
738 *
739 * hw: Struct containing variables accessed by shared code
740 *
741 *****************************************************************************/
742 STATIC void
743 em_initialize_hardware_bits(struct em_hw *hw)
744 {
745 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
746 /* Settings common to all silicon */
747 uint32_t reg_ctrl, reg_ctrl_ext;
748 uint32_t reg_tarc0, reg_tarc1;
749 uint32_t reg_tctl;
750 uint32_t reg_txdctl, reg_txdctl1;
751
752 reg_tarc0 = E1000_READ_REG(hw, TARC0);
753 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 27 */
754
755 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
756 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */
757 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
758
759 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
760 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */
761 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
762
763 switch (hw->mac_type) {
764 case em_82571:
765 case em_82572:
766 reg_tarc1 = E1000_READ_REG(hw, TARC1);
767 reg_tctl = E1000_READ_REG(hw, TCTL);
768
769 /* Set the phy Tx compatible mode bits */
770 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */
771
772 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */
773 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */
774
775 if (reg_tctl & E1000_TCTL_MULR)
776 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */
777 else
778 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */
779
780 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
781 break;
782 case em_82573:
783 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
784 reg_ctrl = E1000_READ_REG(hw, CTRL);
785
786 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */
787 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
788 reg_ctrl &= ~0x20000000; /* Clear bit 29 */
789
790 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
791 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
792 break;
793 case em_80003es2lan:
794 if ((hw->media_type == em_media_type_fiber) ||
795 (hw->media_type == em_media_type_internal_serdes)) {
796 reg_tarc0 &= ~0x00100000; /* Clear bit 20 */
797 }
798
799 reg_tctl = E1000_READ_REG(hw, TCTL);
800 reg_tarc1 = E1000_READ_REG(hw, TARC1);
801 if (reg_tctl & E1000_TCTL_MULR)
802 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */
803 else
804 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */
805
806 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
807 break;
808 case em_ich8lan:
809 case em_ich9lan:
810 if ((hw->revision_id < 3) ||
811 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
812 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
813 reg_tarc0 |= 0x30000000; /* Set TARC0 bits 29 and 28 */
814 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
815 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
816 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
817
818 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 24, 26, 27 */
819
820 reg_tarc1 = E1000_READ_REG(hw, TARC1);
821 reg_tctl = E1000_READ_REG(hw, TCTL);
822
823 if (reg_tctl & E1000_TCTL_MULR)
824 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */
825 else
826 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */
827
828 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 30 */
829
830 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
831 break;
832 default:
833 break;
834 }
835
836 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
837 }
838 }
839
840 /******************************************************************************
841 * Performs basic configuration of the adapter.
842 *
843 * hw - Struct containing variables accessed by shared code
844 *
845 * Assumes that the controller has previously been reset and is in a
846 * post-reset uninitialized state. Initializes the receive address registers,
847 * multicast table, and VLAN filter table. Calls routines to setup link
848 * configuration and flow control settings. Clears all on-chip counters. Leaves
849 * the transmit and receive units disabled and uninitialized.
850 *****************************************************************************/
851 int32_t
852 em_init_hw(struct em_hw *hw)
853 {
854 uint32_t ctrl;
855 uint32_t i;
856 int32_t ret_val;
857 uint16_t pcix_cmd_word;
858 uint16_t pcix_stat_hi_word;
859 uint16_t cmd_mmrbc;
860 uint16_t stat_mmrbc;
861 uint32_t mta_size;
862 uint32_t reg_data;
863 uint32_t ctrl_ext;
864
865 DEBUGFUNC("em_init_hw");
866
867 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
868 if ((hw->mac_type == em_ich8lan) &&
869 ((hw->revision_id < 3) ||
870 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
871 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
872 reg_data = E1000_READ_REG(hw, STATUS);
873 reg_data &= ~0x80000000;
874 E1000_WRITE_REG(hw, STATUS, reg_data);
875 }
876 /* Initialize Identification LED */
877 ret_val = em_id_led_init(hw);
878 if (ret_val) {
879 DEBUGOUT("Error Initializing Identification LED\n");
880 return ret_val;
881 }
882
883 /* Set the media type and TBI compatibility */
884 em_set_media_type(hw);
885
886 /* Disabling VLAN filtering. */
887 DEBUGOUT("Initializing the IEEE VLAN\n");
888 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
889 if (hw->mac_type != em_ich8lan) {
890 if (hw->mac_type < em_82545_rev_3)
891 E1000_WRITE_REG(hw, VET, 0);
892 em_clear_vfta(hw);
893 }
894
895 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
896 if (hw->mac_type == em_82542_rev2_0) {
897 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
898 em_pci_clear_mwi(hw);
899 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
900 E1000_WRITE_FLUSH(hw);
901 msec_delay(5);
902 }
903
904 /* Setup the receive address. This involves initializing all of the Receive
905 * Address Registers (RARs 0 - 15).
906 */
907 em_init_rx_addrs(hw);
908
909 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
910 if (hw->mac_type == em_82542_rev2_0) {
911 E1000_WRITE_REG(hw, RCTL, 0);
912 E1000_WRITE_FLUSH(hw);
913 msec_delay(1);
914 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
915 em_pci_set_mwi(hw);
916 }
917
918 /* Zero out the Multicast HASH table */
919 DEBUGOUT("Zeroing the MTA\n");
920 mta_size = E1000_MC_TBL_SIZE;
921 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
922 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
923 for (i = 0; i < mta_size; i++) {
924 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
925 /* use write flush to prevent Memory Write Block (MWB) from
926 * occuring when accessing our register space */
927 E1000_WRITE_FLUSH(hw);
928 }
929
930 /* Set the PCI priority bit correctly in the CTRL register. This
931 * determines if the adapter gives priority to receives, or if it
932 * gives equal priority to transmits and receives. Valid only on
933 * 82542 and 82543 silicon.
934 */
935 if (hw->dma_fairness && hw->mac_type <= em_82543) {
936 ctrl = E1000_READ_REG(hw, CTRL);
937 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
938 }
939
940 switch (hw->mac_type) {
941 case em_82545_rev_3:
942 case em_82546_rev_3:
943 break;
944 default:
945 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
946 if (hw->bus_type == em_bus_type_pcix) {
947 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
948 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
949 &pcix_stat_hi_word);
950 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
951 PCIX_COMMAND_MMRBC_SHIFT;
952 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
953 PCIX_STATUS_HI_MMRBC_SHIFT;
954 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
955 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
956 if (cmd_mmrbc > stat_mmrbc) {
957 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
958 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
959 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
960 &pcix_cmd_word);
961 }
962 }
963 break;
964 }
965
966 /* More time needed for PHY to initialize */
967 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
968 msec_delay(15);
969
970 /* Call a subroutine to configure the link and setup flow control. */
971 ret_val = em_setup_link(hw);
972
973 /* Set the transmit descriptor write-back policy */
974 if (hw->mac_type > em_82544) {
975 ctrl = E1000_READ_REG(hw, TXDCTL);
976 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
977 E1000_WRITE_REG(hw, TXDCTL, ctrl);
978 }
979
980 if (hw->mac_type == em_82573) {
981 em_enable_tx_pkt_filtering(hw);
982 }
983
984 switch (hw->mac_type) {
985 default:
986 break;
987 case em_80003es2lan:
988 /* Enable retransmit on late collisions */
989 reg_data = E1000_READ_REG(hw, TCTL);
990 reg_data |= E1000_TCTL_RTLC;
991 E1000_WRITE_REG(hw, TCTL, reg_data);
992
993 /* Configure Gigabit Carry Extend Padding */
994 reg_data = E1000_READ_REG(hw, TCTL_EXT);
995 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
996 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
997 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
998
999 /* Configure Transmit Inter-Packet Gap */
1000 reg_data = E1000_READ_REG(hw, TIPG);
1001 reg_data &= ~E1000_TIPG_IPGT_MASK;
1002 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1003 E1000_WRITE_REG(hw, TIPG, reg_data);
1004
1005 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1006 reg_data &= ~0x00100000;
1007 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1008 /* Fall through */
1009 case em_82571:
1010 case em_82572:
1011 case em_ich9lan:
1012 case em_ich8lan:
1013 ctrl = E1000_READ_REG(hw, TXDCTL1);
1014 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1015 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1016 break;
1017 }
1018
1019
1020 if (hw->mac_type == em_82573) {
1021 uint32_t gcr = E1000_READ_REG(hw, GCR);
1022 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1023 E1000_WRITE_REG(hw, GCR, gcr);
1024 }
1025
1026 /* Clear all of the statistics registers (clear on read). It is
1027 * important that we do this after we have tried to establish link
1028 * because the symbol error count will increment wildly if there
1029 * is no link.
1030 */
1031 em_clear_hw_cntrs(hw);
1032
1033 /* ICH8 No-snoop bits are opposite polarity.
1034 * Set to snoop by default after reset. */
1035 if (hw->mac_type == em_ich8lan)
1036 em_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1037
1038 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1039 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1040 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1041 /* Relaxed ordering must be disabled to avoid a parity
1042 * error crash in a PCI slot. */
1043 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1044 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1045 }
1046
1047 /* Must be called after em_set_media_type because media_type is used */
1048 em_initialize_hardware_bits(hw);
1049
1050 return ret_val;
1051 }
1052
1053 /******************************************************************************
1054 * Adjust SERDES output amplitude based on EEPROM setting.
1055 *
1056 * hw - Struct containing variables accessed by shared code.
1057 *****************************************************************************/
1058 static int32_t
1059 em_adjust_serdes_amplitude(struct em_hw *hw)
1060 {
1061 uint16_t eeprom_data;
1062 int32_t ret_val;
1063
1064 DEBUGFUNC("em_adjust_serdes_amplitude");
1065
1066 if (hw->media_type != em_media_type_internal_serdes)
1067 return E1000_SUCCESS;
1068
1069 switch (hw->mac_type) {
1070 case em_82545_rev_3:
1071 case em_82546_rev_3:
1072 break;
1073 default:
1074 return E1000_SUCCESS;
1075 }
1076
1077 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1078 if (ret_val) {
1079 return ret_val;
1080 }
1081
1082 if (eeprom_data != EEPROM_RESERVED_WORD) {
1083 /* Adjust SERDES output amplitude only. */
1084 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1085 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1086 if (ret_val)
1087 return ret_val;
1088 }
1089
1090 return E1000_SUCCESS;
1091 }
1092
1093 /******************************************************************************
1094 * Configures flow control and link settings.
1095 *
1096 * hw - Struct containing variables accessed by shared code
1097 *
1098 * Determines which flow control settings to use. Calls the apropriate media-
1099 * specific link configuration function. Configures the flow control settings.
1100 * Assuming the adapter has a valid link partner, a valid link should be
1101 * established. Assumes the hardware has previously been reset and the
1102 * transmitter and receiver are not enabled.
1103 *****************************************************************************/
1104 int32_t
1105 em_setup_link(struct em_hw *hw)
1106 {
1107 uint32_t ctrl_ext;
1108 int32_t ret_val;
1109 uint16_t eeprom_data;
1110
1111 DEBUGFUNC("em_setup_link");
1112
1113 /* In the case of the phy reset being blocked, we already have a link.
1114 * We do not have to set it up again. */
1115 if (em_check_phy_reset_block(hw))
1116 return E1000_SUCCESS;
1117
1118 /* Read and store word 0x0F of the EEPROM. This word contains bits
1119 * that determine the hardware's default PAUSE (flow control) mode,
1120 * a bit that determines whether the HW defaults to enabling or
1121 * disabling auto-negotiation, and the direction of the
1122 * SW defined pins. If there is no SW over-ride of the flow
1123 * control setting, then the variable hw->fc will
1124 * be initialized based on a value in the EEPROM.
1125 */
1126 if (hw->fc == E1000_FC_DEFAULT) {
1127 switch (hw->mac_type) {
1128 case em_ich8lan:
1129 case em_ich9lan:
1130 case em_82573:
1131 hw->fc = E1000_FC_FULL;
1132 break;
1133 default:
1134 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1135 1, &eeprom_data);
1136 if (ret_val) {
1137 DEBUGOUT("EEPROM Read Error\n");
1138 return -E1000_ERR_EEPROM;
1139 }
1140 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1141 hw->fc = E1000_FC_NONE;
1142 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1143 EEPROM_WORD0F_ASM_DIR)
1144 hw->fc = E1000_FC_TX_PAUSE;
1145 else
1146 hw->fc = E1000_FC_FULL;
1147 break;
1148 }
1149 }
1150
1151 /* We want to save off the original Flow Control configuration just
1152 * in case we get disconnected and then reconnected into a different
1153 * hub or switch with different Flow Control capabilities.
1154 */
1155 if (hw->mac_type == em_82542_rev2_0)
1156 hw->fc &= (~E1000_FC_TX_PAUSE);
1157
1158 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
1159 hw->fc &= (~E1000_FC_RX_PAUSE);
1160
1161 hw->original_fc = hw->fc;
1162
1163 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1164
1165 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1166 * polarity value for the SW controlled pins, and setup the
1167 * Extended Device Control reg with that info.
1168 * This is needed because one of the SW controlled pins is used for
1169 * signal detection. So this should be done before em_setup_pcs_link()
1170 * or em_phy_setup() is called.
1171 */
1172 if (hw->mac_type == em_82543) {
1173 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1174 1, &eeprom_data);
1175 if (ret_val) {
1176 DEBUGOUT("EEPROM Read Error\n");
1177 return -E1000_ERR_EEPROM;
1178 }
1179 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1180 SWDPIO__EXT_SHIFT);
1181 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1182 }
1183
1184 /* Call the necessary subroutine to configure the link. */
1185 ret_val = (hw->media_type == em_media_type_copper) ?
1186 em_setup_copper_link(hw) :
1187 em_setup_fiber_serdes_link(hw);
1188
1189 /* Initialize the flow control address, type, and PAUSE timer
1190 * registers to their default values. This is done even if flow
1191 * control is disabled, because it does not hurt anything to
1192 * initialize these registers.
1193 */
1194 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1195
1196 /* FCAL/H and FCT are hardcoded to standard values in em_ich8lan. */
1197 if (hw->mac_type != em_ich8lan) {
1198 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1199 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1200 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1201 }
1202
1203 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1204
1205 /* Set the flow control receive threshold registers. Normally,
1206 * these registers will be set to a default threshold that may be
1207 * adjusted later by the driver's runtime code. However, if the
1208 * ability to transmit pause frames in not enabled, then these
1209 * registers will be set to 0.
1210 */
1211 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1212 E1000_WRITE_REG(hw, FCRTL, 0);
1213 E1000_WRITE_REG(hw, FCRTH, 0);
1214 } else {
1215 /* We need to set up the Receive Threshold high and low water marks
1216 * as well as (optionally) enabling the transmission of XON frames.
1217 */
1218 if (hw->fc_send_xon) {
1219 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1220 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1221 } else {
1222 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1223 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1224 }
1225 }
1226 return ret_val;
1227 }
1228
1229 /******************************************************************************
1230 * Sets up link for a fiber based or serdes based adapter
1231 *
1232 * hw - Struct containing variables accessed by shared code
1233 *
1234 * Manipulates Physical Coding Sublayer functions in order to configure
1235 * link. Assumes the hardware has been previously reset and the transmitter
1236 * and receiver are not enabled.
1237 *****************************************************************************/
1238 static int32_t
1239 em_setup_fiber_serdes_link(struct em_hw *hw)
1240 {
1241 uint32_t ctrl;
1242 uint32_t status;
1243 uint32_t txcw = 0;
1244 uint32_t i;
1245 uint32_t signal = 0;
1246 int32_t ret_val;
1247
1248 DEBUGFUNC("em_setup_fiber_serdes_link");
1249
1250 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1251 * until explicitly turned off or a power cycle is performed. A read to
1252 * the register does not indicate its status. Therefore, we ensure
1253 * loopback mode is disabled during initialization.
1254 */
1255 if (hw->mac_type == em_82571 || hw->mac_type == em_82572)
1256 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1257
1258 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1259 * set when the optics detect a signal. On older adapters, it will be
1260 * cleared when there is a signal. This applies to fiber media only.
1261 * If we're on serdes media, adjust the output amplitude to value
1262 * set in the EEPROM.
1263 */
1264 ctrl = E1000_READ_REG(hw, CTRL);
1265 if (hw->media_type == em_media_type_fiber)
1266 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
1267
1268 ret_val = em_adjust_serdes_amplitude(hw);
1269 if (ret_val)
1270 return ret_val;
1271
1272 /* Take the link out of reset */
1273 ctrl &= ~(E1000_CTRL_LRST);
1274
1275 /* Adjust VCO speed to improve BER performance */
1276 ret_val = em_set_vco_speed(hw);
1277 if (ret_val)
1278 return ret_val;
1279
1280 em_config_collision_dist(hw);
1281
1282 /* Check for a software override of the flow control settings, and setup
1283 * the device accordingly. If auto-negotiation is enabled, then software
1284 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1285 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1286 * auto-negotiation is disabled, then software will have to manually
1287 * configure the two flow control enable bits in the CTRL register.
1288 *
1289 * The possible values of the "fc" parameter are:
1290 * 0: Flow control is completely disabled
1291 * 1: Rx flow control is enabled (we can receive pause frames, but
1292 * not send pause frames).
1293 * 2: Tx flow control is enabled (we can send pause frames but we do
1294 * not support receiving pause frames).
1295 * 3: Both Rx and TX flow control (symmetric) are enabled.
1296 */
1297 switch (hw->fc) {
1298 case E1000_FC_NONE:
1299 /* Flow control is completely disabled by a software over-ride. */
1300 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1301 break;
1302 case E1000_FC_RX_PAUSE:
1303 /* RX Flow control is enabled and TX Flow control is disabled by a
1304 * software over-ride. Since there really isn't a way to advertise
1305 * that we are capable of RX Pause ONLY, we will advertise that we
1306 * support both symmetric and asymmetric RX PAUSE. Later, we will
1307 * disable the adapter's ability to send PAUSE frames.
1308 */
1309 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1310 break;
1311 case E1000_FC_TX_PAUSE:
1312 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1313 * software over-ride.
1314 */
1315 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1316 break;
1317 case E1000_FC_FULL:
1318 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1319 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1320 break;
1321 default:
1322 DEBUGOUT("Flow control param set incorrectly\n");
1323 return -E1000_ERR_CONFIG;
1324 break;
1325 }
1326
1327 /* Since auto-negotiation is enabled, take the link out of reset (the link
1328 * will be in reset, because we previously reset the chip). This will
1329 * restart auto-negotiation. If auto-neogtiation is successful then the
1330 * link-up status bit will be set and the flow control enable bits (RFCE
1331 * and TFCE) will be set according to their negotiated value.
1332 */
1333 DEBUGOUT("Auto-negotiation enabled\n");
1334
1335 E1000_WRITE_REG(hw, TXCW, txcw);
1336 E1000_WRITE_REG(hw, CTRL, ctrl);
1337 E1000_WRITE_FLUSH(hw);
1338
1339 hw->txcw = txcw;
1340 msec_delay(1);
1341
1342 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1343 * indication in the Device Status Register. Time-out if a link isn't
1344 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1345 * less than 500 milliseconds even if the other end is doing it in SW).
1346 * For internal serdes, we just assume a signal is present, then poll.
1347 */
1348 if (hw->media_type == em_media_type_internal_serdes ||
1349 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1350 DEBUGOUT("Looking for Link\n");
1351 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1352 msec_delay(10);
1353 status = E1000_READ_REG(hw, STATUS);
1354 if (status & E1000_STATUS_LU) break;
1355 }
1356 if (i == (LINK_UP_TIMEOUT / 10)) {
1357 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1358 hw->autoneg_failed = 1;
1359 /* AutoNeg failed to achieve a link, so we'll call
1360 * em_check_for_link. This routine will force the link up if
1361 * we detect a signal. This will allow us to communicate with
1362 * non-autonegotiating link partners.
1363 */
1364 ret_val = em_check_for_link(hw);
1365 if (ret_val) {
1366 DEBUGOUT("Error while checking for link\n");
1367 return ret_val;
1368 }
1369 hw->autoneg_failed = 0;
1370 } else {
1371 hw->autoneg_failed = 0;
1372 DEBUGOUT("Valid Link Found\n");
1373 }
1374 } else {
1375 DEBUGOUT("No Signal Detected\n");
1376 }
1377 return E1000_SUCCESS;
1378 }
1379
1380 /******************************************************************************
1381 * Make sure we have a valid PHY and change PHY mode before link setup.
1382 *
1383 * hw - Struct containing variables accessed by shared code
1384 ******************************************************************************/
1385 static int32_t
1386 em_copper_link_preconfig(struct em_hw *hw)
1387 {
1388 uint32_t ctrl;
1389 int32_t ret_val;
1390 uint16_t phy_data;
1391
1392 DEBUGFUNC("em_copper_link_preconfig");
1393
1394 ctrl = E1000_READ_REG(hw, CTRL);
1395 /* With 82543, we need to force speed and duplex on the MAC equal to what
1396 * the PHY speed and duplex configuration is. In addition, we need to
1397 * perform a hardware reset on the PHY to take it out of reset.
1398 */
1399 if (hw->mac_type > em_82543) {
1400 ctrl |= E1000_CTRL_SLU;
1401 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1402 E1000_WRITE_REG(hw, CTRL, ctrl);
1403 } else {
1404 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1405 E1000_WRITE_REG(hw, CTRL, ctrl);
1406 ret_val = em_phy_hw_reset(hw);
1407 if (ret_val)
1408 return ret_val;
1409 }
1410
1411 /* Make sure we have a valid PHY */
1412 ret_val = em_detect_gig_phy(hw);
1413 if (ret_val) {
1414 DEBUGOUT("Error, did not detect valid phy.\n");
1415 return ret_val;
1416 }
1417 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1418
1419 /* Set PHY to class A mode (if necessary) */
1420 ret_val = em_set_phy_mode(hw);
1421 if (ret_val)
1422 return ret_val;
1423
1424 if ((hw->mac_type == em_82545_rev_3) ||
1425 (hw->mac_type == em_82546_rev_3)) {
1426 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1427 phy_data |= 0x00000008;
1428 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1429 }
1430
1431 if (hw->mac_type <= em_82543 ||
1432 hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
1433 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
1434 hw->phy_reset_disable = FALSE;
1435
1436 return E1000_SUCCESS;
1437 }
1438
1439
1440 /********************************************************************
1441 * Copper link setup for em_phy_igp series.
1442 *
1443 * hw - Struct containing variables accessed by shared code
1444 *********************************************************************/
1445 static int32_t
1446 em_copper_link_igp_setup(struct em_hw *hw)
1447 {
1448 uint32_t led_ctrl;
1449 int32_t ret_val;
1450 uint16_t phy_data;
1451
1452 DEBUGFUNC("em_copper_link_igp_setup");
1453
1454 if (hw->phy_reset_disable)
1455 return E1000_SUCCESS;
1456
1457 ret_val = em_phy_reset(hw);
1458 if (ret_val) {
1459 DEBUGOUT("Error Resetting the PHY\n");
1460 return ret_val;
1461 }
1462
1463 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1464 msec_delay(15);
1465 if (hw->mac_type != em_ich8lan) {
1466 /* Configure activity LED after PHY reset */
1467 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1468 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1469 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1470 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1471 }
1472
1473 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1474 if (hw->phy_type == em_phy_igp) {
1475 /* disable lplu d3 during driver init */
1476 ret_val = em_set_d3_lplu_state(hw, FALSE);
1477 if (ret_val) {
1478 DEBUGOUT("Error Disabling LPLU D3\n");
1479 return ret_val;
1480 }
1481 }
1482
1483 /* disable lplu d0 during driver init */
1484 ret_val = em_set_d0_lplu_state(hw, FALSE);
1485 if (ret_val) {
1486 DEBUGOUT("Error Disabling LPLU D0\n");
1487 return ret_val;
1488 }
1489 /* Configure mdi-mdix settings */
1490 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1491 if (ret_val)
1492 return ret_val;
1493
1494 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1495 hw->dsp_config_state = em_dsp_config_disabled;
1496 /* Force MDI for earlier revs of the IGP PHY */
1497 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1498 hw->mdix = 1;
1499
1500 } else {
1501 hw->dsp_config_state = em_dsp_config_enabled;
1502 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1503
1504 switch (hw->mdix) {
1505 case 1:
1506 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1507 break;
1508 case 2:
1509 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1510 break;
1511 case 0:
1512 default:
1513 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1514 break;
1515 }
1516 }
1517 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1518 if (ret_val)
1519 return ret_val;
1520
1521 /* set auto-master slave resolution settings */
1522 if (hw->autoneg) {
1523 em_ms_type phy_ms_setting = hw->master_slave;
1524
1525 if (hw->ffe_config_state == em_ffe_config_active)
1526 hw->ffe_config_state = em_ffe_config_enabled;
1527
1528 if (hw->dsp_config_state == em_dsp_config_activated)
1529 hw->dsp_config_state = em_dsp_config_enabled;
1530
1531 /* when autonegotiation advertisment is only 1000Mbps then we
1532 * should disable SmartSpeed and enable Auto MasterSlave
1533 * resolution as hardware default. */
1534 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1535 /* Disable SmartSpeed */
1536 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1537 &phy_data);
1538 if (ret_val)
1539 return ret_val;
1540 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1541 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1542 phy_data);
1543 if (ret_val)
1544 return ret_val;
1545 /* Set auto Master/Slave resolution process */
1546 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1547 if (ret_val)
1548 return ret_val;
1549 phy_data &= ~CR_1000T_MS_ENABLE;
1550 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1551 if (ret_val)
1552 return ret_val;
1553 }
1554
1555 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1556 if (ret_val)
1557 return ret_val;
1558
1559 /* load defaults for future use */
1560 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1561 ((phy_data & CR_1000T_MS_VALUE) ?
1562 em_ms_force_master :
1563 em_ms_force_slave) :
1564 em_ms_auto;
1565
1566 switch (phy_ms_setting) {
1567 case em_ms_force_master:
1568 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1569 break;
1570 case em_ms_force_slave:
1571 phy_data |= CR_1000T_MS_ENABLE;
1572 phy_data &= ~(CR_1000T_MS_VALUE);
1573 break;
1574 case em_ms_auto:
1575 phy_data &= ~CR_1000T_MS_ENABLE;
1576 default:
1577 break;
1578 }
1579 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1580 if (ret_val)
1581 return ret_val;
1582 }
1583
1584 return E1000_SUCCESS;
1585 }
1586
1587 /********************************************************************
1588 * Copper link setup for em_phy_gg82563 series.
1589 *
1590 * hw - Struct containing variables accessed by shared code
1591 *********************************************************************/
1592 static int32_t
1593 em_copper_link_ggp_setup(struct em_hw *hw)
1594 {
1595 int32_t ret_val;
1596 uint16_t phy_data;
1597 uint32_t reg_data;
1598
1599 DEBUGFUNC("em_copper_link_ggp_setup");
1600
1601 if (!hw->phy_reset_disable) {
1602
1603 /* Enable CRS on TX for half-duplex operation. */
1604 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1605 &phy_data);
1606 if (ret_val)
1607 return ret_val;
1608
1609 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1610 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1611 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1612
1613 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1614 phy_data);
1615 if (ret_val)
1616 return ret_val;
1617
1618 /* Options:
1619 * MDI/MDI-X = 0 (default)
1620 * 0 - Auto for all speeds
1621 * 1 - MDI mode
1622 * 2 - MDI-X mode
1623 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1624 */
1625 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1626 if (ret_val)
1627 return ret_val;
1628
1629 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1630
1631 switch (hw->mdix) {
1632 case 1:
1633 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1634 break;
1635 case 2:
1636 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1637 break;
1638 case 0:
1639 default:
1640 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1641 break;
1642 }
1643
1644 /* Options:
1645 * disable_polarity_correction = 0 (default)
1646 * Automatic Correction for Reversed Cable Polarity
1647 * 0 - Disabled
1648 * 1 - Enabled
1649 */
1650 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1651 if (hw->disable_polarity_correction == 1)
1652 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1653 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1654
1655 if (ret_val)
1656 return ret_val;
1657
1658 /* SW Reset the PHY so all changes take effect */
1659 ret_val = em_phy_reset(hw);
1660 if (ret_val) {
1661 DEBUGOUT("Error Resetting the PHY\n");
1662 return ret_val;
1663 }
1664 } /* phy_reset_disable */
1665
1666 if (hw->mac_type == em_80003es2lan) {
1667 /* Bypass RX and TX FIFO's */
1668 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1669 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1670 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1671 if (ret_val)
1672 return ret_val;
1673
1674 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1675 if (ret_val)
1676 return ret_val;
1677
1678 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1679 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1680
1681 if (ret_val)
1682 return ret_val;
1683
1684 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1685 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1686 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1687
1688 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1689 &phy_data);
1690 if (ret_val)
1691 return ret_val;
1692
1693 /* Do not init these registers when the HW is in IAMT mode, since the
1694 * firmware will have already initialized them. We only initialize
1695 * them if the HW is not in IAMT mode.
1696 */
1697 if (em_check_mng_mode(hw) == FALSE) {
1698 /* Enable Electrical Idle on the PHY */
1699 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1700 ret_val = em_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1701 phy_data);
1702 if (ret_val)
1703 return ret_val;
1704
1705 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1706 &phy_data);
1707 if (ret_val)
1708 return ret_val;
1709
1710 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1711 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1712 phy_data);
1713
1714 if (ret_val)
1715 return ret_val;
1716 }
1717
1718 /* Workaround: Disable padding in Kumeran interface in the MAC
1719 * and in the PHY to avoid CRC errors.
1720 */
1721 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1722 &phy_data);
1723 if (ret_val)
1724 return ret_val;
1725 phy_data |= GG82563_ICR_DIS_PADDING;
1726 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1727 phy_data);
1728 if (ret_val)
1729 return ret_val;
1730 }
1731
1732 return E1000_SUCCESS;
1733 }
1734
1735 /********************************************************************
1736 * Copper link setup for em_phy_m88 series.
1737 *
1738 * hw - Struct containing variables accessed by shared code
1739 *********************************************************************/
1740 static int32_t
1741 em_copper_link_mgp_setup(struct em_hw *hw)
1742 {
1743 int32_t ret_val;
1744 uint16_t phy_data;
1745
1746 DEBUGFUNC("em_copper_link_mgp_setup");
1747
1748 if (hw->phy_reset_disable)
1749 return E1000_SUCCESS;
1750
1751 /* Enable CRS on TX. This must be set for half-duplex operation. */
1752 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1753 if (ret_val)
1754 return ret_val;
1755
1756 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1757
1758 /* Options:
1759 * MDI/MDI-X = 0 (default)
1760 * 0 - Auto for all speeds
1761 * 1 - MDI mode
1762 * 2 - MDI-X mode
1763 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1764 */
1765 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1766
1767 switch (hw->mdix) {
1768 case 1:
1769 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1770 break;
1771 case 2:
1772 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1773 break;
1774 case 3:
1775 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1776 break;
1777 case 0:
1778 default:
1779 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1780 break;
1781 }
1782
1783 /* Options:
1784 * disable_polarity_correction = 0 (default)
1785 * Automatic Correction for Reversed Cable Polarity
1786 * 0 - Disabled
1787 * 1 - Enabled
1788 */
1789 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1790 if (hw->disable_polarity_correction == 1)
1791 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1792 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1793 if (ret_val)
1794 return ret_val;
1795
1796 if (hw->phy_revision < M88E1011_I_REV_4) {
1797 /* Force TX_CLK in the Extended PHY Specific Control Register
1798 * to 25MHz clock.
1799 */
1800 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1801 if (ret_val)
1802 return ret_val;
1803
1804 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1805
1806 if ((hw->phy_revision == E1000_REVISION_2) &&
1807 (hw->phy_id == M88E1111_I_PHY_ID)) {
1808 /* Vidalia Phy, set the downshift counter to 5x */
1809 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1810 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1811 ret_val = em_write_phy_reg(hw,
1812 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1813 if (ret_val)
1814 return ret_val;
1815 } else {
1816 /* Configure Master and Slave downshift values */
1817 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1818 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1819 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1820 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1821 ret_val = em_write_phy_reg(hw,
1822 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1823 if (ret_val)
1824 return ret_val;
1825 }
1826 }
1827
1828 /* SW Reset the PHY so all changes take effect */
1829 ret_val = em_phy_reset(hw);
1830 if (ret_val) {
1831 DEBUGOUT("Error Resetting the PHY\n");
1832 return ret_val;
1833 }
1834
1835 return E1000_SUCCESS;
1836 }
1837
1838 /********************************************************************
1839 * Setup auto-negotiation and flow control advertisements,
1840 * and then perform auto-negotiation.
1841 *
1842 * hw - Struct containing variables accessed by shared code
1843 *********************************************************************/
1844 static int32_t
1845 em_copper_link_autoneg(struct em_hw *hw)
1846 {
1847 int32_t ret_val;
1848 uint16_t phy_data;
1849
1850 DEBUGFUNC("em_copper_link_autoneg");
1851
1852 /* Perform some bounds checking on the hw->autoneg_advertised
1853 * parameter. If this variable is zero, then set it to the default.
1854 */
1855 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1856
1857 /* If autoneg_advertised is zero, we assume it was not defaulted
1858 * by the calling code so we set to advertise full capability.
1859 */
1860 if (hw->autoneg_advertised == 0)
1861 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1862
1863 /* IFE phy only supports 10/100 */
1864 if (hw->phy_type == em_phy_ife)
1865 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1866
1867 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1868 ret_val = em_phy_setup_autoneg(hw);
1869 if (ret_val) {
1870 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1871 return ret_val;
1872 }
1873 DEBUGOUT("Restarting Auto-Neg\n");
1874
1875 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1876 * the Auto Neg Restart bit in the PHY control register.
1877 */
1878 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
1879 if (ret_val)
1880 return ret_val;
1881
1882 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1883 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
1884 if (ret_val)
1885 return ret_val;
1886
1887 /* Does the user want to wait for Auto-Neg to complete here, or
1888 * check at a later time (for example, callback routine).
1889 */
1890 if (hw->wait_autoneg_complete) {
1891 ret_val = em_wait_autoneg(hw);
1892 if (ret_val) {
1893 DEBUGOUT("Error while waiting for autoneg to complete\n");
1894 return ret_val;
1895 }
1896 }
1897
1898 hw->get_link_status = TRUE;
1899
1900 return E1000_SUCCESS;
1901 }
1902
1903 /******************************************************************************
1904 * Config the MAC and the PHY after link is up.
1905 * 1) Set up the MAC to the current PHY speed/duplex
1906 * if we are on 82543. If we
1907 * are on newer silicon, we only need to configure
1908 * collision distance in the Transmit Control Register.
1909 * 2) Set up flow control on the MAC to that established with
1910 * the link partner.
1911 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1912 *
1913 * hw - Struct containing variables accessed by shared code
1914 ******************************************************************************/
1915 static int32_t
1916 em_copper_link_postconfig(struct em_hw *hw)
1917 {
1918 int32_t ret_val;
1919 DEBUGFUNC("em_copper_link_postconfig");
1920
1921 if (hw->mac_type >= em_82544) {
1922 em_config_collision_dist(hw);
1923 } else {
1924 ret_val = em_config_mac_to_phy(hw);
1925 if (ret_val) {
1926 DEBUGOUT("Error configuring MAC to PHY settings\n");
1927 return ret_val;
1928 }
1929 }
1930 ret_val = em_config_fc_after_link_up(hw);
1931 if (ret_val) {
1932 DEBUGOUT("Error Configuring Flow Control\n");
1933 return ret_val;
1934 }
1935
1936 /* Config DSP to improve Giga link quality */
1937 if (hw->phy_type == em_phy_igp) {
1938 ret_val = em_config_dsp_after_link_change(hw, TRUE);
1939 if (ret_val) {
1940 DEBUGOUT("Error Configuring DSP after link up\n");
1941 return ret_val;
1942 }
1943 }
1944
1945 return E1000_SUCCESS;
1946 }
1947
1948 /******************************************************************************
1949 * Detects which PHY is present and setup the speed and duplex
1950 *
1951 * hw - Struct containing variables accessed by shared code
1952 ******************************************************************************/
1953 static int32_t
1954 em_setup_copper_link(struct em_hw *hw)
1955 {
1956 int32_t ret_val;
1957 uint16_t i;
1958 uint16_t phy_data;
1959 uint16_t reg_data;
1960
1961 DEBUGFUNC("em_setup_copper_link");
1962
1963 switch (hw->mac_type) {
1964 case em_80003es2lan:
1965 case em_ich8lan:
1966 case em_ich9lan:
1967 /* Set the mac to wait the maximum time between each
1968 * iteration and increase the max iterations when
1969 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1970 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1971 if (ret_val)
1972 return ret_val;
1973 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1974 if (ret_val)
1975 return ret_val;
1976 reg_data |= 0x3F;
1977 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1978 if (ret_val)
1979 return ret_val;
1980 default:
1981 break;
1982 }
1983
1984 /* Check if it is a valid PHY and set PHY mode if necessary. */
1985 ret_val = em_copper_link_preconfig(hw);
1986 if (ret_val)
1987 return ret_val;
1988
1989 switch (hw->mac_type) {
1990 case em_80003es2lan:
1991 /* Kumeran registers are written-only */
1992 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1993 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1994 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1995 reg_data);
1996 if (ret_val)
1997 return ret_val;
1998 break;
1999 default:
2000 break;
2001 }
2002
2003 if (hw->phy_type == em_phy_igp ||
2004 hw->phy_type == em_phy_igp_3 ||
2005 hw->phy_type == em_phy_igp_2) {
2006 ret_val = em_copper_link_igp_setup(hw);
2007 if (ret_val)
2008 return ret_val;
2009 } else if (hw->phy_type == em_phy_m88) {
2010 ret_val = em_copper_link_mgp_setup(hw);
2011 if (ret_val)
2012 return ret_val;
2013 } else if (hw->phy_type == em_phy_gg82563) {
2014 ret_val = em_copper_link_ggp_setup(hw);
2015 if (ret_val)
2016 return ret_val;
2017 }
2018
2019 if (hw->autoneg) {
2020 /* Setup autoneg and flow control advertisement
2021 * and perform autonegotiation */
2022 ret_val = em_copper_link_autoneg(hw);
2023 if (ret_val)
2024 return ret_val;
2025 } else {
2026 /* PHY will be set to 10H, 10F, 100H,or 100F
2027 * depending on value from forced_speed_duplex. */
2028 DEBUGOUT("Forcing speed and duplex\n");
2029 ret_val = em_phy_force_speed_duplex(hw);
2030 if (ret_val) {
2031 DEBUGOUT("Error Forcing Speed and Duplex\n");
2032 return ret_val;
2033 }
2034 }
2035
2036 /* Check link status. Wait up to 100 microseconds for link to become
2037 * valid.
2038 */
2039 for (i = 0; i < 10; i++) {
2040 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2041 if (ret_val)
2042 return ret_val;
2043 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2044 if (ret_val)
2045 return ret_val;
2046
2047 if (phy_data & MII_SR_LINK_STATUS) {
2048 /* Config the MAC and PHY after link is up */
2049 ret_val = em_copper_link_postconfig(hw);
2050 if (ret_val)
2051 return ret_val;
2052
2053 DEBUGOUT("Valid link established!!!\n");
2054 return E1000_SUCCESS;
2055 }
2056 usec_delay(10);
2057 }
2058
2059 DEBUGOUT("Unable to establish link!!!\n");
2060 return E1000_SUCCESS;
2061 }
2062
2063 /******************************************************************************
2064 * Configure the MAC-to-PHY interface for 10/100Mbps
2065 *
2066 * hw - Struct containing variables accessed by shared code
2067 ******************************************************************************/
2068 static int32_t
2069 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
2070 {
2071 int32_t ret_val = E1000_SUCCESS;
2072 uint32_t tipg;
2073 uint16_t reg_data;
2074
2075 DEBUGFUNC("em_configure_kmrn_for_10_100");
2076
2077 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2078 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2079 reg_data);
2080 if (ret_val)
2081 return ret_val;
2082
2083 /* Configure Transmit Inter-Packet Gap */
2084 tipg = E1000_READ_REG(hw, TIPG);
2085 tipg &= ~E1000_TIPG_IPGT_MASK;
2086 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2087 E1000_WRITE_REG(hw, TIPG, tipg);
2088
2089 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2090
2091 if (ret_val)
2092 return ret_val;
2093
2094 if (duplex == HALF_DUPLEX)
2095 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2096 else
2097 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2098
2099 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2100
2101 return ret_val;
2102 }
2103
2104 static int32_t
2105 em_configure_kmrn_for_1000(struct em_hw *hw)
2106 {
2107 int32_t ret_val = E1000_SUCCESS;
2108 uint16_t reg_data;
2109 uint32_t tipg;
2110
2111 DEBUGFUNC("em_configure_kmrn_for_1000");
2112
2113 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2114 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2115 reg_data);
2116 if (ret_val)
2117 return ret_val;
2118
2119 /* Configure Transmit Inter-Packet Gap */
2120 tipg = E1000_READ_REG(hw, TIPG);
2121 tipg &= ~E1000_TIPG_IPGT_MASK;
2122 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2123 E1000_WRITE_REG(hw, TIPG, tipg);
2124
2125 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2126
2127 if (ret_val)
2128 return ret_val;
2129
2130 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2131 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2132
2133 return ret_val;
2134 }
2135
2136 /******************************************************************************
2137 * Configures PHY autoneg and flow control advertisement settings
2138 *
2139 * hw - Struct containing variables accessed by shared code
2140 ******************************************************************************/
2141 int32_t
2142 em_phy_setup_autoneg(struct em_hw *hw)
2143 {
2144 int32_t ret_val;
2145 uint16_t mii_autoneg_adv_reg;
2146 uint16_t mii_1000t_ctrl_reg;
2147
2148 DEBUGFUNC("em_phy_setup_autoneg");
2149
2150 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2151 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2152 if (ret_val)
2153 return ret_val;
2154
2155 if (hw->phy_type != em_phy_ife) {
2156 /* Read the MII 1000Base-T Control Register (Address 9). */
2157 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2158 if (ret_val)
2159 return ret_val;
2160 } else
2161 mii_1000t_ctrl_reg=0;
2162
2163 /* Need to parse both autoneg_advertised and fc and set up
2164 * the appropriate PHY registers. First we will parse for
2165 * autoneg_advertised software override. Since we can advertise
2166 * a plethora of combinations, we need to check each bit
2167 * individually.
2168 */
2169
2170 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2171 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2172 * the 1000Base-T Control Register (Address 9).
2173 */
2174 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2175 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2176
2177 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2178
2179 /* Do we want to advertise 10 Mb Half Duplex? */
2180 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2181 DEBUGOUT("Advertise 10mb Half duplex\n");
2182 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2183 }
2184
2185 /* Do we want to advertise 10 Mb Full Duplex? */
2186 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2187 DEBUGOUT("Advertise 10mb Full duplex\n");
2188 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2189 }
2190
2191 /* Do we want to advertise 100 Mb Half Duplex? */
2192 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2193 DEBUGOUT("Advertise 100mb Half duplex\n");
2194 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2195 }
2196
2197 /* Do we want to advertise 100 Mb Full Duplex? */
2198 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2199 DEBUGOUT("Advertise 100mb Full duplex\n");
2200 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2201 }
2202
2203 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2204 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2205 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2206 }
2207
2208 /* Do we want to advertise 1000 Mb Full Duplex? */
2209 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2210 DEBUGOUT("Advertise 1000mb Full duplex\n");
2211 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2212 if (hw->phy_type == em_phy_ife) {
2213 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2214 }
2215 }
2216
2217 /* Check for a software override of the flow control settings, and
2218 * setup the PHY advertisement registers accordingly. If
2219 * auto-negotiation is enabled, then software will have to set the
2220 * "PAUSE" bits to the correct value in the Auto-Negotiation
2221 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2222 *
2223 * The possible values of the "fc" parameter are:
2224 * 0: Flow control is completely disabled
2225 * 1: Rx flow control is enabled (we can receive pause frames
2226 * but not send pause frames).
2227 * 2: Tx flow control is enabled (we can send pause frames
2228 * but we do not support receiving pause frames).
2229 * 3: Both Rx and TX flow control (symmetric) are enabled.
2230 * other: No software override. The flow control configuration
2231 * in the EEPROM is used.
2232 */
2233 switch (hw->fc) {
2234 case E1000_FC_NONE: /* 0 */
2235 /* Flow control (RX & TX) is completely disabled by a
2236 * software over-ride.
2237 */
2238 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2239 break;
2240 case E1000_FC_RX_PAUSE: /* 1 */
2241 /* RX Flow control is enabled, and TX Flow control is
2242 * disabled, by a software over-ride.
2243 */
2244 /* Since there really isn't a way to advertise that we are
2245 * capable of RX Pause ONLY, we will advertise that we
2246 * support both symmetric and asymmetric RX PAUSE. Later
2247 * (in em_config_fc_after_link_up) we will disable the
2248 *hw's ability to send PAUSE frames.
2249 */
2250 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2251 break;
2252 case E1000_FC_TX_PAUSE: /* 2 */
2253 /* TX Flow control is enabled, and RX Flow control is
2254 * disabled, by a software over-ride.
2255 */
2256 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2257 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2258 break;
2259 case E1000_FC_FULL: /* 3 */
2260 /* Flow control (both RX and TX) is enabled by a software
2261 * over-ride.
2262 */
2263 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2264 break;
2265 default:
2266 DEBUGOUT("Flow control param set incorrectly\n");
2267 return -E1000_ERR_CONFIG;
2268 }
2269
2270 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2271 if (ret_val)
2272 return ret_val;
2273
2274 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2275
2276 if (hw->phy_type != em_phy_ife) {
2277 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2278 if (ret_val)
2279 return ret_val;
2280 }
2281
2282 return E1000_SUCCESS;
2283 }
2284
2285 /******************************************************************************
2286 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2287 *
2288 * hw - Struct containing variables accessed by shared code
2289 ******************************************************************************/
2290 static int32_t
2291 em_phy_force_speed_duplex(struct em_hw *hw)
2292 {
2293 uint32_t ctrl;
2294 int32_t ret_val;
2295 uint16_t mii_ctrl_reg;
2296 uint16_t mii_status_reg;
2297 uint16_t phy_data;
2298 uint16_t i;
2299
2300 DEBUGFUNC("em_phy_force_speed_duplex");
2301
2302 /* Turn off Flow control if we are forcing speed and duplex. */
2303 hw->fc = E1000_FC_NONE;
2304
2305 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2306
2307 /* Read the Device Control Register. */
2308 ctrl = E1000_READ_REG(hw, CTRL);
2309
2310 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2311 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2312 ctrl &= ~(DEVICE_SPEED_MASK);
2313
2314 /* Clear the Auto Speed Detect Enable bit. */
2315 ctrl &= ~E1000_CTRL_ASDE;
2316
2317 /* Read the MII Control Register. */
2318 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2319 if (ret_val)
2320 return ret_val;
2321
2322 /* We need to disable autoneg in order to force link and duplex. */
2323
2324 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2325
2326 /* Are we forcing Full or Half Duplex? */
2327 if (hw->forced_speed_duplex == em_100_full ||
2328 hw->forced_speed_duplex == em_10_full) {
2329 /* We want to force full duplex so we SET the full duplex bits in the
2330 * Device and MII Control Registers.
2331 */
2332 ctrl |= E1000_CTRL_FD;
2333 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2334 DEBUGOUT("Full Duplex\n");
2335 } else {
2336 /* We want to force half duplex so we CLEAR the full duplex bits in
2337 * the Device and MII Control Registers.
2338 */
2339 ctrl &= ~E1000_CTRL_FD;
2340 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2341 DEBUGOUT("Half Duplex\n");
2342 }
2343
2344 /* Are we forcing 100Mbps??? */
2345 if (hw->forced_speed_duplex == em_100_full ||
2346 hw->forced_speed_duplex == em_100_half) {
2347 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2348 ctrl |= E1000_CTRL_SPD_100;
2349 mii_ctrl_reg |= MII_CR_SPEED_100;
2350 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2351 DEBUGOUT("Forcing 100mb ");
2352 } else {
2353 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2354 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2355 mii_ctrl_reg |= MII_CR_SPEED_10;
2356 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2357 DEBUGOUT("Forcing 10mb ");
2358 }
2359
2360 em_config_collision_dist(hw);
2361
2362 /* Write the configured values back to the Device Control Reg. */
2363 E1000_WRITE_REG(hw, CTRL, ctrl);
2364
2365 if ((hw->phy_type == em_phy_m88) ||
2366 (hw->phy_type == em_phy_gg82563)) {
2367 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2368 if (ret_val)
2369 return ret_val;
2370
2371 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2372 * forced whenever speed are duplex are forced.
2373 */
2374 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2375 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2376 if (ret_val)
2377 return ret_val;
2378
2379 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2380
2381 /* Need to reset the PHY or these changes will be ignored */
2382 mii_ctrl_reg |= MII_CR_RESET;
2383
2384 /* Disable MDI-X support for 10/100 */
2385 } else if (hw->phy_type == em_phy_ife) {
2386 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2387 if (ret_val)
2388 return ret_val;
2389
2390 phy_data &= ~IFE_PMC_AUTO_MDIX;
2391 phy_data &= ~IFE_PMC_FORCE_MDIX;
2392
2393 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2394 if (ret_val)
2395 return ret_val;
2396
2397 } else {
2398 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2399 * forced whenever speed or duplex are forced.
2400 */
2401 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2402 if (ret_val)
2403 return ret_val;
2404
2405 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2406 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2407
2408 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2409 if (ret_val)
2410 return ret_val;
2411 }
2412
2413 /* Write back the modified PHY MII control register. */
2414 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2415 if (ret_val)
2416 return ret_val;
2417
2418 usec_delay(1);
2419
2420 /* The wait_autoneg_complete flag may be a little misleading here.
2421 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2422 * But we do want to delay for a period while forcing only so we
2423 * don't generate false No Link messages. So we will wait here
2424 * only if the user has set wait_autoneg_complete to 1, which is
2425 * the default.
2426 */
2427 if (hw->wait_autoneg_complete) {
2428 /* We will wait for autoneg to complete. */
2429 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2430 mii_status_reg = 0;
2431
2432 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2433 for (i = PHY_FORCE_TIME; i > 0; i--) {
2434 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2435 * to be set.
2436 */
2437 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2438 if (ret_val)
2439 return ret_val;
2440
2441 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2442 if (ret_val)
2443 return ret_val;
2444
2445 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2446 msec_delay(100);
2447 }
2448 if ((i == 0) &&
2449 ((hw->phy_type == em_phy_m88) ||
2450 (hw->phy_type == em_phy_gg82563))) {
2451 /* We didn't get link. Reset the DSP and wait again for link. */
2452 ret_val = em_phy_reset_dsp(hw);
2453 if (ret_val) {
2454 DEBUGOUT("Error Resetting PHY DSP\n");
2455 return ret_val;
2456 }
2457 }
2458 /* This loop will early-out if the link condition has been met. */
2459 for (i = PHY_FORCE_TIME; i > 0; i--) {
2460 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2461 msec_delay(100);
2462 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2463 * to be set.
2464 */
2465 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2466 if (ret_val)
2467 return ret_val;
2468
2469 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2470 if (ret_val)
2471 return ret_val;
2472 }
2473 }
2474
2475 if (hw->phy_type == em_phy_m88) {
2476 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2477 * Extended PHY Specific Control Register to 25MHz clock. This value
2478 * defaults back to a 2.5MHz clock when the PHY is reset.
2479 */
2480 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2481 if (ret_val)
2482 return ret_val;
2483
2484 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2485 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2486 if (ret_val)
2487 return ret_val;
2488
2489 /* In addition, because of the s/w reset above, we need to enable CRS on
2490 * TX. This must be set for both full and half duplex operation.
2491 */
2492 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2493 if (ret_val)
2494 return ret_val;
2495
2496 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2497 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2498 if (ret_val)
2499 return ret_val;
2500
2501 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
2502 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
2503 hw->forced_speed_duplex == em_10_half)) {
2504 ret_val = em_polarity_reversal_workaround(hw);
2505 if (ret_val)
2506 return ret_val;
2507 }
2508 } else if (hw->phy_type == em_phy_gg82563) {
2509 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2510 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2511 * we're not in a forced 10/duplex configuration. */
2512 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2513 if (ret_val)
2514 return ret_val;
2515
2516 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2517 if ((hw->forced_speed_duplex == em_10_full) ||
2518 (hw->forced_speed_duplex == em_10_half))
2519 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2520 else
2521 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2522
2523 /* Also due to the reset, we need to enable CRS on Tx. */
2524 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2525
2526 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2527 if (ret_val)
2528 return ret_val;
2529 }
2530 return E1000_SUCCESS;
2531 }
2532
2533 /******************************************************************************
2534 * Sets the collision distance in the Transmit Control register
2535 *
2536 * hw - Struct containing variables accessed by shared code
2537 *
2538 * Link should have been established previously. Reads the speed and duplex
2539 * information from the Device Status register.
2540 ******************************************************************************/
2541 void
2542 em_config_collision_dist(struct em_hw *hw)
2543 {
2544 uint32_t tctl, coll_dist;
2545
2546 DEBUGFUNC("em_config_collision_dist");
2547
2548 if (hw->mac_type < em_82543)
2549 coll_dist = E1000_COLLISION_DISTANCE_82542;
2550 else
2551 coll_dist = E1000_COLLISION_DISTANCE;
2552
2553 tctl = E1000_READ_REG(hw, TCTL);
2554
2555 tctl &= ~E1000_TCTL_COLD;
2556 tctl |= coll_dist << E1000_COLD_SHIFT;
2557
2558 E1000_WRITE_REG(hw, TCTL, tctl);
2559 E1000_WRITE_FLUSH(hw);
2560 }
2561
2562 /******************************************************************************
2563 * Sets MAC speed and duplex settings to reflect the those in the PHY
2564 *
2565 * hw - Struct containing variables accessed by shared code
2566 * mii_reg - data to write to the MII control register
2567 *
2568 * The contents of the PHY register containing the needed information need to
2569 * be passed in.
2570 ******************************************************************************/
2571 static int32_t
2572 em_config_mac_to_phy(struct em_hw *hw)
2573 {
2574 uint32_t ctrl;
2575 int32_t ret_val;
2576 uint16_t phy_data;
2577
2578 DEBUGFUNC("em_config_mac_to_phy");
2579
2580 /* 82544 or newer MAC, Auto Speed Detection takes care of
2581 * MAC speed/duplex configuration.*/
2582 if (hw->mac_type >= em_82544)
2583 return E1000_SUCCESS;
2584
2585 /* Read the Device Control Register and set the bits to Force Speed
2586 * and Duplex.
2587 */
2588 ctrl = E1000_READ_REG(hw, CTRL);
2589 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2590 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2591
2592 /* Set up duplex in the Device Control and Transmit Control
2593 * registers depending on negotiated values.
2594 */
2595 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2596 if (ret_val)
2597 return ret_val;
2598
2599 if (phy_data & M88E1000_PSSR_DPLX)
2600 ctrl |= E1000_CTRL_FD;
2601 else
2602 ctrl &= ~E1000_CTRL_FD;
2603
2604 em_config_collision_dist(hw);
2605
2606 /* Set up speed in the Device Control register depending on
2607 * negotiated values.
2608 */
2609 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2610 ctrl |= E1000_CTRL_SPD_1000;
2611 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2612 ctrl |= E1000_CTRL_SPD_100;
2613
2614 /* Write the configured values back to the Device Control Reg. */
2615 E1000_WRITE_REG(hw, CTRL, ctrl);
2616 return E1000_SUCCESS;
2617 }
2618
2619 /******************************************************************************
2620 * Forces the MAC's flow control settings.
2621 *
2622 * hw - Struct containing variables accessed by shared code
2623 *
2624 * Sets the TFCE and RFCE bits in the device control register to reflect
2625 * the adapter settings. TFCE and RFCE need to be explicitly set by
2626 * software when a Copper PHY is used because autonegotiation is managed
2627 * by the PHY rather than the MAC. Software must also configure these
2628 * bits when link is forced on a fiber connection.
2629 *****************************************************************************/
2630 int32_t
2631 em_force_mac_fc(struct em_hw *hw)
2632 {
2633 uint32_t ctrl;
2634
2635 DEBUGFUNC("em_force_mac_fc");
2636
2637 /* Get the current configuration of the Device Control Register */
2638 ctrl = E1000_READ_REG(hw, CTRL);
2639
2640 /* Because we didn't get link via the internal auto-negotiation
2641 * mechanism (we either forced link or we got link via PHY
2642 * auto-neg), we have to manually enable/disable transmit an
2643 * receive flow control.
2644 *
2645 * The "Case" statement below enables/disable flow control
2646 * according to the "hw->fc" parameter.
2647 *
2648 * The possible values of the "fc" parameter are:
2649 * 0: Flow control is completely disabled
2650 * 1: Rx flow control is enabled (we can receive pause
2651 * frames but not send pause frames).
2652 * 2: Tx flow control is enabled (we can send pause frames
2653 * frames but we do not receive pause frames).
2654 * 3: Both Rx and TX flow control (symmetric) is enabled.
2655 * other: No other values should be possible at this point.
2656 */
2657
2658 switch (hw->fc) {
2659 case E1000_FC_NONE:
2660 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2661 break;
2662 case E1000_FC_RX_PAUSE:
2663 ctrl &= (~E1000_CTRL_TFCE);
2664 ctrl |= E1000_CTRL_RFCE;
2665 break;
2666 case E1000_FC_TX_PAUSE:
2667 ctrl &= (~E1000_CTRL_RFCE);
2668 ctrl |= E1000_CTRL_TFCE;
2669 break;
2670 case E1000_FC_FULL:
2671 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2672 break;
2673 default:
2674 DEBUGOUT("Flow control param set incorrectly\n");
2675 return -E1000_ERR_CONFIG;
2676 }
2677
2678 /* Disable TX Flow Control for 82542 (rev 2.0) */
2679 if (hw->mac_type == em_82542_rev2_0)
2680 ctrl &= (~E1000_CTRL_TFCE);
2681
2682 E1000_WRITE_REG(hw, CTRL, ctrl);
2683 return E1000_SUCCESS;
2684 }
2685
2686 /******************************************************************************
2687 * Configures flow control settings after link is established
2688 *
2689 * hw - Struct containing variables accessed by shared code
2690 *
2691 * Should be called immediately after a valid link has been established.
2692 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2693 * and autonegotiation is enabled, the MAC flow control settings will be set
2694 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2695 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2696 *****************************************************************************/
2697 STATIC int32_t
2698 em_config_fc_after_link_up(struct em_hw *hw)
2699 {
2700 int32_t ret_val;
2701 uint16_t mii_status_reg;
2702 uint16_t mii_nway_adv_reg;
2703 uint16_t mii_nway_lp_ability_reg;
2704 uint16_t speed;
2705 uint16_t duplex;
2706
2707 DEBUGFUNC("em_config_fc_after_link_up");
2708
2709 /* Check for the case where we have fiber media and auto-neg failed
2710 * so we had to force link. In this case, we need to force the
2711 * configuration of the MAC to match the "fc" parameter.
2712 */
2713 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
2714 ((hw->media_type == em_media_type_internal_serdes) &&
2715 (hw->autoneg_failed)) ||
2716 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
2717 ret_val = em_force_mac_fc(hw);
2718 if (ret_val) {
2719 DEBUGOUT("Error forcing flow control settings\n");
2720 return ret_val;
2721 }
2722 }
2723
2724 /* Check for the case where we have copper media and auto-neg is
2725 * enabled. In this case, we need to check and see if Auto-Neg
2726 * has completed, and if so, how the PHY and link partner has
2727 * flow control configured.
2728 */
2729 if ((hw->media_type == em_media_type_copper) && hw->autoneg) {
2730 /* Read the MII Status Register and check to see if AutoNeg
2731 * has completed. We read this twice because this reg has
2732 * some "sticky" (latched) bits.
2733 */
2734 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2735 if (ret_val)
2736 return ret_val;
2737 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2738 if (ret_val)
2739 return ret_val;
2740
2741 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2742 /* The AutoNeg process has completed, so we now need to
2743 * read both the Auto Negotiation Advertisement Register
2744 * (Address 4) and the Auto_Negotiation Base Page Ability
2745 * Register (Address 5) to determine how flow control was
2746 * negotiated.
2747 */
2748 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
2749 &mii_nway_adv_reg);
2750 if (ret_val)
2751 return ret_val;
2752 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
2753 &mii_nway_lp_ability_reg);
2754 if (ret_val)
2755 return ret_val;
2756
2757 /* Two bits in the Auto Negotiation Advertisement Register
2758 * (Address 4) and two bits in the Auto Negotiation Base
2759 * Page Ability Register (Address 5) determine flow control
2760 * for both the PHY and the link partner. The following
2761 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2762 * 1999, describes these PAUSE resolution bits and how flow
2763 * control is determined based upon these settings.
2764 * NOTE: DC = Don't Care
2765 *
2766 * LOCAL DEVICE | LINK PARTNER
2767 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2768 *-------|---------|-------|---------|--------------------
2769 * 0 | 0 | DC | DC | em_fc_none
2770 * 0 | 1 | 0 | DC | em_fc_none
2771 * 0 | 1 | 1 | 0 | em_fc_none
2772 * 0 | 1 | 1 | 1 | em_fc_tx_pause
2773 * 1 | 0 | 0 | DC | em_fc_none
2774 * 1 | DC | 1 | DC | em_fc_full
2775 * 1 | 1 | 0 | 0 | em_fc_none
2776 * 1 | 1 | 0 | 1 | em_fc_rx_pause
2777 *
2778 */
2779 /* Are both PAUSE bits set to 1? If so, this implies
2780 * Symmetric Flow Control is enabled at both ends. The
2781 * ASM_DIR bits are irrelevant per the spec.
2782 *
2783 * For Symmetric Flow Control:
2784 *
2785 * LOCAL DEVICE | LINK PARTNER
2786 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2787 *-------|---------|-------|---------|--------------------
2788 * 1 | DC | 1 | DC | em_fc_full
2789 *
2790 */
2791 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2792 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2793 /* Now we need to check if the user selected RX ONLY
2794 * of pause frames. In this case, we had to advertise
2795 * FULL flow control because we could not advertise RX
2796 * ONLY. Hence, we must now check to see if we need to
2797 * turn OFF the TRANSMISSION of PAUSE frames.
2798 */
2799 if (hw->original_fc == E1000_FC_FULL) {
2800 hw->fc = E1000_FC_FULL;
2801 DEBUGOUT("Flow Control = FULL.\n");
2802 } else {
2803 hw->fc = E1000_FC_RX_PAUSE;
2804 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2805 }
2806 }
2807 /* For receiving PAUSE frames ONLY.
2808 *
2809 * LOCAL DEVICE | LINK PARTNER
2810 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2811 *-------|---------|-------|---------|--------------------
2812 * 0 | 1 | 1 | 1 | em_fc_tx_pause
2813 *
2814 */
2815 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2816 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2817 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2818 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2819 hw->fc = E1000_FC_TX_PAUSE;
2820 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2821 }
2822 /* For transmitting PAUSE frames ONLY.
2823 *
2824 * LOCAL DEVICE | LINK PARTNER
2825 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2826 *-------|---------|-------|---------|--------------------
2827 * 1 | 1 | 0 | 1 | em_fc_rx_pause
2828 *
2829 */
2830 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2831 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2832 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2833 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2834 hw->fc = E1000_FC_RX_PAUSE;
2835 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2836 }
2837 /* Per the IEEE spec, at this point flow control should be
2838 * disabled. However, we want to consider that we could
2839 * be connected to a legacy switch that doesn't advertise
2840 * desired flow control, but can be forced on the link
2841 * partner. So if we advertised no flow control, that is
2842 * what we will resolve to. If we advertised some kind of
2843 * receive capability (Rx Pause Only or Full Flow Control)
2844 * and the link partner advertised none, we will configure
2845 * ourselves to enable Rx Flow Control only. We can do
2846 * this safely for two reasons: If the link partner really
2847 * didn't want flow control enabled, and we enable Rx, no
2848 * harm done since we won't be receiving any PAUSE frames
2849 * anyway. If the intent on the link partner was to have
2850 * flow control enabled, then by us enabling RX only, we
2851 * can at least receive pause frames and process them.
2852 * This is a good idea because in most cases, since we are
2853 * predominantly a server NIC, more times than not we will
2854 * be asked to delay transmission of packets than asking
2855 * our link partner to pause transmission of frames.
2856 */
2857 else if ((hw->original_fc == E1000_FC_NONE||
2858 hw->original_fc == E1000_FC_TX_PAUSE) ||
2859 hw->fc_strict_ieee) {
2860 hw->fc = E1000_FC_NONE;
2861 DEBUGOUT("Flow Control = NONE.\n");
2862 } else {
2863 hw->fc = E1000_FC_RX_PAUSE;
2864 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2865 }
2866
2867 /* Now we need to do one last check... If we auto-
2868 * negotiated to HALF DUPLEX, flow control should not be
2869 * enabled per IEEE 802.3 spec.
2870 */
2871 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
2872 if (ret_val) {
2873 DEBUGOUT("Error getting link speed and duplex\n");
2874 return ret_val;
2875 }
2876
2877 if (duplex == HALF_DUPLEX)
2878 hw->fc = E1000_FC_NONE;
2879
2880 /* Now we call a subroutine to actually force the MAC
2881 * controller to use the correct flow control settings.
2882 */
2883 ret_val = em_force_mac_fc(hw);
2884 if (ret_val) {
2885 DEBUGOUT("Error forcing flow control settings\n");
2886 return ret_val;
2887 }
2888 } else {
2889 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2890 }
2891 }
2892 return E1000_SUCCESS;
2893 }
2894
2895 /******************************************************************************
2896 * Checks to see if the link status of the hardware has changed.
2897 *
2898 * hw - Struct containing variables accessed by shared code
2899 *
2900 * Called by any function that needs to check the link status of the adapter.
2901 *****************************************************************************/
2902 int32_t
2903 em_check_for_link(struct em_hw *hw)
2904 {
2905 uint32_t rxcw = 0;
2906 uint32_t ctrl;
2907 uint32_t status;
2908 uint32_t rctl;
2909 uint32_t icr;
2910 uint32_t signal = 0;
2911 int32_t ret_val;
2912 uint16_t phy_data;
2913
2914 DEBUGFUNC("em_check_for_link");
2915
2916 ctrl = E1000_READ_REG(hw, CTRL);
2917 status = E1000_READ_REG(hw, STATUS);
2918
2919 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2920 * set when the optics detect a signal. On older adapters, it will be
2921 * cleared when there is a signal. This applies to fiber media only.
2922 */
2923 if ((hw->media_type == em_media_type_fiber) ||
2924 (hw->media_type == em_media_type_internal_serdes)) {
2925 rxcw = E1000_READ_REG(hw, RXCW);
2926
2927 if (hw->media_type == em_media_type_fiber) {
2928 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
2929 if (status & E1000_STATUS_LU)
2930 hw->get_link_status = FALSE;
2931 }
2932 }
2933
2934 /* If we have a copper PHY then we only want to go out to the PHY
2935 * registers to see if Auto-Neg has completed and/or if our link
2936 * status has changed. The get_link_status flag will be set if we
2937 * receive a Link Status Change interrupt or we have Rx Sequence
2938 * Errors.
2939 */
2940 if ((hw->media_type == em_media_type_copper) && hw->get_link_status) {
2941 /* First we want to see if the MII Status Register reports
2942 * link. If so, then we want to get the current speed/duplex
2943 * of the PHY.
2944 * Read the register twice since the link bit is sticky.
2945 */
2946 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2947 if (ret_val)
2948 return ret_val;
2949 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2950 if (ret_val)
2951 return ret_val;
2952
2953 if (phy_data & MII_SR_LINK_STATUS) {
2954 hw->get_link_status = FALSE;
2955 /* Check if there was DownShift, must be checked immediately after
2956 * link-up */
2957 em_check_downshift(hw);
2958
2959 /* If we are on 82544 or 82543 silicon and speed/duplex
2960 * are forced to 10H or 10F, then we will implement the polarity
2961 * reversal workaround. We disable interrupts first, and upon
2962 * returning, place the devices interrupt state to its previous
2963 * value except for the link status change interrupt which will
2964 * happen due to the execution of this workaround.
2965 */
2966
2967 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
2968 (!hw->autoneg) &&
2969 (hw->forced_speed_duplex == em_10_full ||
2970 hw->forced_speed_duplex == em_10_half)) {
2971 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2972 ret_val = em_polarity_reversal_workaround(hw);
2973 icr = E1000_READ_REG(hw, ICR);
2974 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2975 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2976 }
2977
2978 } else {
2979 /* No link detected */
2980 em_config_dsp_after_link_change(hw, FALSE);
2981 return 0;
2982 }
2983
2984 /* If we are forcing speed/duplex, then we simply return since
2985 * we have already determined whether we have link or not.
2986 */
2987 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2988
2989 /* optimize the dsp settings for the igp phy */
2990 em_config_dsp_after_link_change(hw, TRUE);
2991
2992 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2993 * have Si on board that is 82544 or newer, Auto
2994 * Speed Detection takes care of MAC speed/duplex
2995 * configuration. So we only need to configure Collision
2996 * Distance in the MAC. Otherwise, we need to force
2997 * speed/duplex on the MAC to the current PHY speed/duplex
2998 * settings.
2999 */
3000 if (hw->mac_type >= em_82544)
3001 em_config_collision_dist(hw);
3002 else {
3003 ret_val = em_config_mac_to_phy(hw);
3004 if (ret_val) {
3005 DEBUGOUT("Error configuring MAC to PHY settings\n");
3006 return ret_val;
3007 }
3008 }
3009
3010 /* Configure Flow Control now that Auto-Neg has completed. First, we
3011 * need to restore the desired flow control settings because we may
3012 * have had to re-autoneg with a different link partner.
3013 */
3014 ret_val = em_config_fc_after_link_up(hw);
3015 if (ret_val) {
3016 DEBUGOUT("Error configuring flow control\n");
3017 return ret_val;
3018 }
3019
3020 /* At this point we know that we are on copper and we have
3021 * auto-negotiated link. These are conditions for checking the link
3022 * partner capability register. We use the link speed to determine if
3023 * TBI compatibility needs to be turned on or off. If the link is not
3024 * at gigabit speed, then TBI compatibility is not needed. If we are
3025 * at gigabit speed, we turn on TBI compatibility.
3026 */
3027 if (hw->tbi_compatibility_en) {
3028 uint16_t speed, duplex;
3029 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
3030 if (ret_val) {
3031 DEBUGOUT("Error getting link speed and duplex\n");
3032 return ret_val;
3033 }
3034 if (speed != SPEED_1000) {
3035 /* If link speed is not set to gigabit speed, we do not need
3036 * to enable TBI compatibility.
3037 */
3038 if (hw->tbi_compatibility_on) {
3039 /* If we previously were in the mode, turn it off. */
3040 rctl = E1000_READ_REG(hw, RCTL);
3041 rctl &= ~E1000_RCTL_SBP;
3042 E1000_WRITE_REG(hw, RCTL, rctl);
3043 hw->tbi_compatibility_on = FALSE;
3044 }
3045 } else {
3046 /* If TBI compatibility is was previously off, turn it on. For
3047 * compatibility with a TBI link partner, we will store bad
3048 * packets. Some frames have an additional byte on the end and
3049 * will look like CRC errors to to the hardware.
3050 */
3051 if (!hw->tbi_compatibility_on) {
3052 hw->tbi_compatibility_on = TRUE;
3053 rctl = E1000_READ_REG(hw, RCTL);
3054 rctl |= E1000_RCTL_SBP;
3055 E1000_WRITE_REG(hw, RCTL, rctl);
3056 }
3057 }
3058 }
3059 }
3060 /* If we don't have link (auto-negotiation failed or link partner cannot
3061 * auto-negotiate), the cable is plugged in (we have signal), and our
3062 * link partner is not trying to auto-negotiate with us (we are receiving
3063 * idles or data), we need to force link up. We also need to give
3064 * auto-negotiation time to complete, in case the cable was just plugged
3065 * in. The autoneg_failed flag does this.
3066 */
3067 else if ((((hw->media_type == em_media_type_fiber) &&
3068 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3069 (hw->media_type == em_media_type_internal_serdes)) &&
3070 (!(status & E1000_STATUS_LU)) &&
3071 (!(rxcw & E1000_RXCW_C))) {
3072 if (hw->autoneg_failed == 0) {
3073 hw->autoneg_failed = 1;
3074 return 0;
3075 }
3076 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3077
3078 /* Disable auto-negotiation in the TXCW register */
3079 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3080
3081 /* Force link-up and also force full-duplex. */
3082 ctrl = E1000_READ_REG(hw, CTRL);
3083 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3084 E1000_WRITE_REG(hw, CTRL, ctrl);
3085
3086 /* Configure Flow Control after forcing link up. */
3087 ret_val = em_config_fc_after_link_up(hw);
3088 if (ret_val) {
3089 DEBUGOUT("Error configuring flow control\n");
3090 return ret_val;
3091 }
3092 }
3093 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3094 * auto-negotiation in the TXCW register and disable forced link in the
3095 * Device Control register in an attempt to auto-negotiate with our link
3096 * partner.
3097 */
3098 else if (((hw->media_type == em_media_type_fiber) ||
3099 (hw->media_type == em_media_type_internal_serdes)) &&
3100 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3101 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3102 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3103 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3104
3105 hw->serdes_link_down = FALSE;
3106 }
3107 /* If we force link for non-auto-negotiation switch, check link status
3108 * based on MAC synchronization for internal serdes media type.
3109 */
3110 else if ((hw->media_type == em_media_type_internal_serdes) &&
3111 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3112 /* SYNCH bit and IV bit are sticky. */
3113 usec_delay(10);
3114 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3115 if (!(rxcw & E1000_RXCW_IV)) {
3116 hw->serdes_link_down = FALSE;
3117 DEBUGOUT("SERDES: Link is up.\n");
3118 }
3119 } else {
3120 hw->serdes_link_down = TRUE;
3121 DEBUGOUT("SERDES: Link is down.\n");
3122 }
3123 }
3124 if ((hw->media_type == em_media_type_internal_serdes) &&
3125 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3126 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3127 }
3128 return E1000_SUCCESS;
3129 }
3130
3131 /******************************************************************************
3132 * Detects the current speed and duplex settings of the hardware.
3133 *
3134 * hw - Struct containing variables accessed by shared code
3135 * speed - Speed of the connection
3136 * duplex - Duplex setting of the connection
3137 *****************************************************************************/
3138 int32_t
3139 em_get_speed_and_duplex(struct em_hw *hw,
3140 uint16_t *speed,
3141 uint16_t *duplex)
3142 {
3143 uint32_t status;
3144 int32_t ret_val;
3145 uint16_t phy_data;
3146
3147 DEBUGFUNC("em_get_speed_and_duplex");
3148
3149 if (hw->mac_type >= em_82543) {
3150 status = E1000_READ_REG(hw, STATUS);
3151 if (status & E1000_STATUS_SPEED_1000) {
3152 *speed = SPEED_1000;
3153 DEBUGOUT("1000 Mbs, ");
3154 } else if (status & E1000_STATUS_SPEED_100) {
3155 *speed = SPEED_100;
3156 DEBUGOUT("100 Mbs, ");
3157 } else {
3158 *speed = SPEED_10;
3159 DEBUGOUT("10 Mbs, ");
3160 }
3161
3162 if (status & E1000_STATUS_FD) {
3163 *duplex = FULL_DUPLEX;
3164 DEBUGOUT("Full Duplex\n");
3165 } else {
3166 *duplex = HALF_DUPLEX;
3167 DEBUGOUT(" Half Duplex\n");
3168 }
3169 } else {
3170 DEBUGOUT("1000 Mbs, Full Duplex\n");
3171 *speed = SPEED_1000;
3172 *duplex = FULL_DUPLEX;
3173 }
3174
3175 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3176 * if it is operating at half duplex. Here we set the duplex settings to
3177 * match the duplex in the link partner's capabilities.
3178 */
3179 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
3180 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3181 if (ret_val)
3182 return ret_val;
3183
3184 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3185 *duplex = HALF_DUPLEX;
3186 else {
3187 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3188 if (ret_val)
3189 return ret_val;
3190 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3191 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3192 *duplex = HALF_DUPLEX;
3193 }
3194 }
3195
3196 if ((hw->mac_type == em_80003es2lan) &&
3197 (hw->media_type == em_media_type_copper)) {
3198 if (*speed == SPEED_1000)
3199 ret_val = em_configure_kmrn_for_1000(hw);
3200 else
3201 ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
3202 if (ret_val)
3203 return ret_val;
3204 }
3205
3206 if ((hw->phy_type == em_phy_igp_3) && (*speed == SPEED_1000)) {
3207 ret_val = em_kumeran_lock_loss_workaround(hw);
3208 if (ret_val)
3209 return ret_val;
3210 }
3211
3212 return E1000_SUCCESS;
3213 }
3214
3215 /******************************************************************************
3216 * Blocks until autoneg completes or times out (~4.5 seconds)
3217 *
3218 * hw - Struct containing variables accessed by shared code
3219 ******************************************************************************/
3220 STATIC int32_t
3221 em_wait_autoneg(struct em_hw *hw)
3222 {
3223 int32_t ret_val;
3224 uint16_t i;
3225 uint16_t phy_data;
3226
3227 DEBUGFUNC("em_wait_autoneg");
3228 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3229
3230 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3231 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3232 /* Read the MII Status Register and wait for Auto-Neg
3233 * Complete bit to be set.
3234 */
3235 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3236 if (ret_val)
3237 return ret_val;
3238 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3239 if (ret_val)
3240 return ret_val;
3241 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3242 return E1000_SUCCESS;
3243 }
3244 msec_delay(100);
3245 }
3246 return E1000_SUCCESS;
3247 }
3248
3249 /******************************************************************************
3250 * Raises the Management Data Clock
3251 *
3252 * hw - Struct containing variables accessed by shared code
3253 * ctrl - Device control register's current value
3254 ******************************************************************************/
3255 static void
3256 em_raise_mdi_clk(struct em_hw *hw,
3257 uint32_t *ctrl)
3258 {
3259 /* Raise the clock input to the Management Data Clock (by setting the MDC
3260 * bit), and then delay 10 microseconds.
3261 */
3262 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3263 E1000_WRITE_FLUSH(hw);
3264 usec_delay(10);
3265 }
3266
3267 /******************************************************************************
3268 * Lowers the Management Data Clock
3269 *
3270 * hw - Struct containing variables accessed by shared code
3271 * ctrl - Device control register's current value
3272 ******************************************************************************/
3273 static void
3274 em_lower_mdi_clk(struct em_hw *hw,
3275 uint32_t *ctrl)
3276 {
3277 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3278 * bit), and then delay 10 microseconds.
3279 */
3280 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3281 E1000_WRITE_FLUSH(hw);
3282 usec_delay(10);
3283 }
3284
3285 /******************************************************************************
3286 * Shifts data bits out to the PHY
3287 *
3288 * hw - Struct containing variables accessed by shared code
3289 * data - Data to send out to the PHY
3290 * count - Number of bits to shift out
3291 *
3292 * Bits are shifted out in MSB to LSB order.
3293 ******************************************************************************/
3294 static void
3295 em_shift_out_mdi_bits(struct em_hw *hw,
3296 uint32_t data,
3297 uint16_t count)
3298 {
3299 uint32_t ctrl;
3300 uint32_t mask;
3301
3302 /* We need to shift "count" number of bits out to the PHY. So, the value
3303 * in the "data" parameter will be shifted out to the PHY one bit at a
3304 * time. In order to do this, "data" must be broken down into bits.
3305 */
3306 mask = 0x01;
3307 mask <<= (count - 1);
3308
3309 ctrl = E1000_READ_REG(hw, CTRL);
3310
3311 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3312 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3313
3314 while (mask) {
3315 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3316 * then raising and lowering the Management Data Clock. A "0" is
3317 * shifted out to the PHY by setting the MDIO bit to "0" and then
3318 * raising and lowering the clock.
3319 */
3320 if (data & mask)
3321 ctrl |= E1000_CTRL_MDIO;
3322 else
3323 ctrl &= ~E1000_CTRL_MDIO;
3324
3325 E1000_WRITE_REG(hw, CTRL, ctrl);
3326 E1000_WRITE_FLUSH(hw);
3327
3328 usec_delay(10);
3329
3330 em_raise_mdi_clk(hw, &ctrl);
3331 em_lower_mdi_clk(hw, &ctrl);
3332
3333 mask = mask >> 1;
3334 }
3335 }
3336
3337 /******************************************************************************
3338 * Shifts data bits in from the PHY
3339 *
3340 * hw - Struct containing variables accessed by shared code
3341 *
3342 * Bits are shifted in in MSB to LSB order.
3343 ******************************************************************************/
3344 static uint16_t
3345 em_shift_in_mdi_bits(struct em_hw *hw)
3346 {
3347 uint32_t ctrl;
3348 uint16_t data = 0;
3349 uint8_t i;
3350
3351 /* In order to read a register from the PHY, we need to shift in a total
3352 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3353 * to avoid contention on the MDIO pin when a read operation is performed.
3354 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3355 * by raising the input to the Management Data Clock (setting the MDC bit),
3356 * and then reading the value of the MDIO bit.
3357 */
3358 ctrl = E1000_READ_REG(hw, CTRL);
3359
3360 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3361 ctrl &= ~E1000_CTRL_MDIO_DIR;
3362 ctrl &= ~E1000_CTRL_MDIO;
3363
3364 E1000_WRITE_REG(hw, CTRL, ctrl);
3365 E1000_WRITE_FLUSH(hw);
3366
3367 /* Raise and Lower the clock before reading in the data. This accounts for
3368 * the turnaround bits. The first clock occurred when we clocked out the
3369 * last bit of the Register Address.
3370 */
3371 em_raise_mdi_clk(hw, &ctrl);
3372 em_lower_mdi_clk(hw, &ctrl);
3373
3374 for (data = 0, i = 0; i < 16; i++) {
3375 data = data << 1;
3376 em_raise_mdi_clk(hw, &ctrl);
3377 ctrl = E1000_READ_REG(hw, CTRL);
3378 /* Check to see if we shifted in a "1". */
3379 if (ctrl & E1000_CTRL_MDIO)
3380 data |= 1;
3381 em_lower_mdi_clk(hw, &ctrl);
3382 }
3383
3384 em_raise_mdi_clk(hw, &ctrl);
3385 em_lower_mdi_clk(hw, &ctrl);
3386
3387 return data;
3388 }
3389
3390 STATIC int32_t
3391 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
3392 {
3393 uint32_t swfw_sync = 0;
3394 uint32_t swmask = mask;
3395 uint32_t fwmask = mask << 16;
3396 int32_t timeout = 200;
3397
3398 DEBUGFUNC("em_swfw_sync_acquire");
3399
3400 if (hw->swfwhw_semaphore_present)
3401 return em_get_software_flag(hw);
3402
3403 if (!hw->swfw_sync_present)
3404 return em_get_hw_eeprom_semaphore(hw);
3405
3406 while (timeout) {
3407 if (em_get_hw_eeprom_semaphore(hw))
3408 return -E1000_ERR_SWFW_SYNC;
3409
3410 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3411 if (!(swfw_sync & (fwmask | swmask))) {
3412 break;
3413 }
3414
3415 /* firmware currently using resource (fwmask) */
3416 /* or other software thread currently using resource (swmask) */
3417 em_put_hw_eeprom_semaphore(hw);
3418 msec_delay_irq(5);
3419 timeout--;
3420 }
3421
3422 if (!timeout) {
3423 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3424 return -E1000_ERR_SWFW_SYNC;
3425 }
3426
3427 swfw_sync |= swmask;
3428 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3429
3430 em_put_hw_eeprom_semaphore(hw);
3431 return E1000_SUCCESS;
3432 }
3433
3434 STATIC void
3435 em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
3436 {
3437 uint32_t swfw_sync;
3438 uint32_t swmask = mask;
3439
3440 DEBUGFUNC("em_swfw_sync_release");
3441
3442 if (hw->swfwhw_semaphore_present) {
3443 em_release_software_flag(hw);
3444 return;
3445 }
3446
3447 if (!hw->swfw_sync_present) {
3448 em_put_hw_eeprom_semaphore(hw);
3449 return;
3450 }
3451
3452 /* if (em_get_hw_eeprom_semaphore(hw))
3453 * return -E1000_ERR_SWFW_SYNC; */
3454 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3455 /* empty */
3456
3457 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3458 swfw_sync &= ~swmask;
3459 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3460
3461 em_put_hw_eeprom_semaphore(hw);
3462 }
3463
3464 /*****************************************************************************
3465 * Reads the value from a PHY register, if the value is on a specific non zero
3466 * page, sets the page first.
3467 * hw - Struct containing variables accessed by shared code
3468 * reg_addr - address of the PHY register to read
3469 ******************************************************************************/
3470 int32_t
3471 em_read_phy_reg(struct em_hw *hw,
3472 uint32_t reg_addr,
3473 uint16_t *phy_data)
3474 {
3475 uint32_t ret_val;
3476 uint16_t swfw;
3477
3478 DEBUGFUNC("em_read_phy_reg");
3479
3480 if ((hw->mac_type == em_80003es2lan) &&
3481 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3482 swfw = E1000_SWFW_PHY1_SM;
3483 } else {
3484 swfw = E1000_SWFW_PHY0_SM;
3485 }
3486 if (em_swfw_sync_acquire(hw, swfw))
3487 return -E1000_ERR_SWFW_SYNC;
3488
3489 if ((hw->phy_type == em_phy_igp ||
3490 hw->phy_type == em_phy_igp_3 ||
3491 hw->phy_type == em_phy_igp_2) &&
3492 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3493 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3494 (uint16_t)reg_addr);
3495 if (ret_val) {
3496 em_swfw_sync_release(hw, swfw);
3497 return ret_val;
3498 }
3499 } else if (hw->phy_type == em_phy_gg82563) {
3500 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3501 (hw->mac_type == em_80003es2lan)) {
3502 /* Select Configuration Page */
3503 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3504 ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3505 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3506 } else {
3507 /* Use Alternative Page Select register to access
3508 * registers 30 and 31
3509 */
3510 ret_val = em_write_phy_reg_ex(hw,
3511 GG82563_PHY_PAGE_SELECT_ALT,
3512 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3513 }
3514
3515 if (ret_val) {
3516 em_swfw_sync_release(hw, swfw);
3517 return ret_val;
3518 }
3519 }
3520 }
3521
3522 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3523 phy_data);
3524
3525 em_swfw_sync_release(hw, swfw);
3526 return ret_val;
3527 }
3528
3529 STATIC int32_t
3530 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
3531 uint16_t *phy_data)
3532 {
3533 uint32_t i;
3534 uint32_t mdic = 0;
3535 const uint32_t phy_addr = 1;
3536
3537 DEBUGFUNC("em_read_phy_reg_ex");
3538
3539 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3540 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3541 return -E1000_ERR_PARAM;
3542 }
3543
3544 if (hw->mac_type > em_82543) {
3545 /* Set up Op-code, Phy Address, and register address in the MDI
3546 * Control register. The MAC will take care of interfacing with the
3547 * PHY to retrieve the desired data.
3548 */
3549 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3550 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3551 (E1000_MDIC_OP_READ));
3552
3553 E1000_WRITE_REG(hw, MDIC, mdic);
3554
3555 /* Poll the ready bit to see if the MDI read completed */
3556 for (i = 0; i < 64; i++) {
3557 usec_delay(50);
3558 mdic = E1000_READ_REG(hw, MDIC);
3559 if (mdic & E1000_MDIC_READY) break;
3560 }
3561 if (!(mdic & E1000_MDIC_READY)) {
3562 DEBUGOUT("MDI Read did not complete\n");
3563 return -E1000_ERR_PHY;
3564 }
3565 if (mdic & E1000_MDIC_ERROR) {
3566 DEBUGOUT("MDI Error\n");
3567 return -E1000_ERR_PHY;
3568 }
3569 *phy_data = (uint16_t) mdic;
3570 } else {
3571 /* We must first send a preamble through the MDIO pin to signal the
3572 * beginning of an MII instruction. This is done by sending 32
3573 * consecutive "1" bits.
3574 */
3575 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3576
3577 /* Now combine the next few fields that are required for a read
3578 * operation. We use this method instead of calling the
3579 * em_shift_out_mdi_bits routine five different times. The format of
3580 * a MII read instruction consists of a shift out of 14 bits and is
3581 * defined as follows:
3582 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3583 * followed by a shift in of 18 bits. This first two bits shifted in
3584 * are TurnAround bits used to avoid contention on the MDIO pin when a
3585 * READ operation is performed. These two bits are thrown away
3586 * followed by a shift in of 16 bits which contains the desired data.
3587 */
3588 mdic = ((reg_addr) | (phy_addr << 5) |
3589 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3590
3591 em_shift_out_mdi_bits(hw, mdic, 14);
3592
3593 /* Now that we've shifted out the read command to the MII, we need to
3594 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3595 * register address.
3596 */
3597 *phy_data = em_shift_in_mdi_bits(hw);
3598 }
3599 return E1000_SUCCESS;
3600 }
3601
3602 /******************************************************************************
3603 * Writes a value to a PHY register
3604 *
3605 * hw - Struct containing variables accessed by shared code
3606 * reg_addr - address of the PHY register to write
3607 * data - data to write to the PHY
3608 ******************************************************************************/
3609 int32_t
3610 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr,
3611 uint16_t phy_data)
3612 {
3613 uint32_t ret_val;
3614 uint16_t swfw;
3615
3616 DEBUGFUNC("em_write_phy_reg");
3617
3618 if ((hw->mac_type == em_80003es2lan) &&
3619 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3620 swfw = E1000_SWFW_PHY1_SM;
3621 } else {
3622 swfw = E1000_SWFW_PHY0_SM;
3623 }
3624 if (em_swfw_sync_acquire(hw, swfw))
3625 return -E1000_ERR_SWFW_SYNC;
3626
3627 if ((hw->phy_type == em_phy_igp ||
3628 hw->phy_type == em_phy_igp_3 ||
3629 hw->phy_type == em_phy_igp_2) &&
3630 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3631 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3632 (uint16_t)reg_addr);
3633 if (ret_val) {
3634 em_swfw_sync_release(hw, swfw);
3635 return ret_val;
3636 }
3637 } else if (hw->phy_type == em_phy_gg82563) {
3638 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3639 (hw->mac_type == em_80003es2lan)) {
3640 /* Select Configuration Page */
3641 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3642 ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3643 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3644 } else {
3645 /* Use Alternative Page Select register to access
3646 * registers 30 and 31
3647 */
3648 ret_val = em_write_phy_reg_ex(hw,
3649 GG82563_PHY_PAGE_SELECT_ALT,
3650 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3651 }
3652
3653 if (ret_val) {
3654 em_swfw_sync_release(hw, swfw);
3655 return ret_val;
3656 }
3657 }
3658 }
3659
3660 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3661 phy_data);
3662
3663 em_swfw_sync_release(hw, swfw);
3664 return ret_val;
3665 }
3666
3667 STATIC int32_t
3668 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
3669 uint16_t phy_data)
3670 {
3671 uint32_t i;
3672 uint32_t mdic = 0;
3673 const uint32_t phy_addr = 1;
3674
3675 DEBUGFUNC("em_write_phy_reg_ex");
3676
3677 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3678 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3679 return -E1000_ERR_PARAM;
3680 }
3681
3682 if (hw->mac_type > em_82543) {
3683 /* Set up Op-code, Phy Address, register address, and data intended
3684 * for the PHY register in the MDI Control register. The MAC will take
3685 * care of interfacing with the PHY to send the desired data.
3686 */
3687 mdic = (((uint32_t) phy_data) |
3688 (reg_addr << E1000_MDIC_REG_SHIFT) |
3689 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3690 (E1000_MDIC_OP_WRITE));
3691
3692 E1000_WRITE_REG(hw, MDIC, mdic);
3693
3694 /* Poll the ready bit to see if the MDI read completed */
3695 for (i = 0; i < 641; i++) {
3696 usec_delay(5);
3697 mdic = E1000_READ_REG(hw, MDIC);
3698 if (mdic & E1000_MDIC_READY) break;
3699 }
3700 if (!(mdic & E1000_MDIC_READY)) {
3701 DEBUGOUT("MDI Write did not complete\n");
3702 return -E1000_ERR_PHY;
3703 }
3704 } else {
3705 /* We'll need to use the SW defined pins to shift the write command
3706 * out to the PHY. We first send a preamble to the PHY to signal the
3707 * beginning of the MII instruction. This is done by sending 32
3708 * consecutive "1" bits.
3709 */
3710 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3711
3712 /* Now combine the remaining required fields that will indicate a
3713 * write operation. We use this method instead of calling the
3714 * em_shift_out_mdi_bits routine for each field in the command. The
3715 * format of a MII write instruction is as follows:
3716 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3717 */
3718 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3719 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3720 mdic <<= 16;
3721 mdic |= (uint32_t) phy_data;
3722
3723 em_shift_out_mdi_bits(hw, mdic, 32);
3724 }
3725
3726 return E1000_SUCCESS;
3727 }
3728
3729 STATIC int32_t
3730 em_read_kmrn_reg(struct em_hw *hw,
3731 uint32_t reg_addr,
3732 uint16_t *data)
3733 {
3734 uint32_t reg_val;
3735 uint16_t swfw;
3736 DEBUGFUNC("em_read_kmrn_reg");
3737
3738 if ((hw->mac_type == em_80003es2lan) &&
3739 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3740 swfw = E1000_SWFW_PHY1_SM;
3741 } else {
3742 swfw = E1000_SWFW_PHY0_SM;
3743 }
3744 if (em_swfw_sync_acquire(hw, swfw))
3745 return -E1000_ERR_SWFW_SYNC;
3746
3747 /* Write register address */
3748 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3749 E1000_KUMCTRLSTA_OFFSET) |
3750 E1000_KUMCTRLSTA_REN;
3751 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3752 usec_delay(2);
3753
3754 /* Read the data returned */
3755 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3756 *data = (uint16_t)reg_val;
3757
3758 em_swfw_sync_release(hw, swfw);
3759 return E1000_SUCCESS;
3760 }
3761
3762 STATIC int32_t
3763 em_write_kmrn_reg(struct em_hw *hw,
3764 uint32_t reg_addr,
3765 uint16_t data)
3766 {
3767 uint32_t reg_val;
3768 uint16_t swfw;
3769 DEBUGFUNC("em_write_kmrn_reg");
3770
3771 if ((hw->mac_type == em_80003es2lan) &&
3772 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3773 swfw = E1000_SWFW_PHY1_SM;
3774 } else {
3775 swfw = E1000_SWFW_PHY0_SM;
3776 }
3777 if (em_swfw_sync_acquire(hw, swfw))
3778 return -E1000_ERR_SWFW_SYNC;
3779
3780 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3781 E1000_KUMCTRLSTA_OFFSET) | data;
3782 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3783 usec_delay(2);
3784
3785 em_swfw_sync_release(hw, swfw);
3786 return E1000_SUCCESS;
3787 }
3788
3789 /******************************************************************************
3790 * Returns the PHY to the power-on reset state
3791 *
3792 * hw - Struct containing variables accessed by shared code
3793 ******************************************************************************/
3794 int32_t
3795 em_phy_hw_reset(struct em_hw *hw)
3796 {
3797 uint32_t ctrl, ctrl_ext;
3798 uint32_t led_ctrl;
3799 int32_t ret_val;
3800 uint16_t swfw;
3801
3802 DEBUGFUNC("em_phy_hw_reset");
3803
3804 /* In the case of the phy reset being blocked, it's not an error, we
3805 * simply return success without performing the reset. */
3806 ret_val = em_check_phy_reset_block(hw);
3807 if (ret_val)
3808 return E1000_SUCCESS;
3809
3810 DEBUGOUT("Resetting Phy...\n");
3811
3812 if (hw->mac_type > em_82543) {
3813 if ((hw->mac_type == em_80003es2lan) &&
3814 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3815 swfw = E1000_SWFW_PHY1_SM;
3816 } else {
3817 swfw = E1000_SWFW_PHY0_SM;
3818 }
3819 if (em_swfw_sync_acquire(hw, swfw)) {
3820 DEBUGOUT("Unable to acquire swfw sync\n");
3821 return -E1000_ERR_SWFW_SYNC;
3822 }
3823 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3824 * bit. Then, take it out of reset.
3825 * For pre-em_82571 hardware, we delay for 10ms between the assert
3826 * and deassert. For em_82571 hardware and later, we instead delay
3827 * for 50us between and 10ms after the deassertion.
3828 */
3829 ctrl = E1000_READ_REG(hw, CTRL);
3830 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3831 E1000_WRITE_FLUSH(hw);
3832
3833 if (hw->mac_type < em_82571)
3834 msec_delay(10);
3835 else
3836 usec_delay(100);
3837
3838 E1000_WRITE_REG(hw, CTRL, ctrl);
3839 E1000_WRITE_FLUSH(hw);
3840
3841 if (hw->mac_type >= em_82571)
3842 msec_delay_irq(10);
3843
3844 em_swfw_sync_release(hw, swfw);
3845 } else {
3846 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3847 * bit to put the PHY into reset. Then, take it out of reset.
3848 */
3849 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3850 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3851 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3852 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3853 E1000_WRITE_FLUSH(hw);
3854 msec_delay(10);
3855 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3856 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3857 E1000_WRITE_FLUSH(hw);
3858 }
3859 usec_delay(150);
3860
3861 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
3862 /* Configure activity LED after PHY reset */
3863 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3864 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3865 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3866 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3867 }
3868
3869 /* Wait for FW to finish PHY configuration. */
3870 ret_val = em_get_phy_cfg_done(hw);
3871 if (ret_val != E1000_SUCCESS)
3872 return ret_val;
3873 em_release_software_semaphore(hw);
3874
3875 if (((hw->mac_type == em_ich8lan) || (hw->mac_type == em_ich9lan))
3876 && (hw->phy_type == em_phy_igp_3))
3877 ret_val = em_init_lcd_from_nvm(hw);
3878
3879 return ret_val;
3880 }
3881
3882 /******************************************************************************
3883 * Resets the PHY
3884 *
3885 * hw - Struct containing variables accessed by shared code
3886 *
3887 * Sets bit 15 of the MII Control regiser
3888 ******************************************************************************/
3889 int32_t
3890 em_phy_reset(struct em_hw *hw)
3891 {
3892 int32_t ret_val;
3893 uint16_t phy_data;
3894
3895 DEBUGFUNC("em_phy_reset");
3896
3897 /* In the case of the phy reset being blocked, it's not an error, we
3898 * simply return success without performing the reset. */
3899 ret_val = em_check_phy_reset_block(hw);
3900 if (ret_val)
3901 return E1000_SUCCESS;
3902
3903 switch (hw->phy_type) {
3904 case em_phy_igp:
3905 case em_phy_igp_2:
3906 case em_phy_igp_3:
3907 case em_phy_ife:
3908 ret_val = em_phy_hw_reset(hw);
3909 if (ret_val)
3910 return ret_val;
3911 break;
3912 default:
3913 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
3914 if (ret_val)
3915 return ret_val;
3916
3917 phy_data |= MII_CR_RESET;
3918 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
3919 if (ret_val)
3920 return ret_val;
3921
3922 usec_delay(1);
3923 break;
3924 }
3925
3926 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
3927 em_phy_init_script(hw);
3928
3929 return E1000_SUCCESS;
3930 }
3931
3932 /******************************************************************************
3933 * Work-around for 82566 power-down: on D3 entry-
3934 * 1) disable gigabit link
3935 * 2) write VR power-down enable
3936 * 3) read it back
3937 * if successful continue, else issue LCD reset and repeat
3938 *
3939 * hw - struct containing variables accessed by shared code
3940 ******************************************************************************/
3941 void
3942 em_phy_powerdown_workaround(struct em_hw *hw)
3943 {
3944 int32_t reg;
3945 uint16_t phy_data;
3946 int32_t retry = 0;
3947
3948 DEBUGFUNC("em_phy_powerdown_workaround");
3949
3950 if (hw->phy_type != em_phy_igp_3)
3951 return;
3952
3953 do {
3954 /* Disable link */
3955 reg = E1000_READ_REG(hw, PHY_CTRL);
3956 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3957 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3958
3959 /* Write VR power-down enable - bits 9:8 should be 10b */
3960 em_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3961 phy_data |= (1 << 9);
3962 phy_data &= ~(1 << 8);
3963 em_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3964
3965 /* Read it back and test */
3966 em_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3967 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3968 break;
3969
3970 /* Issue PHY reset and repeat at most one more time */
3971 reg = E1000_READ_REG(hw, CTRL);
3972 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3973 retry++;
3974 } while (retry);
3975
3976 return;
3977
3978 }
3979
3980 /******************************************************************************
3981 * Work-around for 82566 Kumeran PCS lock loss:
3982 * On link status change (i.e. PCI reset, speed change) and link is up and
3983 * speed is gigabit-
3984 * 0) if workaround is optionally disabled do nothing
3985 * 1) wait 1ms for Kumeran link to come up
3986 * 2) check Kumeran Diagnostic register PCS lock loss bit
3987 * 3) if not set the link is locked (all is good), otherwise...
3988 * 4) reset the PHY
3989 * 5) repeat up to 10 times
3990 * Note: this is only called for IGP3 copper when speed is 1gb.
3991 *
3992 * hw - struct containing variables accessed by shared code
3993 ******************************************************************************/
3994 STATIC int32_t
3995 em_kumeran_lock_loss_workaround(struct em_hw *hw)
3996 {
3997 int32_t ret_val;
3998 int32_t reg;
3999 int32_t cnt;
4000 uint16_t phy_data;
4001
4002 if (hw->kmrn_lock_loss_workaround_disabled)
4003 return E1000_SUCCESS;
4004
4005 /* Make sure link is up before proceeding. If not just return.
4006 * Attempting this while link is negotiating fouled up link
4007 * stability */
4008 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4009 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4010
4011 if (phy_data & MII_SR_LINK_STATUS) {
4012 for (cnt = 0; cnt < 10; cnt++) {
4013 /* read once to clear */
4014 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4015 if (ret_val)
4016 return ret_val;
4017 /* and again to get new status */
4018 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4019 if (ret_val)
4020 return ret_val;
4021
4022 /* check for PCS lock */
4023 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4024 return E1000_SUCCESS;
4025
4026 /* Issue PHY reset */
4027 em_phy_hw_reset(hw);
4028 msec_delay_irq(5);
4029 }
4030 /* Disable GigE link negotiation */
4031 reg = E1000_READ_REG(hw, PHY_CTRL);
4032 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4033 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4034
4035 /* unable to acquire PCS lock */
4036 return E1000_ERR_PHY;
4037 }
4038
4039 return E1000_SUCCESS;
4040 }
4041
4042 /******************************************************************************
4043 * Probes the expected PHY address for known PHY IDs
4044 *
4045 * hw - Struct containing variables accessed by shared code
4046 ******************************************************************************/
4047 STATIC int32_t
4048 em_detect_gig_phy(struct em_hw *hw)
4049 {
4050 int32_t phy_init_status, ret_val;
4051 uint16_t phy_id_high, phy_id_low;
4052 boolean_t match = FALSE;
4053
4054 DEBUGFUNC("em_detect_gig_phy");
4055
4056 if (hw->phy_id != 0)
4057 return E1000_SUCCESS;
4058
4059 /* The 82571 firmware may still be configuring the PHY. In this
4060 * case, we cannot access the PHY until the configuration is done. So
4061 * we explicitly set the PHY values. */
4062 if (hw->mac_type == em_82571 ||
4063 hw->mac_type == em_82572) {
4064 hw->phy_id = IGP01E1000_I_PHY_ID;
4065 hw->phy_type = em_phy_igp_2;
4066 return E1000_SUCCESS;
4067 }
4068
4069 /* ESB-2 PHY reads require em_phy_gg82563 to be set because of a work-
4070 * around that forces PHY page 0 to be set or the reads fail. The rest of
4071 * the code in this routine uses em_read_phy_reg to read the PHY ID.
4072 * So for ESB-2 we need to have this set so our reads won't fail. If the
4073 * attached PHY is not a em_phy_gg82563, the routines below will figure
4074 * this out as well. */
4075 if (hw->mac_type == em_80003es2lan)
4076 hw->phy_type = em_phy_gg82563;
4077
4078 /* Read the PHY ID Registers to identify which PHY is onboard. */
4079 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4080 if (ret_val)
4081 return ret_val;
4082
4083 hw->phy_id = (uint32_t) (phy_id_high << 16);
4084 usec_delay(20);
4085 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4086 if (ret_val)
4087 return ret_val;
4088
4089 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4090 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4091
4092 switch (hw->mac_type) {
4093 case em_82543:
4094 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4095 break;
4096 case em_82544:
4097 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4098 break;
4099 case em_82540:
4100 case em_82545:
4101 case em_82545_rev_3:
4102 case em_82546:
4103 case em_82546_rev_3:
4104 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4105 break;
4106 case em_82541:
4107 case em_82541_rev_2:
4108 case em_82547:
4109 case em_82547_rev_2:
4110 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4111 break;
4112 case em_82573:
4113 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4114 break;
4115 case em_80003es2lan:
4116 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4117 break;
4118 case em_ich8lan:
4119 case em_ich9lan:
4120 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4121 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4122 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4123 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4124 break;
4125 default:
4126 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4127 return -E1000_ERR_CONFIG;
4128 }
4129 phy_init_status = em_set_phy_type(hw);
4130
4131 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4132 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4133 return E1000_SUCCESS;
4134 }
4135 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4136 return -E1000_ERR_PHY;
4137 }
4138
4139 /******************************************************************************
4140 * Resets the PHY's DSP
4141 *
4142 * hw - Struct containing variables accessed by shared code
4143 ******************************************************************************/
4144 static int32_t
4145 em_phy_reset_dsp(struct em_hw *hw)
4146 {
4147 int32_t ret_val;
4148 DEBUGFUNC("em_phy_reset_dsp");
4149
4150 do {
4151 if (hw->phy_type != em_phy_gg82563) {
4152 ret_val = em_write_phy_reg(hw, 29, 0x001d);
4153 if (ret_val) break;
4154 }
4155 ret_val = em_write_phy_reg(hw, 30, 0x00c1);
4156 if (ret_val) break;
4157 ret_val = em_write_phy_reg(hw, 30, 0x0000);
4158 if (ret_val) break;
4159 ret_val = E1000_SUCCESS;
4160 } while (0);
4161
4162 return ret_val;
4163 }
4164
4165 /******************************************************************************
4166 * Get PHY information from various PHY registers for igp PHY only.
4167 *
4168 * hw - Struct containing variables accessed by shared code
4169 * phy_info - PHY information structure
4170 ******************************************************************************/
4171 STATIC int32_t
4172 em_phy_igp_get_info(struct em_hw *hw,
4173 struct em_phy_info *phy_info)
4174 {
4175 int32_t ret_val;
4176 uint16_t phy_data, min_length, max_length, average;
4177 em_rev_polarity polarity;
4178
4179 DEBUGFUNC("em_phy_igp_get_info");
4180
4181 /* The downshift status is checked only once, after link is established,
4182 * and it stored in the hw->speed_downgraded parameter. */
4183 phy_info->downshift = (em_downshift)hw->speed_downgraded;
4184
4185 /* IGP01E1000 does not need to support it. */
4186 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
4187
4188 /* IGP01E1000 always correct polarity reversal */
4189 phy_info->polarity_correction = em_polarity_reversal_enabled;
4190
4191 /* Check polarity status */
4192 ret_val = em_check_polarity(hw, &polarity);
4193 if (ret_val)
4194 return ret_val;
4195
4196 phy_info->cable_polarity = polarity;
4197
4198 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4199 if (ret_val)
4200 return ret_val;
4201
4202 phy_info->mdix_mode = (em_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4203 IGP01E1000_PSSR_MDIX_SHIFT);
4204
4205 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4206 IGP01E1000_PSSR_SPEED_1000MBPS) {
4207 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4208 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4209 if (ret_val)
4210 return ret_val;
4211
4212 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4213 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4214 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4215 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4216 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4217 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4218
4219 /* Get cable length */
4220 ret_val = em_get_cable_length(hw, &min_length, &max_length);
4221 if (ret_val)
4222 return ret_val;
4223
4224 /* Translate to old method */
4225 average = (max_length + min_length) / 2;
4226
4227 if (average <= em_igp_cable_length_50)
4228 phy_info->cable_length = em_cable_length_50;
4229 else if (average <= em_igp_cable_length_80)
4230 phy_info->cable_length = em_cable_length_50_80;
4231 else if (average <= em_igp_cable_length_110)
4232 phy_info->cable_length = em_cable_length_80_110;
4233 else if (average <= em_igp_cable_length_140)
4234 phy_info->cable_length = em_cable_length_110_140;
4235 else
4236 phy_info->cable_length = em_cable_length_140;
4237 }
4238
4239 return E1000_SUCCESS;
4240 }
4241
4242 /******************************************************************************
4243 * Get PHY information from various PHY registers for ife PHY only.
4244 *
4245 * hw - Struct containing variables accessed by shared code
4246 * phy_info - PHY information structure
4247 ******************************************************************************/
4248 STATIC int32_t
4249 em_phy_ife_get_info(struct em_hw *hw,
4250 struct em_phy_info *phy_info)
4251 {
4252 int32_t ret_val;
4253 uint16_t phy_data;
4254 em_rev_polarity polarity;
4255
4256 DEBUGFUNC("em_phy_ife_get_info");
4257
4258 phy_info->downshift = (em_downshift)hw->speed_downgraded;
4259 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
4260
4261 ret_val = em_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4262 if (ret_val)
4263 return ret_val;
4264 phy_info->polarity_correction =
4265 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4266 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4267 em_polarity_reversal_disabled : em_polarity_reversal_enabled;
4268
4269 if (phy_info->polarity_correction == em_polarity_reversal_enabled) {
4270 ret_val = em_check_polarity(hw, &polarity);
4271 if (ret_val)
4272 return ret_val;
4273 } else {
4274 /* Polarity is forced. */
4275 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4276 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4277 em_rev_polarity_reversed : em_rev_polarity_normal;
4278 }
4279 phy_info->cable_polarity = polarity;
4280
4281 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4282 if (ret_val)
4283 return ret_val;
4284
4285 phy_info->mdix_mode = (em_auto_x_mode)
4286 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4287 IFE_PMC_MDIX_MODE_SHIFT);
4288
4289 return E1000_SUCCESS;
4290 }
4291
4292 /******************************************************************************
4293 * Get PHY information from various PHY registers fot m88 PHY only.
4294 *
4295 * hw - Struct containing variables accessed by shared code
4296 * phy_info - PHY information structure
4297 ******************************************************************************/
4298 STATIC int32_t
4299 em_phy_m88_get_info(struct em_hw *hw,
4300 struct em_phy_info *phy_info)
4301 {
4302 int32_t ret_val;
4303 uint16_t phy_data;
4304 em_rev_polarity polarity;
4305
4306 DEBUGFUNC("em_phy_m88_get_info");
4307
4308 /* The downshift status is checked only once, after link is established,
4309 * and it stored in the hw->speed_downgraded parameter. */
4310 phy_info->downshift = (em_downshift)hw->speed_downgraded;
4311
4312 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4313 if (ret_val)
4314 return ret_val;
4315
4316 phy_info->extended_10bt_distance =
4317 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4318 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4319 em_10bt_ext_dist_enable_lower : em_10bt_ext_dist_enable_normal;
4320
4321 phy_info->polarity_correction =
4322 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4323 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4324 em_polarity_reversal_disabled : em_polarity_reversal_enabled;
4325
4326 /* Check polarity status */
4327 ret_val = em_check_polarity(hw, &polarity);
4328 if (ret_val)
4329 return ret_val;
4330 phy_info->cable_polarity = polarity;
4331
4332 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4333 if (ret_val)
4334 return ret_val;
4335
4336 phy_info->mdix_mode = (em_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4337 M88E1000_PSSR_MDIX_SHIFT);
4338
4339 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4340 /* Cable Length Estimation and Local/Remote Receiver Information
4341 * are only valid at 1000 Mbps.
4342 */
4343 if (hw->phy_type != em_phy_gg82563) {
4344 phy_info->cable_length = (em_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4345 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4346 } else {
4347 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4348 &phy_data);
4349 if (ret_val)
4350 return ret_val;
4351
4352 phy_info->cable_length = (em_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4353 }
4354
4355 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4356 if (ret_val)
4357 return ret_val;
4358
4359 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4360 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4361 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4362 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4363 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4364 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4365
4366 }
4367
4368 return E1000_SUCCESS;
4369 }
4370
4371 /******************************************************************************
4372 * Get PHY information from various PHY registers
4373 *
4374 * hw - Struct containing variables accessed by shared code
4375 * phy_info - PHY information structure
4376 ******************************************************************************/
4377 int32_t
4378 em_phy_get_info(struct em_hw *hw,
4379 struct em_phy_info *phy_info)
4380 {
4381 int32_t ret_val;
4382 uint16_t phy_data;
4383
4384 DEBUGFUNC("em_phy_get_info");
4385
4386 phy_info->cable_length = em_cable_length_undefined;
4387 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
4388 phy_info->cable_polarity = em_rev_polarity_undefined;
4389 phy_info->downshift = em_downshift_undefined;
4390 phy_info->polarity_correction = em_polarity_reversal_undefined;
4391 phy_info->mdix_mode = em_auto_x_mode_undefined;
4392 phy_info->local_rx = em_1000t_rx_status_undefined;
4393 phy_info->remote_rx = em_1000t_rx_status_undefined;
4394
4395 if (hw->media_type != em_media_type_copper) {
4396 DEBUGOUT("PHY info is only valid for copper media\n");
4397 return -E1000_ERR_CONFIG;
4398 }
4399
4400 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4401 if (ret_val)
4402 return ret_val;
4403
4404 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4405 if (ret_val)
4406 return ret_val;
4407
4408 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4409 DEBUGOUT("PHY info is only valid if link is up\n");
4410 return -E1000_ERR_CONFIG;
4411 }
4412
4413 if (hw->phy_type == em_phy_igp ||
4414 hw->phy_type == em_phy_igp_3 ||
4415 hw->phy_type == em_phy_igp_2)
4416 return em_phy_igp_get_info(hw, phy_info);
4417 else if (hw->phy_type == em_phy_ife)
4418 return em_phy_ife_get_info(hw, phy_info);
4419 else
4420 return em_phy_m88_get_info(hw, phy_info);
4421 }
4422
4423 int32_t
4424 em_validate_mdi_setting(struct em_hw *hw)
4425 {
4426 DEBUGFUNC("em_validate_mdi_settings");
4427
4428 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4429 DEBUGOUT("Invalid MDI setting detected\n");
4430 hw->mdix = 1;
4431 return -E1000_ERR_CONFIG;
4432 }
4433 return E1000_SUCCESS;
4434 }
4435
4436
4437 /******************************************************************************
4438 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4439 * is configured. Additionally, if this is ICH8, the flash controller GbE
4440 * registers must be mapped, or this will crash.
4441 *
4442 * hw - Struct containing variables accessed by shared code
4443 *****************************************************************************/
4444 int32_t
4445 em_init_eeprom_params(struct em_hw *hw)
4446 {
4447 struct em_eeprom_info *eeprom = &hw->eeprom;
4448 uint32_t eecd = E1000_READ_REG(hw, EECD);
4449 int32_t ret_val = E1000_SUCCESS;
4450 uint16_t eeprom_size;
4451
4452 DEBUGFUNC("em_init_eeprom_params");
4453
4454 switch (hw->mac_type) {
4455 case em_82542_rev2_0:
4456 case em_82542_rev2_1:
4457 case em_82543:
4458 case em_82544:
4459 eeprom->type = em_eeprom_microwire;
4460 eeprom->word_size = 64;
4461 eeprom->opcode_bits = 3;
4462 eeprom->address_bits = 6;
4463 eeprom->delay_usec = 50;
4464 eeprom->use_eerd = FALSE;
4465 eeprom->use_eewr = FALSE;
4466 break;
4467 case em_82540:
4468 case em_82545:
4469 case em_82545_rev_3:
4470 case em_82546:
4471 case em_82546_rev_3:
4472 eeprom->type = em_eeprom_microwire;
4473 eeprom->opcode_bits = 3;
4474 eeprom->delay_usec = 50;
4475 if (eecd & E1000_EECD_SIZE) {
4476 eeprom->word_size = 256;
4477 eeprom->address_bits = 8;
4478 } else {
4479 eeprom->word_size = 64;
4480 eeprom->address_bits = 6;
4481 }
4482 eeprom->use_eerd = FALSE;
4483 eeprom->use_eewr = FALSE;
4484 break;
4485 case em_82541:
4486 case em_82541_rev_2:
4487 case em_82547:
4488 case em_82547_rev_2:
4489 if (eecd & E1000_EECD_TYPE) {
4490 eeprom->type = em_eeprom_spi;
4491 eeprom->opcode_bits = 8;
4492 eeprom->delay_usec = 1;
4493 if (eecd & E1000_EECD_ADDR_BITS) {
4494 eeprom->page_size = 32;
4495 eeprom->address_bits = 16;
4496 } else {
4497 eeprom->page_size = 8;
4498 eeprom->address_bits = 8;
4499 }
4500 } else {
4501 eeprom->type = em_eeprom_microwire;
4502 eeprom->opcode_bits = 3;
4503 eeprom->delay_usec = 50;
4504 if (eecd & E1000_EECD_ADDR_BITS) {
4505 eeprom->word_size = 256;
4506 eeprom->address_bits = 8;
4507 } else {
4508 eeprom->word_size = 64;
4509 eeprom->address_bits = 6;
4510 }
4511 }
4512 eeprom->use_eerd = FALSE;
4513 eeprom->use_eewr = FALSE;
4514 break;
4515 case em_82571:
4516 case em_82572:
4517 eeprom->type = em_eeprom_spi;
4518 eeprom->opcode_bits = 8;
4519 eeprom->delay_usec = 1;
4520 if (eecd & E1000_EECD_ADDR_BITS) {
4521 eeprom->page_size = 32;
4522 eeprom->address_bits = 16;
4523 } else {
4524 eeprom->page_size = 8;
4525 eeprom->address_bits = 8;
4526 }
4527 eeprom->use_eerd = FALSE;
4528 eeprom->use_eewr = FALSE;
4529 break;
4530 case em_82573:
4531 eeprom->type = em_eeprom_spi;
4532 eeprom->opcode_bits = 8;
4533 eeprom->delay_usec = 1;
4534 if (eecd & E1000_EECD_ADDR_BITS) {
4535 eeprom->page_size = 32;
4536 eeprom->address_bits = 16;
4537 } else {
4538 eeprom->page_size = 8;
4539 eeprom->address_bits = 8;
4540 }
4541 eeprom->use_eerd = TRUE;
4542 eeprom->use_eewr = TRUE;
4543 if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
4544 eeprom->type = em_eeprom_flash;
4545 eeprom->word_size = 2048;
4546
4547 /* Ensure that the Autonomous FLASH update bit is cleared due to
4548 * Flash update issue on parts which use a FLASH for NVM. */
4549 eecd &= ~E1000_EECD_AUPDEN;
4550 E1000_WRITE_REG(hw, EECD, eecd);
4551 }
4552 break;
4553 case em_80003es2lan:
4554 eeprom->type = em_eeprom_spi;
4555 eeprom->opcode_bits = 8;
4556 eeprom->delay_usec = 1;
4557 if (eecd & E1000_EECD_ADDR_BITS) {
4558 eeprom->page_size = 32;
4559 eeprom->address_bits = 16;
4560 } else {
4561 eeprom->page_size = 8;
4562 eeprom->address_bits = 8;
4563 }
4564 eeprom->use_eerd = TRUE;
4565 eeprom->use_eewr = FALSE;
4566 break;
4567 case em_ich8lan:
4568 case em_ich9lan:
4569 {
4570 int32_t i = 0;
4571 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4572
4573 eeprom->type = em_eeprom_ich8;
4574 eeprom->use_eerd = FALSE;
4575 eeprom->use_eewr = FALSE;
4576 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4577
4578 /* Zero the shadow RAM structure. But don't load it from NVM
4579 * so as to save time for driver init */
4580 if (hw->eeprom_shadow_ram != NULL) {
4581 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4582 hw->eeprom_shadow_ram[i].modified = FALSE;
4583 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4584 }
4585 }
4586
4587 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4588 ICH_FLASH_SECTOR_SIZE;
4589
4590 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4591 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4592
4593 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4594
4595 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4596
4597 break;
4598 }
4599 default:
4600 break;
4601 }
4602
4603 if (eeprom->type == em_eeprom_spi) {
4604 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4605 * 32KB (incremented by powers of 2).
4606 */
4607 if (hw->mac_type <= em_82547_rev_2) {
4608 /* Set to default value for initial eeprom read. */
4609 eeprom->word_size = 64;
4610 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4611 if (ret_val)
4612 return ret_val;
4613 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4614 /* 256B eeprom size was not supported in earlier hardware, so we
4615 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4616 * is never the result used in the shifting logic below. */
4617 if (eeprom_size)
4618 eeprom_size++;
4619 } else {
4620 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4621 E1000_EECD_SIZE_EX_SHIFT);
4622 }
4623
4624 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4625 }
4626 return ret_val;
4627 }
4628
4629 /******************************************************************************
4630 * Raises the EEPROM's clock input.
4631 *
4632 * hw - Struct containing variables accessed by shared code
4633 * eecd - EECD's current value
4634 *****************************************************************************/
4635 static void
4636 em_raise_ee_clk(struct em_hw *hw,
4637 uint32_t *eecd)
4638 {
4639 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4640 * wait <delay> microseconds.
4641 */
4642 *eecd = *eecd | E1000_EECD_SK;
4643 E1000_WRITE_REG(hw, EECD, *eecd);
4644 E1000_WRITE_FLUSH(hw);
4645 usec_delay(hw->eeprom.delay_usec);
4646 }
4647
4648 /******************************************************************************
4649 * Lowers the EEPROM's clock input.
4650 *
4651 * hw - Struct containing variables accessed by shared code
4652 * eecd - EECD's current value
4653 *****************************************************************************/
4654 static void
4655 em_lower_ee_clk(struct em_hw *hw,
4656 uint32_t *eecd)
4657 {
4658 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4659 * wait 50 microseconds.
4660 */
4661 *eecd = *eecd & ~E1000_EECD_SK;
4662 E1000_WRITE_REG(hw, EECD, *eecd);
4663 E1000_WRITE_FLUSH(hw);
4664 usec_delay(hw->eeprom.delay_usec);
4665 }
4666
4667 /******************************************************************************
4668 * Shift data bits out to the EEPROM.
4669 *
4670 * hw - Struct containing variables accessed by shared code
4671 * data - data to send to the EEPROM
4672 * count - number of bits to shift out
4673 *****************************************************************************/
4674 static void
4675 em_shift_out_ee_bits(struct em_hw *hw,
4676 uint16_t data,
4677 uint16_t count)
4678 {
4679 struct em_eeprom_info *eeprom = &hw->eeprom;
4680 uint32_t eecd;
4681 uint32_t mask;
4682
4683 /* We need to shift "count" bits out to the EEPROM. So, value in the
4684 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4685 * In order to do this, "data" must be broken down into bits.
4686 */
4687 mask = 0x01 << (count - 1);
4688 eecd = E1000_READ_REG(hw, EECD);
4689 if (eeprom->type == em_eeprom_microwire) {
4690 eecd &= ~E1000_EECD_DO;
4691 } else if (eeprom->type == em_eeprom_spi) {
4692 eecd |= E1000_EECD_DO;
4693 }
4694 do {
4695 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4696 * and then raising and then lowering the clock (the SK bit controls
4697 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4698 * by setting "DI" to "0" and then raising and then lowering the clock.
4699 */
4700 eecd &= ~E1000_EECD_DI;
4701
4702 if (data & mask)
4703 eecd |= E1000_EECD_DI;
4704
4705 E1000_WRITE_REG(hw, EECD, eecd);
4706 E1000_WRITE_FLUSH(hw);
4707
4708 usec_delay(eeprom->delay_usec);
4709
4710 em_raise_ee_clk(hw, &eecd);
4711 em_lower_ee_clk(hw, &eecd);
4712
4713 mask = mask >> 1;
4714
4715 } while (mask);
4716
4717 /* We leave the "DI" bit set to "0" when we leave this routine. */
4718 eecd &= ~E1000_EECD_DI;
4719 E1000_WRITE_REG(hw, EECD, eecd);
4720 }
4721
4722 /******************************************************************************
4723 * Shift data bits in from the EEPROM
4724 *
4725 * hw - Struct containing variables accessed by shared code
4726 *****************************************************************************/
4727 static uint16_t
4728 em_shift_in_ee_bits(struct em_hw *hw,
4729 uint16_t count)
4730 {
4731 uint32_t eecd;
4732 uint32_t i;
4733 uint16_t data;
4734
4735 /* In order to read a register from the EEPROM, we need to shift 'count'
4736 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4737 * input to the EEPROM (setting the SK bit), and then reading the value of
4738 * the "DO" bit. During this "shifting in" process the "DI" bit should
4739 * always be clear.
4740 */
4741
4742 eecd = E1000_READ_REG(hw, EECD);
4743
4744 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4745 data = 0;
4746
4747 for (i = 0; i < count; i++) {
4748 data = data << 1;
4749 em_raise_ee_clk(hw, &eecd);
4750
4751 eecd = E1000_READ_REG(hw, EECD);
4752
4753 eecd &= ~(E1000_EECD_DI);
4754 if (eecd & E1000_EECD_DO)
4755 data |= 1;
4756
4757 em_lower_ee_clk(hw, &eecd);
4758 }
4759
4760 return data;
4761 }
4762
4763 /******************************************************************************
4764 * Prepares EEPROM for access
4765 *
4766 * hw - Struct containing variables accessed by shared code
4767 *
4768 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4769 * function should be called before issuing a command to the EEPROM.
4770 *****************************************************************************/
4771 static int32_t
4772 em_acquire_eeprom(struct em_hw *hw)
4773 {
4774 struct em_eeprom_info *eeprom = &hw->eeprom;
4775 uint32_t eecd, i=0;
4776
4777 DEBUGFUNC("em_acquire_eeprom");
4778
4779 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4780 return -E1000_ERR_SWFW_SYNC;
4781 eecd = E1000_READ_REG(hw, EECD);
4782
4783 if (hw->mac_type != em_82573) {
4784 /* Request EEPROM Access */
4785 if (hw->mac_type > em_82544) {
4786 eecd |= E1000_EECD_REQ;
4787 E1000_WRITE_REG(hw, EECD, eecd);
4788 eecd = E1000_READ_REG(hw, EECD);
4789 while ((!(eecd & E1000_EECD_GNT)) &&
4790 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4791 i++;
4792 usec_delay(5);
4793 eecd = E1000_READ_REG(hw, EECD);
4794 }
4795 if (!(eecd & E1000_EECD_GNT)) {
4796 eecd &= ~E1000_EECD_REQ;
4797 E1000_WRITE_REG(hw, EECD, eecd);
4798 DEBUGOUT("Could not acquire EEPROM grant\n");
4799 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4800 return -E1000_ERR_EEPROM;
4801 }
4802 }
4803 }
4804
4805 /* Setup EEPROM for Read/Write */
4806
4807 if (eeprom->type == em_eeprom_microwire) {
4808 /* Clear SK and DI */
4809 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4810 E1000_WRITE_REG(hw, EECD, eecd);
4811
4812 /* Set CS */
4813 eecd |= E1000_EECD_CS;
4814 E1000_WRITE_REG(hw, EECD, eecd);
4815 } else if (eeprom->type == em_eeprom_spi) {
4816 /* Clear SK and CS */
4817 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4818 E1000_WRITE_REG(hw, EECD, eecd);
4819 usec_delay(1);
4820 }
4821
4822 return E1000_SUCCESS;
4823 }
4824
4825 /******************************************************************************
4826 * Returns EEPROM to a "standby" state
4827 *
4828 * hw - Struct containing variables accessed by shared code
4829 *****************************************************************************/
4830 static void
4831 em_standby_eeprom(struct em_hw *hw)
4832 {
4833 struct em_eeprom_info *eeprom = &hw->eeprom;
4834 uint32_t eecd;
4835
4836 eecd = E1000_READ_REG(hw, EECD);
4837
4838 if (eeprom->type == em_eeprom_microwire) {
4839 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4840 E1000_WRITE_REG(hw, EECD, eecd);
4841 E1000_WRITE_FLUSH(hw);
4842 usec_delay(eeprom->delay_usec);
4843
4844 /* Clock high */
4845 eecd |= E1000_EECD_SK;
4846 E1000_WRITE_REG(hw, EECD, eecd);
4847 E1000_WRITE_FLUSH(hw);
4848 usec_delay(eeprom->delay_usec);
4849
4850 /* Select EEPROM */
4851 eecd |= E1000_EECD_CS;
4852 E1000_WRITE_REG(hw, EECD, eecd);
4853 E1000_WRITE_FLUSH(hw);
4854 usec_delay(eeprom->delay_usec);
4855
4856 /* Clock low */
4857 eecd &= ~E1000_EECD_SK;
4858 E1000_WRITE_REG(hw, EECD, eecd);
4859 E1000_WRITE_FLUSH(hw);
4860 usec_delay(eeprom->delay_usec);
4861 } else if (eeprom->type == em_eeprom_spi) {
4862 /* Toggle CS to flush commands */
4863 eecd |= E1000_EECD_CS;
4864 E1000_WRITE_REG(hw, EECD, eecd);
4865 E1000_WRITE_FLUSH(hw);
4866 usec_delay(eeprom->delay_usec);
4867 eecd &= ~E1000_EECD_CS;
4868 E1000_WRITE_REG(hw, EECD, eecd);
4869 E1000_WRITE_FLUSH(hw);
4870 usec_delay(eeprom->delay_usec);
4871 }
4872 }
4873
4874 /******************************************************************************
4875 * Terminates a command by inverting the EEPROM's chip select pin
4876 *
4877 * hw - Struct containing variables accessed by shared code
4878 *****************************************************************************/
4879 static void
4880 em_release_eeprom(struct em_hw *hw)
4881 {
4882 uint32_t eecd;
4883
4884 DEBUGFUNC("em_release_eeprom");
4885
4886 eecd = E1000_READ_REG(hw, EECD);
4887
4888 if (hw->eeprom.type == em_eeprom_spi) {
4889 eecd |= E1000_EECD_CS; /* Pull CS high */
4890 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4891
4892 E1000_WRITE_REG(hw, EECD, eecd);
4893
4894 usec_delay(hw->eeprom.delay_usec);
4895 } else if (hw->eeprom.type == em_eeprom_microwire) {
4896 /* cleanup eeprom */
4897
4898 /* CS on Microwire is active-high */
4899 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4900
4901 E1000_WRITE_REG(hw, EECD, eecd);
4902
4903 /* Rising edge of clock */
4904 eecd |= E1000_EECD_SK;
4905 E1000_WRITE_REG(hw, EECD, eecd);
4906 E1000_WRITE_FLUSH(hw);
4907 usec_delay(hw->eeprom.delay_usec);
4908
4909 /* Falling edge of clock */
4910 eecd &= ~E1000_EECD_SK;
4911 E1000_WRITE_REG(hw, EECD, eecd);
4912 E1000_WRITE_FLUSH(hw);
4913 usec_delay(hw->eeprom.delay_usec);
4914 }
4915
4916 /* Stop requesting EEPROM access */
4917 if (hw->mac_type > em_82544) {
4918 eecd &= ~E1000_EECD_REQ;
4919 E1000_WRITE_REG(hw, EECD, eecd);
4920 }
4921
4922 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4923 }
4924
4925 /******************************************************************************
4926 * Reads a 16 bit word from the EEPROM.
4927 *
4928 * hw - Struct containing variables accessed by shared code
4929 *****************************************************************************/
4930 STATIC int32_t
4931 em_spi_eeprom_ready(struct em_hw *hw)
4932 {
4933 uint16_t retry_count = 0;
4934 uint8_t spi_stat_reg;
4935
4936 DEBUGFUNC("em_spi_eeprom_ready");
4937
4938 /* Read "Status Register" repeatedly until the LSB is cleared. The
4939 * EEPROM will signal that the command has been completed by clearing
4940 * bit 0 of the internal status register. If it's not cleared within
4941 * 5 milliseconds, then error out.
4942 */
4943 retry_count = 0;
4944 do {
4945 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4946 hw->eeprom.opcode_bits);
4947 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
4948 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4949 break;
4950
4951 usec_delay(5);
4952 retry_count += 5;
4953
4954 em_standby_eeprom(hw);
4955 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4956
4957 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4958 * only 0-5mSec on 5V devices)
4959 */
4960 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4961 DEBUGOUT("SPI EEPROM Status error\n");
4962 return -E1000_ERR_EEPROM;
4963 }
4964
4965 return E1000_SUCCESS;
4966 }
4967
4968 /******************************************************************************
4969 * Reads a 16 bit word from the EEPROM.
4970 *
4971 * hw - Struct containing variables accessed by shared code
4972 * offset - offset of word in the EEPROM to read
4973 * data - word read from the EEPROM
4974 * words - number of words to read
4975 *****************************************************************************/
4976 int32_t
4977 em_read_eeprom(struct em_hw *hw,
4978 uint16_t offset,
4979 uint16_t words,
4980 uint16_t *data)
4981 {
4982 struct em_eeprom_info *eeprom = &hw->eeprom;
4983 uint32_t i = 0;
4984
4985 DEBUGFUNC("em_read_eeprom");
4986
4987 /* If eeprom is not yet detected, do so now */
4988 if (eeprom->word_size == 0)
4989 em_init_eeprom_params(hw);
4990
4991 /* A check for invalid values: offset too large, too many words, and not
4992 * enough words.
4993 */
4994 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4995 (words == 0)) {
4996 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4997 return -E1000_ERR_EEPROM;
4998 }
4999
5000 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
5001 * directly. In this case, we need to acquire the EEPROM so that
5002 * FW or other port software does not interrupt.
5003 */
5004 if (em_is_onboard_nvm_eeprom(hw) == TRUE &&
5005 hw->eeprom.use_eerd == FALSE) {
5006 /* Prepare the EEPROM for bit-bang reading */
5007 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
5008 return -E1000_ERR_EEPROM;
5009 }
5010
5011 /* Eerd register EEPROM access requires no eeprom aquire/release */
5012 if (eeprom->use_eerd == TRUE)
5013 return em_read_eeprom_eerd(hw, offset, words, data);
5014
5015 /* ICH EEPROM access is done via the ICH flash controller */
5016 if (eeprom->type == em_eeprom_ich8)
5017 return em_read_eeprom_ich8(hw, offset, words, data);
5018
5019 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5020 * acquired the EEPROM at this point, so any returns should relase it */
5021 if (eeprom->type == em_eeprom_spi) {
5022 uint16_t word_in;
5023 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5024
5025 if (em_spi_eeprom_ready(hw)) {
5026 em_release_eeprom(hw);
5027 return -E1000_ERR_EEPROM;
5028 }
5029
5030 em_standby_eeprom(hw);
5031
5032 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5033 if ((eeprom->address_bits == 8) && (offset >= 128))
5034 read_opcode |= EEPROM_A8_OPCODE_SPI;
5035
5036 /* Send the READ command (opcode + addr) */
5037 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5038 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5039
5040 /* Read the data. The address of the eeprom internally increments with
5041 * each byte (spi) being read, saving on the overhead of eeprom setup
5042 * and tear-down. The address counter will roll over if reading beyond
5043 * the size of the eeprom, thus allowing the entire memory to be read
5044 * starting from any offset. */
5045 for (i = 0; i < words; i++) {
5046 word_in = em_shift_in_ee_bits(hw, 16);
5047 data[i] = (word_in >> 8) | (word_in << 8);
5048 }
5049 } else if (eeprom->type == em_eeprom_microwire) {
5050 for (i = 0; i < words; i++) {
5051 /* Send the READ command (opcode + addr) */
5052 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5053 eeprom->opcode_bits);
5054 em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5055 eeprom->address_bits);
5056
5057 /* Read the data. For microwire, each word requires the overhead
5058 * of eeprom setup and tear-down. */
5059 data[i] = em_shift_in_ee_bits(hw, 16);
5060 em_standby_eeprom(hw);
5061 }
5062 }
5063
5064 /* End this read operation */
5065 em_release_eeprom(hw);
5066
5067 return E1000_SUCCESS;
5068 }
5069
5070 /******************************************************************************
5071 * Reads a 16 bit word from the EEPROM using the EERD register.
5072 *
5073 * hw - Struct containing variables accessed by shared code
5074 * offset - offset of word in the EEPROM to read
5075 * data - word read from the EEPROM
5076 * words - number of words to read
5077 *****************************************************************************/
5078 STATIC int32_t
5079 em_read_eeprom_eerd(struct em_hw *hw,
5080 uint16_t offset,
5081 uint16_t words,
5082 uint16_t *data)
5083 {
5084 uint32_t i, eerd = 0;
5085 int32_t error = 0;
5086
5087 for (i = 0; i < words; i++) {
5088 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5089 E1000_EEPROM_RW_REG_START;
5090
5091 E1000_WRITE_REG(hw, EERD, eerd);
5092 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5093
5094 if (error) {
5095 break;
5096 }
5097 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5098
5099 }
5100
5101 return error;
5102 }
5103
5104 /******************************************************************************
5105 * Writes a 16 bit word from the EEPROM using the EEWR register.
5106 *
5107 * hw - Struct containing variables accessed by shared code
5108 * offset - offset of word in the EEPROM to read
5109 * data - word read from the EEPROM
5110 * words - number of words to read
5111 *****************************************************************************/
5112 STATIC int32_t
5113 em_write_eeprom_eewr(struct em_hw *hw,
5114 uint16_t offset,
5115 uint16_t words,
5116 uint16_t *data)
5117 {
5118 uint32_t register_value = 0;
5119 uint32_t i = 0;
5120 int32_t error = 0;
5121
5122 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5123 return -E1000_ERR_SWFW_SYNC;
5124
5125 for (i = 0; i < words; i++) {
5126 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5127 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5128 E1000_EEPROM_RW_REG_START;
5129
5130 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5131 if (error) {
5132 break;
5133 }
5134
5135 E1000_WRITE_REG(hw, EEWR, register_value);
5136
5137 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5138
5139 if (error) {
5140 break;
5141 }
5142 }
5143
5144 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5145 return error;
5146 }
5147
5148 /******************************************************************************
5149 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5150 *
5151 * hw - Struct containing variables accessed by shared code
5152 *****************************************************************************/
5153 STATIC int32_t
5154 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
5155 {
5156 uint32_t attempts = 100000;
5157 uint32_t i, reg = 0;
5158 int32_t done = E1000_ERR_EEPROM;
5159
5160 for (i = 0; i < attempts; i++) {
5161 if (eerd == E1000_EEPROM_POLL_READ)
5162 reg = E1000_READ_REG(hw, EERD);
5163 else
5164 reg = E1000_READ_REG(hw, EEWR);
5165
5166 if (reg & E1000_EEPROM_RW_REG_DONE) {
5167 done = E1000_SUCCESS;
5168 break;
5169 }
5170 usec_delay(5);
5171 }
5172
5173 return done;
5174 }
5175
5176 /***************************************************************************
5177 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5178 *
5179 * hw - Struct containing variables accessed by shared code
5180 ****************************************************************************/
5181 STATIC boolean_t
5182 em_is_onboard_nvm_eeprom(struct em_hw *hw)
5183 {
5184 uint32_t eecd = 0;
5185
5186 DEBUGFUNC("em_is_onboard_nvm_eeprom");
5187
5188 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
5189 return FALSE;
5190
5191 if (hw->mac_type == em_82573) {
5192 eecd = E1000_READ_REG(hw, EECD);
5193
5194 /* Isolate bits 15 & 16 */
5195 eecd = ((eecd >> 15) & 0x03);
5196
5197 /* If both bits are set, device is Flash type */
5198 if (eecd == 0x03) {
5199 return FALSE;
5200 }
5201 }
5202 return TRUE;
5203 }
5204
5205 /******************************************************************************
5206 * Verifies that the EEPROM has a valid checksum
5207 *
5208 * hw - Struct containing variables accessed by shared code
5209 *
5210 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5211 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5212 * valid.
5213 *****************************************************************************/
5214 int32_t
5215 em_validate_eeprom_checksum(struct em_hw *hw)
5216 {
5217 uint16_t checksum = 0;
5218 uint16_t i, eeprom_data;
5219
5220 DEBUGFUNC("em_validate_eeprom_checksum");
5221
5222 if ((hw->mac_type == em_82573) &&
5223 (em_is_onboard_nvm_eeprom(hw) == FALSE)) {
5224 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5225 * 10h-12h. Checksum may need to be fixed. */
5226 em_read_eeprom(hw, 0x10, 1, &eeprom_data);
5227 if ((eeprom_data & 0x10) == 0) {
5228 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5229 * has already been fixed. If the checksum is still wrong and this
5230 * bit is a 1, we need to return bad checksum. Otherwise, we need
5231 * to set this bit to a 1 and update the checksum. */
5232 em_read_eeprom(hw, 0x23, 1, &eeprom_data);
5233 if ((eeprom_data & 0x8000) == 0) {
5234 eeprom_data |= 0x8000;
5235 em_write_eeprom(hw, 0x23, 1, &eeprom_data);
5236 em_update_eeprom_checksum(hw);
5237 }
5238 }
5239 }
5240
5241 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
5242 /* Drivers must allocate the shadow ram structure for the
5243 * EEPROM checksum to be updated. Otherwise, this bit as well
5244 * as the checksum must both be set correctly for this
5245 * validation to pass.
5246 */
5247 em_read_eeprom(hw, 0x19, 1, &eeprom_data);
5248 if ((eeprom_data & 0x40) == 0) {
5249 eeprom_data |= 0x40;
5250 em_write_eeprom(hw, 0x19, 1, &eeprom_data);
5251 em_update_eeprom_checksum(hw);
5252 }
5253 }
5254
5255 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5256 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5257 DEBUGOUT("EEPROM Read Error\n");
5258 return -E1000_ERR_EEPROM;
5259 }
5260 checksum += eeprom_data;
5261 }
5262
5263 if (checksum == (uint16_t) EEPROM_SUM)
5264 return E1000_SUCCESS;
5265 else {
5266 DEBUGOUT("EEPROM Checksum Invalid\n");
5267 return -E1000_ERR_EEPROM;
5268 }
5269 }
5270
5271 /******************************************************************************
5272 * Calculates the EEPROM checksum and writes it to the EEPROM
5273 *
5274 * hw - Struct containing variables accessed by shared code
5275 *
5276 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5277 * Writes the difference to word offset 63 of the EEPROM.
5278 *****************************************************************************/
5279 int32_t
5280 em_update_eeprom_checksum(struct em_hw *hw)
5281 {
5282 uint32_t ctrl_ext;
5283 uint16_t checksum = 0;
5284 uint16_t i, eeprom_data;
5285
5286 DEBUGFUNC("em_update_eeprom_checksum");
5287
5288 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5289 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5290 DEBUGOUT("EEPROM Read Error\n");
5291 return -E1000_ERR_EEPROM;
5292 }
5293 checksum += eeprom_data;
5294 }
5295 checksum = (uint16_t) EEPROM_SUM - checksum;
5296 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5297 DEBUGOUT("EEPROM Write Error\n");
5298 return -E1000_ERR_EEPROM;
5299 } else if (hw->eeprom.type == em_eeprom_flash) {
5300 em_commit_shadow_ram(hw);
5301 } else if (hw->eeprom.type == em_eeprom_ich8) {
5302 em_commit_shadow_ram(hw);
5303 /* Reload the EEPROM, or else modifications will not appear
5304 * until after next adapter reset. */
5305 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5306 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5307 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5308 msec_delay(10);
5309 }
5310 return E1000_SUCCESS;
5311 }
5312
5313 /******************************************************************************
5314 * Parent function for writing words to the different EEPROM types.
5315 *
5316 * hw - Struct containing variables accessed by shared code
5317 * offset - offset within the EEPROM to be written to
5318 * words - number of words to write
5319 * data - 16 bit word to be written to the EEPROM
5320 *
5321 * If em_update_eeprom_checksum is not called after this function, the
5322 * EEPROM will most likely contain an invalid checksum.
5323 *****************************************************************************/
5324 int32_t
5325 em_write_eeprom(struct em_hw *hw,
5326 uint16_t offset,
5327 uint16_t words,
5328 uint16_t *data)
5329 {
5330 struct em_eeprom_info *eeprom = &hw->eeprom;
5331 int32_t status = 0;
5332
5333 DEBUGFUNC("em_write_eeprom");
5334
5335 /* If eeprom is not yet detected, do so now */
5336 if (eeprom->word_size == 0)
5337 em_init_eeprom_params(hw);
5338
5339 /* A check for invalid values: offset too large, too many words, and not
5340 * enough words.
5341 */
5342 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5343 (words == 0)) {
5344 DEBUGOUT("\"words\" parameter out of bounds\n");
5345 return -E1000_ERR_EEPROM;
5346 }
5347
5348 /* 82573 writes only through eewr */
5349 if (eeprom->use_eewr == TRUE)
5350 return em_write_eeprom_eewr(hw, offset, words, data);
5351
5352 if (eeprom->type == em_eeprom_ich8)
5353 return em_write_eeprom_ich8(hw, offset, words, data);
5354
5355 /* Prepare the EEPROM for writing */
5356 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
5357 return -E1000_ERR_EEPROM;
5358
5359 if (eeprom->type == em_eeprom_microwire) {
5360 status = em_write_eeprom_microwire(hw, offset, words, data);
5361 } else {
5362 status = em_write_eeprom_spi(hw, offset, words, data);
5363 msec_delay(10);
5364 }
5365
5366 /* Done with writing */
5367 em_release_eeprom(hw);
5368
5369 return status;
5370 }
5371
5372 /******************************************************************************
5373 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5374 *
5375 * hw - Struct containing variables accessed by shared code
5376 * offset - offset within the EEPROM to be written to
5377 * words - number of words to write
5378 * data - pointer to array of 8 bit words to be written to the EEPROM
5379 *
5380 *****************************************************************************/
5381 STATIC int32_t
5382 em_write_eeprom_spi(struct em_hw *hw,
5383 uint16_t offset,
5384 uint16_t words,
5385 uint16_t *data)
5386 {
5387 struct em_eeprom_info *eeprom = &hw->eeprom;
5388 uint16_t widx = 0;
5389
5390 DEBUGFUNC("em_write_eeprom_spi");
5391
5392 while (widx < words) {
5393 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5394
5395 if (em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5396
5397 em_standby_eeprom(hw);
5398
5399 /* Send the WRITE ENABLE command (8 bit opcode ) */
5400 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5401 eeprom->opcode_bits);
5402
5403 em_standby_eeprom(hw);
5404
5405 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5406 if ((eeprom->address_bits == 8) && (offset >= 128))
5407 write_opcode |= EEPROM_A8_OPCODE_SPI;
5408
5409 /* Send the Write command (8-bit opcode + addr) */
5410 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5411
5412 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5413 eeprom->address_bits);
5414
5415 /* Send the data */
5416
5417 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5418 while (widx < words) {
5419 uint16_t word_out = data[widx];
5420 word_out = (word_out >> 8) | (word_out << 8);
5421 em_shift_out_ee_bits(hw, word_out, 16);
5422 widx++;
5423
5424 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5425 * operation, while the smaller eeproms are capable of an 8-byte
5426 * PAGE WRITE operation. Break the inner loop to pass new address
5427 */
5428 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5429 em_standby_eeprom(hw);
5430 break;
5431 }
5432 }
5433 }
5434
5435 return E1000_SUCCESS;
5436 }
5437
5438 /******************************************************************************
5439 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5440 *
5441 * hw - Struct containing variables accessed by shared code
5442 * offset - offset within the EEPROM to be written to
5443 * words - number of words to write
5444 * data - pointer to array of 16 bit words to be written to the EEPROM
5445 *
5446 *****************************************************************************/
5447 STATIC int32_t
5448 em_write_eeprom_microwire(struct em_hw *hw,
5449 uint16_t offset,
5450 uint16_t words,
5451 uint16_t *data)
5452 {
5453 struct em_eeprom_info *eeprom = &hw->eeprom;
5454 uint32_t eecd;
5455 uint16_t words_written = 0;
5456 uint16_t i = 0;
5457
5458 DEBUGFUNC("em_write_eeprom_microwire");
5459
5460 /* Send the write enable command to the EEPROM (3-bit opcode plus
5461 * 6/8-bit dummy address beginning with 11). It's less work to include
5462 * the 11 of the dummy address as part of the opcode than it is to shift
5463 * it over the correct number of bits for the address. This puts the
5464 * EEPROM into write/erase mode.
5465 */
5466 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5467 (uint16_t)(eeprom->opcode_bits + 2));
5468
5469 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5470
5471 /* Prepare the EEPROM */
5472 em_standby_eeprom(hw);
5473
5474 while (words_written < words) {
5475 /* Send the Write command (3-bit opcode + addr) */
5476 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5477 eeprom->opcode_bits);
5478
5479 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5480 eeprom->address_bits);
5481
5482 /* Send the data */
5483 em_shift_out_ee_bits(hw, data[words_written], 16);
5484
5485 /* Toggle the CS line. This in effect tells the EEPROM to execute
5486 * the previous command.
5487 */
5488 em_standby_eeprom(hw);
5489
5490 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5491 * signal that the command has been completed by raising the DO signal.
5492 * If DO does not go high in 10 milliseconds, then error out.
5493 */
5494 for (i = 0; i < 200; i++) {
5495 eecd = E1000_READ_REG(hw, EECD);
5496 if (eecd & E1000_EECD_DO) break;
5497 usec_delay(50);
5498 }
5499 if (i == 200) {
5500 DEBUGOUT("EEPROM Write did not complete\n");
5501 return -E1000_ERR_EEPROM;
5502 }
5503
5504 /* Recover from write */
5505 em_standby_eeprom(hw);
5506
5507 words_written++;
5508 }
5509
5510 /* Send the write disable command to the EEPROM (3-bit opcode plus
5511 * 6/8-bit dummy address beginning with 10). It's less work to include
5512 * the 10 of the dummy address as part of the opcode than it is to shift
5513 * it over the correct number of bits for the address. This takes the
5514 * EEPROM out of write/erase mode.
5515 */
5516 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5517 (uint16_t)(eeprom->opcode_bits + 2));
5518
5519 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5520
5521 return E1000_SUCCESS;
5522 }
5523
5524 /******************************************************************************
5525 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5526 * in the eeprom cache and the non modified values in the currently active bank
5527 * to the new bank.
5528 *
5529 * hw - Struct containing variables accessed by shared code
5530 * offset - offset of word in the EEPROM to read
5531 * data - word read from the EEPROM
5532 * words - number of words to read
5533 *****************************************************************************/
5534 STATIC int32_t
5535 em_commit_shadow_ram(struct em_hw *hw)
5536 {
5537 uint32_t attempts = 100000;
5538 uint32_t eecd = 0;
5539 uint32_t flop = 0;
5540 uint32_t i = 0;
5541 int32_t error = E1000_SUCCESS;
5542 uint32_t old_bank_offset = 0;
5543 uint32_t new_bank_offset = 0;
5544 uint8_t low_byte = 0;
5545 uint8_t high_byte = 0;
5546 boolean_t sector_write_failed = FALSE;
5547
5548 if (hw->mac_type == em_82573) {
5549 /* The flop register will be used to determine if flash type is STM */
5550 flop = E1000_READ_REG(hw, FLOP);
5551 for (i=0; i < attempts; i++) {
5552 eecd = E1000_READ_REG(hw, EECD);
5553 if ((eecd & E1000_EECD_FLUPD) == 0) {
5554 break;
5555 }
5556 usec_delay(5);
5557 }
5558
5559 if (i == attempts) {
5560 return -E1000_ERR_EEPROM;
5561 }
5562
5563 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5564 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5565 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5566 }
5567
5568 /* Perform the flash update */
5569 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5570
5571 for (i=0; i < attempts; i++) {
5572 eecd = E1000_READ_REG(hw, EECD);
5573 if ((eecd & E1000_EECD_FLUPD) == 0) {
5574 break;
5575 }
5576 usec_delay(5);
5577 }
5578
5579 if (i == attempts) {
5580 return -E1000_ERR_EEPROM;
5581 }
5582 }
5583
5584 if (((hw->mac_type == em_ich8lan) || (hw->mac_type == em_ich9lan)) &&
5585 hw->eeprom_shadow_ram != NULL) {
5586 /* We're writing to the opposite bank so if we're on bank 1,
5587 * write to bank 0 etc. We also need to erase the segment that
5588 * is going to be written */
5589 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5590 new_bank_offset = hw->flash_bank_size * 2;
5591 old_bank_offset = 0;
5592 em_erase_ich8_4k_segment(hw, 1);
5593 } else {
5594 old_bank_offset = hw->flash_bank_size * 2;
5595 new_bank_offset = 0;
5596 em_erase_ich8_4k_segment(hw, 0);
5597 }
5598
5599 sector_write_failed = FALSE;
5600 /* Loop for every byte in the shadow RAM,
5601 * which is in units of words. */
5602 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5603 /* Determine whether to write the value stored
5604 * in the other NVM bank or a modified value stored
5605 * in the shadow RAM */
5606 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5607 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5608 usec_delay(100);
5609 error = em_verify_write_ich8_byte(hw,
5610 (i << 1) + new_bank_offset, low_byte);
5611
5612 if (error != E1000_SUCCESS)
5613 sector_write_failed = TRUE;
5614 else {
5615 high_byte =
5616 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5617 usec_delay(100);
5618 }
5619 } else {
5620 em_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5621 &low_byte);
5622 usec_delay(100);
5623 error = em_verify_write_ich8_byte(hw,
5624 (i << 1) + new_bank_offset, low_byte);
5625
5626 if (error != E1000_SUCCESS)
5627 sector_write_failed = TRUE;
5628 else {
5629 em_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5630 &high_byte);
5631 usec_delay(100);
5632 }
5633 }
5634
5635 /* If the write of the low byte was successful, go ahread and
5636 * write the high byte while checking to make sure that if it
5637 * is the signature byte, then it is handled properly */
5638 if (sector_write_failed == FALSE) {
5639 /* If the word is 0x13, then make sure the signature bits
5640 * (15:14) are 11b until the commit has completed.
5641 * This will allow us to write 10b which indicates the
5642 * signature is valid. We want to do this after the write
5643 * has completed so that we don't mark the segment valid
5644 * while the write is still in progress */
5645 if (i == E1000_ICH_NVM_SIG_WORD)
5646 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5647
5648 error = em_verify_write_ich8_byte(hw,
5649 (i << 1) + new_bank_offset + 1, high_byte);
5650 if (error != E1000_SUCCESS)
5651 sector_write_failed = TRUE;
5652
5653 } else {
5654 /* If the write failed then break from the loop and
5655 * return an error */
5656 break;
5657 }
5658 }
5659
5660 /* Don't bother writing the segment valid bits if sector
5661 * programming failed. */
5662 if (sector_write_failed == FALSE) {
5663 /* Finally validate the new segment by setting bit 15:14
5664 * to 10b in word 0x13 , this can be done without an
5665 * erase as well since these bits are 11 to start with
5666 * and we need to change bit 14 to 0b */
5667 em_read_ich8_byte(hw,
5668 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5669 &high_byte);
5670 high_byte &= 0xBF;
5671 error = em_verify_write_ich8_byte(hw,
5672 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5673 /* And invalidate the previously valid segment by setting
5674 * its signature word (0x13) high_byte to 0b. This can be
5675 * done without an erase because flash erase sets all bits
5676 * to 1's. We can write 1's to 0's without an erase */
5677 if (error == E1000_SUCCESS) {
5678 error = em_verify_write_ich8_byte(hw,
5679 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5680 }
5681
5682 /* Clear the now not used entry in the cache */
5683 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5684 hw->eeprom_shadow_ram[i].modified = FALSE;
5685 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5686 }
5687 }
5688 }
5689
5690 return error;
5691 }
5692
5693 /******************************************************************************
5694 * Reads the adapter's part number from the EEPROM
5695 *
5696 * hw - Struct containing variables accessed by shared code
5697 * part_num - Adapter's part number
5698 *****************************************************************************/
5699 int32_t
5700 em_read_part_num(struct em_hw *hw,
5701 uint32_t *part_num)
5702 {
5703 uint16_t offset = EEPROM_PBA_BYTE_1;
5704 uint16_t eeprom_data;
5705
5706 DEBUGFUNC("em_read_part_num");
5707
5708 /* Get word 0 from EEPROM */
5709 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5710 DEBUGOUT("EEPROM Read Error\n");
5711 return -E1000_ERR_EEPROM;
5712 }
5713 /* Save word 0 in upper half of part_num */
5714 *part_num = (uint32_t) (eeprom_data << 16);
5715
5716 /* Get word 1 from EEPROM */
5717 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5718 DEBUGOUT("EEPROM Read Error\n");
5719 return -E1000_ERR_EEPROM;
5720 }
5721 /* Save word 1 in lower half of part_num */
5722 *part_num |= eeprom_data;
5723
5724 return E1000_SUCCESS;
5725 }
5726
5727 /******************************************************************************
5728 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5729 * second function of dual function devices
5730 *
5731 * hw - Struct containing variables accessed by shared code
5732 *****************************************************************************/
5733 int32_t
5734 em_read_mac_addr(struct em_hw * hw)
5735 {
5736 uint16_t offset;
5737 uint16_t eeprom_data, i;
5738
5739 DEBUGFUNC("em_read_mac_addr");
5740
5741 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5742 offset = i >> 1;
5743 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5744 DEBUGOUT("EEPROM Read Error\n");
5745 return -E1000_ERR_EEPROM;
5746 }
5747 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5748 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5749 }
5750
5751 switch (hw->mac_type) {
5752 default:
5753 break;
5754 case em_82546:
5755 case em_82546_rev_3:
5756 case em_82571:
5757 case em_80003es2lan:
5758 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5759 hw->perm_mac_addr[5] ^= 0x01;
5760 break;
5761 }
5762
5763 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5764 hw->mac_addr[i] = hw->perm_mac_addr[i];
5765 return E1000_SUCCESS;
5766 }
5767
5768 /******************************************************************************
5769 * Initializes receive address filters.
5770 *
5771 * hw - Struct containing variables accessed by shared code
5772 *
5773 * Places the MAC address in receive address register 0 and clears the rest
5774 * of the receive addresss registers. Clears the multicast table. Assumes
5775 * the receiver is in reset when the routine is called.
5776 *****************************************************************************/
5777 STATIC void
5778 em_init_rx_addrs(struct em_hw *hw)
5779 {
5780 uint32_t i;
5781 uint32_t rar_num;
5782
5783 DEBUGFUNC("em_init_rx_addrs");
5784
5785 /* Setup the receive address. */
5786 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5787
5788 em_rar_set(hw, hw->mac_addr, 0);
5789
5790 rar_num = E1000_RAR_ENTRIES;
5791
5792 /* Reserve a spot for the Locally Administered Address to work around
5793 * an 82571 issue in which a reset on one port will reload the MAC on
5794 * the other port. */
5795 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
5796 rar_num -= 1;
5797 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
5798 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5799
5800 /* Zero out the other 15 receive addresses. */
5801 DEBUGOUT("Clearing RAR[1-15]\n");
5802 for (i = 1; i < rar_num; i++) {
5803 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5804 E1000_WRITE_FLUSH(hw);
5805 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5806 E1000_WRITE_FLUSH(hw);
5807 }
5808 }
5809
5810 /******************************************************************************
5811 * Updates the MAC's list of multicast addresses.
5812 *
5813 * hw - Struct containing variables accessed by shared code
5814 * mc_addr_list - the list of new multicast addresses
5815 * mc_addr_count - number of addresses
5816 * pad - number of bytes between addresses in the list
5817 * rar_used_count - offset where to start adding mc addresses into the RAR's
5818 *
5819 * The given list replaces any existing list. Clears the last 15 receive
5820 * address registers and the multicast table. Uses receive address registers
5821 * for the first 15 multicast addresses, and hashes the rest into the
5822 * multicast table.
5823 *****************************************************************************/
5824 void
5825 em_mc_addr_list_update(struct em_hw *hw,
5826 uint8_t *mc_addr_list,
5827 uint32_t mc_addr_count,
5828 uint32_t pad,
5829 uint32_t rar_used_count)
5830 {
5831 uint32_t hash_value;
5832 uint32_t i;
5833 uint32_t num_rar_entry;
5834 uint32_t num_mta_entry;
5835
5836 DEBUGFUNC("em_mc_addr_list_update");
5837
5838 /* Set the new number of MC addresses that we are being requested to use. */
5839 hw->num_mc_addrs = mc_addr_count;
5840
5841 /* Clear RAR[1-15] */
5842 DEBUGOUT(" Clearing RAR[1-15]\n");
5843 num_rar_entry = E1000_RAR_ENTRIES;
5844 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
5845 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5846
5847 /* Reserve a spot for the Locally Administered Address to work around
5848 * an 82571 issue in which a reset on one port will reload the MAC on
5849 * the other port. */
5850 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
5851 num_rar_entry -= 1;
5852
5853 for (i = rar_used_count; i < num_rar_entry; i++) {
5854 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5855 E1000_WRITE_FLUSH(hw);
5856 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5857 E1000_WRITE_FLUSH(hw);
5858 }
5859
5860 /* Clear the MTA */
5861 DEBUGOUT(" Clearing MTA\n");
5862 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5863 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
5864 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5865
5866 for (i = 0; i < num_mta_entry; i++) {
5867 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5868 E1000_WRITE_FLUSH(hw);
5869 }
5870
5871 /* Add the new addresses */
5872 for (i = 0; i < mc_addr_count; i++) {
5873 DEBUGOUT(" Adding the multicast addresses:\n");
5874 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5875 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5876 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5877 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5878 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5879 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5880 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5881
5882 hash_value = em_hash_mc_addr(hw,
5883 mc_addr_list +
5884 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5885
5886 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5887
5888 /* Place this multicast address in the RAR if there is room, *
5889 * else put it in the MTA
5890 */
5891 if (rar_used_count < num_rar_entry) {
5892 em_rar_set(hw,
5893 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5894 rar_used_count);
5895 rar_used_count++;
5896 } else {
5897 em_mta_set(hw, hash_value);
5898 }
5899 }
5900 DEBUGOUT("MC Update Complete\n");
5901 }
5902
5903 /******************************************************************************
5904 * Hashes an address to determine its location in the multicast table
5905 *
5906 * hw - Struct containing variables accessed by shared code
5907 * mc_addr - the multicast address to hash
5908 *****************************************************************************/
5909 uint32_t
5910 em_hash_mc_addr(struct em_hw *hw,
5911 uint8_t *mc_addr)
5912 {
5913 uint32_t hash_value = 0;
5914
5915 /* The portion of the address that is used for the hash table is
5916 * determined by the mc_filter_type setting.
5917 */
5918 switch (hw->mc_filter_type) {
5919 /* [0] [1] [2] [3] [4] [5]
5920 * 01 AA 00 12 34 56
5921 * LSB MSB
5922 */
5923 case 0:
5924 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
5925 /* [47:38] i.e. 0x158 for above example address */
5926 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5927 } else {
5928 /* [47:36] i.e. 0x563 for above example address */
5929 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5930 }
5931 break;
5932 case 1:
5933 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
5934 /* [46:37] i.e. 0x2B1 for above example address */
5935 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5936 } else {
5937 /* [46:35] i.e. 0xAC6 for above example address */
5938 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5939 }
5940 break;
5941 case 2:
5942 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
5943 /*[45:36] i.e. 0x163 for above example address */
5944 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5945 } else {
5946 /* [45:34] i.e. 0x5D8 for above example address */
5947 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5948 }
5949 break;
5950 case 3:
5951 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
5952 /* [43:34] i.e. 0x18D for above example address */
5953 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5954 } else {
5955 /* [43:32] i.e. 0x634 for above example address */
5956 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5957 }
5958 break;
5959 }
5960
5961 hash_value &= 0xFFF;
5962 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
5963 hash_value &= 0x3FF;
5964
5965 return hash_value;
5966 }
5967
5968 /******************************************************************************
5969 * Sets the bit in the multicast table corresponding to the hash value.
5970 *
5971 * hw - Struct containing variables accessed by shared code
5972 * hash_value - Multicast address hash value
5973 *****************************************************************************/
5974 void
5975 em_mta_set(struct em_hw *hw,
5976 uint32_t hash_value)
5977 {
5978 uint32_t hash_bit, hash_reg;
5979 uint32_t mta;
5980 uint32_t temp;
5981
5982 /* The MTA is a register array of 128 32-bit registers.
5983 * It is treated like an array of 4096 bits. We want to set
5984 * bit BitArray[hash_value]. So we figure out what register
5985 * the bit is in, read it, OR in the new bit, then write
5986 * back the new value. The register is determined by the
5987 * upper 7 bits of the hash value and the bit within that
5988 * register are determined by the lower 5 bits of the value.
5989 */
5990 hash_reg = (hash_value >> 5) & 0x7F;
5991 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
5992 hash_reg &= 0x1F;
5993
5994 hash_bit = hash_value & 0x1F;
5995
5996 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5997
5998 mta |= (1 << hash_bit);
5999
6000 /* If we are on an 82544 and we are trying to write an odd offset
6001 * in the MTA, save off the previous entry before writing and
6002 * restore the old value after writing.
6003 */
6004 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
6005 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
6006 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
6007 E1000_WRITE_FLUSH(hw);
6008 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
6009 E1000_WRITE_FLUSH(hw);
6010 } else {
6011 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
6012 E1000_WRITE_FLUSH(hw);
6013 }
6014 }
6015
6016 /******************************************************************************
6017 * Puts an ethernet address into a receive address register.
6018 *
6019 * hw - Struct containing variables accessed by shared code
6020 * addr - Address to put into receive address register
6021 * index - Receive address register to write
6022 *****************************************************************************/
6023 void
6024 em_rar_set(struct em_hw *hw,
6025 uint8_t *addr,
6026 uint32_t index)
6027 {
6028 uint32_t rar_low, rar_high;
6029
6030 /* HW expects these in little endian so we reverse the byte order
6031 * from network order (big endian) to little endian
6032 */
6033 rar_low = ((uint32_t) addr[0] |
6034 ((uint32_t) addr[1] << 8) |
6035 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
6036 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
6037
6038 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
6039 * unit hang.
6040 *
6041 * Description:
6042 * If there are any Rx frames queued up or otherwise present in the HW
6043 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
6044 * hang. To work around this issue, we have to disable receives and
6045 * flush out all Rx frames before we enable RSS. To do so, we modify we
6046 * redirect all Rx traffic to manageability and then reset the HW.
6047 * This flushes away Rx frames, and (since the redirections to
6048 * manageability persists across resets) keeps new ones from coming in
6049 * while we work. Then, we clear the Address Valid AV bit for all MAC
6050 * addresses and undo the re-direction to manageability.
6051 * Now, frames are coming in again, but the MAC won't accept them, so
6052 * far so good. We now proceed to initialize RSS (if necessary) and
6053 * configure the Rx unit. Last, we re-enable the AV bits and continue
6054 * on our merry way.
6055 */
6056 switch (hw->mac_type) {
6057 case em_82571:
6058 case em_82572:
6059 case em_80003es2lan:
6060 if (hw->leave_av_bit_off == TRUE)
6061 break;
6062 default:
6063 /* Indicate to hardware the Address is Valid. */
6064 rar_high |= E1000_RAH_AV;
6065 break;
6066 }
6067
6068 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
6069 E1000_WRITE_FLUSH(hw);
6070 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
6071 E1000_WRITE_FLUSH(hw);
6072 }
6073
6074 /******************************************************************************
6075 * Writes a value to the specified offset in the VLAN filter table.
6076 *
6077 * hw - Struct containing variables accessed by shared code
6078 * offset - Offset in VLAN filer table to write
6079 * value - Value to write into VLAN filter table
6080 *****************************************************************************/
6081 void
6082 em_write_vfta(struct em_hw *hw,
6083 uint32_t offset,
6084 uint32_t value)
6085 {
6086 uint32_t temp;
6087
6088 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
6089 return;
6090
6091 if ((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
6092 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
6093 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6094 E1000_WRITE_FLUSH(hw);
6095 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
6096 E1000_WRITE_FLUSH(hw);
6097 } else {
6098 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6099 E1000_WRITE_FLUSH(hw);
6100 }
6101 }
6102
6103 /******************************************************************************
6104 * Clears the VLAN filer table
6105 *
6106 * hw - Struct containing variables accessed by shared code
6107 *****************************************************************************/
6108 STATIC void
6109 em_clear_vfta(struct em_hw *hw)
6110 {
6111 uint32_t offset;
6112 uint32_t vfta_value = 0;
6113 uint32_t vfta_offset = 0;
6114 uint32_t vfta_bit_in_reg = 0;
6115
6116 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
6117 return;
6118
6119 if (hw->mac_type == em_82573) {
6120 if (hw->mng_cookie.vlan_id != 0) {
6121 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
6122 * ID. The following operations determine which 32b entry
6123 * (i.e. offset) into the array we want to set the VLAN ID
6124 * (i.e. bit) of the manageability unit. */
6125 vfta_offset = (hw->mng_cookie.vlan_id >>
6126 E1000_VFTA_ENTRY_SHIFT) &
6127 E1000_VFTA_ENTRY_MASK;
6128 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
6129 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
6130 }
6131 }
6132 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
6133 /* If the offset we want to clear is the same offset of the
6134 * manageability VLAN ID, then clear all bits except that of the
6135 * manageability unit */
6136 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6137 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6138 E1000_WRITE_FLUSH(hw);
6139 }
6140 }
6141
6142 STATIC int32_t
6143 em_id_led_init(struct em_hw * hw)
6144 {
6145 uint32_t ledctl;
6146 const uint32_t ledctl_mask = 0x000000FF;
6147 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6148 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6149 uint16_t eeprom_data, i, temp;
6150 const uint16_t led_mask = 0x0F;
6151
6152 DEBUGFUNC("em_id_led_init");
6153
6154 if (hw->mac_type < em_82540) {
6155 /* Nothing to do */
6156 return E1000_SUCCESS;
6157 }
6158
6159 ledctl = E1000_READ_REG(hw, LEDCTL);
6160 hw->ledctl_default = ledctl;
6161 hw->ledctl_mode1 = hw->ledctl_default;
6162 hw->ledctl_mode2 = hw->ledctl_default;
6163
6164 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6165 DEBUGOUT("EEPROM Read Error\n");
6166 return -E1000_ERR_EEPROM;
6167 }
6168
6169 if ((hw->mac_type == em_82573) &&
6170 (eeprom_data == ID_LED_RESERVED_82573))
6171 eeprom_data = ID_LED_DEFAULT_82573;
6172 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6173 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6174 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan)
6175 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6176 else
6177 eeprom_data = ID_LED_DEFAULT;
6178 }
6179
6180 for (i = 0; i < 4; i++) {
6181 temp = (eeprom_data >> (i << 2)) & led_mask;
6182 switch (temp) {
6183 case ID_LED_ON1_DEF2:
6184 case ID_LED_ON1_ON2:
6185 case ID_LED_ON1_OFF2:
6186 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6187 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6188 break;
6189 case ID_LED_OFF1_DEF2:
6190 case ID_LED_OFF1_ON2:
6191 case ID_LED_OFF1_OFF2:
6192 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6193 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6194 break;
6195 default:
6196 /* Do nothing */
6197 break;
6198 }
6199 switch (temp) {
6200 case ID_LED_DEF1_ON2:
6201 case ID_LED_ON1_ON2:
6202 case ID_LED_OFF1_ON2:
6203 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6204 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6205 break;
6206 case ID_LED_DEF1_OFF2:
6207 case ID_LED_ON1_OFF2:
6208 case ID_LED_OFF1_OFF2:
6209 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6210 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6211 break;
6212 default:
6213 /* Do nothing */
6214 break;
6215 }
6216 }
6217 return E1000_SUCCESS;
6218 }
6219
6220 /******************************************************************************
6221 * Prepares SW controlable LED for use and saves the current state of the LED.
6222 *
6223 * hw - Struct containing variables accessed by shared code
6224 *****************************************************************************/
6225 int32_t
6226 em_setup_led(struct em_hw *hw)
6227 {
6228 uint32_t ledctl;
6229 int32_t ret_val = E1000_SUCCESS;
6230
6231 DEBUGFUNC("em_setup_led");
6232
6233 switch (hw->mac_type) {
6234 case em_82542_rev2_0:
6235 case em_82542_rev2_1:
6236 case em_82543:
6237 case em_82544:
6238 /* No setup necessary */
6239 break;
6240 case em_82541:
6241 case em_82547:
6242 case em_82541_rev_2:
6243 case em_82547_rev_2:
6244 /* Turn off PHY Smart Power Down (if enabled) */
6245 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6246 &hw->phy_spd_default);
6247 if (ret_val)
6248 return ret_val;
6249 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6250 (uint16_t)(hw->phy_spd_default &
6251 ~IGP01E1000_GMII_SPD));
6252 if (ret_val)
6253 return ret_val;
6254 /* Fall Through */
6255 default:
6256 if (hw->media_type == em_media_type_fiber) {
6257 ledctl = E1000_READ_REG(hw, LEDCTL);
6258 /* Save current LEDCTL settings */
6259 hw->ledctl_default = ledctl;
6260 /* Turn off LED0 */
6261 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6262 E1000_LEDCTL_LED0_BLINK |
6263 E1000_LEDCTL_LED0_MODE_MASK);
6264 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6265 E1000_LEDCTL_LED0_MODE_SHIFT);
6266 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6267 } else if (hw->media_type == em_media_type_copper)
6268 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6269 break;
6270 }
6271
6272 return E1000_SUCCESS;
6273 }
6274
6275
6276 /******************************************************************************
6277 * Used on 82571 and later Si that has LED blink bits.
6278 * Callers must use their own timer and should have already called
6279 * em_id_led_init()
6280 * Call em_cleanup led() to stop blinking
6281 *
6282 * hw - Struct containing variables accessed by shared code
6283 *****************************************************************************/
6284 int32_t
6285 em_blink_led_start(struct em_hw *hw)
6286 {
6287 int16_t i;
6288 uint32_t ledctl_blink = 0;
6289
6290 DEBUGFUNC("em_id_led_blink_on");
6291
6292 if (hw->mac_type < em_82571) {
6293 /* Nothing to do */
6294 return E1000_SUCCESS;
6295 }
6296 if (hw->media_type == em_media_type_fiber) {
6297 /* always blink LED0 for PCI-E fiber */
6298 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6299 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6300 } else {
6301 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6302 ledctl_blink = hw->ledctl_mode2;
6303 for (i=0; i < 4; i++)
6304 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6305 E1000_LEDCTL_MODE_LED_ON)
6306 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6307 }
6308
6309 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6310
6311 return E1000_SUCCESS;
6312 }
6313
6314 /******************************************************************************
6315 * Restores the saved state of the SW controlable LED.
6316 *
6317 * hw - Struct containing variables accessed by shared code
6318 *****************************************************************************/
6319 int32_t
6320 em_cleanup_led(struct em_hw *hw)
6321 {
6322 int32_t ret_val = E1000_SUCCESS;
6323
6324 DEBUGFUNC("em_cleanup_led");
6325
6326 switch (hw->mac_type) {
6327 case em_82542_rev2_0:
6328 case em_82542_rev2_1:
6329 case em_82543:
6330 case em_82544:
6331 /* No cleanup necessary */
6332 break;
6333 case em_82541:
6334 case em_82547:
6335 case em_82541_rev_2:
6336 case em_82547_rev_2:
6337 /* Turn on PHY Smart Power Down (if previously enabled) */
6338 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6339 hw->phy_spd_default);
6340 if (ret_val)
6341 return ret_val;
6342 /* Fall Through */
6343 default:
6344 if (hw->phy_type == em_phy_ife) {
6345 em_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6346 break;
6347 }
6348 /* Restore LEDCTL settings */
6349 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6350 break;
6351 }
6352
6353 return E1000_SUCCESS;
6354 }
6355
6356 /******************************************************************************
6357 * Turns on the software controllable LED
6358 *
6359 * hw - Struct containing variables accessed by shared code
6360 *****************************************************************************/
6361 int32_t
6362 em_led_on(struct em_hw *hw)
6363 {
6364 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6365
6366 DEBUGFUNC("em_led_on");
6367
6368 switch (hw->mac_type) {
6369 case em_82542_rev2_0:
6370 case em_82542_rev2_1:
6371 case em_82543:
6372 /* Set SW Defineable Pin 0 to turn on the LED */
6373 ctrl |= E1000_CTRL_SWDPIN0;
6374 ctrl |= E1000_CTRL_SWDPIO0;
6375 break;
6376 case em_82544:
6377 if (hw->media_type == em_media_type_fiber) {
6378 /* Set SW Defineable Pin 0 to turn on the LED */
6379 ctrl |= E1000_CTRL_SWDPIN0;
6380 ctrl |= E1000_CTRL_SWDPIO0;
6381 } else {
6382 /* Clear SW Defineable Pin 0 to turn on the LED */
6383 ctrl &= ~E1000_CTRL_SWDPIN0;
6384 ctrl |= E1000_CTRL_SWDPIO0;
6385 }
6386 break;
6387 default:
6388 if (hw->media_type == em_media_type_fiber) {
6389 /* Clear SW Defineable Pin 0 to turn on the LED */
6390 ctrl &= ~E1000_CTRL_SWDPIN0;
6391 ctrl |= E1000_CTRL_SWDPIO0;
6392 } else if (hw->phy_type == em_phy_ife) {
6393 em_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6394 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6395 } else if (hw->media_type == em_media_type_copper) {
6396 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6397 return E1000_SUCCESS;
6398 }
6399 break;
6400 }
6401
6402 E1000_WRITE_REG(hw, CTRL, ctrl);
6403
6404 return E1000_SUCCESS;
6405 }
6406
6407 /******************************************************************************
6408 * Turns off the software controllable LED
6409 *
6410 * hw - Struct containing variables accessed by shared code
6411 *****************************************************************************/
6412 int32_t
6413 em_led_off(struct em_hw *hw)
6414 {
6415 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6416
6417 DEBUGFUNC("em_led_off");
6418
6419 switch (hw->mac_type) {
6420 case em_82542_rev2_0:
6421 case em_82542_rev2_1:
6422 case em_82543:
6423 /* Clear SW Defineable Pin 0 to turn off the LED */
6424 ctrl &= ~E1000_CTRL_SWDPIN0;
6425 ctrl |= E1000_CTRL_SWDPIO0;
6426 break;
6427 case em_82544:
6428 if (hw->media_type == em_media_type_fiber) {
6429 /* Clear SW Defineable Pin 0 to turn off the LED */
6430 ctrl &= ~E1000_CTRL_SWDPIN0;
6431 ctrl |= E1000_CTRL_SWDPIO0;
6432 } else {
6433 /* Set SW Defineable Pin 0 to turn off the LED */
6434 ctrl |= E1000_CTRL_SWDPIN0;
6435 ctrl |= E1000_CTRL_SWDPIO0;
6436 }
6437 break;
6438 default:
6439 if (hw->media_type == em_media_type_fiber) {
6440 /* Set SW Defineable Pin 0 to turn off the LED */
6441 ctrl |= E1000_CTRL_SWDPIN0;
6442 ctrl |= E1000_CTRL_SWDPIO0;
6443 } else if (hw->phy_type == em_phy_ife) {
6444 em_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6445 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6446 } else if (hw->media_type == em_media_type_copper) {
6447 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6448 return E1000_SUCCESS;
6449 }
6450 break;
6451 }
6452
6453 E1000_WRITE_REG(hw, CTRL, ctrl);
6454
6455 return E1000_SUCCESS;
6456 }
6457
6458 /******************************************************************************
6459 * Clears all hardware statistics counters.
6460 *
6461 * hw - Struct containing variables accessed by shared code
6462 *****************************************************************************/
6463 void
6464 em_clear_hw_cntrs(struct em_hw *hw)
6465 {
6466 volatile uint32_t temp;
6467
6468 temp = E1000_READ_REG(hw, CRCERRS);
6469 temp = E1000_READ_REG(hw, SYMERRS);
6470 temp = E1000_READ_REG(hw, MPC);
6471 temp = E1000_READ_REG(hw, SCC);
6472 temp = E1000_READ_REG(hw, ECOL);
6473 temp = E1000_READ_REG(hw, MCC);
6474 temp = E1000_READ_REG(hw, LATECOL);
6475 temp = E1000_READ_REG(hw, COLC);
6476 temp = E1000_READ_REG(hw, DC);
6477 temp = E1000_READ_REG(hw, SEC);
6478 temp = E1000_READ_REG(hw, RLEC);
6479 temp = E1000_READ_REG(hw, XONRXC);
6480 temp = E1000_READ_REG(hw, XONTXC);
6481 temp = E1000_READ_REG(hw, XOFFRXC);
6482 temp = E1000_READ_REG(hw, XOFFTXC);
6483 temp = E1000_READ_REG(hw, FCRUC);
6484
6485 if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) {
6486 temp = E1000_READ_REG(hw, PRC64);
6487 temp = E1000_READ_REG(hw, PRC127);
6488 temp = E1000_READ_REG(hw, PRC255);
6489 temp = E1000_READ_REG(hw, PRC511);
6490 temp = E1000_READ_REG(hw, PRC1023);
6491 temp = E1000_READ_REG(hw, PRC1522);
6492 }
6493
6494 temp = E1000_READ_REG(hw, GPRC);
6495 temp = E1000_READ_REG(hw, BPRC);
6496 temp = E1000_READ_REG(hw, MPRC);
6497 temp = E1000_READ_REG(hw, GPTC);
6498 temp = E1000_READ_REG(hw, GORCL);
6499 temp = E1000_READ_REG(hw, GORCH);
6500 temp = E1000_READ_REG(hw, GOTCL);
6501 temp = E1000_READ_REG(hw, GOTCH);
6502 temp = E1000_READ_REG(hw, RNBC);
6503 temp = E1000_READ_REG(hw, RUC);
6504 temp = E1000_READ_REG(hw, RFC);
6505 temp = E1000_READ_REG(hw, ROC);
6506 temp = E1000_READ_REG(hw, RJC);
6507 temp = E1000_READ_REG(hw, TORL);
6508 temp = E1000_READ_REG(hw, TORH);
6509 temp = E1000_READ_REG(hw, TOTL);
6510 temp = E1000_READ_REG(hw, TOTH);
6511 temp = E1000_READ_REG(hw, TPR);
6512 temp = E1000_READ_REG(hw, TPT);
6513
6514 if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) {
6515 temp = E1000_READ_REG(hw, PTC64);
6516 temp = E1000_READ_REG(hw, PTC127);
6517 temp = E1000_READ_REG(hw, PTC255);
6518 temp = E1000_READ_REG(hw, PTC511);
6519 temp = E1000_READ_REG(hw, PTC1023);
6520 temp = E1000_READ_REG(hw, PTC1522);
6521 }
6522
6523 temp = E1000_READ_REG(hw, MPTC);
6524 temp = E1000_READ_REG(hw, BPTC);
6525
6526 if (hw->mac_type < em_82543) return;
6527
6528 temp = E1000_READ_REG(hw, ALGNERRC);
6529 temp = E1000_READ_REG(hw, RXERRC);
6530 temp = E1000_READ_REG(hw, TNCRS);
6531 temp = E1000_READ_REG(hw, CEXTERR);
6532 temp = E1000_READ_REG(hw, TSCTC);
6533 temp = E1000_READ_REG(hw, TSCTFC);
6534
6535 if (hw->mac_type <= em_82544) return;
6536
6537 temp = E1000_READ_REG(hw, MGTPRC);
6538 temp = E1000_READ_REG(hw, MGTPDC);
6539 temp = E1000_READ_REG(hw, MGTPTC);
6540
6541 if (hw->mac_type <= em_82547_rev_2) return;
6542
6543 temp = E1000_READ_REG(hw, IAC);
6544 temp = E1000_READ_REG(hw, ICRXOC);
6545
6546 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) return;
6547
6548 temp = E1000_READ_REG(hw, ICRXPTC);
6549 temp = E1000_READ_REG(hw, ICRXATC);
6550 temp = E1000_READ_REG(hw, ICTXPTC);
6551 temp = E1000_READ_REG(hw, ICTXATC);
6552 temp = E1000_READ_REG(hw, ICTXQEC);
6553 temp = E1000_READ_REG(hw, ICTXQMTC);
6554 temp = E1000_READ_REG(hw, ICRXDMTC);
6555
6556 }
6557
6558 /******************************************************************************
6559 * Resets Adaptive IFS to its default state.
6560 *
6561 * hw - Struct containing variables accessed by shared code
6562 *
6563 * Call this after em_init_hw. You may override the IFS defaults by setting
6564 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6565 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6566 * before calling this function.
6567 *****************************************************************************/
6568 void
6569 em_reset_adaptive(struct em_hw *hw)
6570 {
6571 DEBUGFUNC("em_reset_adaptive");
6572
6573 if (hw->adaptive_ifs) {
6574 if (!hw->ifs_params_forced) {
6575 hw->current_ifs_val = 0;
6576 hw->ifs_min_val = IFS_MIN;
6577 hw->ifs_max_val = IFS_MAX;
6578 hw->ifs_step_size = IFS_STEP;
6579 hw->ifs_ratio = IFS_RATIO;
6580 }
6581 hw->in_ifs_mode = FALSE;
6582 E1000_WRITE_REG(hw, AIT, 0);
6583 } else {
6584 DEBUGOUT("Not in Adaptive IFS mode!\n");
6585 }
6586 }
6587
6588 /******************************************************************************
6589 * Called during the callback/watchdog routine to update IFS value based on
6590 * the ratio of transmits to collisions.
6591 *
6592 * hw - Struct containing variables accessed by shared code
6593 * tx_packets - Number of transmits since last callback
6594 * total_collisions - Number of collisions since last callback
6595 *****************************************************************************/
6596 void
6597 em_update_adaptive(struct em_hw *hw)
6598 {
6599 DEBUGFUNC("em_update_adaptive");
6600
6601 if (hw->adaptive_ifs) {
6602 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6603 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6604 hw->in_ifs_mode = TRUE;
6605 if (hw->current_ifs_val < hw->ifs_max_val) {
6606 if (hw->current_ifs_val == 0)
6607 hw->current_ifs_val = hw->ifs_min_val;
6608 else
6609 hw->current_ifs_val += hw->ifs_step_size;
6610 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6611 }
6612 }
6613 } else {
6614 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6615 hw->current_ifs_val = 0;
6616 hw->in_ifs_mode = FALSE;
6617 E1000_WRITE_REG(hw, AIT, 0);
6618 }
6619 }
6620 } else {
6621 DEBUGOUT("Not in Adaptive IFS mode!\n");
6622 }
6623 }
6624
6625 /******************************************************************************
6626 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6627 *
6628 * hw - Struct containing variables accessed by shared code
6629 * frame_len - The length of the frame in question
6630 * mac_addr - The Ethernet destination address of the frame in question
6631 *****************************************************************************/
6632 void
6633 em_tbi_adjust_stats(struct em_hw *hw,
6634 struct em_hw_stats *stats,
6635 uint32_t frame_len,
6636 uint8_t *mac_addr)
6637 {
6638 uint64_t carry_bit;
6639
6640 /* First adjust the frame length. */
6641 frame_len--;
6642 /* We need to adjust the statistics counters, since the hardware
6643 * counters overcount this packet as a CRC error and undercount
6644 * the packet as a good packet
6645 */
6646 /* This packet should not be counted as a CRC error. */
6647 stats->crcerrs--;
6648 /* This packet does count as a Good Packet Received. */
6649 stats->gprc++;
6650
6651 /* Adjust the Good Octets received counters */
6652 carry_bit = 0x80000000 & stats->gorcl;
6653 stats->gorcl += frame_len;
6654 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6655 * Received Count) was one before the addition,
6656 * AND it is zero after, then we lost the carry out,
6657 * need to add one to Gorch (Good Octets Received Count High).
6658 * This could be simplified if all environments supported
6659 * 64-bit integers.
6660 */
6661 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6662 stats->gorch++;
6663 /* Is this a broadcast or multicast? Check broadcast first,
6664 * since the test for a multicast frame will test positive on
6665 * a broadcast frame.
6666 */
6667 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6668 /* Broadcast packet */
6669 stats->bprc++;
6670 else if (*mac_addr & 0x01)
6671 /* Multicast packet */
6672 stats->mprc++;
6673
6674 if (frame_len == hw->max_frame_size) {
6675 /* In this case, the hardware has overcounted the number of
6676 * oversize frames.
6677 */
6678 if (stats->roc > 0)
6679 stats->roc--;
6680 }
6681
6682 /* Adjust the bin counters when the extra byte put the frame in the
6683 * wrong bin. Remember that the frame_len was adjusted above.
6684 */
6685 if (frame_len == 64) {
6686 stats->prc64++;
6687 stats->prc127--;
6688 } else if (frame_len == 127) {
6689 stats->prc127++;
6690 stats->prc255--;
6691 } else if (frame_len == 255) {
6692 stats->prc255++;
6693 stats->prc511--;
6694 } else if (frame_len == 511) {
6695 stats->prc511++;
6696 stats->prc1023--;
6697 } else if (frame_len == 1023) {
6698 stats->prc1023++;
6699 stats->prc1522--;
6700 } else if (frame_len == 1522) {
6701 stats->prc1522++;
6702 }
6703 }
6704
6705 /******************************************************************************
6706 * Gets the current PCI bus type, speed, and width of the hardware
6707 *
6708 * hw - Struct containing variables accessed by shared code
6709 *****************************************************************************/
6710 void
6711 em_get_bus_info(struct em_hw *hw)
6712 {
6713 int32_t ret_val;
6714 uint16_t pci_ex_link_status;
6715 uint32_t status;
6716
6717 switch (hw->mac_type) {
6718 case em_82542_rev2_0:
6719 case em_82542_rev2_1:
6720 hw->bus_type = em_bus_type_unknown;
6721 hw->bus_speed = em_bus_speed_unknown;
6722 hw->bus_width = em_bus_width_unknown;
6723 break;
6724 case em_82571:
6725 case em_82572:
6726 case em_82573:
6727 case em_80003es2lan:
6728 hw->bus_type = em_bus_type_pci_express;
6729 hw->bus_speed = em_bus_speed_2500;
6730 ret_val = em_read_pcie_cap_reg(hw,
6731 PCI_EX_LINK_STATUS,
6732 &pci_ex_link_status);
6733 if (ret_val)
6734 hw->bus_width = em_bus_width_unknown;
6735 else
6736 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6737 PCI_EX_LINK_WIDTH_SHIFT;
6738 break;
6739 case em_ich8lan:
6740 case em_ich9lan:
6741 hw->bus_type = em_bus_type_pci_express;
6742 hw->bus_speed = em_bus_speed_2500;
6743 hw->bus_width = em_bus_width_pciex_1;
6744 break;
6745 default:
6746 status = E1000_READ_REG(hw, STATUS);
6747 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6748 em_bus_type_pcix : em_bus_type_pci;
6749
6750 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6751 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
6752 em_bus_speed_66 : em_bus_speed_120;
6753 } else if (hw->bus_type == em_bus_type_pci) {
6754 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6755 em_bus_speed_66 : em_bus_speed_33;
6756 } else {
6757 switch (status & E1000_STATUS_PCIX_SPEED) {
6758 case E1000_STATUS_PCIX_SPEED_66:
6759 hw->bus_speed = em_bus_speed_66;
6760 break;
6761 case E1000_STATUS_PCIX_SPEED_100:
6762 hw->bus_speed = em_bus_speed_100;
6763 break;
6764 case E1000_STATUS_PCIX_SPEED_133:
6765 hw->bus_speed = em_bus_speed_133;
6766 break;
6767 default:
6768 hw->bus_speed = em_bus_speed_reserved;
6769 break;
6770 }
6771 }
6772 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6773 em_bus_width_64 : em_bus_width_32;
6774 break;
6775 }
6776 }
6777
6778 /******************************************************************************
6779 * Writes a value to one of the devices registers using port I/O (as opposed to
6780 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6781 *
6782 * hw - Struct containing variables accessed by shared code
6783 * offset - offset to write to
6784 * value - value to write
6785 *****************************************************************************/
6786 STATIC void
6787 em_write_reg_io(struct em_hw *hw,
6788 uint32_t offset,
6789 uint32_t value)
6790 {
6791 unsigned long io_addr = hw->io_base;
6792 unsigned long io_data = hw->io_base + 4;
6793
6794 em_io_write(hw, io_addr, offset);
6795 em_io_write(hw, io_data, value);
6796 }
6797
6798 /******************************************************************************
6799 * Estimates the cable length.
6800 *
6801 * hw - Struct containing variables accessed by shared code
6802 * min_length - The estimated minimum length
6803 * max_length - The estimated maximum length
6804 *
6805 * returns: - E1000_ERR_XXX
6806 * E1000_SUCCESS
6807 *
6808 * This function always returns a ranged length (minimum & maximum).
6809 * So for M88 phy's, this function interprets the one value returned from the
6810 * register to the minimum and maximum range.
6811 * For IGP phy's, the function calculates the range by the AGC registers.
6812 *****************************************************************************/
6813 STATIC int32_t
6814 em_get_cable_length(struct em_hw *hw,
6815 uint16_t *min_length,
6816 uint16_t *max_length)
6817 {
6818 int32_t ret_val;
6819 uint16_t agc_value = 0;
6820 uint16_t i, phy_data;
6821 uint16_t cable_length;
6822
6823 DEBUGFUNC("em_get_cable_length");
6824
6825 *min_length = *max_length = 0;
6826
6827 /* Use old method for Phy older than IGP */
6828 if (hw->phy_type == em_phy_m88) {
6829
6830 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6831 &phy_data);
6832 if (ret_val)
6833 return ret_val;
6834 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6835 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6836
6837 /* Convert the enum value to ranged values */
6838 switch (cable_length) {
6839 case em_cable_length_50:
6840 *min_length = 0;
6841 *max_length = em_igp_cable_length_50;
6842 break;
6843 case em_cable_length_50_80:
6844 *min_length = em_igp_cable_length_50;
6845 *max_length = em_igp_cable_length_80;
6846 break;
6847 case em_cable_length_80_110:
6848 *min_length = em_igp_cable_length_80;
6849 *max_length = em_igp_cable_length_110;
6850 break;
6851 case em_cable_length_110_140:
6852 *min_length = em_igp_cable_length_110;
6853 *max_length = em_igp_cable_length_140;
6854 break;
6855 case em_cable_length_140:
6856 *min_length = em_igp_cable_length_140;
6857 *max_length = em_igp_cable_length_170;
6858 break;
6859 default:
6860 return -E1000_ERR_PHY;
6861 break;
6862 }
6863 } else if (hw->phy_type == em_phy_gg82563) {
6864 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6865 &phy_data);
6866 if (ret_val)
6867 return ret_val;
6868 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6869
6870 switch (cable_length) {
6871 case em_gg_cable_length_60:
6872 *min_length = 0;
6873 *max_length = em_igp_cable_length_60;
6874 break;
6875 case em_gg_cable_length_60_115:
6876 *min_length = em_igp_cable_length_60;
6877 *max_length = em_igp_cable_length_115;
6878 break;
6879 case em_gg_cable_length_115_150:
6880 *min_length = em_igp_cable_length_115;
6881 *max_length = em_igp_cable_length_150;
6882 break;
6883 case em_gg_cable_length_150:
6884 *min_length = em_igp_cable_length_150;
6885 *max_length = em_igp_cable_length_180;
6886 break;
6887 default:
6888 return -E1000_ERR_PHY;
6889 break;
6890 }
6891 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */
6892 uint16_t cur_agc_value;
6893 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6894 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6895 {IGP01E1000_PHY_AGC_A,
6896 IGP01E1000_PHY_AGC_B,
6897 IGP01E1000_PHY_AGC_C,
6898 IGP01E1000_PHY_AGC_D};
6899 /* Read the AGC registers for all channels */
6900 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6901
6902 ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6903 if (ret_val)
6904 return ret_val;
6905
6906 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6907
6908 /* Value bound check. */
6909 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6910 (cur_agc_value == 0))
6911 return -E1000_ERR_PHY;
6912
6913 agc_value += cur_agc_value;
6914
6915 /* Update minimal AGC value. */
6916 if (min_agc_value > cur_agc_value)
6917 min_agc_value = cur_agc_value;
6918 }
6919
6920 /* Remove the minimal AGC result for length < 50m */
6921 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) {
6922 agc_value -= min_agc_value;
6923
6924 /* Get the average length of the remaining 3 channels */
6925 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6926 } else {
6927 /* Get the average length of all the 4 channels. */
6928 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6929 }
6930
6931 /* Set the range of the calculated length. */
6932 *min_length = ((em_igp_cable_length_table[agc_value] -
6933 IGP01E1000_AGC_RANGE) > 0) ?
6934 (em_igp_cable_length_table[agc_value] -
6935 IGP01E1000_AGC_RANGE) : 0;
6936 *max_length = em_igp_cable_length_table[agc_value] +
6937 IGP01E1000_AGC_RANGE;
6938 } else if (hw->phy_type == em_phy_igp_2 ||
6939 hw->phy_type == em_phy_igp_3) {
6940 uint16_t cur_agc_index, max_agc_index = 0;
6941 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6942 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6943 {IGP02E1000_PHY_AGC_A,
6944 IGP02E1000_PHY_AGC_B,
6945 IGP02E1000_PHY_AGC_C,
6946 IGP02E1000_PHY_AGC_D};
6947 /* Read the AGC registers for all channels */
6948 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6949 ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6950 if (ret_val)
6951 return ret_val;
6952
6953 /* Getting bits 15:9, which represent the combination of course and
6954 * fine gain values. The result is a number that can be put into
6955 * the lookup table to obtain the approximate cable length. */
6956 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6957 IGP02E1000_AGC_LENGTH_MASK;
6958
6959 /* Array index bound check. */
6960 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6961 (cur_agc_index == 0))
6962 return -E1000_ERR_PHY;
6963
6964 /* Remove min & max AGC values from calculation. */
6965 if (em_igp_2_cable_length_table[min_agc_index] >
6966 em_igp_2_cable_length_table[cur_agc_index])
6967 min_agc_index = cur_agc_index;
6968 if (em_igp_2_cable_length_table[max_agc_index] <
6969 em_igp_2_cable_length_table[cur_agc_index])
6970 max_agc_index = cur_agc_index;
6971
6972 agc_value += em_igp_2_cable_length_table[cur_agc_index];
6973 }
6974
6975 agc_value -= (em_igp_2_cable_length_table[min_agc_index] +
6976 em_igp_2_cable_length_table[max_agc_index]);
6977 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6978
6979 /* Calculate cable length with the error range of +/- 10 meters. */
6980 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6981 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6982 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6983 }
6984
6985 return E1000_SUCCESS;
6986 }
6987
6988 /******************************************************************************
6989 * Check the cable polarity
6990 *
6991 * hw - Struct containing variables accessed by shared code
6992 * polarity - output parameter : 0 - Polarity is not reversed
6993 * 1 - Polarity is reversed.
6994 *
6995 * returns: - E1000_ERR_XXX
6996 * E1000_SUCCESS
6997 *
6998 * For phy's older then IGP, this function simply reads the polarity bit in the
6999 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
7000 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
7001 * return 0. If the link speed is 1000 Mbps the polarity status is in the
7002 * IGP01E1000_PHY_PCS_INIT_REG.
7003 *****************************************************************************/
7004 STATIC int32_t
7005 em_check_polarity(struct em_hw *hw,
7006 em_rev_polarity *polarity)
7007 {
7008 int32_t ret_val;
7009 uint16_t phy_data;
7010
7011 DEBUGFUNC("em_check_polarity");
7012
7013 if ((hw->phy_type == em_phy_m88) ||
7014 (hw->phy_type == em_phy_gg82563)) {
7015 /* return the Polarity bit in the Status register. */
7016 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7017 &phy_data);
7018 if (ret_val)
7019 return ret_val;
7020 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
7021 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
7022 em_rev_polarity_reversed : em_rev_polarity_normal;
7023
7024 } else if (hw->phy_type == em_phy_igp ||
7025 hw->phy_type == em_phy_igp_3 ||
7026 hw->phy_type == em_phy_igp_2) {
7027 /* Read the Status register to check the speed */
7028 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
7029 &phy_data);
7030 if (ret_val)
7031 return ret_val;
7032
7033 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
7034 * find the polarity status */
7035 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
7036 IGP01E1000_PSSR_SPEED_1000MBPS) {
7037
7038 /* Read the GIG initialization PCS register (0x00B4) */
7039 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
7040 &phy_data);
7041 if (ret_val)
7042 return ret_val;
7043
7044 /* Check the polarity bits */
7045 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
7046 em_rev_polarity_reversed : em_rev_polarity_normal;
7047 } else {
7048 /* For 10 Mbps, read the polarity bit in the status register. (for
7049 * 100 Mbps this bit is always 0) */
7050 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
7051 em_rev_polarity_reversed : em_rev_polarity_normal;
7052 }
7053 } else if (hw->phy_type == em_phy_ife) {
7054 ret_val = em_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
7055 &phy_data);
7056 if (ret_val)
7057 return ret_val;
7058 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
7059 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
7060 em_rev_polarity_reversed : em_rev_polarity_normal;
7061 }
7062 return E1000_SUCCESS;
7063 }
7064
7065 /******************************************************************************
7066 * Check if Downshift occured
7067 *
7068 * hw - Struct containing variables accessed by shared code
7069 * downshift - output parameter : 0 - No Downshift ocured.
7070 * 1 - Downshift ocured.
7071 *
7072 * returns: - E1000_ERR_XXX
7073 * E1000_SUCCESS
7074 *
7075 * For phy's older then IGP, this function reads the Downshift bit in the Phy
7076 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
7077 * Link Health register. In IGP this bit is latched high, so the driver must
7078 * read it immediately after link is established.
7079 *****************************************************************************/
7080 STATIC int32_t
7081 em_check_downshift(struct em_hw *hw)
7082 {
7083 int32_t ret_val;
7084 uint16_t phy_data;
7085
7086 DEBUGFUNC("em_check_downshift");
7087
7088 if (hw->phy_type == em_phy_igp ||
7089 hw->phy_type == em_phy_igp_3 ||
7090 hw->phy_type == em_phy_igp_2) {
7091 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
7092 &phy_data);
7093 if (ret_val)
7094 return ret_val;
7095
7096 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
7097 } else if ((hw->phy_type == em_phy_m88) ||
7098 (hw->phy_type == em_phy_gg82563)) {
7099 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7100 &phy_data);
7101 if (ret_val)
7102 return ret_val;
7103
7104 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
7105 M88E1000_PSSR_DOWNSHIFT_SHIFT;
7106 } else if (hw->phy_type == em_phy_ife) {
7107 /* em_phy_ife supports 10/100 speed only */
7108 hw->speed_downgraded = FALSE;
7109 }
7110
7111 return E1000_SUCCESS;
7112 }
7113
7114 /*****************************************************************************
7115 *
7116 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
7117 * gigabit link is achieved to improve link quality.
7118 *
7119 * hw: Struct containing variables accessed by shared code
7120 *
7121 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7122 * E1000_SUCCESS at any other case.
7123 *
7124 ****************************************************************************/
7125
7126 STATIC int32_t
7127 em_config_dsp_after_link_change(struct em_hw *hw,
7128 boolean_t link_up)
7129 {
7130 int32_t ret_val;
7131 uint16_t phy_data, phy_saved_data, speed, duplex, i;
7132 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7133 {IGP01E1000_PHY_AGC_PARAM_A,
7134 IGP01E1000_PHY_AGC_PARAM_B,
7135 IGP01E1000_PHY_AGC_PARAM_C,
7136 IGP01E1000_PHY_AGC_PARAM_D};
7137 uint16_t min_length, max_length;
7138
7139 DEBUGFUNC("em_config_dsp_after_link_change");
7140
7141 if (hw->phy_type != em_phy_igp)
7142 return E1000_SUCCESS;
7143
7144 if (link_up) {
7145 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
7146 if (ret_val) {
7147 DEBUGOUT("Error getting link speed and duplex\n");
7148 return ret_val;
7149 }
7150
7151 if (speed == SPEED_1000) {
7152
7153 ret_val = em_get_cable_length(hw, &min_length, &max_length);
7154 if (ret_val)
7155 return ret_val;
7156
7157 if ((hw->dsp_config_state == em_dsp_config_enabled) &&
7158 min_length >= em_igp_cable_length_50) {
7159
7160 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7161 ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
7162 &phy_data);
7163 if (ret_val)
7164 return ret_val;
7165
7166 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7167
7168 ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
7169 phy_data);
7170 if (ret_val)
7171 return ret_val;
7172 }
7173 hw->dsp_config_state = em_dsp_config_activated;
7174 }
7175
7176 if ((hw->ffe_config_state == em_ffe_config_enabled) &&
7177 (min_length < em_igp_cable_length_50)) {
7178
7179 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7180 uint32_t idle_errs = 0;
7181
7182 /* clear previous idle error counts */
7183 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
7184 &phy_data);
7185 if (ret_val)
7186 return ret_val;
7187
7188 for (i = 0; i < ffe_idle_err_timeout; i++) {
7189 usec_delay(1000);
7190 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
7191 &phy_data);
7192 if (ret_val)
7193 return ret_val;
7194
7195 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7196 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7197 hw->ffe_config_state = em_ffe_config_active;
7198
7199 ret_val = em_write_phy_reg(hw,
7200 IGP01E1000_PHY_DSP_FFE,
7201 IGP01E1000_PHY_DSP_FFE_CM_CP);
7202 if (ret_val)
7203 return ret_val;
7204 break;
7205 }
7206
7207 if (idle_errs)
7208 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7209 }
7210 }
7211 }
7212 } else {
7213 if (hw->dsp_config_state == em_dsp_config_activated) {
7214 /* Save off the current value of register 0x2F5B to be restored at
7215 * the end of the routines. */
7216 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7217
7218 if (ret_val)
7219 return ret_val;
7220
7221 /* Disable the PHY transmitter */
7222 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
7223
7224 if (ret_val)
7225 return ret_val;
7226
7227 msec_delay_irq(20);
7228
7229 ret_val = em_write_phy_reg(hw, 0x0000,
7230 IGP01E1000_IEEE_FORCE_GIGA);
7231 if (ret_val)
7232 return ret_val;
7233 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7234 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7235 if (ret_val)
7236 return ret_val;
7237
7238 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7239 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7240
7241 ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7242 if (ret_val)
7243 return ret_val;
7244 }
7245
7246 ret_val = em_write_phy_reg(hw, 0x0000,
7247 IGP01E1000_IEEE_RESTART_AUTONEG);
7248 if (ret_val)
7249 return ret_val;
7250
7251 msec_delay_irq(20);
7252
7253 /* Now enable the transmitter */
7254 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7255
7256 if (ret_val)
7257 return ret_val;
7258
7259 hw->dsp_config_state = em_dsp_config_enabled;
7260 }
7261
7262 if (hw->ffe_config_state == em_ffe_config_active) {
7263 /* Save off the current value of register 0x2F5B to be restored at
7264 * the end of the routines. */
7265 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7266
7267 if (ret_val)
7268 return ret_val;
7269
7270 /* Disable the PHY transmitter */
7271 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
7272
7273 if (ret_val)
7274 return ret_val;
7275
7276 msec_delay_irq(20);
7277
7278 ret_val = em_write_phy_reg(hw, 0x0000,
7279 IGP01E1000_IEEE_FORCE_GIGA);
7280 if (ret_val)
7281 return ret_val;
7282 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7283 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7284 if (ret_val)
7285 return ret_val;
7286
7287 ret_val = em_write_phy_reg(hw, 0x0000,
7288 IGP01E1000_IEEE_RESTART_AUTONEG);
7289 if (ret_val)
7290 return ret_val;
7291
7292 msec_delay_irq(20);
7293
7294 /* Now enable the transmitter */
7295 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7296
7297 if (ret_val)
7298 return ret_val;
7299
7300 hw->ffe_config_state = em_ffe_config_enabled;
7301 }
7302 }
7303 return E1000_SUCCESS;
7304 }
7305
7306 /*****************************************************************************
7307 * Set PHY to class A mode
7308 * Assumes the following operations will follow to enable the new class mode.
7309 * 1. Do a PHY soft reset
7310 * 2. Restart auto-negotiation or force link.
7311 *
7312 * hw - Struct containing variables accessed by shared code
7313 ****************************************************************************/
7314 static int32_t
7315 em_set_phy_mode(struct em_hw *hw)
7316 {
7317 int32_t ret_val;
7318 uint16_t eeprom_data;
7319
7320 DEBUGFUNC("em_set_phy_mode");
7321
7322 if ((hw->mac_type == em_82545_rev_3) &&
7323 (hw->media_type == em_media_type_copper)) {
7324 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7325 if (ret_val) {
7326 return ret_val;
7327 }
7328
7329 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7330 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7331 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7332 if (ret_val)
7333 return ret_val;
7334 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7335 if (ret_val)
7336 return ret_val;
7337
7338 hw->phy_reset_disable = FALSE;
7339 }
7340 }
7341
7342 return E1000_SUCCESS;
7343 }
7344
7345 /*****************************************************************************
7346 *
7347 * This function sets the lplu state according to the active flag. When
7348 * activating lplu this function also disables smart speed and vise versa.
7349 * lplu will not be activated unless the device autonegotiation advertisment
7350 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7351 * hw: Struct containing variables accessed by shared code
7352 * active - true to enable lplu false to disable lplu.
7353 *
7354 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7355 * E1000_SUCCESS at any other case.
7356 *
7357 ****************************************************************************/
7358
7359 STATIC int32_t
7360 em_set_d3_lplu_state(struct em_hw *hw,
7361 boolean_t active)
7362 {
7363 uint32_t phy_ctrl = 0;
7364 int32_t ret_val;
7365 uint16_t phy_data;
7366 DEBUGFUNC("em_set_d3_lplu_state");
7367
7368 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2
7369 && hw->phy_type != em_phy_igp_3)
7370 return E1000_SUCCESS;
7371
7372 /* During driver activity LPLU should not be used or it will attain link
7373 * from the lowest speeds starting from 10Mbps. The capability is used for
7374 * Dx transitions and states */
7375 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
7376 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7377 if (ret_val)
7378 return ret_val;
7379 } else if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
7380 /* MAC writes into PHY register based on the state transition
7381 * and start auto-negotiation. SW driver can overwrite the settings
7382 * in CSR PHY power control E1000_PHY_CTRL register. */
7383 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7384 } else {
7385 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7386 if (ret_val)
7387 return ret_val;
7388 }
7389
7390 if (!active) {
7391 if (hw->mac_type == em_82541_rev_2 ||
7392 hw->mac_type == em_82547_rev_2) {
7393 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7394 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7395 if (ret_val)
7396 return ret_val;
7397 } else {
7398 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
7399 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7400 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7401 } else {
7402 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7403 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7404 phy_data);
7405 if (ret_val)
7406 return ret_val;
7407 }
7408 }
7409
7410 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7411 * Dx states where the power conservation is most important. During
7412 * driver activity we should enable SmartSpeed, so performance is
7413 * maintained. */
7414 if (hw->smart_speed == em_smart_speed_on) {
7415 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7416 &phy_data);
7417 if (ret_val)
7418 return ret_val;
7419
7420 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7421 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7422 phy_data);
7423 if (ret_val)
7424 return ret_val;
7425 } else if (hw->smart_speed == em_smart_speed_off) {
7426 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7427 &phy_data);
7428 if (ret_val)
7429 return ret_val;
7430
7431 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7432 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7433 phy_data);
7434 if (ret_val)
7435 return ret_val;
7436 }
7437
7438 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7439 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7440 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7441
7442 if (hw->mac_type == em_82541_rev_2 ||
7443 hw->mac_type == em_82547_rev_2) {
7444 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7445 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7446 if (ret_val)
7447 return ret_val;
7448 } else {
7449 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
7450 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7451 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7452 } else {
7453 phy_data |= IGP02E1000_PM_D3_LPLU;
7454 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7455 phy_data);
7456 if (ret_val)
7457 return ret_val;
7458 }
7459 }
7460
7461 /* When LPLU is enabled we should disable SmartSpeed */
7462 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7463 if (ret_val)
7464 return ret_val;
7465
7466 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7467 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7468 if (ret_val)
7469 return ret_val;
7470
7471 }
7472 return E1000_SUCCESS;
7473 }
7474
7475 /*****************************************************************************
7476 *
7477 * This function sets the lplu d0 state according to the active flag. When
7478 * activating lplu this function also disables smart speed and vise versa.
7479 * lplu will not be activated unless the device autonegotiation advertisment
7480 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7481 * hw: Struct containing variables accessed by shared code
7482 * active - true to enable lplu false to disable lplu.
7483 *
7484 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7485 * E1000_SUCCESS at any other case.
7486 *
7487 ****************************************************************************/
7488
7489 STATIC int32_t
7490 em_set_d0_lplu_state(struct em_hw *hw,
7491 boolean_t active)
7492 {
7493 uint32_t phy_ctrl = 0;
7494 int32_t ret_val;
7495 uint16_t phy_data;
7496 DEBUGFUNC("em_set_d0_lplu_state");
7497
7498 if (hw->mac_type <= em_82547_rev_2)
7499 return E1000_SUCCESS;
7500
7501 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
7502 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7503 } else {
7504 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7505 if (ret_val)
7506 return ret_val;
7507 }
7508
7509 if (!active) {
7510 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
7511 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7512 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7513 } else {
7514 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7515 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7516 if (ret_val)
7517 return ret_val;
7518 }
7519
7520 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7521 * Dx states where the power conservation is most important. During
7522 * driver activity we should enable SmartSpeed, so performance is
7523 * maintained. */
7524 if (hw->smart_speed == em_smart_speed_on) {
7525 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7526 &phy_data);
7527 if (ret_val)
7528 return ret_val;
7529
7530 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7531 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7532 phy_data);
7533 if (ret_val)
7534 return ret_val;
7535 } else if (hw->smart_speed == em_smart_speed_off) {
7536 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7537 &phy_data);
7538 if (ret_val)
7539 return ret_val;
7540
7541 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7542 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7543 phy_data);
7544 if (ret_val)
7545 return ret_val;
7546 }
7547
7548
7549 } else {
7550
7551 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
7552 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7553 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7554 } else {
7555 phy_data |= IGP02E1000_PM_D0_LPLU;
7556 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7557 if (ret_val)
7558 return ret_val;
7559 }
7560
7561 /* When LPLU is enabled we should disable SmartSpeed */
7562 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7563 if (ret_val)
7564 return ret_val;
7565
7566 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7567 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7568 if (ret_val)
7569 return ret_val;
7570
7571 }
7572 return E1000_SUCCESS;
7573 }
7574
7575 /******************************************************************************
7576 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7577 *
7578 * hw - Struct containing variables accessed by shared code
7579 *****************************************************************************/
7580 static int32_t
7581 em_set_vco_speed(struct em_hw *hw)
7582 {
7583 int32_t ret_val;
7584 uint16_t default_page = 0;
7585 uint16_t phy_data;
7586
7587 DEBUGFUNC("em_set_vco_speed");
7588
7589 switch (hw->mac_type) {
7590 case em_82545_rev_3:
7591 case em_82546_rev_3:
7592 break;
7593 default:
7594 return E1000_SUCCESS;
7595 }
7596
7597 /* Set PHY register 30, page 5, bit 8 to 0 */
7598
7599 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7600 if (ret_val)
7601 return ret_val;
7602
7603 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7604 if (ret_val)
7605 return ret_val;
7606
7607 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7608 if (ret_val)
7609 return ret_val;
7610
7611 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7612 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7613 if (ret_val)
7614 return ret_val;
7615
7616 /* Set PHY register 30, page 4, bit 11 to 1 */
7617
7618 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7619 if (ret_val)
7620 return ret_val;
7621
7622 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7623 if (ret_val)
7624 return ret_val;
7625
7626 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7627 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7628 if (ret_val)
7629 return ret_val;
7630
7631 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7632 if (ret_val)
7633 return ret_val;
7634
7635 return E1000_SUCCESS;
7636 }
7637
7638
7639 /*****************************************************************************
7640 * This function reads the cookie from ARC ram.
7641 *
7642 * returns: - E1000_SUCCESS .
7643 ****************************************************************************/
7644 STATIC int32_t
7645 em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer)
7646 {
7647 uint8_t i;
7648 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7649 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7650
7651 length = (length >> 2);
7652 offset = (offset >> 2);
7653
7654 for (i = 0; i < length; i++) {
7655 *((uint32_t *) buffer + i) =
7656 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7657 }
7658 return E1000_SUCCESS;
7659 }
7660
7661
7662 /*****************************************************************************
7663 * This function checks whether the HOST IF is enabled for command operaton
7664 * and also checks whether the previous command is completed.
7665 * It busy waits in case of previous command is not completed.
7666 *
7667 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7668 * timeout
7669 * - E1000_SUCCESS for success.
7670 ****************************************************************************/
7671 STATIC int32_t
7672 em_mng_enable_host_if(struct em_hw * hw)
7673 {
7674 uint32_t hicr;
7675 uint8_t i;
7676
7677 /* Check that the host interface is enabled. */
7678 hicr = E1000_READ_REG(hw, HICR);
7679 if ((hicr & E1000_HICR_EN) == 0) {
7680 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7681 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7682 }
7683 /* check the previous command is completed */
7684 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7685 hicr = E1000_READ_REG(hw, HICR);
7686 if (!(hicr & E1000_HICR_C))
7687 break;
7688 msec_delay_irq(1);
7689 }
7690
7691 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7692 DEBUGOUT("Previous command timeout failed .\n");
7693 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7694 }
7695 return E1000_SUCCESS;
7696 }
7697
7698 /*****************************************************************************
7699 * This function writes the buffer content at the offset given on the host if.
7700 * It also does alignment considerations to do the writes in most efficient way.
7701 * Also fills up the sum of the buffer in *buffer parameter.
7702 *
7703 * returns - E1000_SUCCESS for success.
7704 ****************************************************************************/
7705 STATIC int32_t
7706 em_mng_host_if_write(struct em_hw * hw, uint8_t *buffer,
7707 uint16_t length, uint16_t offset, uint8_t *sum)
7708 {
7709 uint8_t *tmp;
7710 uint8_t *bufptr = buffer;
7711 uint32_t data = 0;
7712 uint16_t remaining, i, j, prev_bytes;
7713
7714 /* sum = only sum of the data and it is not checksum */
7715
7716 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7717 return -E1000_ERR_PARAM;
7718 }
7719
7720 tmp = (uint8_t *)&data;
7721 prev_bytes = offset & 0x3;
7722 offset &= 0xFFFC;
7723 offset >>= 2;
7724
7725 if (prev_bytes) {
7726 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7727 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7728 *(tmp + j) = *bufptr++;
7729 *sum += *(tmp + j);
7730 }
7731 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7732 length -= j - prev_bytes;
7733 offset++;
7734 }
7735
7736 remaining = length & 0x3;
7737 length -= remaining;
7738
7739 /* Calculate length in DWORDs */
7740 length >>= 2;
7741
7742 /* The device driver writes the relevant command block into the
7743 * ram area. */
7744 for (i = 0; i < length; i++) {
7745 for (j = 0; j < sizeof(uint32_t); j++) {
7746 *(tmp + j) = *bufptr++;
7747 *sum += *(tmp + j);
7748 }
7749
7750 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7751 }
7752 if (remaining) {
7753 for (j = 0; j < sizeof(uint32_t); j++) {
7754 if (j < remaining)
7755 *(tmp + j) = *bufptr++;
7756 else
7757 *(tmp + j) = 0;
7758
7759 *sum += *(tmp + j);
7760 }
7761 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7762 }
7763
7764 return E1000_SUCCESS;
7765 }
7766
7767
7768 /*****************************************************************************
7769 * This function writes the command header after does the checksum calculation.
7770 *
7771 * returns - E1000_SUCCESS for success.
7772 ****************************************************************************/
7773 STATIC int32_t
7774 em_mng_write_cmd_header(struct em_hw * hw,
7775 struct em_host_mng_command_header * hdr)
7776 {
7777 uint16_t i;
7778 uint8_t sum;
7779 uint8_t *buffer;
7780
7781 /* Write the whole command header structure which includes sum of
7782 * the buffer */
7783
7784 uint16_t length = sizeof(struct em_host_mng_command_header);
7785
7786 sum = hdr->checksum;
7787 hdr->checksum = 0;
7788
7789 buffer = (uint8_t *) hdr;
7790 i = length;
7791 while (i--)
7792 sum += buffer[i];
7793
7794 hdr->checksum = 0 - sum;
7795
7796 length >>= 2;
7797 /* The device driver writes the relevant command block into the ram area. */
7798 for (i = 0; i < length; i++) {
7799 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7800 E1000_WRITE_FLUSH(hw);
7801 }
7802
7803 return E1000_SUCCESS;
7804 }
7805
7806
7807 /*****************************************************************************
7808 * This function indicates to ARC that a new command is pending which completes
7809 * one write operation by the driver.
7810 *
7811 * returns - E1000_SUCCESS for success.
7812 ****************************************************************************/
7813 STATIC int32_t
7814 em_mng_write_commit(struct em_hw * hw)
7815 {
7816 uint32_t hicr;
7817
7818 hicr = E1000_READ_REG(hw, HICR);
7819 /* Setting this bit tells the ARC that a new command is pending. */
7820 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7821
7822 return E1000_SUCCESS;
7823 }
7824
7825
7826 /*****************************************************************************
7827 * This function checks the mode of the firmware.
7828 *
7829 * returns - TRUE when the mode is IAMT or FALSE.
7830 ****************************************************************************/
7831 boolean_t
7832 em_check_mng_mode(struct em_hw *hw)
7833 {
7834 uint32_t fwsm;
7835
7836 fwsm = E1000_READ_REG(hw, FWSM);
7837
7838 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich8lan) {
7839 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7840 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7841 return TRUE;
7842 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7843 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7844 return TRUE;
7845
7846 return FALSE;
7847 }
7848
7849
7850 /*****************************************************************************
7851 * This function writes the dhcp info .
7852 ****************************************************************************/
7853 int32_t
7854 em_mng_write_dhcp_info(struct em_hw * hw, uint8_t *buffer,
7855 uint16_t length)
7856 {
7857 int32_t ret_val;
7858 struct em_host_mng_command_header hdr;
7859
7860 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7861 hdr.command_length = length;
7862 hdr.reserved1 = 0;
7863 hdr.reserved2 = 0;
7864 hdr.checksum = 0;
7865
7866 ret_val = em_mng_enable_host_if(hw);
7867 if (ret_val == E1000_SUCCESS) {
7868 ret_val = em_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7869 &(hdr.checksum));
7870 if (ret_val == E1000_SUCCESS) {
7871 ret_val = em_mng_write_cmd_header(hw, &hdr);
7872 if (ret_val == E1000_SUCCESS)
7873 ret_val = em_mng_write_commit(hw);
7874 }
7875 }
7876 return ret_val;
7877 }
7878
7879
7880 /*****************************************************************************
7881 * This function calculates the checksum.
7882 *
7883 * returns - checksum of buffer contents.
7884 ****************************************************************************/
7885 STATIC uint8_t
7886 em_calculate_mng_checksum(char *buffer, uint32_t length)
7887 {
7888 uint8_t sum = 0;
7889 uint32_t i;
7890
7891 if (!buffer)
7892 return 0;
7893
7894 for (i=0; i < length; i++)
7895 sum += buffer[i];
7896
7897 return (uint8_t) (0 - sum);
7898 }
7899
7900 /*****************************************************************************
7901 * This function checks whether tx pkt filtering needs to be enabled or not.
7902 *
7903 * returns - TRUE for packet filtering or FALSE.
7904 ****************************************************************************/
7905 boolean_t
7906 em_enable_tx_pkt_filtering(struct em_hw *hw)
7907 {
7908 /* called in init as well as watchdog timer functions */
7909
7910 int32_t ret_val, checksum;
7911 boolean_t tx_filter = FALSE;
7912 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7913 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7914
7915 if (em_check_mng_mode(hw)) {
7916 ret_val = em_mng_enable_host_if(hw);
7917 if (ret_val == E1000_SUCCESS) {
7918 ret_val = em_host_if_read_cookie(hw, buffer);
7919 if (ret_val == E1000_SUCCESS) {
7920 checksum = hdr->checksum;
7921 hdr->checksum = 0;
7922 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7923 checksum == em_calculate_mng_checksum((char *)buffer,
7924 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7925 if (hdr->status &
7926 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7927 tx_filter = TRUE;
7928 } else
7929 tx_filter = TRUE;
7930 } else
7931 tx_filter = TRUE;
7932 }
7933 }
7934
7935 hw->tx_pkt_filtering = tx_filter;
7936 return tx_filter;
7937 }
7938
7939 /******************************************************************************
7940 * Verifies the hardware needs to allow ARPs to be processed by the host
7941 *
7942 * hw - Struct containing variables accessed by shared code
7943 *
7944 * returns: - TRUE/FALSE
7945 *
7946 *****************************************************************************/
7947 uint32_t
7948 em_enable_mng_pass_thru(struct em_hw *hw)
7949 {
7950 uint32_t manc;
7951 uint32_t fwsm, factps;
7952
7953 if (hw->asf_firmware_present) {
7954 manc = E1000_READ_REG(hw, MANC);
7955
7956 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7957 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7958 return FALSE;
7959 if (em_arc_subsystem_valid(hw) == TRUE) {
7960 fwsm = E1000_READ_REG(hw, FWSM);
7961 factps = E1000_READ_REG(hw, FACTPS);
7962
7963 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7964 (em_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7965 (factps & E1000_FACTPS_MNGCG))
7966 return TRUE;
7967 } else
7968 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7969 return TRUE;
7970 }
7971 return FALSE;
7972 }
7973
7974 static int32_t
7975 em_polarity_reversal_workaround(struct em_hw *hw)
7976 {
7977 int32_t ret_val;
7978 uint16_t mii_status_reg;
7979 uint16_t i;
7980
7981 /* Polarity reversal workaround for forced 10F/10H links. */
7982
7983 /* Disable the transmitter on the PHY */
7984
7985 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7986 if (ret_val)
7987 return ret_val;
7988 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7989 if (ret_val)
7990 return ret_val;
7991
7992 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7993 if (ret_val)
7994 return ret_val;
7995
7996 /* This loop will early-out if the NO link condition has been met. */
7997 for (i = PHY_FORCE_TIME; i > 0; i--) {
7998 /* Read the MII Status Register and wait for Link Status bit
7999 * to be clear.
8000 */
8001
8002 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8003 if (ret_val)
8004 return ret_val;
8005
8006 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8007 if (ret_val)
8008 return ret_val;
8009
8010 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
8011 msec_delay_irq(100);
8012 }
8013
8014 /* Recommended delay time after link has been lost */
8015 msec_delay_irq(1000);
8016
8017 /* Now we will re-enable th transmitter on the PHY */
8018
8019 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8020 if (ret_val)
8021 return ret_val;
8022 msec_delay_irq(50);
8023 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8024 if (ret_val)
8025 return ret_val;
8026 msec_delay_irq(50);
8027 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8028 if (ret_val)
8029 return ret_val;
8030 msec_delay_irq(50);
8031 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8032 if (ret_val)
8033 return ret_val;
8034
8035 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8036 if (ret_val)
8037 return ret_val;
8038
8039 /* This loop will early-out if the link condition has been met. */
8040 for (i = PHY_FORCE_TIME; i > 0; i--) {
8041 /* Read the MII Status Register and wait for Link Status bit
8042 * to be set.
8043 */
8044
8045 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8046 if (ret_val)
8047 return ret_val;
8048
8049 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8050 if (ret_val)
8051 return ret_val;
8052
8053 if (mii_status_reg & MII_SR_LINK_STATUS) break;
8054 msec_delay_irq(100);
8055 }
8056 return E1000_SUCCESS;
8057 }
8058
8059 /***************************************************************************
8060 *
8061 * Disables PCI-Express master access.
8062 *
8063 * hw: Struct containing variables accessed by shared code
8064 *
8065 * returns: - none.
8066 *
8067 ***************************************************************************/
8068 STATIC void
8069 em_set_pci_express_master_disable(struct em_hw *hw)
8070 {
8071 uint32_t ctrl;
8072
8073 DEBUGFUNC("em_set_pci_express_master_disable");
8074
8075 if (hw->bus_type != em_bus_type_pci_express)
8076 return;
8077
8078 ctrl = E1000_READ_REG(hw, CTRL);
8079 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
8080 E1000_WRITE_REG(hw, CTRL, ctrl);
8081 }
8082
8083 /*******************************************************************************
8084 *
8085 * Disables PCI-Express master access and verifies there are no pending requests
8086 *
8087 * hw: Struct containing variables accessed by shared code
8088 *
8089 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
8090 * caused the master requests to be disabled.
8091 * E1000_SUCCESS master requests disabled.
8092 *
8093 ******************************************************************************/
8094 int32_t
8095 em_disable_pciex_master(struct em_hw *hw)
8096 {
8097 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
8098
8099 DEBUGFUNC("em_disable_pciex_master");
8100
8101 if (hw->bus_type != em_bus_type_pci_express)
8102 return E1000_SUCCESS;
8103
8104 em_set_pci_express_master_disable(hw);
8105
8106 while (timeout) {
8107 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
8108 break;
8109 else
8110 usec_delay(100);
8111 timeout--;
8112 }
8113
8114 if (!timeout) {
8115 DEBUGOUT("Master requests are pending.\n");
8116 return -E1000_ERR_MASTER_REQUESTS_PENDING;
8117 }
8118
8119 return E1000_SUCCESS;
8120 }
8121
8122 /*******************************************************************************
8123 *
8124 * Check for EEPROM Auto Read bit done.
8125 *
8126 * hw: Struct containing variables accessed by shared code
8127 *
8128 * returns: - E1000_ERR_RESET if fail to reset MAC
8129 * E1000_SUCCESS at any other case.
8130 *
8131 ******************************************************************************/
8132 STATIC int32_t
8133 em_get_auto_rd_done(struct em_hw *hw)
8134 {
8135 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
8136
8137 DEBUGFUNC("em_get_auto_rd_done");
8138
8139 switch (hw->mac_type) {
8140 default:
8141 msec_delay(5);
8142 break;
8143 case em_82571:
8144 case em_82572:
8145 case em_82573:
8146 case em_80003es2lan:
8147 case em_ich9lan:
8148 case em_ich8lan:
8149 while (timeout) {
8150 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8151 break;
8152 else msec_delay(1);
8153 timeout--;
8154 }
8155
8156 if (!timeout) {
8157 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8158 return -E1000_ERR_RESET;
8159 }
8160 break;
8161 }
8162
8163 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8164 * Need to wait for PHY configuration completion before accessing NVM
8165 * and PHY. */
8166 if (hw->mac_type == em_82573)
8167 msec_delay(25);
8168
8169 return E1000_SUCCESS;
8170 }
8171
8172 /***************************************************************************
8173 * Checks if the PHY configuration is done
8174 *
8175 * hw: Struct containing variables accessed by shared code
8176 *
8177 * returns: - E1000_ERR_RESET if fail to reset MAC
8178 * E1000_SUCCESS at any other case.
8179 *
8180 ***************************************************************************/
8181 STATIC int32_t
8182 em_get_phy_cfg_done(struct em_hw *hw)
8183 {
8184 int32_t timeout = PHY_CFG_TIMEOUT;
8185 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8186
8187 DEBUGFUNC("em_get_phy_cfg_done");
8188
8189 switch (hw->mac_type) {
8190 default:
8191 msec_delay_irq(10);
8192 break;
8193 case em_80003es2lan:
8194 /* Separate *_CFG_DONE_* bit for each port */
8195 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8196 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8197 /* Fall Through */
8198 case em_82571:
8199 case em_82572:
8200 while (timeout) {
8201 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8202 break;
8203 else
8204 msec_delay(1);
8205 timeout--;
8206 }
8207 if (!timeout) {
8208 DEBUGOUT("MNG configuration cycle has not completed.\n");
8209 return -E1000_ERR_RESET;
8210 }
8211 break;
8212 }
8213
8214 return E1000_SUCCESS;
8215 }
8216
8217 /***************************************************************************
8218 *
8219 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8220 * adapter or Eeprom access.
8221 *
8222 * hw: Struct containing variables accessed by shared code
8223 *
8224 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8225 * E1000_SUCCESS at any other case.
8226 *
8227 ***************************************************************************/
8228 STATIC int32_t
8229 em_get_hw_eeprom_semaphore(struct em_hw *hw)
8230 {
8231 int32_t timeout;
8232 uint32_t swsm;
8233
8234 DEBUGFUNC("em_get_hw_eeprom_semaphore");
8235
8236 if (!hw->eeprom_semaphore_present)
8237 return E1000_SUCCESS;
8238
8239 if (hw->mac_type == em_80003es2lan) {
8240 /* Get the SW semaphore. */
8241 if (em_get_software_semaphore(hw) != E1000_SUCCESS)
8242 return -E1000_ERR_EEPROM;
8243 }
8244
8245 /* Get the FW semaphore. */
8246 timeout = hw->eeprom.word_size + 1;
8247 while (timeout) {
8248 swsm = E1000_READ_REG(hw, SWSM);
8249 swsm |= E1000_SWSM_SWESMBI;
8250 E1000_WRITE_REG(hw, SWSM, swsm);
8251 /* if we managed to set the bit we got the semaphore. */
8252 swsm = E1000_READ_REG(hw, SWSM);
8253 if (swsm & E1000_SWSM_SWESMBI)
8254 break;
8255
8256 usec_delay(50);
8257 timeout--;
8258 }
8259
8260 if (!timeout) {
8261 /* Release semaphores */
8262 em_put_hw_eeprom_semaphore(hw);
8263 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8264 return -E1000_ERR_EEPROM;
8265 }
8266
8267 return E1000_SUCCESS;
8268 }
8269
8270 /***************************************************************************
8271 * This function clears HW semaphore bits.
8272 *
8273 * hw: Struct containing variables accessed by shared code
8274 *
8275 * returns: - None.
8276 *
8277 ***************************************************************************/
8278 STATIC void
8279 em_put_hw_eeprom_semaphore(struct em_hw *hw)
8280 {
8281 uint32_t swsm;
8282
8283 DEBUGFUNC("em_put_hw_eeprom_semaphore");
8284
8285 if (!hw->eeprom_semaphore_present)
8286 return;
8287
8288 swsm = E1000_READ_REG(hw, SWSM);
8289 if (hw->mac_type == em_80003es2lan) {
8290 /* Release both semaphores. */
8291 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8292 } else
8293 swsm &= ~(E1000_SWSM_SWESMBI);
8294 E1000_WRITE_REG(hw, SWSM, swsm);
8295 }
8296
8297 /***************************************************************************
8298 *
8299 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8300 *
8301 * hw: Struct containing variables accessed by shared code
8302 *
8303 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8304 * E1000_SUCCESS at any other case.
8305 *
8306 ***************************************************************************/
8307 STATIC int32_t
8308 em_get_software_semaphore(struct em_hw *hw)
8309 {
8310 int32_t timeout = hw->eeprom.word_size + 1;
8311 uint32_t swsm;
8312
8313 DEBUGFUNC("em_get_software_semaphore");
8314
8315 if (hw->mac_type != em_80003es2lan) {
8316 return E1000_SUCCESS;
8317 }
8318
8319 while (timeout) {
8320 swsm = E1000_READ_REG(hw, SWSM);
8321 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8322 if (!(swsm & E1000_SWSM_SMBI))
8323 break;
8324 msec_delay_irq(1);
8325 timeout--;
8326 }
8327
8328 if (!timeout) {
8329 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8330 return -E1000_ERR_RESET;
8331 }
8332
8333 return E1000_SUCCESS;
8334 }
8335
8336 /***************************************************************************
8337 *
8338 * Release semaphore bit (SMBI).
8339 *
8340 * hw: Struct containing variables accessed by shared code
8341 *
8342 ***************************************************************************/
8343 STATIC void
8344 em_release_software_semaphore(struct em_hw *hw)
8345 {
8346 uint32_t swsm;
8347
8348 DEBUGFUNC("em_release_software_semaphore");
8349
8350 if (hw->mac_type != em_80003es2lan) {
8351 return;
8352 }
8353
8354 swsm = E1000_READ_REG(hw, SWSM);
8355 /* Release the SW semaphores.*/
8356 swsm &= ~E1000_SWSM_SMBI;
8357 E1000_WRITE_REG(hw, SWSM, swsm);
8358 }
8359
8360 /******************************************************************************
8361 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8362 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8363 * the caller to figure out how to deal with it.
8364 *
8365 * hw - Struct containing variables accessed by shared code
8366 *
8367 * returns: - E1000_BLK_PHY_RESET
8368 * E1000_SUCCESS
8369 *
8370 *****************************************************************************/
8371 int32_t
8372 em_check_phy_reset_block(struct em_hw *hw)
8373 {
8374 uint32_t manc = 0;
8375 uint32_t fwsm = 0;
8376
8377 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
8378 fwsm = E1000_READ_REG(hw, FWSM);
8379 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8380 : E1000_BLK_PHY_RESET;
8381 }
8382
8383 if (hw->mac_type > em_82547_rev_2)
8384 manc = E1000_READ_REG(hw, MANC);
8385 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8386 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8387 }
8388
8389 STATIC uint8_t
8390 em_arc_subsystem_valid(struct em_hw *hw)
8391 {
8392 uint32_t fwsm;
8393
8394 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8395 * may not be provided a DMA clock when no manageability features are
8396 * enabled. We do not want to perform any reads/writes to these registers
8397 * if this is the case. We read FWSM to determine the manageability mode.
8398 */
8399 switch (hw->mac_type) {
8400 case em_82571:
8401 case em_82572:
8402 case em_82573:
8403 case em_80003es2lan:
8404 fwsm = E1000_READ_REG(hw, FWSM);
8405 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8406 return TRUE;
8407 break;
8408 case em_ich8lan:
8409 case em_ich9lan:
8410 return TRUE;
8411 default:
8412 break;
8413 }
8414 return FALSE;
8415 }
8416
8417
8418 /******************************************************************************
8419 * Configure PCI-Ex no-snoop
8420 *
8421 * hw - Struct containing variables accessed by shared code.
8422 * no_snoop - Bitmap of no-snoop events.
8423 *
8424 * returns: E1000_SUCCESS
8425 *
8426 *****************************************************************************/
8427 STATIC int32_t
8428 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)
8429 {
8430 uint32_t gcr_reg = 0;
8431
8432 DEBUGFUNC("em_set_pci_ex_no_snoop");
8433
8434 if (hw->bus_type == em_bus_type_unknown)
8435 em_get_bus_info(hw);
8436
8437 if (hw->bus_type != em_bus_type_pci_express)
8438 return E1000_SUCCESS;
8439
8440 if (no_snoop) {
8441 gcr_reg = E1000_READ_REG(hw, GCR);
8442 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8443 gcr_reg |= no_snoop;
8444 E1000_WRITE_REG(hw, GCR, gcr_reg);
8445 }
8446 if (hw->mac_type == em_ich8lan) {
8447 uint32_t ctrl_ext;
8448
8449 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8450
8451 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8452 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8453 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8454 }
8455
8456 return E1000_SUCCESS;
8457 }
8458
8459 /***************************************************************************
8460 *
8461 * Get software semaphore FLAG bit (SWFLAG).
8462 * SWFLAG is used to synchronize the access to all shared resource between
8463 * SW, FW and HW.
8464 *
8465 * hw: Struct containing variables accessed by shared code
8466 *
8467 ***************************************************************************/
8468 STATIC int32_t
8469 em_get_software_flag(struct em_hw *hw)
8470 {
8471 int32_t timeout = PHY_CFG_TIMEOUT;
8472 uint32_t extcnf_ctrl;
8473
8474 DEBUGFUNC("em_get_software_flag");
8475
8476 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
8477 while (timeout) {
8478 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8479 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8480 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8481
8482 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8483 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8484 break;
8485 msec_delay_irq(1);
8486 timeout--;
8487 }
8488
8489 if (!timeout) {
8490 DEBUGOUT("FW or HW locks the resource too long.\n");
8491 return -E1000_ERR_CONFIG;
8492 }
8493 }
8494
8495 return E1000_SUCCESS;
8496 }
8497
8498 /***************************************************************************
8499 *
8500 * Release software semaphore FLAG bit (SWFLAG).
8501 * SWFLAG is used to synchronize the access to all shared resource between
8502 * SW, FW and HW.
8503 *
8504 * hw: Struct containing variables accessed by shared code
8505 *
8506 ***************************************************************************/
8507 STATIC void
8508 em_release_software_flag(struct em_hw *hw)
8509 {
8510 uint32_t extcnf_ctrl;
8511
8512 DEBUGFUNC("em_release_software_flag");
8513
8514 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) {
8515 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8516 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8517 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8518 }
8519
8520 return;
8521 }
8522
8523
8524 /******************************************************************************
8525 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8526 * register.
8527 *
8528 * hw - Struct containing variables accessed by shared code
8529 * offset - offset of word in the EEPROM to read
8530 * data - word read from the EEPROM
8531 * words - number of words to read
8532 *****************************************************************************/
8533 STATIC int32_t
8534 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
8535 uint16_t *data)
8536 {
8537 int32_t error = E1000_SUCCESS;
8538 uint32_t flash_bank = 0;
8539 uint32_t act_offset = 0;
8540 uint32_t bank_offset = 0;
8541 uint16_t word = 0;
8542 uint16_t i = 0;
8543
8544 /* We need to know which is the valid flash bank. In the event
8545 * that we didn't allocate eeprom_shadow_ram, we may not be
8546 * managing flash_bank. So it cannot be trusted and needs
8547 * to be updated with each read.
8548 */
8549 /* Value of bit 22 corresponds to the flash bank we're on. */
8550 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8551
8552 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8553 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8554
8555 error = em_get_software_flag(hw);
8556 if (error != E1000_SUCCESS)
8557 return error;
8558
8559 for (i = 0; i < words; i++) {
8560 if (hw->eeprom_shadow_ram != NULL &&
8561 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8562 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8563 } else {
8564 /* The NVM part needs a byte offset, hence * 2 */
8565 act_offset = bank_offset + ((offset + i) * 2);
8566 error = em_read_ich8_word(hw, act_offset, &word);
8567 if (error != E1000_SUCCESS)
8568 break;
8569 data[i] = word;
8570 }
8571 }
8572
8573 em_release_software_flag(hw);
8574
8575 return error;
8576 }
8577
8578 /******************************************************************************
8579 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8580 * register. Actually, writes are written to the shadow ram cache in the hw
8581 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to
8582 * the NVM, which occurs when the NVM checksum is updated.
8583 *
8584 * hw - Struct containing variables accessed by shared code
8585 * offset - offset of word in the EEPROM to write
8586 * words - number of words to write
8587 * data - words to write to the EEPROM
8588 *****************************************************************************/
8589 STATIC int32_t
8590 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
8591 uint16_t *data)
8592 {
8593 uint32_t i = 0;
8594 int32_t error = E1000_SUCCESS;
8595
8596 error = em_get_software_flag(hw);
8597 if (error != E1000_SUCCESS)
8598 return error;
8599
8600 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8601 * allocated. Subsequent reads to the modified words are read from
8602 * this cached structure as well. Writes will only go into this
8603 * cached structure unless it's followed by a call to
8604 * em_update_eeprom_checksum() where it will commit the changes
8605 * and clear the "modified" field.
8606 */
8607 if (hw->eeprom_shadow_ram != NULL) {
8608 for (i = 0; i < words; i++) {
8609 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8610 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8611 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8612 } else {
8613 error = -E1000_ERR_EEPROM;
8614 break;
8615 }
8616 }
8617 } else {
8618 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8619 * as they don't perform any NVM writes. An attempt in doing so
8620 * will result in this error.
8621 */
8622 error = -E1000_ERR_EEPROM;
8623 }
8624
8625 em_release_software_flag(hw);
8626
8627 return error;
8628 }
8629
8630 /******************************************************************************
8631 * This function does initial flash setup so that a new read/write/erase cycle
8632 * can be started.
8633 *
8634 * hw - The pointer to the hw structure
8635 ****************************************************************************/
8636 STATIC int32_t
8637 em_ich8_cycle_init(struct em_hw *hw)
8638 {
8639 union ich8_hws_flash_status hsfsts;
8640 int32_t error = E1000_ERR_EEPROM;
8641 int32_t i = 0;
8642
8643 DEBUGFUNC("em_ich8_cycle_init");
8644
8645 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8646
8647 /* May be check the Flash Des Valid bit in Hw status */
8648 if (hsfsts.hsf_status.fldesvalid == 0) {
8649 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8650 return error;
8651 }
8652
8653 /* Clear FCERR in Hw status by writing 1 */
8654 /* Clear DAEL in Hw status by writing a 1 */
8655 hsfsts.hsf_status.flcerr = 1;
8656 hsfsts.hsf_status.dael = 1;
8657
8658 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8659
8660 /* Either we should have a hardware SPI cycle in progress bit to check
8661 * against, in order to start a new cycle or FDONE bit should be changed
8662 * in the hardware so that it is 1 after harware reset, which can then be
8663 * used as an indication whether a cycle is in progress or has been
8664 * completed .. we should also have some software semaphore mechanism to
8665 * guard FDONE or the cycle in progress bit so that two threads access to
8666 * those bits can be sequentiallized or a way so that 2 threads dont
8667 * start the cycle at the same time */
8668
8669 if (hsfsts.hsf_status.flcinprog == 0) {
8670 /* There is no cycle running at present, so we can start a cycle */
8671 /* Begin by setting Flash Cycle Done. */
8672 hsfsts.hsf_status.flcdone = 1;
8673 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8674 error = E1000_SUCCESS;
8675 } else {
8676 /* otherwise poll for sometime so the current cycle has a chance
8677 * to end before giving up. */
8678 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8679 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8680 if (hsfsts.hsf_status.flcinprog == 0) {
8681 error = E1000_SUCCESS;
8682 break;
8683 }
8684 usec_delay(1);
8685 }
8686 if (error == E1000_SUCCESS) {
8687 /* Successful in waiting for previous cycle to timeout,
8688 * now set the Flash Cycle Done. */
8689 hsfsts.hsf_status.flcdone = 1;
8690 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8691 } else {
8692 DEBUGOUT("Flash controller busy, cannot get access");
8693 }
8694 }
8695 return error;
8696 }
8697
8698 /******************************************************************************
8699 * This function starts a flash cycle and waits for its completion
8700 *
8701 * hw - The pointer to the hw structure
8702 ****************************************************************************/
8703 STATIC int32_t
8704 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)
8705 {
8706 union ich8_hws_flash_ctrl hsflctl;
8707 union ich8_hws_flash_status hsfsts;
8708 int32_t error = E1000_ERR_EEPROM;
8709 uint32_t i = 0;
8710
8711 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8712 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8713 hsflctl.hsf_ctrl.flcgo = 1;
8714 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8715
8716 /* wait till FDONE bit is set to 1 */
8717 do {
8718 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8719 if (hsfsts.hsf_status.flcdone == 1)
8720 break;
8721 usec_delay(1);
8722 i++;
8723 } while (i < timeout);
8724 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8725 error = E1000_SUCCESS;
8726 }
8727 return error;
8728 }
8729
8730 /******************************************************************************
8731 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8732 *
8733 * hw - The pointer to the hw structure
8734 * index - The index of the byte or word to read.
8735 * size - Size of data to read, 1=byte 2=word
8736 * data - Pointer to the word to store the value read.
8737 *****************************************************************************/
8738 STATIC int32_t
8739 em_read_ich8_data(struct em_hw *hw, uint32_t index,
8740 uint32_t size, uint16_t* data)
8741 {
8742 union ich8_hws_flash_status hsfsts;
8743 union ich8_hws_flash_ctrl hsflctl;
8744 uint32_t flash_linear_address;
8745 uint32_t flash_data = 0;
8746 int32_t error = -E1000_ERR_EEPROM;
8747 int32_t count = 0;
8748
8749 DEBUGFUNC("em_read_ich8_data");
8750
8751 if (size < 1 || size > 2 || data == 0x0 ||
8752 index > ICH_FLASH_LINEAR_ADDR_MASK)
8753 return error;
8754
8755 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8756 hw->flash_base_addr;
8757
8758 do {
8759 usec_delay(1);
8760 /* Steps */
8761 error = em_ich8_cycle_init(hw);
8762 if (error != E1000_SUCCESS)
8763 break;
8764
8765 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8766 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8767 hsflctl.hsf_ctrl.fldbcount = size - 1;
8768 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8769 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8770
8771 /* Write the last 24 bits of index into Flash Linear address field in
8772 * Flash Address */
8773 /* TODO: TBD maybe check the index against the size of flash */
8774
8775 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8776
8777 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8778
8779 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8780 * sequence a few more times, else read in (shift in) the Flash Data0,
8781 * the order is least significant byte first msb to lsb */
8782 if (error == E1000_SUCCESS) {
8783 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8784 if (size == 1) {
8785 *data = (uint8_t)(flash_data & 0x000000FF);
8786 } else if (size == 2) {
8787 *data = (uint16_t)(flash_data & 0x0000FFFF);
8788 }
8789 break;
8790 } else {
8791 /* If we've gotten here, then things are probably completely hosed,
8792 * but if the error condition is detected, it won't hurt to give
8793 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8794 */
8795 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8796 if (hsfsts.hsf_status.flcerr == 1) {
8797 /* Repeat for some time before giving up. */
8798 continue;
8799 } else if (hsfsts.hsf_status.flcdone == 0) {
8800 DEBUGOUT("Timeout error - flash cycle did not complete.");
8801 break;
8802 }
8803 }
8804 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8805
8806 return error;
8807 }
8808
8809 /******************************************************************************
8810 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8811 *
8812 * hw - The pointer to the hw structure
8813 * index - The index of the byte/word to read.
8814 * size - Size of data to read, 1=byte 2=word
8815 * data - The byte(s) to write to the NVM.
8816 *****************************************************************************/
8817 STATIC int32_t
8818 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
8819 uint16_t data)
8820 {
8821 union ich8_hws_flash_status hsfsts;
8822 union ich8_hws_flash_ctrl hsflctl;
8823 uint32_t flash_linear_address;
8824 uint32_t flash_data = 0;
8825 int32_t error = -E1000_ERR_EEPROM;
8826 int32_t count = 0;
8827
8828 DEBUGFUNC("em_write_ich8_data");
8829
8830 if (size < 1 || size > 2 || data > size * 0xff ||
8831 index > ICH_FLASH_LINEAR_ADDR_MASK)
8832 return error;
8833
8834 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8835 hw->flash_base_addr;
8836
8837 do {
8838 usec_delay(1);
8839 /* Steps */
8840 error = em_ich8_cycle_init(hw);
8841 if (error != E1000_SUCCESS)
8842 break;
8843
8844 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8845 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8846 hsflctl.hsf_ctrl.fldbcount = size -1;
8847 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8848 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8849
8850 /* Write the last 24 bits of index into Flash Linear address field in
8851 * Flash Address */
8852 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8853
8854 if (size == 1)
8855 flash_data = (uint32_t)data & 0x00FF;
8856 else
8857 flash_data = (uint32_t)data;
8858
8859 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8860
8861 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8862 * sequence a few more times else done */
8863 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8864 if (error == E1000_SUCCESS) {
8865 break;
8866 } else {
8867 /* If we're here, then things are most likely completely hosed,
8868 * but if the error condition is detected, it won't hurt to give
8869 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8870 */
8871 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8872 if (hsfsts.hsf_status.flcerr == 1) {
8873 /* Repeat for some time before giving up. */
8874 continue;
8875 } else if (hsfsts.hsf_status.flcdone == 0) {
8876 DEBUGOUT("Timeout error - flash cycle did not complete.");
8877 break;
8878 }
8879 }
8880 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8881
8882 return error;
8883 }
8884
8885 /******************************************************************************
8886 * Reads a single byte from the NVM using the ICH8 flash access registers.
8887 *
8888 * hw - pointer to em_hw structure
8889 * index - The index of the byte to read.
8890 * data - Pointer to a byte to store the value read.
8891 *****************************************************************************/
8892 STATIC int32_t
8893 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t* data)
8894 {
8895 int32_t status = E1000_SUCCESS;
8896 uint16_t word = 0;
8897
8898 status = em_read_ich8_data(hw, index, 1, &word);
8899 if (status == E1000_SUCCESS) {
8900 *data = (uint8_t)word;
8901 }
8902
8903 return status;
8904 }
8905
8906 /******************************************************************************
8907 * Writes a single byte to the NVM using the ICH8 flash access registers.
8908 * Performs verification by reading back the value and then going through
8909 * a retry algorithm before giving up.
8910 *
8911 * hw - pointer to em_hw structure
8912 * index - The index of the byte to write.
8913 * byte - The byte to write to the NVM.
8914 *****************************************************************************/
8915 STATIC int32_t
8916 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)
8917 {
8918 int32_t error = E1000_SUCCESS;
8919 int32_t program_retries = 0;
8920
8921 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8922
8923 error = em_write_ich8_byte(hw, index, byte);
8924
8925 if (error != E1000_SUCCESS) {
8926 for (program_retries = 0; program_retries < 100; program_retries++) {
8927 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8928 error = em_write_ich8_byte(hw, index, byte);
8929 usec_delay(100);
8930 if (error == E1000_SUCCESS)
8931 break;
8932 }
8933 }
8934
8935 if (program_retries == 100)
8936 error = E1000_ERR_EEPROM;
8937
8938 return error;
8939 }
8940
8941 /******************************************************************************
8942 * Writes a single byte to the NVM using the ICH8 flash access registers.
8943 *
8944 * hw - pointer to em_hw structure
8945 * index - The index of the byte to read.
8946 * data - The byte to write to the NVM.
8947 *****************************************************************************/
8948 STATIC int32_t
8949 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)
8950 {
8951 int32_t status = E1000_SUCCESS;
8952 uint16_t word = (uint16_t)data;
8953
8954 status = em_write_ich8_data(hw, index, 1, word);
8955
8956 return status;
8957 }
8958
8959 /******************************************************************************
8960 * Reads a word from the NVM using the ICH8 flash access registers.
8961 *
8962 * hw - pointer to em_hw structure
8963 * index - The starting byte index of the word to read.
8964 * data - Pointer to a word to store the value read.
8965 *****************************************************************************/
8966 STATIC int32_t
8967 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)
8968 {
8969 int32_t status = E1000_SUCCESS;
8970 status = em_read_ich8_data(hw, index, 2, data);
8971 return status;
8972 }
8973
8974
8975 /******************************************************************************
8976 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8977 * based.
8978 *
8979 * hw - pointer to em_hw structure
8980 * bank - 0 for first bank, 1 for second bank
8981 *
8982 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8983 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8984 * bank size may be 4, 8 or 64 KBytes
8985 *****************************************************************************/
8986 int32_t
8987 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)
8988 {
8989 union ich8_hws_flash_status hsfsts;
8990 union ich8_hws_flash_ctrl hsflctl;
8991 uint32_t flash_linear_address;
8992 int32_t count = 0;
8993 int32_t error = E1000_ERR_EEPROM;
8994 int32_t iteration;
8995 int32_t sub_sector_size = 0;
8996 int32_t bank_size;
8997 int32_t j = 0;
8998 int32_t error_flag = 0;
8999
9000 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
9001
9002 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
9003 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
9004 * consecutive sectors. The start index for the nth Hw sector can be
9005 * calculated as bank * 4096 + n * 256
9006 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
9007 * The start index for the nth Hw sector can be calculated
9008 * as bank * 4096
9009 * 10: The HW sector is 8K bytes
9010 * 11: The Hw sector size is 64K bytes */
9011 if (hsfsts.hsf_status.berasesz == 0x0) {
9012 /* Hw sector size 256 */
9013 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
9014 bank_size = ICH_FLASH_SECTOR_SIZE;
9015 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
9016 } else if (hsfsts.hsf_status.berasesz == 0x1) {
9017 bank_size = ICH_FLASH_SEG_SIZE_4K;
9018 iteration = 1;
9019 } else if (hsfsts.hsf_status.berasesz == 0x2) {
9020 if (hw->mac_type == em_ich9lan) {
9021 sub_sector_size = ICH_FLASH_SEG_SIZE_8K;
9022 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K;
9023 }
9024 } else if (hsfsts.hsf_status.berasesz == 0x3) {
9025 bank_size = ICH_FLASH_SEG_SIZE_64K;
9026 iteration = 1;
9027 } else {
9028 return error;
9029 }
9030
9031 for (j = 0; j < iteration ; j++) {
9032 do {
9033 count++;
9034 /* Steps */
9035 error = em_ich8_cycle_init(hw);
9036 if (error != E1000_SUCCESS) {
9037 error_flag = 1;
9038 break;
9039 }
9040
9041 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
9042 * Control */
9043 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
9044 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
9045 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
9046
9047 /* Write the last 24 bits of an index within the block into Flash
9048 * Linear address field in Flash Address. This probably needs to
9049 * be calculated here based off the on-chip erase sector size and
9050 * the software bank size (4, 8 or 64 KBytes) */
9051 flash_linear_address = bank * bank_size + j * sub_sector_size;
9052 flash_linear_address += hw->flash_base_addr;
9053 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
9054
9055 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
9056
9057 error = em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
9058 /* Check if FCERR is set to 1. If 1, clear it and try the whole
9059 * sequence a few more times else Done */
9060 if (error == E1000_SUCCESS) {
9061 break;
9062 } else {
9063 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
9064 if (hsfsts.hsf_status.flcerr == 1) {
9065 /* repeat for some time before giving up */
9066 continue;
9067 } else if (hsfsts.hsf_status.flcdone == 0) {
9068 error_flag = 1;
9069 break;
9070 }
9071 }
9072 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
9073 if (error_flag == 1)
9074 break;
9075 }
9076 if (error_flag != 1)
9077 error = E1000_SUCCESS;
9078 return error;
9079 }
9080
9081
9082 STATIC int32_t
9083 em_init_lcd_from_nvm_config_region(struct em_hw *hw,
9084 uint32_t cnf_base_addr, uint32_t cnf_size)
9085 {
9086 uint32_t ret_val = E1000_SUCCESS;
9087 uint16_t word_addr, reg_data, reg_addr;
9088 uint16_t i;
9089
9090 /* cnf_base_addr is in DWORD */
9091 word_addr = (uint16_t)(cnf_base_addr << 1);
9092
9093 /* cnf_size is returned in size of dwords */
9094 for (i = 0; i < cnf_size; i++) {
9095 ret_val = em_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9096 if (ret_val)
9097 return ret_val;
9098
9099 ret_val = em_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9100 if (ret_val)
9101 return ret_val;
9102
9103 ret_val = em_get_software_flag(hw);
9104 if (ret_val != E1000_SUCCESS)
9105 return ret_val;
9106
9107 ret_val = em_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9108
9109 em_release_software_flag(hw);
9110 }
9111
9112 return ret_val;
9113 }
9114
9115
9116 /******************************************************************************
9117 * This function initializes the PHY from the NVM on ICH8 platforms. This
9118 * is needed due to an issue where the NVM configuration is not properly
9119 * autoloaded after power transitions. Therefore, after each PHY reset, we
9120 * will load the configuration data out of the NVM manually.
9121 *
9122 * hw: Struct containing variables accessed by shared code
9123 *****************************************************************************/
9124 STATIC int32_t
9125 em_init_lcd_from_nvm(struct em_hw *hw)
9126 {
9127 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9128
9129 if (hw->phy_type != em_phy_igp_3)
9130 return E1000_SUCCESS;
9131
9132 /* Check if SW needs configure the PHY */
9133 reg_data = E1000_READ_REG(hw, FEXTNVM);
9134 if (!(reg_data & FEXTNVM_SW_CONFIG))
9135 return E1000_SUCCESS;
9136
9137 /* Wait for basic configuration completes before proceeding*/
9138 loop = 0;
9139 do {
9140 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9141 usec_delay(100);
9142 loop++;
9143 } while ((!reg_data) && (loop < 50));
9144
9145 /* Clear the Init Done bit for the next init event */
9146 reg_data = E1000_READ_REG(hw, STATUS);
9147 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9148 E1000_WRITE_REG(hw, STATUS, reg_data);
9149
9150 /* Make sure HW does not configure LCD from PHY extended configuration
9151 before SW configuration */
9152 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9153 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9154 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9155 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9156 cnf_size >>= 16;
9157 if (cnf_size) {
9158 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9159 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9160 /* cnf_base_addr is in DWORD */
9161 cnf_base_addr >>= 16;
9162
9163 /* Configure LCD from extended configuration region. */
9164 ret_val = em_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9165 cnf_size);
9166 if (ret_val)
9167 return ret_val;
9168 }
9169 }
9170
9171 return E1000_SUCCESS;
9172 }
9173
DragonFly BSD