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Add ID for ICH8M in compatibility mode. This makes Thinkpad X61s report
[dragonfly.git] / sys / dev / disk / nata / ata-chipset.c
blob0f9556ce20717c2f4e68fd0a4e2ce595c4055d38
1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.11 2007/12/17 09:24:40 hasso Exp $
28 */
29
30 #include "opt_ata.h"
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/bus_dma.h>
35 #include <sys/bus_resource.h>
36 #include <sys/callout.h>
37 #include <sys/endian.h>
38 #include <sys/libkern.h>
39 #include <sys/lock.h> /* for {get,rel}_mplock() */
40 #include <sys/malloc.h>
41 #include <sys/nata.h>
42 #include <sys/queue.h>
43 #include <sys/rman.h>
44 #include <sys/spinlock.h>
45 #include <sys/spinlock2.h>
46 #include <sys/systm.h>
47 #include <sys/taskqueue.h>
48
49 #include <machine/bus_dma.h>
50
51 #include <bus/pci/pcireg.h>
52 #include <bus/pci/pcivar.h>
53
54 #include "ata-all.h"
55 #include "ata-pci.h"
56 #include "ata_if.h"
57
58 /* local prototypes */
59 /* ata-chipset.c */
60 static int ata_generic_chipinit(device_t dev);
61 static void ata_generic_intr(void *data);
62 static void ata_generic_setmode(device_t dev, int mode);
63 static void ata_sata_phy_check_events(device_t dev);
64 static void ata_sata_phy_event(void *context, int dummy);
65 static int ata_sata_phy_reset(device_t dev);
66 static int ata_sata_connect(struct ata_channel *ch);
67 static void ata_sata_setmode(device_t dev, int mode);
68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
69 static int ata_ahci_chipinit(device_t dev);
70 static int ata_ahci_allocate(device_t dev);
71 static int ata_ahci_status(device_t dev);
72 static int ata_ahci_begin_transaction(struct ata_request *request);
73 static int ata_ahci_end_transaction(struct ata_request *request);
74 static void ata_ahci_reset(device_t dev);
75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
76 static void ata_ahci_dmainit(device_t dev);
77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
78 static int ata_genahci_chipinit(device_t dev);
79 static int ata_acard_chipinit(device_t dev);
80 static int ata_acard_allocate(device_t dev);
81 static int ata_acard_status(device_t dev);
82 static void ata_acard_850_setmode(device_t dev, int mode);
83 static void ata_acard_86X_setmode(device_t dev, int mode);
84 static int ata_ali_chipinit(device_t dev);
85 static int ata_ali_allocate(device_t dev);
86 static int ata_ali_sata_allocate(device_t dev);
87 static void ata_ali_reset(device_t dev);
88 static void ata_ali_setmode(device_t dev, int mode);
89 static int ata_amd_chipinit(device_t dev);
90 static int ata_ati_chipinit(device_t dev);
91 static void ata_ati_setmode(device_t dev, int mode);
92 static int ata_cyrix_chipinit(device_t dev);
93 static void ata_cyrix_setmode(device_t dev, int mode);
94 static int ata_cypress_chipinit(device_t dev);
95 static void ata_cypress_setmode(device_t dev, int mode);
96 static int ata_highpoint_chipinit(device_t dev);
97 static int ata_highpoint_allocate(device_t dev);
98 static void ata_highpoint_setmode(device_t dev, int mode);
99 static int ata_highpoint_check_80pin(device_t dev, int mode);
100 static int ata_intel_chipinit(device_t dev);
101 static int ata_intel_allocate(device_t dev);
102 static void ata_intel_reset(device_t dev);
103 static void ata_intel_old_setmode(device_t dev, int mode);
104 static void ata_intel_new_setmode(device_t dev, int mode);
105 static int ata_intel_31244_allocate(device_t dev);
106 static int ata_intel_31244_status(device_t dev);
107 static int ata_intel_31244_command(struct ata_request *request);
108 static void ata_intel_31244_reset(device_t dev);
109 static int ata_ite_chipinit(device_t dev);
110 static void ata_ite_setmode(device_t dev, int mode);
111 static int ata_jmicron_chipinit(device_t dev);
112 static int ata_jmicron_allocate(device_t dev);
113 static void ata_jmicron_reset(device_t dev);
114 static void ata_jmicron_dmainit(device_t dev);
115 static void ata_jmicron_setmode(device_t dev, int mode);
116 static int ata_marvell_pata_chipinit(device_t dev);
117 static int ata_marvell_pata_allocate(device_t dev);
118 static void ata_marvell_pata_setmode(device_t dev, int mode);
119 static int ata_marvell_edma_chipinit(device_t dev);
120 static int ata_marvell_edma_allocate(device_t dev);
121 static int ata_marvell_edma_status(device_t dev);
122 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
123 static int ata_marvell_edma_end_transaction(struct ata_request *request);
124 static void ata_marvell_edma_reset(device_t dev);
125 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
126 static void ata_marvell_edma_dmainit(device_t dev);
127 static int ata_national_chipinit(device_t dev);
128 static void ata_national_setmode(device_t dev, int mode);
129 static int ata_netcell_chipinit(device_t dev);
130 static int ata_netcell_allocate(device_t dev);
131 static int ata_nvidia_chipinit(device_t dev);
132 static int ata_nvidia_allocate(device_t dev);
133 static int ata_nvidia_status(device_t dev);
134 static void ata_nvidia_reset(device_t dev);
135 static int ata_promise_chipinit(device_t dev);
136 static int ata_promise_allocate(device_t dev);
137 static int ata_promise_status(device_t dev);
138 static int ata_promise_dmastart(device_t dev);
139 static int ata_promise_dmastop(device_t dev);
140 static void ata_promise_dmareset(device_t dev);
141 static void ata_promise_dmainit(device_t dev);
142 static void ata_promise_setmode(device_t dev, int mode);
143 static int ata_promise_tx2_allocate(device_t dev);
144 static int ata_promise_tx2_status(device_t dev);
145 static int ata_promise_mio_allocate(device_t dev);
146 static void ata_promise_mio_intr(void *data);
147 static int ata_promise_mio_status(device_t dev);
148 static int ata_promise_mio_command(struct ata_request *request);
149 static void ata_promise_mio_reset(device_t dev);
150 static void ata_promise_mio_dmainit(device_t dev);
151 static void ata_promise_mio_setmode(device_t dev, int mode);
152 static void ata_promise_sx4_intr(void *data);
153 static int ata_promise_sx4_command(struct ata_request *request);
154 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
155 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
156 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
157 static int ata_serverworks_chipinit(device_t dev);
158 static int ata_serverworks_allocate(device_t dev);
159 static void ata_serverworks_setmode(device_t dev, int mode);
160 static int ata_sii_chipinit(device_t dev);
161 static int ata_cmd_allocate(device_t dev);
162 static int ata_cmd_status(device_t dev);
163 static void ata_cmd_setmode(device_t dev, int mode);
164 static int ata_sii_allocate(device_t dev);
165 static int ata_sii_status(device_t dev);
166 static void ata_sii_reset(device_t dev);
167 static void ata_sii_setmode(device_t dev, int mode);
168 static int ata_siiprb_allocate(device_t dev);
169 static int ata_siiprb_status(device_t dev);
170 static int ata_siiprb_begin_transaction(struct ata_request *request);
171 static int ata_siiprb_end_transaction(struct ata_request *request);
172 static void ata_siiprb_reset(device_t dev);
173 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
174 static void ata_siiprb_dmainit(device_t dev);
175 static int ata_sis_chipinit(device_t dev);
176 static int ata_sis_allocate(device_t dev);
177 static void ata_sis_reset(device_t dev);
178 static void ata_sis_setmode(device_t dev, int mode);
179 static int ata_via_chipinit(device_t dev);
180 static int ata_via_allocate(device_t dev);
181 static void ata_via_reset(device_t dev);
182 static void ata_via_setmode(device_t dev, int mode);
183 static void ata_via_southbridge_fixup(device_t dev);
184 static void ata_via_family_setmode(device_t dev, int mode);
185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
187 static int ata_setup_interrupt(device_t dev);
188 static int ata_serialize(device_t dev, int flags);
189 static void ata_print_cable(device_t dev, u_int8_t *who);
190 static int ata_atapi(device_t dev);
191 static int ata_check_80pin(device_t dev, int mode);
192 static int ata_mode2idx(int mode);
193
194
195 /*
196 * generic ATA support functions
197 */
198 int
199 ata_generic_ident(device_t dev)
200 {
201 struct ata_pci_controller *ctlr = device_get_softc(dev);
202
203 device_set_desc(dev, "GENERIC ATA controller");
204 ctlr->chipinit = ata_generic_chipinit;
205 return 0;
206 }
207
208 static int
209 ata_generic_chipinit(device_t dev)
210 {
211 struct ata_pci_controller *ctlr = device_get_softc(dev);
212
213 if (ata_setup_interrupt(dev))
214 return ENXIO;
215 ctlr->setmode = ata_generic_setmode;
216 return 0;
217 }
218
219 static void
220 ata_generic_intr(void *data)
221 {
222 struct ata_pci_controller *ctlr = data;
223 struct ata_channel *ch;
224 int unit;
225
226 for (unit = 0; unit < ctlr->channels; unit++) {
227 if ((ch = ctlr->interrupt[unit].argument))
228 ctlr->interrupt[unit].function(ch);
229 }
230 }
231
232 static void
233 ata_generic_setmode(device_t dev, int mode)
234 {
235 struct ata_device *atadev = device_get_softc(dev);
236
237 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
238 mode = ata_check_80pin(dev, mode);
239 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
240 atadev->mode = mode;
241 }
242
243
244 /*
245 * SATA support functions
246 */
247 static void
248 ata_sata_phy_check_events(device_t dev)
249 {
250 struct ata_channel *ch = device_get_softc(dev);
251 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
252
253 /* clear error bits/interrupt */
254 ATA_IDX_OUTL(ch, ATA_SERROR, error);
255
256 /* do we have any events flagged ? */
257 if (error) {
258 struct ata_connect_task *tp;
259 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
260
261 /* if we have a connection event deal with it */
262 if ((error & ATA_SE_PHY_CHANGED) &&
263 (tp = (struct ata_connect_task *)
264 kmalloc(sizeof(struct ata_connect_task),
265 M_ATA, M_INTWAIT | M_ZERO))) {
266
267 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
268 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
269 if (bootverbose)
270 device_printf(ch->dev, "CONNECT requested\n");
271 tp->action = ATA_C_ATTACH;
272 }
273 else {
274 if (bootverbose)
275 device_printf(ch->dev, "DISCONNECT requested\n");
276 tp->action = ATA_C_DETACH;
277 }
278 tp->dev = ch->dev;
279 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
280 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
281 }
282 }
283 }
284
285 static void
286 ata_sata_phy_event(void *context, int dummy)
287 {
288 struct ata_connect_task *tp = (struct ata_connect_task *)context;
289 struct ata_channel *ch = device_get_softc(tp->dev);
290 device_t *children;
291 int nchildren, i;
292
293 get_mplock();
294 if (tp->action == ATA_C_ATTACH) {
295 if (bootverbose)
296 device_printf(tp->dev, "CONNECTED\n");
297 ATA_RESET(tp->dev);
298 ata_identify(tp->dev);
299 }
300 if (tp->action == ATA_C_DETACH) {
301 if (!device_get_children(tp->dev, &children, &nchildren)) {
302 for (i = 0; i < nchildren; i++)
303 if (children[i])
304 device_delete_child(tp->dev, children[i]);
305 kfree(children, M_TEMP);
306 }
307 spin_lock_wr(&ch->state_mtx);
308 ch->state = ATA_IDLE;
309 spin_unlock_wr(&ch->state_mtx);
310 if (bootverbose)
311 device_printf(tp->dev, "DISCONNECTED\n");
312 }
313 rel_mplock();
314 kfree(tp, M_ATA);
315 }
316
317 static int
318 ata_sata_phy_reset(device_t dev)
319 {
320 struct ata_channel *ch = device_get_softc(dev);
321 int loop, retry;
322
323 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
324 return ata_sata_connect(ch);
325
326 for (retry = 0; retry < 10; retry++) {
327 for (loop = 0; loop < 10; loop++) {
328 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
329 ata_udelay(100);
330 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
331 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
332 break;
333 }
334 ata_udelay(5000);
335 for (loop = 0; loop < 10; loop++) {
336 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
337 ATA_SC_IPM_DIS_PARTIAL |
338 ATA_SC_IPM_DIS_SLUMBER);
339 ata_udelay(100);
340 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
341 return ata_sata_connect(ch);
342 }
343 }
344 return 0;
345 }
346
347 static int
348 ata_sata_connect(struct ata_channel *ch)
349 {
350 u_int32_t status;
351 int timeout;
352
353 /* wait up to 1 second for "connect well" */
354 for (timeout = 0; timeout < 100 ; timeout++) {
355 status = ATA_IDX_INL(ch, ATA_SSTATUS);
356 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
357 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
358 break;
359 ata_udelay(10000);
360 }
361 if (timeout >= 100) {
362 if (bootverbose)
363 device_printf(ch->dev, "SATA connect status=%08x\n", status);
364 return 0;
365 }
366
367 if (bootverbose)
368 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
369
370 /* clear SATA error register */
371 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
372
373 return 1;
374 }
375
376 static void
377 ata_sata_setmode(device_t dev, int mode)
378 {
379 struct ata_device *atadev = device_get_softc(dev);
380
381 /*
382 * if we detect that the device isn't a real SATA device we limit
383 * the transfer mode to UDMA5/ATA100.
384 * this works around the problems some devices has with the
385 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
386 */
387 if (atadev->param.satacapabilities != 0x0000 &&
388 atadev->param.satacapabilities != 0xffff) {
389 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
390
391 /* on some drives we need to set the transfer mode */
392 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
393 ata_limit_mode(dev, mode, ATA_UDMA6));
394
395 /* query SATA STATUS for the speed */
396 if (ch->r_io[ATA_SSTATUS].res &&
397 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
398 ATA_SS_CONWELL_GEN2))
399 atadev->mode = ATA_SA300;
400 else
401 atadev->mode = ATA_SA150;
402 }
403 else {
404 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
405 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
406 atadev->mode = mode;
407 }
408 }
409
410 static int
411 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
412 {
413 struct ata_device *atadev = device_get_softc(request->dev);
414
415 if (request->flags & ATA_R_ATAPI) {
416 fis[0] = 0x27; /* host to device */
417 fis[1] = 0x80; /* command FIS (note PM goes here) */
418 fis[2] = ATA_PACKET_CMD;
419 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
420 fis[3] = ATA_F_DMA;
421 else {
422 fis[5] = request->transfersize;
423 fis[6] = request->transfersize >> 8;
424 }
425 fis[7] = ATA_D_LBA | atadev->unit;
426 fis[15] = ATA_A_4BIT;
427 return 20;
428 }
429 else {
430 ata_modify_if_48bit(request);
431 fis[0] = 0x27; /* host to device */
432 fis[1] = 0x80; /* command FIS (note PM goes here) */
433 fis[2] = request->u.ata.command;
434 fis[3] = request->u.ata.feature;
435 fis[4] = request->u.ata.lba;
436 fis[5] = request->u.ata.lba >> 8;
437 fis[6] = request->u.ata.lba >> 16;
438 fis[7] = ATA_D_LBA | atadev->unit;
439 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
440 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
441 fis[8] = request->u.ata.lba >> 24;
442 fis[9] = request->u.ata.lba >> 32;
443 fis[10] = request->u.ata.lba >> 40;
444 fis[11] = request->u.ata.feature >> 8;
445 fis[12] = request->u.ata.count;
446 fis[13] = request->u.ata.count >> 8;
447 fis[15] = ATA_A_4BIT;
448 return 20;
449 }
450 return 0;
451 }
452
453 /*
454 * AHCI v1.x compliant SATA chipset support functions
455 */
456 static int
457 ata_ahci_chipinit(device_t dev)
458 {
459 struct ata_pci_controller *ctlr = device_get_softc(dev);
460 u_int32_t version;
461 int unit;
462
463 /* reset AHCI controller */
464 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
465 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
466 DELAY(1000000);
467 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
468 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
469 device_printf(dev, "AHCI controller reset failure\n");
470 return ENXIO;
471 }
472
473 /* enable AHCI mode */
474 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
475 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE);
476
477 /* get the number of HW channels */
478 ctlr->channels =
479 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
480 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
481
482 /* disable interrupt sources and clear interrupts */
483 for (unit = 0; unit < ctlr->channels; unit++) {
484 int offset = unit << 7;
485 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
486 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1);
487 }
488 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
489
490 /* enable AHCI interrupts */
491 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
492 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
493
494 ctlr->reset = ata_ahci_reset;
495 ctlr->dmainit = ata_ahci_dmainit;
496 ctlr->allocate = ata_ahci_allocate;
497 ctlr->setmode = ata_sata_setmode;
498
499 /* enable PCI interrupt */
500 pci_write_config(dev, PCIR_COMMAND,
501 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
502
503 /* announce we support the HW */
504 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
505 device_printf(dev,
506 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
507 (version >> 24) & 0xff, (version >> 16) & 0xff,
508 (version >> 8) & 0xff, version & 0xff,
509 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
510 return 0;
511 }
512
513 static int
514 ata_ahci_allocate(device_t dev)
515 {
516 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
517 struct ata_channel *ch = device_get_softc(dev);
518 u_int64_t work;
519 int offset = ch->unit << 7;
520
521 /* set the SATA resources */
522 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
523 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
524 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
525 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
526 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
527 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
528 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
529 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
530
531 ch->hw.status = ata_ahci_status;
532 ch->hw.begin_transaction = ata_ahci_begin_transaction;
533 ch->hw.end_transaction = ata_ahci_end_transaction;
534 ch->hw.command = NULL; /* not used here */
535
536 /* setup work areas */
537 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
538 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
539 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
540
541 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
542 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
543 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
544
545 /* enable wanted port interrupts */
546 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
547 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
548 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
549 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
550 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
551 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
552
553 /* start operations on this channel */
554 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
555 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
556 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
557 return 0;
558 }
559
560 static int
561 ata_ahci_status(device_t dev)
562 {
563 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
564 struct ata_channel *ch = device_get_softc(dev);
565 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
566 int offset = ch->unit << 7;
567 int tag = 0;
568
569 if (action & (1 << ch->unit)) {
570 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
571 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
572
573 /* clear interrupt(s) */
574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
575 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
576
577 /* do we have any PHY events ? */
578 /* XXX SOS check istatus phy bits */
579 ata_sata_phy_check_events(dev);
580
581 /* do we have a potentially hanging engine to take care of? */
582 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
583
584 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
585 int timeout = 0;
586
587 /* kill off all activity on this channel */
588 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
589 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
590
591 /* XXX SOS this is not entirely wrong */
592 do {
593 DELAY(1000);
594 if (timeout++ > 500) {
595 device_printf(dev, "stopping AHCI engine failed\n");
596 break;
597 }
598 } while (ATA_INL(ctlr->r_res2,
599 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
600
601 /* start operations on this channel */
602 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
603 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
604
605 return 1;
606 }
607 else
608 return (!(cstatus & (1 << tag)));
609 }
610 return 0;
611 }
612
613 /* must be called with ATA channel locked and state_mtx held */
614 static int
615 ata_ahci_begin_transaction(struct ata_request *request)
616 {
617 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
618 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
619 struct ata_ahci_cmd_tab *ctp;
620 struct ata_ahci_cmd_list *clp;
621 int offset = ch->unit << 7;
622 int tag = 0, entries = 0;
623 int fis_size;
624
625 /* get a piece of the workspace for this request */
626 ctp = (struct ata_ahci_cmd_tab *)
627 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
628
629 /* setup the FIS for this request */
630 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
631 device_printf(request->dev, "setting up SATA FIS failed\n");
632 request->result = EIO;
633 return ATA_OP_FINISHED;
634 }
635
636 /* if request moves data setup and load SG list */
637 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
638 if (ch->dma->load(ch->dev, request->data, request->bytecount,
639 request->flags & ATA_R_READ,
640 ctp->prd_tab, &entries)) {
641 device_printf(request->dev, "setting up DMA failed\n");
642 request->result = EIO;
643 return ATA_OP_FINISHED;
644 }
645 }
646
647 /* setup the command list entry */
648 clp = (struct ata_ahci_cmd_list *)
649 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
650
651 clp->prd_length = entries;
652 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
653 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
654 (fis_size / sizeof(u_int32_t));
655 clp->bytecount = 0;
656 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
657 (ATA_AHCI_CT_SIZE * tag));
658
659 /* clear eventual ACTIVE bit */
660 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
661
662 /* set command type bit */
663 if (request->flags & ATA_R_ATAPI)
664 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
665 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
666 ATA_AHCI_P_CMD_ATAPI);
667 else
668 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
669 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
670 ~ATA_AHCI_P_CMD_ATAPI);
671
672 /* issue command to controller */
673 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
674
675 if (!(request->flags & ATA_R_ATAPI)) {
676 /* device reset doesn't interrupt */
677 if (request->u.ata.command == ATA_DEVICE_RESET) {
678 u_int32_t tf_data;
679 int timeout = 1000000;
680
681 do {
682 DELAY(10);
683 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
684 } while ((tf_data & ATA_S_BUSY) && timeout--);
685 if (bootverbose)
686 device_printf(ch->dev, "device_reset timeout=%dus\n",
687 (1000000-timeout)*10);
688 request->status = tf_data;
689 if (request->status & ATA_S_ERROR)
690 request->error = tf_data >> 8;
691 return ATA_OP_FINISHED;
692 }
693 }
694
695 /* start the timeout */
696 callout_reset(&request->callout, request->timeout * hz,
697 (timeout_t*)ata_timeout, request);
698 return ATA_OP_CONTINUES;
699 }
700
701 /* must be called with ATA channel locked and state_mtx held */
702 static int
703 ata_ahci_end_transaction(struct ata_request *request)
704 {
705 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
706 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
707 struct ata_ahci_cmd_list *clp;
708 u_int32_t tf_data;
709 int offset = ch->unit << 7;
710 int tag = 0;
711
712 /* kill the timeout */
713 callout_stop(&request->callout);
714
715 /* get status */
716 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
717 request->status = tf_data;
718
719 /* if error status get details */
720 if (request->status & ATA_S_ERROR)
721 request->error = tf_data >> 8;
722
723 /* record how much data we actually moved */
724 clp = (struct ata_ahci_cmd_list *)
725 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
726 request->donecount = clp->bytecount;
727
728 /* release SG list etc */
729 ch->dma->unload(ch->dev);
730
731 return ATA_OP_FINISHED;
732 }
733
734 static void
735 ata_ahci_reset(device_t dev)
736 {
737 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
738 struct ata_channel *ch = device_get_softc(dev);
739 u_int32_t cmd, signature;
740 int offset = ch->unit << 7;
741 int timeout;
742
743 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
744 device_printf(dev, "port not implemented\n");
745 return;
746 }
747 ch->devices = 0;
748
749 /* kill off all activity on this channel */
750 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
751 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
752 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
753
754 /* XXX SOS this is not entirely wrong */
755 timeout = 0;
756 do {
757 DELAY(1000);
758 if (timeout++ > 500) {
759 device_printf(dev, "stopping AHCI engine failed\n");
760 break;
761 }
762 }
763 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
764
765 /* issue Command List Override if supported */
766 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
767 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
768 cmd |= ATA_AHCI_P_CMD_CLO;
769 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
770 timeout = 0;
771 do {
772 DELAY(1000);
773 if (timeout++ > 500) {
774 device_printf(dev, "executing CLO failed\n");
775 break;
776 }
777 }
778 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
779 }
780
781 /* reset PHY and decide what is present */
782 if (ata_sata_phy_reset(dev)) {
783
784 /* clear any interrupts pending on this channel */
785 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
786 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
787
788 /* clear SATA error register */
789 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
790
791 /* start operations on this channel */
792 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
793 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
794 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
795
796 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
797 switch (signature) {
798 case 0x00000101:
799 ch->devices = ATA_ATA_MASTER;
800 break;
801 case 0x96690101:
802 ch->devices = ATA_PORTMULTIPLIER;
803 device_printf(ch->dev, "Portmultipliers not supported yet\n");
804 ch->devices = 0;
805 break;
806 case 0xeb140101:
807 ch->devices = ATA_ATAPI_MASTER;
808 break;
809 default: /* SOS XXX */
810 if (bootverbose)
811 device_printf(ch->dev, "No signature, assuming disk device\n");
812 ch->devices = ATA_ATA_MASTER;
813 }
814 }
815 if (bootverbose)
816 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
817 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
818 }
819
820 static void
821 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
822 {
823 struct ata_dmasetprd_args *args = xsc;
824 struct ata_ahci_dma_prd *prd = args->dmatab;
825 int i;
826
827 if (!(args->error = error)) {
828 for (i = 0; i < nsegs; i++) {
829 prd[i].dba = htole64(segs[i].ds_addr);
830 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
831 }
832 }
833 args->nsegs = nsegs;
834 }
835
836 static void
837 ata_ahci_dmainit(device_t dev)
838 {
839 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
840 struct ata_channel *ch = device_get_softc(dev);
841
842 ata_dmainit(dev);
843 if (ch->dma) {
844 /* note start and stop are not used here */
845 ch->dma->setprd = ata_ahci_dmasetprd;
846 ch->dma->max_iosize = 8192 * DEV_BSIZE;
847 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
848 ch->dma->max_address = BUS_SPACE_MAXADDR;
849 }
850 }
851
852 static int
853 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
854 {
855 bzero(ctp->cfis, 64);
856 if (request->flags & ATA_R_ATAPI) {
857 bzero(ctp->acmd, 32);
858 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
859 }
860 return ata_request2fis_h2d(request, &ctp->cfis[0]);
861 }
862
863 /*
864 * Generic AHCI part support functions.
865 */
866 int
867 ata_genahci_ident(device_t dev)
868 {
869 struct ata_pci_controller *ctlr = device_get_softc(dev);
870 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"};
871 char buffer[64];
872
873 if(!(pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) {
874 return ENXIO;
875 }
876
877 ksprintf(buffer, "GENERIC %s %s controller", id.text, ata_mode2str(id.max_dma));
878 device_set_desc_copy(dev, buffer);
879 ctlr->chip = &id;
880 ctlr->chipinit = ata_genahci_chipinit;
881 return 0;
882 }
883
884 static int
885 ata_genahci_chipinit(device_t dev)
886 {
887 struct ata_pci_controller *ctlr = device_get_softc(dev);
888
889 if (ata_setup_interrupt(dev))
890 return ENXIO;
891
892 /* Check if the chip has PCI BAR 5 as memory resource. */
893 ctlr->r_type2 = SYS_RES_MEMORY;
894 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */
895 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
896 &ctlr->r_rid2, RF_ACTIVE))) {
897 return ata_ahci_chipinit(dev);
898 } else
899 return ENXIO;
900 }
901
902 /*
903 * Acard chipset support functions
904 */
905 int
906 ata_acard_ident(device_t dev)
907 {
908 struct ata_pci_controller *ctlr = device_get_softc(dev);
909 struct ata_chip_id *idx;
910 static struct ata_chip_id ids[] =
911 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
912 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
913 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
914 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
915 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
916 { 0, 0, 0, 0, 0, 0}};
917 char buffer[64];
918
919 if (!(idx = ata_match_chip(dev, ids)))
920 return ENXIO;
921
922 ksprintf(buffer, "Acard %s %s controller",
923 idx->text, ata_mode2str(idx->max_dma));
924 device_set_desc_copy(dev, buffer);
925 ctlr->chip = idx;
926 ctlr->chipinit = ata_acard_chipinit;
927 return 0;
928 }
929
930 static int
931 ata_acard_chipinit(device_t dev)
932 {
933 struct ata_pci_controller *ctlr = device_get_softc(dev);
934
935 if (ata_setup_interrupt(dev))
936 return ENXIO;
937
938 ctlr->allocate = ata_acard_allocate;
939 if (ctlr->chip->cfg1 == ATPOLD) {
940 ctlr->setmode = ata_acard_850_setmode;
941 ctlr->locking = ata_serialize;
942 }
943 else
944 ctlr->setmode = ata_acard_86X_setmode;
945 return 0;
946 }
947
948 static int
949 ata_acard_allocate(device_t dev)
950 {
951 struct ata_channel *ch = device_get_softc(dev);
952
953 /* setup the usual register normal pci style */
954 if (ata_pci_allocate(dev))
955 return ENXIO;
956
957 ch->hw.status = ata_acard_status;
958 return 0;
959 }
960
961 static int
962 ata_acard_status(device_t dev)
963 {
964 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
965 struct ata_channel *ch = device_get_softc(dev);
966
967 if (ctlr->chip->cfg1 == ATPOLD &&
968 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
969 return 0;
970 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
971 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
972
973 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
974 ATA_BMSTAT_INTERRUPT)
975 return 0;
976 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
977 DELAY(1);
978 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
979 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
980 DELAY(1);
981 }
982 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
983 DELAY(100);
984 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
985 return 0;
986 }
987 return 1;
988 }
989
990 static void
991 ata_acard_850_setmode(device_t dev, int mode)
992 {
993 device_t gparent = GRANDPARENT(dev);
994 struct ata_pci_controller *ctlr = device_get_softc(gparent);
995 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
996 struct ata_device *atadev = device_get_softc(dev);
997 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
998 int error;
999
1000 mode = ata_limit_mode(dev, mode,
1001 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1002
1003 /* XXX SOS missing WDMA0+1 + PIO modes */
1004 if (mode >= ATA_WDMA2) {
1005 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1006 if (bootverbose)
1007 device_printf(dev, "%ssetting %s on %s chip\n",
1008 (error) ? "FAILURE " : "",
1009 ata_mode2str(mode), ctlr->chip->text);
1010 if (!error) {
1011 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1012
1013 reg54 &= ~(0x03 << (devno << 1));
1014 if (mode >= ATA_UDMA0)
1015 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1016 pci_write_config(gparent, 0x54, reg54, 1);
1017 pci_write_config(gparent, 0x4a, 0xa6, 1);
1018 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1019 atadev->mode = mode;
1020 return;
1021 }
1022 }
1023 /* we could set PIO mode timings, but we assume the BIOS did that */
1024 }
1025
1026 static void
1027 ata_acard_86X_setmode(device_t dev, int mode)
1028 {
1029 device_t gparent = GRANDPARENT(dev);
1030 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1031 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1032 struct ata_device *atadev = device_get_softc(dev);
1033 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1034 int error;
1035
1036
1037 mode = ata_limit_mode(dev, mode,
1038 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1039
1040 mode = ata_check_80pin(dev, mode);
1041
1042 /* XXX SOS missing WDMA0+1 + PIO modes */
1043 if (mode >= ATA_WDMA2) {
1044 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1045 if (bootverbose)
1046 device_printf(dev, "%ssetting %s on %s chip\n",
1047 (error) ? "FAILURE " : "",
1048 ata_mode2str(mode), ctlr->chip->text);
1049 if (!error) {
1050 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1051
1052 reg44 &= ~(0x000f << (devno << 2));
1053 if (mode >= ATA_UDMA0)
1054 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1055 pci_write_config(gparent, 0x44, reg44, 2);
1056 pci_write_config(gparent, 0x4a, 0xa6, 1);
1057 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1058 atadev->mode = mode;
1059 return;
1060 }
1061 }
1062 /* we could set PIO mode timings, but we assume the BIOS did that */
1063 }
1064
1065
1066 /*
1067 * Acer Labs Inc (ALI) chipset support functions
1068 */
1069 int
1070 ata_ali_ident(device_t dev)
1071 {
1072 struct ata_pci_controller *ctlr = device_get_softc(dev);
1073 struct ata_chip_id *idx;
1074 static struct ata_chip_id ids[] =
1075 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1076 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1077 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1078 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1079 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1080 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1081 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1082 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1083 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1084 { 0, 0, 0, 0, 0, 0}};
1085 char buffer[64];
1086
1087 if (!(idx = ata_match_chip(dev, ids)))
1088 return ENXIO;
1089
1090 ksprintf(buffer, "AcerLabs %s %s controller",
1091 idx->text, ata_mode2str(idx->max_dma));
1092 device_set_desc_copy(dev, buffer);
1093 ctlr->chip = idx;
1094 ctlr->chipinit = ata_ali_chipinit;
1095 return 0;
1096 }
1097
1098 static int
1099 ata_ali_chipinit(device_t dev)
1100 {
1101 struct ata_pci_controller *ctlr = device_get_softc(dev);
1102
1103 if (ata_setup_interrupt(dev))
1104 return ENXIO;
1105
1106 switch (ctlr->chip->cfg2) {
1107 case ALISATA:
1108 ctlr->channels = ctlr->chip->cfg1;
1109 ctlr->allocate = ata_ali_sata_allocate;
1110 ctlr->setmode = ata_sata_setmode;
1111
1112 /* if we have a memory resource we can likely do AHCI */
1113 ctlr->r_type2 = SYS_RES_MEMORY;
1114 ctlr->r_rid2 = PCIR_BAR(5);
1115 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1116 &ctlr->r_rid2, RF_ACTIVE)))
1117 return ata_ahci_chipinit(dev);
1118
1119 /* enable PCI interrupt */
1120 pci_write_config(dev, PCIR_COMMAND,
1121 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1122 break;
1123
1124 case ALINEW:
1125 /* use device interrupt as byte count end */
1126 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1127
1128 /* enable cable detection and UDMA support on newer chips */
1129 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1130
1131 /* enable ATAPI UDMA mode */
1132 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1133
1134 /* only chips with revision > 0xc4 can do 48bit DMA */
1135 if (ctlr->chip->chiprev <= 0xc4)
1136 device_printf(dev,
1137 "using PIO transfers above 137GB as workaround for "
1138 "48bit DMA access bug, expect reduced performance\n");
1139 ctlr->allocate = ata_ali_allocate;
1140 ctlr->reset = ata_ali_reset;
1141 ctlr->setmode = ata_ali_setmode;
1142 break;
1143
1144 case ALIOLD:
1145 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1146 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1147 ctlr->setmode = ata_ali_setmode;
1148 break;
1149 }
1150 return 0;
1151 }
1152
1153 static int
1154 ata_ali_allocate(device_t dev)
1155 {
1156 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1157 struct ata_channel *ch = device_get_softc(dev);
1158
1159 /* setup the usual register normal pci style */
1160 if (ata_pci_allocate(dev))
1161 return ENXIO;
1162
1163 /* older chips can't do 48bit DMA transfers */
1164 if (ctlr->chip->chiprev <= 0xc4)
1165 ch->flags |= ATA_NO_48BIT_DMA;
1166
1167 return 0;
1168 }
1169
1170 static int
1171 ata_ali_sata_allocate(device_t dev)
1172 {
1173 device_t parent = device_get_parent(dev);
1174 struct ata_pci_controller *ctlr = device_get_softc(parent);
1175 struct ata_channel *ch = device_get_softc(dev);
1176 struct resource *io = NULL, *ctlio = NULL;
1177 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1178 int i, rid;
1179
1180 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1181 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1182 if (!io)
1183 return ENXIO;
1184
1185 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1186 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1187 if (!ctlio) {
1188 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1189 return ENXIO;
1190 }
1191
1192 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1193 ch->r_io[i].res = io;
1194 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1195 }
1196 ch->r_io[ATA_CONTROL].res = ctlio;
1197 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1198 ch->r_io[ATA_IDX_ADDR].res = io;
1199 ata_default_registers(dev);
1200 if (ctlr->r_res1) {
1201 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1202 ch->r_io[i].res = ctlr->r_res1;
1203 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1204 }
1205 }
1206 ch->flags |= ATA_NO_SLAVE;
1207
1208 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1209 ata_pci_hw(dev);
1210 return 0;
1211 }
1212
1213 static void
1214 ata_ali_reset(device_t dev)
1215 {
1216 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1217 struct ata_channel *ch = device_get_softc(dev);
1218 device_t *children;
1219 int nchildren, i;
1220
1221 ata_generic_reset(dev);
1222
1223 /*
1224 * workaround for datacorruption bug found on at least SUN Blade-100
1225 * find the ISA function on the southbridge and disable then enable
1226 * the ATA channel tristate buffer
1227 */
1228 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1229 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1230 for (i = 0; i < nchildren; i++) {
1231 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1232 pci_write_config(children[i], 0x58,
1233 pci_read_config(children[i], 0x58, 1) &
1234 ~(0x04 << ch->unit), 1);
1235 pci_write_config(children[i], 0x58,
1236 pci_read_config(children[i], 0x58, 1) |
1237 (0x04 << ch->unit), 1);
1238 break;
1239 }
1240 }
1241 kfree(children, M_TEMP);
1242 }
1243 }
1244 }
1245
1246 static void
1247 ata_ali_setmode(device_t dev, int mode)
1248 {
1249 device_t gparent = GRANDPARENT(dev);
1250 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1251 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1252 struct ata_device *atadev = device_get_softc(dev);
1253 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1254 int error;
1255
1256 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1257
1258 if (ctlr->chip->cfg2 & ALINEW) {
1259 if (mode > ATA_UDMA2 &&
1260 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1261 ata_print_cable(dev, "controller");
1262 mode = ATA_UDMA2;
1263 }
1264 }
1265 else
1266 mode = ata_check_80pin(dev, mode);
1267
1268 if (ctlr->chip->cfg2 & ALIOLD) {
1269 /* doesn't support ATAPI DMA on write */
1270 ch->flags |= ATA_ATAPI_DMA_RO;
1271 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1272 /* doesn't support ATAPI DMA on two ATAPI devices */
1273 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1274 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1275 }
1276 }
1277
1278 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1279
1280 if (bootverbose)
1281 device_printf(dev, "%ssetting %s on %s chip\n",
1282 (error) ? "FAILURE " : "",
1283 ata_mode2str(mode), ctlr->chip->text);
1284 if (!error) {
1285 if (mode >= ATA_UDMA0) {
1286 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1287 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1288
1289 word54 &= ~(0x000f000f << (devno << 2));
1290 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1291 pci_write_config(gparent, 0x54, word54, 4);
1292 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1293 0x00310001, 4);
1294 }
1295 else {
1296 u_int32_t piotimings[] =
1297 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1298 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1299
1300 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1301 ~(0x0008000f << (devno << 2)), 4);
1302 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1303 piotimings[ata_mode2idx(mode)], 4);
1304 }
1305 atadev->mode = mode;
1306 }
1307 }
1308
1309
1310 /*
1311 * American Micro Devices (AMD) chipset support functions
1312 */
1313 int
1314 ata_amd_ident(device_t dev)
1315 {
1316 struct ata_pci_controller *ctlr = device_get_softc(dev);
1317 struct ata_chip_id *idx;
1318 static struct ata_chip_id ids[] =
1319 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1320 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1321 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1322 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1323 { 0, 0, 0, 0, 0, 0}};
1324 char buffer[64];
1325
1326 if (!(idx = ata_match_chip(dev, ids)))
1327 return ENXIO;
1328
1329 ksprintf(buffer, "AMD %s %s controller",
1330 idx->text, ata_mode2str(idx->max_dma));
1331 device_set_desc_copy(dev, buffer);
1332 ctlr->chip = idx;
1333 ctlr->chipinit = ata_amd_chipinit;
1334 return 0;
1335 }
1336
1337 static int
1338 ata_amd_chipinit(device_t dev)
1339 {
1340 struct ata_pci_controller *ctlr = device_get_softc(dev);
1341
1342 if (ata_setup_interrupt(dev))
1343 return ENXIO;
1344
1345 /* disable/set prefetch, postwrite */
1346 if (ctlr->chip->cfg2 & AMDBUG)
1347 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1348 else
1349 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1350
1351 ctlr->setmode = ata_via_family_setmode;
1352 return 0;
1353 }
1354
1355
1356 /*
1357 * ATI chipset support functions
1358 */
1359 int
1360 ata_ati_ident(device_t dev)
1361 {
1362 struct ata_pci_controller *ctlr = device_get_softc(dev);
1363 struct ata_chip_id *idx;
1364 static struct ata_chip_id ids[] =
1365 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1366 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1367 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1368 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" },
1369 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1370 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1371 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1372 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1373 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1374 { 0, 0, 0, 0, 0, 0}};
1375 char buffer[64];
1376
1377 if (!(idx = ata_match_chip(dev, ids)))
1378 return ENXIO;
1379
1380 ksprintf(buffer, "ATI %s %s controller",
1381 idx->text, ata_mode2str(idx->max_dma));
1382 device_set_desc_copy(dev, buffer);
1383 ctlr->chip = idx;
1384
1385 /*
1386 * The ATI SATA controllers are actually a SiI 3112 controller, except
1387 * for the SB600.
1388 */
1389 if (ctlr->chip->cfg1 & SIIMEMIO)
1390 ctlr->chipinit = ata_sii_chipinit;
1391 else
1392 ctlr->chipinit = ata_ati_chipinit;
1393 return 0;
1394 }
1395
1396 static int
1397 ata_ati_chipinit(device_t dev)
1398 {
1399 struct ata_pci_controller *ctlr = device_get_softc(dev);
1400
1401 if (ata_setup_interrupt(dev))
1402 return ENXIO;
1403
1404 /* The SB600 needs special treatment. */
1405 if (ctlr->chip->cfg1 & ATIAHCI) {
1406 /* Check if the chip is configured as an AHCI part. */
1407 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) &&
1408 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) {
1409 /* Check if the chip has PCI BAR 5 as memory resource. */
1410 ctlr->r_type2 = SYS_RES_MEMORY;
1411 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */
1412 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1413 &ctlr->r_rid2,
1414 RF_ACTIVE))) {
1415 return ata_ahci_chipinit(dev);
1416 }
1417 }
1418 }
1419
1420 ctlr->setmode = ata_ati_setmode;
1421 return 0;
1422 }
1423
1424 static void
1425 ata_ati_setmode(device_t dev, int mode)
1426 {
1427 device_t gparent = GRANDPARENT(dev);
1428 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1429 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1430 struct ata_device *atadev = device_get_softc(dev);
1431 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1432 int offset = (devno ^ 0x01) << 3;
1433 int error;
1434 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1435 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1436 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1437
1438 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1439
1440 mode = ata_check_80pin(dev, mode);
1441
1442 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1443
1444 if (bootverbose)
1445 device_printf(dev, "%ssetting %s on %s chip\n",
1446 (error) ? "FAILURE " : "",
1447 ata_mode2str(mode), ctlr->chip->text);
1448 if (!error) {
1449 if (mode >= ATA_UDMA0) {
1450 pci_write_config(gparent, 0x56,
1451 (pci_read_config(gparent, 0x56, 2) &
1452 ~(0xf << (devno << 2))) |
1453 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1454 pci_write_config(gparent, 0x54,
1455 pci_read_config(gparent, 0x54, 1) |
1456 (0x01 << devno), 1);
1457 pci_write_config(gparent, 0x44,
1458 (pci_read_config(gparent, 0x44, 4) &
1459 ~(0xff << offset)) |
1460 (dmatimings[2] << offset), 4);
1461 }
1462 else if (mode >= ATA_WDMA0) {
1463 pci_write_config(gparent, 0x54,
1464 pci_read_config(gparent, 0x54, 1) &
1465 ~(0x01 << devno), 1);
1466 pci_write_config(gparent, 0x44,
1467 (pci_read_config(gparent, 0x44, 4) &
1468 ~(0xff << offset)) |
1469 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1470 }
1471 else
1472 pci_write_config(gparent, 0x54,
1473 pci_read_config(gparent, 0x54, 1) &
1474 ~(0x01 << devno), 1);
1475
1476 pci_write_config(gparent, 0x4a,
1477 (pci_read_config(gparent, 0x4a, 2) &
1478 ~(0xf << (devno << 2))) |
1479 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1480 pci_write_config(gparent, 0x40,
1481 (pci_read_config(gparent, 0x40, 4) &
1482 ~(0xff << offset)) |
1483 (piotimings[ata_mode2idx(mode)] << offset), 4);
1484 atadev->mode = mode;
1485 }
1486 }
1487
1488 /*
1489 * Cyrix chipset support functions
1490 */
1491 int
1492 ata_cyrix_ident(device_t dev)
1493 {
1494 struct ata_pci_controller *ctlr = device_get_softc(dev);
1495
1496 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1497 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1498 ctlr->chipinit = ata_cyrix_chipinit;
1499 return 0;
1500 }
1501 return ENXIO;
1502 }
1503
1504 static int
1505 ata_cyrix_chipinit(device_t dev)
1506 {
1507 struct ata_pci_controller *ctlr = device_get_softc(dev);
1508
1509 if (ata_setup_interrupt(dev))
1510 return ENXIO;
1511
1512 if (ctlr->r_res1)
1513 ctlr->setmode = ata_cyrix_setmode;
1514 else
1515 ctlr->setmode = ata_generic_setmode;
1516 return 0;
1517 }
1518
1519 static void
1520 ata_cyrix_setmode(device_t dev, int mode)
1521 {
1522 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1523 struct ata_device *atadev = device_get_softc(dev);
1524 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1525 u_int32_t piotiming[] =
1526 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1527 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1528 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1529 int error;
1530
1531 ch->dma->alignment = 16;
1532 ch->dma->max_iosize = 126 * DEV_BSIZE;
1533
1534 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1535
1536 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1537
1538 if (bootverbose)
1539 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1540 (error) ? "FAILURE " : "", ata_mode2str(mode));
1541 if (!error) {
1542 if (mode >= ATA_UDMA0) {
1543 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1544 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1545 }
1546 else if (mode >= ATA_WDMA0) {
1547 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1548 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1549 }
1550 else {
1551 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1552 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1553 }
1554 atadev->mode = mode;
1555 }
1556 }
1557
1558
1559 /*
1560 * Cypress chipset support functions
1561 */
1562 int
1563 ata_cypress_ident(device_t dev)
1564 {
1565 struct ata_pci_controller *ctlr = device_get_softc(dev);
1566
1567 /*
1568 * the Cypress chip is a mess, it contains two ATA functions, but
1569 * both channels are visible on the first one.
1570 * simply ignore the second function for now, as the right
1571 * solution (ignoring the second channel on the first function)
1572 * doesn't work with the crappy ATA interrupt setup on the alpha.
1573 */
1574 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1575 pci_get_function(dev) == 1 &&
1576 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1577 device_set_desc(dev, "Cypress 82C693 ATA controller");
1578 ctlr->chipinit = ata_cypress_chipinit;
1579 return 0;
1580 }
1581 return ENXIO;
1582 }
1583
1584 static int
1585 ata_cypress_chipinit(device_t dev)
1586 {
1587 struct ata_pci_controller *ctlr = device_get_softc(dev);
1588
1589 if (ata_setup_interrupt(dev))
1590 return ENXIO;
1591
1592 ctlr->setmode = ata_cypress_setmode;
1593 return 0;
1594 }
1595
1596 static void
1597 ata_cypress_setmode(device_t dev, int mode)
1598 {
1599 device_t gparent = GRANDPARENT(dev);
1600 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1601 struct ata_device *atadev = device_get_softc(dev);
1602 int error;
1603
1604 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1605
1606 /* XXX SOS missing WDMA0+1 + PIO modes */
1607 if (mode == ATA_WDMA2) {
1608 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1609 if (bootverbose)
1610 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1611 error ? "FAILURE " : "");
1612 if (!error) {
1613 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1614 atadev->mode = mode;
1615 return;
1616 }
1617 }
1618 /* we could set PIO mode timings, but we assume the BIOS did that */
1619 }
1620
1621
1622 /*
1623 * HighPoint chipset support functions
1624 */
1625 int
1626 ata_highpoint_ident(device_t dev)
1627 {
1628 struct ata_pci_controller *ctlr = device_get_softc(dev);
1629 struct ata_chip_id *idx;
1630 static struct ata_chip_id ids[] =
1631 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1632 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1633 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1634 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1635 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1636 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1637 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1638 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1639 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1640 { 0, 0, 0, 0, 0, 0}};
1641 char buffer[64];
1642
1643 if (!(idx = ata_match_chip(dev, ids)))
1644 return ENXIO;
1645
1646 strcpy(buffer, "HighPoint ");
1647 strcat(buffer, idx->text);
1648 if (idx->cfg1 == HPT374) {
1649 if (pci_get_function(dev) == 0)
1650 strcat(buffer, " (channel 0+1)");
1651 if (pci_get_function(dev) == 1)
1652 strcat(buffer, " (channel 2+3)");
1653 }
1654 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1655 device_set_desc_copy(dev, buffer);
1656 ctlr->chip = idx;
1657 ctlr->chipinit = ata_highpoint_chipinit;
1658 return 0;
1659 }
1660
1661 static int
1662 ata_highpoint_chipinit(device_t dev)
1663 {
1664 struct ata_pci_controller *ctlr = device_get_softc(dev);
1665
1666 if (ata_setup_interrupt(dev))
1667 return ENXIO;
1668
1669 if (ctlr->chip->cfg2 == HPTOLD) {
1670 /* disable interrupt prediction */
1671 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1672 }
1673 else {
1674 /* disable interrupt prediction */
1675 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1676 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1677
1678 /* enable interrupts */
1679 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1680
1681 /* set clocks etc */
1682 if (ctlr->chip->cfg1 < HPT372)
1683 pci_write_config(dev, 0x5b, 0x22, 1);
1684 else
1685 pci_write_config(dev, 0x5b,
1686 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1687 }
1688 ctlr->allocate = ata_highpoint_allocate;
1689 ctlr->setmode = ata_highpoint_setmode;
1690 return 0;
1691 }
1692
1693 static int
1694 ata_highpoint_allocate(device_t dev)
1695 {
1696 struct ata_channel *ch = device_get_softc(dev);
1697
1698 /* setup the usual register normal pci style */
1699 if (ata_pci_allocate(dev))
1700 return ENXIO;
1701
1702 ch->flags |= ATA_ALWAYS_DMASTAT;
1703 return 0;
1704 }
1705
1706 static void
1707 ata_highpoint_setmode(device_t dev, int mode)
1708 {
1709 device_t gparent = GRANDPARENT(dev);
1710 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1711 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1712 struct ata_device *atadev = device_get_softc(dev);
1713 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1714 int error;
1715 u_int32_t timings33[][4] = {
1716 /* HPT366 HPT370 HPT372 HPT374 mode */
1717 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1718 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1719 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1720 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1721 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1722 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1723 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1724 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1725 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1726 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1727 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1728 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1729 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1730 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1731 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1732 };
1733
1734 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1735
1736 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1737 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1738
1739 mode = ata_highpoint_check_80pin(dev, mode);
1740
1741 /*
1742 * most if not all HPT chips cant really handle that the device is
1743 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1744 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1745 */
1746 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1747 ata_limit_mode(dev, mode, ATA_UDMA5));
1748 if (bootverbose)
1749 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1750 (error) ? "FAILURE " : "", ata_mode2str(mode));
1751 if (!error)
1752 pci_write_config(gparent, 0x40 + (devno << 2),
1753 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1754 atadev->mode = mode;
1755 }
1756
1757 static int
1758 ata_highpoint_check_80pin(device_t dev, int mode)
1759 {
1760 device_t gparent = GRANDPARENT(dev);
1761 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1762 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1763 u_int8_t reg, val, res;
1764
1765 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1766 reg = ch->unit ? 0x57 : 0x53;
1767 val = pci_read_config(gparent, reg, 1);
1768 pci_write_config(gparent, reg, val | 0x80, 1);
1769 }
1770 else {
1771 reg = 0x5b;
1772 val = pci_read_config(gparent, reg, 1);
1773 pci_write_config(gparent, reg, val & 0xfe, 1);
1774 }
1775 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1776 pci_write_config(gparent, reg, val, 1);
1777
1778 if (mode > ATA_UDMA2 && res) {
1779 ata_print_cable(dev, "controller");
1780 mode = ATA_UDMA2;
1781 }
1782 return mode;
1783 }
1784
1785
1786 /*
1787 * Intel chipset support functions
1788 */
1789 int
1790 ata_intel_ident(device_t dev)
1791 {
1792 struct ata_pci_controller *ctlr = device_get_softc(dev);
1793 struct ata_chip_id *idx;
1794 static struct ata_chip_id ids[] =
1795 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1796 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1797 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1798 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1799 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1800 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1801 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1802 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1803 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1804 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1805 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1806 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1807 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1808 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1809 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1810 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1811 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1812 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1813 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1814 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1815 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1816 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1817 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1818 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1819 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1820 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1821 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1822 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1823 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1824 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1825 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1826 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1827 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1828 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1829 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1830 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1831 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1832 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1833 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1834 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1835 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1836 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" },
1837 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1838 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1839 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1840 { 0, 0, 0, 0, 0, 0}};
1841 char buffer[64];
1842
1843 if (!(idx = ata_match_chip(dev, ids)))
1844 return ENXIO;
1845
1846 ksprintf(buffer, "Intel %s %s controller",
1847 idx->text, ata_mode2str(idx->max_dma));
1848 device_set_desc_copy(dev, buffer);
1849 ctlr->chip = idx;
1850 ctlr->chipinit = ata_intel_chipinit;
1851 return 0;
1852 }
1853
1854 static int
1855 ata_intel_chipinit(device_t dev)
1856 {
1857 struct ata_pci_controller *ctlr = device_get_softc(dev);
1858
1859 if (ata_setup_interrupt(dev))
1860 return ENXIO;
1861
1862 /* good old PIIX needs special treatment (not implemented) */
1863 if (ctlr->chip->chipid == ATA_I82371FB) {
1864 ctlr->setmode = ata_intel_old_setmode;
1865 }
1866
1867 /* the intel 31244 needs special care if in DPA mode */
1868 else if (ctlr->chip->chipid == ATA_I31244) {
1869 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1870 ctlr->r_type2 = SYS_RES_MEMORY;
1871 ctlr->r_rid2 = PCIR_BAR(0);
1872 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1873 &ctlr->r_rid2,
1874 RF_ACTIVE)))
1875 return ENXIO;
1876 ctlr->channels = 4;
1877 ctlr->allocate = ata_intel_31244_allocate;
1878 ctlr->reset = ata_intel_31244_reset;
1879 }
1880 ctlr->setmode = ata_sata_setmode;
1881 }
1882
1883 /* non SATA intel chips goes here */
1884 else if (ctlr->chip->max_dma < ATA_SA150) {
1885 ctlr->allocate = ata_intel_allocate;
1886 ctlr->setmode = ata_intel_new_setmode;
1887 }
1888
1889 /* SATA parts can be either compat or AHCI */
1890 else {
1891 /* force all ports active "the legacy way" */
1892 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1893
1894 ctlr->allocate = ata_intel_allocate;
1895 ctlr->reset = ata_intel_reset;
1896
1897 /*
1898 * if we have AHCI capability and BAR(5) as a memory resource
1899 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode
1900 */
1901 if ((ctlr->chip->cfg1 == AHCI) &&
1902 (pci_read_config(dev, 0x90, 1) & 0xc0)) {
1903 ctlr->r_type2 = SYS_RES_MEMORY;
1904 ctlr->r_rid2 = PCIR_BAR(5);
1905 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1906 &ctlr->r_rid2,
1907 RF_ACTIVE)))
1908 return ata_ahci_chipinit(dev);
1909 }
1910 ctlr->setmode = ata_sata_setmode;
1911
1912 /* enable PCI interrupt */
1913 pci_write_config(dev, PCIR_COMMAND,
1914 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1915 }
1916 return 0;
1917 }
1918
1919 static int
1920 ata_intel_allocate(device_t dev)
1921 {
1922 struct ata_channel *ch = device_get_softc(dev);
1923
1924 /* setup the usual register normal pci style */
1925 if (ata_pci_allocate(dev))
1926 return ENXIO;
1927
1928 ch->flags |= ATA_ALWAYS_DMASTAT;
1929 return 0;
1930 }
1931
1932 static void
1933 ata_intel_reset(device_t dev)
1934 {
1935 device_t parent = device_get_parent(dev);
1936 struct ata_pci_controller *ctlr = device_get_softc(parent);
1937 struct ata_channel *ch = device_get_softc(dev);
1938 int mask, timeout;
1939
1940 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1941 if (ctlr->chip->cfg1) {
1942 mask = (0x0005 << ch->unit);
1943 }
1944 else {
1945 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1946 if (pci_read_config(parent, 0x90, 1) & 0x04)
1947 mask = 0x0003;
1948 else {
1949 mask = (0x0001 << ch->unit);
1950 /* XXX SOS should be in intel_allocate if we grow it */
1951 ch->flags |= ATA_NO_SLAVE;
1952 }
1953 }
1954 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1955 DELAY(10);
1956 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1957
1958 /* wait up to 1 sec for "connect well" */
1959 for (timeout = 0; timeout < 100 ; timeout++) {
1960 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1961 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1962 break;
1963 ata_udelay(10000);
1964 }
1965 ata_generic_reset(dev);
1966 }
1967
1968 static void
1969 ata_intel_old_setmode(device_t dev, int mode)
1970 {
1971 /* NOT YET */
1972 }
1973
1974 static void
1975 ata_intel_new_setmode(device_t dev, int mode)
1976 {
1977 device_t gparent = GRANDPARENT(dev);
1978 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1979 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1980 struct ata_device *atadev = device_get_softc(dev);
1981 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1982 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1983 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1984 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1985 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1986 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1987 u_int32_t mask40 = 0, new40 = 0;
1988 u_int8_t mask44 = 0, new44 = 0;
1989 int error;
1990 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1991 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1992 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */
1993 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */
1994
1995 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1996
1997 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1998 ata_print_cable(dev, "controller");
1999 mode = ATA_UDMA2;
2000 }
2001
2002 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2003
2004 if (bootverbose)
2005 device_printf(dev, "%ssetting %s on %s chip\n",
2006 (error) ? "FAILURE " : "",
2007 ata_mode2str(mode), ctlr->chip->text);
2008 if (error)
2009 return;
2010
2011 /*
2012 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary
2013 * drive 0, secondary drive 1)
2014 *
2015 * 0 Disable Ultra DMA mode
2016 * 1 Enable Ultra DMA mode
2017 *
2018 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary
2019 * drive 0, secondary drive 1).
2020 * 0000 UDMA mode 0
2021 * 0001 UDMA mode 1, 3, 5
2022 * 0010 UDMA mode 2, 4, reserved
2023 * 0011 reserved
2024 * (top two bits for each drive reserved)
2025 */
2026 #if 0
2027 device_printf(dev,
2028 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2029 reg40, reg44, reg48 ,reg4a, reg54);
2030 #endif
2031 reg48 &= ~(0x0001 << devno);
2032 reg4a &= ~(0x3 << (devno << 2));
2033 if (mode >= ATA_UDMA0) {
2034 reg48 |= 0x0001 << devno;
2035 if (mode > ATA_UDMA0)
2036 reg4a |= (1 + !(mode & 0x01)) << (devno << 2);
2037 }
2038 pci_write_config(gparent, 0x48, reg48, 2);
2039 pci_write_config(gparent, 0x4a, reg4a, 2);
2040
2041 /*
2042 * reg54:
2043 *
2044 * 32:20 reserved
2045 * 19:18 Secondary ATA signal mode
2046 * 17:16 Primary ATA signal mode
2047 * 00 = Normal (enabled)
2048 * 01 = Tri-state (disabled)
2049 * 10 = Drive Low (disabled)
2050 * 11 = Reserved
2051 *
2052 * 15 Secondary drive 1 - Base Clock
2053 * 14 Secondary drive 0 - Base Clock
2054 * 13 Primary drive 1 - Base Clock
2055 * 12 Primary drive 0 - Base Clock
2056 * 0 = Select 33 MHz clock
2057 * 1 = Select 100 Mhz clock
2058 *
2059 * 11 Reserved
2060 * 10 Vendor specific (set by BIOS?)
2061 * 09:08 Reserved
2062 *
2063 * 07 Secondary drive 1 - Cable Type
2064 * 06 Secondary drive 0 - Cable Type
2065 * 05 Primary drive 1 - Cable Type
2066 * 04 Primary drive 0 - Cable Type
2067 * 0 = 40 Conductor
2068 * 1 = 80 Conductor (or high speed cable)
2069 *
2070 * 03 Secondary drive 1 - Select 33/66 clock
2071 * 02 Secondary drive 0 - Select 33/66 clock
2072 * 01 Primary drive 1 - Select 33/66 clock
2073 * 00 Primary drive 0 - Select 33/66 clock
2074 * 0 = Select 33 MHz
2075 * 1 = Select 66 MHz
2076 *
2077 * It is unclear what this should be set to when operating
2078 * in 100MHz mode.
2079 *
2080 * NOTE: UDMA2 = 33 MHz
2081 * UDMA3 = 40 MHz (?) - unsupported
2082 * UDMA4 = 66 MHz
2083 * UDMA5 = 100 MHz
2084 * UDMA6 = 133 Mhz
2085 */
2086 reg54 |= 0x0400; /* set vendor specific bit */
2087 reg54 &= ~((0x1 << devno) | (0x1000 << devno));
2088
2089 if (mode >= ATA_UDMA5)
2090 reg54 |= (0x1000 << devno);
2091 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */
2092 reg54 |= (0x1 << devno);
2093
2094 pci_write_config(gparent, 0x54, reg54, 2);
2095
2096 /*
2097 * Reg40 (32 bits... well, actually two 16 bit registers)
2098 *
2099 * Primary channel bits 15:00, Secondary channel bits 31:00. Note
2100 * that slave timings are handled in register 44.
2101 *
2102 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges
2103 *
2104 * 14 Slave ATA Timing Register Enable (R/W)
2105 *
2106 * 13:12 IORDY Sample Mode
2107 * 00 PIO-0
2108 * 01 PIO-2, SW-2
2109 * 10 PIO-3, PIO-4, MW-1, MW-2
2110 * 11 Reserved
2111 *
2112 * 11:10 Reserved
2113 *
2114 * 09:08 Recovery Mode
2115 * 00 PIO-0, PIO-2, SW-2
2116 * 01 PIO-3, MW-1
2117 * 10 Reserved
2118 * 11 PIO-4, MW-2
2119 *
2120 * 07:04 Secondary Device Control Bits
2121 * 03:00 Primary Device Control Bits
2122 *
2123 * bit 3 DMA Timing Enable
2124 *
2125 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device
2126 *
2127 * bit 1 Enable IORDY sample point capability for PIO
2128 * xfers. Always enabled for PIO4 and PIO3, enabled
2129 * for PIO2 if indicated by the device, and otherwise
2130 * probably should be 0.
2131 *
2132 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0
2133 * timing modes.
2134 */
2135
2136 /*
2137 * Modify reg40 according to the table
2138 */
2139 if (atadev->unit == ATA_MASTER) {
2140 mask40 = 0x3300;
2141 new40 = timings[ata_mode2idx(mode)] << 8;
2142 }
2143 else {
2144 mask44 = 0x0f;
2145 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2146 (timings[ata_mode2idx(mode)] & 0x03);
2147 }
2148
2149 /*
2150 * Slave ATA timing register enable
2151 */
2152 mask40 |= 0x4000;
2153 new40 |= 0x4000;
2154
2155 /*
2156 * Device control bits 3:0 for master, 7:4 for slave.
2157 *
2158 * bit3 DMA Timing enable.
2159 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly
2160 * bit1 Enable IORDY sample point capability for PIO xfers. Always
2161 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by
2162 * the device, and otherwise should be 0.
2163 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes.
2164 *
2165 * Set to: 0 x 1 1
2166 */
2167
2168 if (atadev->unit == ATA_MASTER) {
2169 mask40 |= 0x0F;
2170 new40 |= 0x03;
2171 if (!ata_atapi(dev))
2172 new40 |= 0x04;
2173 } else {
2174 mask40 |= 0xF0;
2175 new40 |= 0x30;
2176 if (!ata_atapi(dev))
2177 new40 |= 0x40;
2178 }
2179 /*
2180 reg40 &= ~0x00ff00ff;
2181 reg40 |= 0x40774077;
2182 */
2183
2184 /*
2185 * Primary or Secondary controller
2186 */
2187 if (ch->unit) {
2188 mask40 <<= 16;
2189 new40 <<= 16;
2190 mask44 <<= 4;
2191 new44 <<= 4;
2192 }
2193 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2194 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2195
2196 #if 0
2197 reg40 = pci_read_config(gparent, 0x40, 4);
2198 reg44 = pci_read_config(gparent, 0x44, 1);
2199 reg48 = pci_read_config(gparent, 0x48, 1);
2200 reg4a = pci_read_config(gparent, 0x4a, 2);
2201 reg54 = pci_read_config(gparent, 0x54, 2);
2202 device_printf(dev,
2203 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2204 reg40, reg44, reg48 ,reg4a, reg54);
2205 #endif
2206
2207 atadev->mode = mode;
2208 }
2209
2210 static int
2211 ata_intel_31244_allocate(device_t dev)
2212 {
2213 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2214 struct ata_channel *ch = device_get_softc(dev);
2215 int i;
2216 int ch_offset;
2217
2218 ch_offset = 0x200 + ch->unit * 0x200;
2219
2220 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2221 ch->r_io[i].res = ctlr->r_res2;
2222
2223 /* setup ATA registers */
2224 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2225 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2226 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2227 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2228 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2229 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2230 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2231 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2232 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2233 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2234 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2235 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2236
2237 /* setup DMA registers */
2238 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2239 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2240 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2241
2242 /* setup SATA registers */
2243 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2244 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2245 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2246
2247 ch->flags |= ATA_NO_SLAVE;
2248 ata_pci_hw(dev);
2249 ch->hw.status = ata_intel_31244_status;
2250 ch->hw.command = ata_intel_31244_command;
2251
2252 /* enable PHY state change interrupt */
2253 ATA_OUTL(ctlr->r_res2, 0x4,
2254 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2255 return 0;
2256 }
2257
2258 static int
2259 ata_intel_31244_status(device_t dev)
2260 {
2261 /* do we have any PHY events ? */
2262 ata_sata_phy_check_events(dev);
2263
2264 /* any drive action to take care of ? */
2265 return ata_pci_status(dev);
2266 }
2267
2268 static int
2269 ata_intel_31244_command(struct ata_request *request)
2270 {
2271 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2272 struct ata_device *atadev = device_get_softc(request->dev);
2273 u_int64_t lba;
2274
2275 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2276 return (ata_generic_command(request));
2277
2278 lba = request->u.ata.lba;
2279 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2280 /* enable interrupt */
2281 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2282 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2283 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2284 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2285 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2286 ((lba >> 8) & 0x00ff));
2287 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2288 ((lba >> 16) & 0x00ff));
2289
2290 /* issue command to controller */
2291 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2292
2293 return 0;
2294 }
2295
2296 static void
2297 ata_intel_31244_reset(device_t dev)
2298 {
2299 if (ata_sata_phy_reset(dev))
2300 ata_generic_reset(dev);
2301 }
2302
2303
2304 /*
2305 * Integrated Technology Express Inc. (ITE) chipset support functions
2306 */
2307 int
2308 ata_ite_ident(device_t dev)
2309 {
2310 struct ata_pci_controller *ctlr = device_get_softc(dev);
2311 struct ata_chip_id *idx;
2312 static struct ata_chip_id ids[] =
2313 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2314 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2315 { 0, 0, 0, 0, 0, 0}};
2316 char buffer[64];
2317
2318 if (!(idx = ata_match_chip(dev, ids)))
2319 return ENXIO;
2320
2321 ksprintf(buffer, "ITE %s %s controller",
2322 idx->text, ata_mode2str(idx->max_dma));
2323 device_set_desc_copy(dev, buffer);
2324 ctlr->chip = idx;
2325 ctlr->chipinit = ata_ite_chipinit;
2326 return 0;
2327 }
2328
2329 static int
2330 ata_ite_chipinit(device_t dev)
2331 {
2332 struct ata_pci_controller *ctlr = device_get_softc(dev);
2333
2334 if (ata_setup_interrupt(dev))
2335 return ENXIO;
2336
2337 ctlr->setmode = ata_ite_setmode;
2338
2339 /* set PCI mode and 66Mhz reference clock */
2340 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2341
2342 /* set default active & recover timings */
2343 pci_write_config(dev, 0x54, 0x31, 1);
2344 pci_write_config(dev, 0x56, 0x31, 1);
2345 return 0;
2346 }
2347
2348 static void
2349 ata_ite_setmode(device_t dev, int mode)
2350 {
2351 device_t gparent = GRANDPARENT(dev);
2352 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2353 struct ata_device *atadev = device_get_softc(dev);
2354 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2355 int error;
2356
2357 /* correct the mode for what the HW supports */
2358 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2359
2360 /* check the CBLID bits for 80 conductor cable detection */
2361 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2362 (ch->unit ? (1<<3) : (1<<2)))) {
2363 ata_print_cable(dev, "controller");
2364 mode = ATA_UDMA2;
2365 }
2366
2367 /* set the wanted mode on the device */
2368 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2369
2370 if (bootverbose)
2371 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2372 (error) ? "failed" : "success", ata_mode2str(mode));
2373
2374 /* if the device accepted the mode change, setup the HW accordingly */
2375 if (!error) {
2376 if (mode >= ATA_UDMA0) {
2377 u_int8_t udmatiming[] =
2378 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2379
2380 /* enable UDMA mode */
2381 pci_write_config(gparent, 0x50,
2382 pci_read_config(gparent, 0x50, 1) &
2383 ~(1 << (devno + 3)), 1);
2384
2385 /* set UDMA timing */
2386 pci_write_config(gparent,
2387 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2388 udmatiming[mode & ATA_MODE_MASK], 1);
2389 }
2390 else {
2391 u_int8_t chtiming[] =
2392 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2393
2394 /* disable UDMA mode */
2395 pci_write_config(gparent, 0x50,
2396 pci_read_config(gparent, 0x50, 1) |
2397 (1 << (devno + 3)), 1);
2398
2399 /* set active and recover timing (shared between master & slave) */
2400 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2401 chtiming[ata_mode2idx(mode)])
2402 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2403 chtiming[ata_mode2idx(mode)], 1);
2404 }
2405 atadev->mode = mode;
2406 }
2407 }
2408
2409
2410 /*
2411 * JMicron chipset support functions
2412 */
2413 int
2414 ata_jmicron_ident(device_t dev)
2415 {
2416 struct ata_pci_controller *ctlr = device_get_softc(dev);
2417 struct ata_chip_id *idx;
2418 static struct ata_chip_id ids[] =
2419 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2420 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2421 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2422 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2423 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2424 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2425 { 0, 0, 0, 0, 0, 0}};
2426 char buffer[64];
2427
2428 if (!(idx = ata_match_chip(dev, ids)))
2429 return ENXIO;
2430
2431 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2432 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2433 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2434 idx->text, ata_mode2str(ATA_UDMA6));
2435 else
2436 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2437 idx->text, ata_mode2str(idx->max_dma));
2438 device_set_desc_copy(dev, buffer);
2439 ctlr->chip = idx;
2440 ctlr->chipinit = ata_jmicron_chipinit;
2441 return 0;
2442 }
2443
2444 static int
2445 ata_jmicron_chipinit(device_t dev)
2446 {
2447 struct ata_pci_controller *ctlr = device_get_softc(dev);
2448 int error;
2449
2450 if (ata_setup_interrupt(dev))
2451 return ENXIO;
2452
2453 /* do we have multiple PCI functions ? */
2454 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2455 /* if we have a memory BAR(5) we are on the AHCI part */
2456 ctlr->r_type2 = SYS_RES_MEMORY;
2457 ctlr->r_rid2 = PCIR_BAR(5);
2458 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2459 &ctlr->r_rid2, RF_ACTIVE)))
2460 return ata_ahci_chipinit(dev);
2461
2462 /* otherwise we are on the PATA part */
2463 ctlr->allocate = ata_pci_allocate;
2464 ctlr->reset = ata_generic_reset;
2465 ctlr->dmainit = ata_pci_dmainit;
2466 ctlr->setmode = ata_jmicron_setmode;
2467 ctlr->channels = ctlr->chip->cfg2;
2468 }
2469 else {
2470 /* set controller configuration to a combined setup we support */
2471 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2472 pci_write_config(dev, 0x80, 0x01200000, 4);
2473
2474 ctlr->r_type2 = SYS_RES_MEMORY;
2475 ctlr->r_rid2 = PCIR_BAR(5);
2476 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2477 &ctlr->r_rid2, RF_ACTIVE))) {
2478 if ((error = ata_ahci_chipinit(dev)))
2479 return error;
2480 }
2481
2482 ctlr->allocate = ata_jmicron_allocate;
2483 ctlr->reset = ata_jmicron_reset;
2484 ctlr->dmainit = ata_jmicron_dmainit;
2485 ctlr->setmode = ata_jmicron_setmode;
2486
2487 /* set the number of HW channels */
2488 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2489 }
2490 return 0;
2491 }
2492
2493 static int
2494 ata_jmicron_allocate(device_t dev)
2495 {
2496 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2497 struct ata_channel *ch = device_get_softc(dev);
2498 int error;
2499
2500 if (ch->unit >= ctlr->chip->cfg1) {
2501 ch->unit -= ctlr->chip->cfg1;
2502 error = ata_pci_allocate(dev);
2503 ch->unit += ctlr->chip->cfg1;
2504 }
2505 else
2506 error = ata_ahci_allocate(dev);
2507 return error;
2508 }
2509
2510 static void
2511 ata_jmicron_reset(device_t dev)
2512 {
2513 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2514 struct ata_channel *ch = device_get_softc(dev);
2515
2516 if (ch->unit >= ctlr->chip->cfg1)
2517 ata_generic_reset(dev);
2518 else
2519 ata_ahci_reset(dev);
2520 }
2521
2522 static void
2523 ata_jmicron_dmainit(device_t dev)
2524 {
2525 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2526 struct ata_channel *ch = device_get_softc(dev);
2527
2528 if (ch->unit >= ctlr->chip->cfg1)
2529 ata_pci_dmainit(dev);
2530 else
2531 ata_ahci_dmainit(dev);
2532 }
2533
2534 static void
2535 ata_jmicron_setmode(device_t dev, int mode)
2536 {
2537 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2538 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2539
2540 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2541 struct ata_device *atadev = device_get_softc(dev);
2542
2543 /* check for 80pin cable present */
2544 if (pci_read_config(dev, 0x40, 1) & 0x08)
2545 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2546 else
2547 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2548
2549 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2550 atadev->mode = mode;
2551 }
2552 else
2553 ata_sata_setmode(dev, mode);
2554 }
2555
2556
2557 /*
2558 * Marvell chipset support functions
2559 */
2560 #define ATA_MV_HOST_BASE(ch) \
2561 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2562 #define ATA_MV_EDMA_BASE(ch) \
2563 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2564
2565 struct ata_marvell_response {
2566 u_int16_t tag;
2567 u_int8_t edma_status;
2568 u_int8_t dev_status;
2569 u_int32_t timestamp;
2570 };
2571
2572 struct ata_marvell_dma_prdentry {
2573 u_int32_t addrlo;
2574 u_int32_t count;
2575 u_int32_t addrhi;
2576 u_int32_t reserved;
2577 };
2578
2579 int
2580 ata_marvell_ident(device_t dev)
2581 {
2582 struct ata_pci_controller *ctlr = device_get_softc(dev);
2583 struct ata_chip_id *idx;
2584 static struct ata_chip_id ids[] =
2585 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2586 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2587 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2588 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2589 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2590 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2591 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2592 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2593 { 0, 0, 0, 0, 0, 0}};
2594 char buffer[64];
2595
2596 if (!(idx = ata_match_chip(dev, ids)))
2597 return ENXIO;
2598
2599 ksprintf(buffer, "Marvell %s %s controller",
2600 idx->text, ata_mode2str(idx->max_dma));
2601 device_set_desc_copy(dev, buffer);
2602 ctlr->chip = idx;
2603 switch (ctlr->chip->cfg2) {
2604 case MV50XX:
2605 case MV60XX:
2606 ctlr->chipinit = ata_marvell_edma_chipinit;
2607 break;
2608 case MV61XX:
2609 ctlr->chipinit = ata_marvell_pata_chipinit;
2610 break;
2611 }
2612 return 0;
2613 }
2614
2615 static int
2616 ata_marvell_pata_chipinit(device_t dev)
2617 {
2618 struct ata_pci_controller *ctlr = device_get_softc(dev);
2619
2620 if (ata_setup_interrupt(dev))
2621 return ENXIO;
2622
2623 ctlr->allocate = ata_marvell_pata_allocate;
2624 ctlr->setmode = ata_marvell_pata_setmode;
2625 ctlr->channels = ctlr->chip->cfg1;
2626 return 0;
2627 }
2628
2629 static int
2630 ata_marvell_pata_allocate(device_t dev)
2631 {
2632 struct ata_channel *ch = device_get_softc(dev);
2633
2634 /* setup the usual register normal pci style */
2635 if (ata_pci_allocate(dev))
2636 return ENXIO;
2637
2638 /* dont use 32 bit PIO transfers */
2639 ch->flags |= ATA_USE_16BIT;
2640
2641 return 0;
2642 }
2643
2644 static void
2645 ata_marvell_pata_setmode(device_t dev, int mode)
2646 {
2647 device_t gparent = GRANDPARENT(dev);
2648 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2649 struct ata_device *atadev = device_get_softc(dev);
2650
2651 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2652 mode = ata_check_80pin(dev, mode);
2653 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2654 atadev->mode = mode;
2655 }
2656
2657 static int
2658 ata_marvell_edma_chipinit(device_t dev)
2659 {
2660 struct ata_pci_controller *ctlr = device_get_softc(dev);
2661
2662 if (ata_setup_interrupt(dev))
2663 return ENXIO;
2664
2665 ctlr->r_type1 = SYS_RES_MEMORY;
2666 ctlr->r_rid1 = PCIR_BAR(0);
2667 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2668 &ctlr->r_rid1, RF_ACTIVE)))
2669 return ENXIO;
2670
2671 /* mask all host controller interrupts */
2672 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2673
2674 /* mask all PCI interrupts */
2675 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2676
2677 ctlr->allocate = ata_marvell_edma_allocate;
2678 ctlr->reset = ata_marvell_edma_reset;
2679 ctlr->dmainit = ata_marvell_edma_dmainit;
2680 ctlr->setmode = ata_sata_setmode;
2681 ctlr->channels = ctlr->chip->cfg1;
2682
2683 /* clear host controller interrupts */
2684 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2685 if (ctlr->chip->cfg1 > 4)
2686 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2687
2688 /* clear PCI interrupts */
2689 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2690
2691 /* unmask PCI interrupts we want */
2692 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2693
2694 /* unmask host controller interrupts we want */
2695 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2696 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2697
2698 /* enable PCI interrupt */
2699 pci_write_config(dev, PCIR_COMMAND,
2700 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2701 return 0;
2702 }
2703
2704 static int
2705 ata_marvell_edma_allocate(device_t dev)
2706 {
2707 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2708 struct ata_channel *ch = device_get_softc(dev);
2709 u_int64_t work = ch->dma->work_bus;
2710 int i;
2711
2712 /* clear work area */
2713 bzero(ch->dma->work, 1024+256);
2714
2715 /* set legacy ATA resources */
2716 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2717 ch->r_io[i].res = ctlr->r_res1;
2718 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2719 }
2720 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2721 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2722 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2723 ata_default_registers(dev);
2724
2725 /* set SATA resources */
2726 switch (ctlr->chip->cfg2) {
2727 case MV50XX:
2728 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2729 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2730 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2731 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2732 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2733 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2734 break;
2735 case MV60XX:
2736 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2737 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2738 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2739 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2740 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2741 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2742 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2743 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2744 break;
2745 }
2746
2747 ch->flags |= ATA_NO_SLAVE;
2748 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2749 ata_generic_hw(dev);
2750 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2751 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2752 ch->hw.status = ata_marvell_edma_status;
2753
2754 /* disable the EDMA machinery */
2755 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2756 DELAY(100000); /* SOS should poll for disabled */
2757
2758 /* set configuration to non-queued 128b read transfers stop on error */
2759 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2760
2761 /* request queue base high */
2762 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2763
2764 /* request queue in ptr */
2765 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2766
2767 /* request queue out ptr */
2768 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2769
2770 /* response queue base high */
2771 work += 1024;
2772 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2773
2774 /* response queue in ptr */
2775 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2776
2777 /* response queue out ptr */
2778 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2779
2780 /* clear SATA error register */
2781 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2782
2783 /* clear any outstanding error interrupts */
2784 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2785
2786 /* unmask all error interrupts */
2787 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2788
2789 /* enable EDMA machinery */
2790 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2791 return 0;
2792 }
2793
2794 static int
2795 ata_marvell_edma_status(device_t dev)
2796 {
2797 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2798 struct ata_channel *ch = device_get_softc(dev);
2799 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2800 int shift = (ch->unit << 1) + (ch->unit > 3);
2801
2802 if (cause & (1 << shift)) {
2803
2804 /* clear interrupt(s) */
2805 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2806
2807 /* do we have any PHY events ? */
2808 ata_sata_phy_check_events(dev);
2809 }
2810
2811 /* do we have any device action ? */
2812 return (cause & (2 << shift));
2813 }
2814
2815 /* must be called with ATA channel locked and state_mtx held */
2816 static int
2817 ata_marvell_edma_begin_transaction(struct ata_request *request)
2818 {
2819 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2820 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2821 u_int32_t req_in;
2822 u_int8_t *bytep;
2823 u_int16_t *wordp;
2824 u_int32_t *quadp;
2825 int i, tag = 0x07;
2826 int dummy, error, slot;
2827
2828 /* only DMA R/W goes through the EMDA machine */
2829 if (request->u.ata.command != ATA_READ_DMA &&
2830 request->u.ata.command != ATA_WRITE_DMA) {
2831
2832 /* disable the EDMA machinery */
2833 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2834 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2835 return ata_begin_transaction(request);
2836 }
2837
2838 /* check for 48 bit access and convert if needed */
2839 ata_modify_if_48bit(request);
2840
2841 /* check sanity, setup SG list and DMA engine */
2842 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2843 request->flags & ATA_R_READ, ch->dma->sg,
2844 &dummy))) {
2845 device_printf(request->dev, "setting up DMA failed\n");
2846 request->result = error;
2847 return ATA_OP_FINISHED;
2848 }
2849
2850 /* get next free request queue slot */
2851 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2852 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2853 bytep = (u_int8_t *)(ch->dma->work);
2854 bytep += (slot << 5);
2855 wordp = (u_int16_t *)bytep;
2856 quadp = (u_int32_t *)bytep;
2857
2858 /* fill in this request */
2859 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2860 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2861 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2862
2863 i = 10;
2864 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2865 bytep[i++] = 0x10 | ATA_COUNT;
2866 bytep[i++] = request->u.ata.count & 0xff;
2867 bytep[i++] = 0x10 | ATA_COUNT;
2868
2869 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2870 bytep[i++] = 0x10 | ATA_SECTOR;
2871 bytep[i++] = request->u.ata.lba & 0xff;
2872 bytep[i++] = 0x10 | ATA_SECTOR;
2873
2874 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2875 bytep[i++] = 0x10 | ATA_CYL_LSB;
2876 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2877 bytep[i++] = 0x10 | ATA_CYL_LSB;
2878
2879 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2880 bytep[i++] = 0x10 | ATA_CYL_MSB;
2881 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2882 bytep[i++] = 0x10 | ATA_CYL_MSB;
2883
2884 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2885 bytep[i++] = 0x10 | ATA_DRIVE;
2886
2887 bytep[i++] = request->u.ata.command;
2888 bytep[i++] = 0x90 | ATA_COMMAND;
2889
2890 /* enable EDMA machinery if needed */
2891 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2892 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2893 while (!(ATA_INL(ctlr->r_res1,
2894 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2895 DELAY(10);
2896 }
2897
2898 /* tell EDMA it has a new request */
2899 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2900 req_in &= 0xfffffc00;
2901 req_in += (slot << 5);
2902 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2903
2904 return ATA_OP_CONTINUES;
2905 }
2906
2907 /* must be called with ATA channel locked and state_mtx held */
2908 static int
2909 ata_marvell_edma_end_transaction(struct ata_request *request)
2910 {
2911 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2912 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2913 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2914 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2915 int res;
2916
2917 /* EDMA interrupt */
2918 if ((icr & (0x0001 << (ch->unit & 3)))) {
2919 struct ata_marvell_response *response;
2920 u_int32_t rsp_in, rsp_out;
2921 int slot;
2922
2923 /* stop timeout */
2924 callout_stop(&request->callout);
2925
2926 /* get response ptr's */
2927 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2928 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2929 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2930 rsp_out &= 0xffffff00;
2931 rsp_out += (slot << 3);
2932 response = (struct ata_marvell_response *)
2933 (ch->dma->work + 1024 + (slot << 3));
2934
2935 /* record status for this request */
2936 request->status = response->dev_status;
2937 request->error = 0;
2938
2939 /* ack response */
2940 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2941
2942 /* update progress */
2943 if (!(request->status & ATA_S_ERROR) &&
2944 !(request->flags & ATA_R_TIMEOUT))
2945 request->donecount = request->bytecount;
2946
2947 /* unload SG list */
2948 ch->dma->unload(ch->dev);
2949
2950 res = ATA_OP_FINISHED;
2951 }
2952
2953 /* legacy ATA interrupt */
2954 else {
2955 res = ata_end_transaction(request);
2956 }
2957
2958 /* ack interrupt */
2959 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2960 return res;
2961 }
2962
2963 static void
2964 ata_marvell_edma_reset(device_t dev)
2965 {
2966 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2967 struct ata_channel *ch = device_get_softc(dev);
2968
2969 /* disable the EDMA machinery */
2970 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2971 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2972 DELAY(10);
2973
2974 /* clear SATA error register */
2975 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2976
2977 /* clear any outstanding error interrupts */
2978 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2979
2980 /* unmask all error interrupts */
2981 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2982
2983 /* enable channel and test for devices */
2984 if (ata_sata_phy_reset(dev))
2985 ata_generic_reset(dev);
2986
2987 /* enable EDMA machinery */
2988 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2989 }
2990
2991 static void
2992 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2993 int error)
2994 {
2995 struct ata_dmasetprd_args *args = xsc;
2996 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2997 int i;
2998
2999 if ((args->error = error))
3000 return;
3001
3002 for (i = 0; i < nsegs; i++) {
3003 prd[i].addrlo = htole32(segs[i].ds_addr);
3004 prd[i].count = htole32(segs[i].ds_len);
3005 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
3006 }
3007 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3008 }
3009
3010 static void
3011 ata_marvell_edma_dmainit(device_t dev)
3012 {
3013 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3014 struct ata_channel *ch = device_get_softc(dev);
3015
3016 ata_dmainit(dev);
3017 if (ch->dma) {
3018 /* note start and stop are not used here */
3019 ch->dma->setprd = ata_marvell_edma_dmasetprd;
3020
3021 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
3022 ch->dma->max_address = BUS_SPACE_MAXADDR;
3023 }
3024 }
3025
3026
3027 /*
3028 * National chipset support functions
3029 */
3030 int
3031 ata_national_ident(device_t dev)
3032 {
3033 struct ata_pci_controller *ctlr = device_get_softc(dev);
3034
3035 /* this chip is a clone of the Cyrix chip, bugs and all */
3036 if (pci_get_devid(dev) == ATA_SC1100) {
3037 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
3038 ctlr->chipinit = ata_national_chipinit;
3039 return 0;
3040 }
3041 return ENXIO;
3042 }
3043
3044 static int
3045 ata_national_chipinit(device_t dev)
3046 {
3047 struct ata_pci_controller *ctlr = device_get_softc(dev);
3048
3049 if (ata_setup_interrupt(dev))
3050 return ENXIO;
3051
3052 ctlr->setmode = ata_national_setmode;
3053 return 0;
3054 }
3055
3056 static void
3057 ata_national_setmode(device_t dev, int mode)
3058 {
3059 device_t gparent = GRANDPARENT(dev);
3060 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3061 struct ata_device *atadev = device_get_softc(dev);
3062 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3063 u_int32_t piotiming[] =
3064 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
3065 0x00803020, 0x20102010, 0x00100010,
3066 0x00100010, 0x00100010, 0x00100010 };
3067 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
3068 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
3069 int error;
3070
3071 ch->dma->alignment = 16;
3072 ch->dma->max_iosize = 126 * DEV_BSIZE;
3073
3074 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
3075
3076 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3077
3078 if (bootverbose)
3079 device_printf(dev, "%s setting %s on National chip\n",
3080 (error) ? "failed" : "success", ata_mode2str(mode));
3081 if (!error) {
3082 if (mode >= ATA_UDMA0) {
3083 pci_write_config(gparent, 0x44 + (devno << 3),
3084 udmatiming[mode & ATA_MODE_MASK], 4);
3085 }
3086 else if (mode >= ATA_WDMA0) {
3087 pci_write_config(gparent, 0x44 + (devno << 3),
3088 dmatiming[mode & ATA_MODE_MASK], 4);
3089 }
3090 else {
3091 pci_write_config(gparent, 0x44 + (devno << 3),
3092 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
3093 0x80000000, 4);
3094 }
3095 pci_write_config(gparent, 0x40 + (devno << 3),
3096 piotiming[ata_mode2idx(mode)], 4);
3097 atadev->mode = mode;
3098 }
3099 }
3100
3101 /*
3102 * NetCell chipset support functions
3103 */
3104 int
3105 ata_netcell_ident(device_t dev)
3106 {
3107 struct ata_pci_controller *ctlr = device_get_softc(dev);
3108
3109 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
3110 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
3111 ctlr->chipinit = ata_netcell_chipinit;
3112 return 0;
3113 }
3114 return ENXIO;
3115 }
3116
3117 static int
3118 ata_netcell_chipinit(device_t dev)
3119 {
3120 struct ata_pci_controller *ctlr = device_get_softc(dev);
3121
3122 if (ata_generic_chipinit(dev))
3123 return ENXIO;
3124
3125 ctlr->allocate = ata_netcell_allocate;
3126 return 0;
3127 }
3128
3129 static int
3130 ata_netcell_allocate(device_t dev)
3131 {
3132 struct ata_channel *ch = device_get_softc(dev);
3133
3134 /* setup the usual register normal pci style */
3135 if (ata_pci_allocate(dev))
3136 return ENXIO;
3137
3138 /* the NetCell only supports 16 bit PIO transfers */
3139 ch->flags |= ATA_USE_16BIT;
3140
3141 return 0;
3142 }
3143
3144
3145 /*
3146 * nVidia chipset support functions
3147 */
3148 int
3149 ata_nvidia_ident(device_t dev)
3150 {
3151 struct ata_pci_controller *ctlr = device_get_softc(dev);
3152 struct ata_chip_id *idx;
3153 static struct ata_chip_id ids[] =
3154 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3155 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3156 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3157 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3158 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3159 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3160 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3161 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3162 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3163 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3164 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3165 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3166 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3167 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3168 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3169 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3170 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3171 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3172 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3173 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3174 { 0, 0, 0, 0, 0, 0}} ;
3175 char buffer[64] ;
3176
3177 if (!(idx = ata_match_chip(dev, ids)))
3178 return ENXIO;
3179
3180 ksprintf(buffer, "nVidia %s %s controller",
3181 idx->text, ata_mode2str(idx->max_dma));
3182 device_set_desc_copy(dev, buffer);
3183 ctlr->chip = idx;
3184 ctlr->chipinit = ata_nvidia_chipinit;
3185 return 0;
3186 }
3187
3188 static int
3189 ata_nvidia_chipinit(device_t dev)
3190 {
3191 struct ata_pci_controller *ctlr = device_get_softc(dev);
3192
3193 if (ata_setup_interrupt(dev))
3194 return ENXIO;
3195
3196 if (ctlr->chip->max_dma >= ATA_SA150) {
3197 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3198 ctlr->r_type2 = SYS_RES_IOPORT;
3199 else
3200 ctlr->r_type2 = SYS_RES_MEMORY;
3201 ctlr->r_rid2 = PCIR_BAR(5);
3202 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3203 &ctlr->r_rid2, RF_ACTIVE))) {
3204 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3205
3206 ctlr->allocate = ata_nvidia_allocate;
3207 ctlr->reset = ata_nvidia_reset;
3208
3209 /* enable control access */
3210 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3211
3212 if (ctlr->chip->cfg2 & NVQ) {
3213 /* clear interrupt status */
3214 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3215
3216 /* enable device and PHY state change interrupts */
3217 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3218
3219 /* disable NCQ support */
3220 ATA_OUTL(ctlr->r_res2, 0x0400,
3221 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3222 }
3223 else {
3224 /* clear interrupt status */
3225 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3226
3227 /* enable device and PHY state change interrupts */
3228 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3229 }
3230
3231 /* enable PCI interrupt */
3232 pci_write_config(dev, PCIR_COMMAND,
3233 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3234
3235 }
3236 ctlr->setmode = ata_sata_setmode;
3237 }
3238 else {
3239 /* disable prefetch, postwrite */
3240 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3241 ctlr->setmode = ata_via_family_setmode;
3242 }
3243 return 0;
3244 }
3245
3246 static int
3247 ata_nvidia_allocate(device_t dev)
3248 {
3249 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3250 struct ata_channel *ch = device_get_softc(dev);
3251
3252 /* setup the usual register normal pci style */
3253 if (ata_pci_allocate(dev))
3254 return ENXIO;
3255
3256 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3257 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3258 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3259 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3260 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3261 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3262
3263 ch->hw.status = ata_nvidia_status;
3264 ch->flags |= ATA_NO_SLAVE;
3265
3266 return 0;
3267 }
3268
3269 static int
3270 ata_nvidia_status(device_t dev)
3271 {
3272 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3273 struct ata_channel *ch = device_get_softc(dev);
3274 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3275 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3276 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3277
3278 /* do we have any PHY events ? */
3279 if (istatus & (0x0c << shift))
3280 ata_sata_phy_check_events(dev);
3281
3282 /* clear interrupt(s) */
3283 ATA_OUTB(ctlr->r_res2, offset,
3284 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3285
3286 /* do we have any device action ? */
3287 return (istatus & (0x01 << shift));
3288 }
3289
3290 static void
3291 ata_nvidia_reset(device_t dev)
3292 {
3293 if (ata_sata_phy_reset(dev))
3294 ata_generic_reset(dev);
3295 }
3296
3297
3298 /*
3299 * Promise chipset support functions
3300 */
3301 #define ATA_PDC_APKT_OFFSET 0x00000010
3302 #define ATA_PDC_HPKT_OFFSET 0x00000040
3303 #define ATA_PDC_ASG_OFFSET 0x00000080
3304 #define ATA_PDC_LSG_OFFSET 0x000000c0
3305 #define ATA_PDC_HSG_OFFSET 0x00000100
3306 #define ATA_PDC_CHN_OFFSET 0x00000400
3307 #define ATA_PDC_BUF_BASE 0x00400000
3308 #define ATA_PDC_BUF_OFFSET 0x00100000
3309 #define ATA_PDC_MAX_HPKT 8
3310 #define ATA_PDC_WRITE_REG 0x00
3311 #define ATA_PDC_WRITE_CTL 0x0e
3312 #define ATA_PDC_WRITE_END 0x08
3313 #define ATA_PDC_WAIT_NBUSY 0x10
3314 #define ATA_PDC_WAIT_READY 0x18
3315 #define ATA_PDC_1B 0x20
3316 #define ATA_PDC_2B 0x40
3317
3318 struct host_packet {
3319 u_int32_t addr;
3320 TAILQ_ENTRY(host_packet) chain;
3321 };
3322
3323 struct ata_promise_sx4 {
3324 struct spinlock mtx;
3325 TAILQ_HEAD(, host_packet) queue;
3326 int busy;
3327 };
3328
3329 int
3330 ata_promise_ident(device_t dev)
3331 {
3332 struct ata_pci_controller *ctlr = device_get_softc(dev);
3333 struct ata_chip_id *idx;
3334 static struct ata_chip_id ids[] =
3335 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3336 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3337 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3338 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3339 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3340 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3341 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3342 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3343 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3344 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3345 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3346 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3347 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3348 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3349 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3350 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3351 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3352 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3353 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3354 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3355 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3356 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3357 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3358 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3359 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3360 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3361 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3362 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3363 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3364 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3365 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3366 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3367 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3368 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3369 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3370 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3371 { 0, 0, 0, 0, 0, 0}};
3372 char buffer[64];
3373 uintptr_t devid = 0;
3374
3375 if (!(idx = ata_match_chip(dev, ids)))
3376 return ENXIO;
3377
3378 /* if we are on a SuperTrak SX6000 dont attach */
3379 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3380 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3381 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3382 devid == ATA_I960RM)
3383 return ENXIO;
3384
3385 strcpy(buffer, "Promise ");
3386 strcat(buffer, idx->text);
3387
3388 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3389 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3390 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3391 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3392 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3393 static long start = 0, end = 0;
3394
3395 if (pci_get_slot(dev) == 1) {
3396 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3397 strcat(buffer, " (channel 0+1)");
3398 }
3399 else if (pci_get_slot(dev) == 2 && start && end) {
3400 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3401 strcat(buffer, " (channel 2+3)");
3402 }
3403 else {
3404 start = end = 0;
3405 }
3406 }
3407 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3408 device_set_desc_copy(dev, buffer);
3409 ctlr->chip = idx;
3410 ctlr->chipinit = ata_promise_chipinit;
3411 return 0;
3412 }
3413
3414 static int
3415 ata_promise_chipinit(device_t dev)
3416 {
3417 struct ata_pci_controller *ctlr = device_get_softc(dev);
3418 int fake_reg, stat_reg;
3419
3420 if (ata_setup_interrupt(dev))
3421 return ENXIO;
3422
3423 switch (ctlr->chip->cfg1) {
3424 case PRNEW:
3425 /* setup clocks */
3426 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3427
3428 ctlr->dmainit = ata_promise_dmainit;
3429 /* FALLTHROUGH */
3430
3431 case PROLD:
3432 /* enable burst mode */
3433 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3434 ctlr->allocate = ata_promise_allocate;
3435 ctlr->setmode = ata_promise_setmode;
3436 return 0;
3437
3438 case PRTX:
3439 ctlr->allocate = ata_promise_tx2_allocate;
3440 ctlr->setmode = ata_promise_setmode;
3441 return 0;
3442
3443 case PRMIO:
3444 ctlr->r_type1 = SYS_RES_MEMORY;
3445 ctlr->r_rid1 = PCIR_BAR(4);
3446 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3447 &ctlr->r_rid1, RF_ACTIVE)))
3448 goto failnfree;
3449
3450 ctlr->r_type2 = SYS_RES_MEMORY;
3451 ctlr->r_rid2 = PCIR_BAR(3);
3452 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3453 &ctlr->r_rid2, RF_ACTIVE)))
3454 goto failnfree;
3455
3456 if (ctlr->chip->cfg2 == PRSX4X) {
3457 struct ata_promise_sx4 *hpkt;
3458 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3459
3460 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3461 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3462 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) {
3463 device_printf(dev, "unable to setup interrupt\n");
3464 goto failnfree;
3465 }
3466
3467 /* print info about cache memory */
3468 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3469 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3470 ((dimm >> 24) & 0xff),
3471 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3472 " ECC enabled" : "" );
3473
3474 /* adjust cache memory parameters */
3475 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3476 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3477
3478 /* setup host packet controls */
3479 hpkt = kmalloc(sizeof(struct ata_promise_sx4),
3480 M_TEMP, M_INTWAIT | M_ZERO);
3481 spin_init(&hpkt->mtx);
3482 TAILQ_INIT(&hpkt->queue);
3483 hpkt->busy = 0;
3484 device_set_ivars(dev, hpkt);
3485 ctlr->allocate = ata_promise_mio_allocate;
3486 ctlr->reset = ata_promise_mio_reset;
3487 ctlr->dmainit = ata_promise_mio_dmainit;
3488 ctlr->setmode = ata_promise_setmode;
3489 ctlr->channels = 4;
3490 return 0;
3491 }
3492
3493 /* mio type controllers need an interrupt intercept */
3494 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3495 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3496 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) {
3497 device_printf(dev, "unable to setup interrupt\n");
3498 goto failnfree;
3499 }
3500
3501 switch (ctlr->chip->cfg2) {
3502 case PRPATA:
3503 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3504 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3505 goto sata150;
3506 case PRCMBO:
3507 ctlr->channels = 3;
3508 goto sata150;
3509 case PRSATA:
3510 ctlr->channels = 4;
3511 sata150:
3512 fake_reg = 0x60;
3513 stat_reg = 0x6c;
3514 break;
3515
3516 case PRCMBO2:
3517 ctlr->channels = 3;
3518 goto sataii;
3519 case PRSATA2:
3520 default:
3521 ctlr->channels = 4;
3522 sataii:
3523 fake_reg = 0x54;
3524 stat_reg = 0x60;
3525 break;
3526 }
3527
3528 /* prime fake interrupt register */
3529 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3530
3531 /* clear SATA status */
3532 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3533
3534 ctlr->allocate = ata_promise_mio_allocate;
3535 ctlr->reset = ata_promise_mio_reset;
3536 ctlr->dmainit = ata_promise_mio_dmainit;
3537 ctlr->setmode = ata_promise_mio_setmode;
3538
3539 return 0;
3540 }
3541
3542 failnfree:
3543 if (ctlr->r_res2)
3544 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3545 if (ctlr->r_res1)
3546 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3547 return ENXIO;
3548 }
3549
3550 static int
3551 ata_promise_allocate(device_t dev)
3552 {
3553 struct ata_channel *ch = device_get_softc(dev);
3554
3555 if (ata_pci_allocate(dev))
3556 return ENXIO;
3557
3558 ch->hw.status = ata_promise_status;
3559 return 0;
3560 }
3561
3562 static int
3563 ata_promise_status(device_t dev)
3564 {
3565 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3566 struct ata_channel *ch = device_get_softc(dev);
3567
3568 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3569 return ata_pci_status(dev);
3570 }
3571 return 0;
3572 }
3573
3574 static int
3575 ata_promise_dmastart(device_t dev)
3576 {
3577 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3578 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3579 struct ata_device *atadev = device_get_softc(dev);
3580
3581 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3582 ATA_OUTB(ctlr->r_res1, 0x11,
3583 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3584 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3585 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3586 (ch->dma->cur_iosize >> 1));
3587 }
3588 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3589 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3590 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3591 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3592 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3593 ATA_BMCMD_START_STOP);
3594 ch->flags |= ATA_DMA_ACTIVE;
3595 return 0;
3596 }
3597
3598 static int
3599 ata_promise_dmastop(device_t dev)
3600 {
3601 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3602 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3603 struct ata_device *atadev = device_get_softc(dev);
3604 int error;
3605
3606 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3607 ATA_OUTB(ctlr->r_res1, 0x11,
3608 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3609 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3610 }
3611 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3612 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3613 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3614 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3615 ch->flags &= ~ATA_DMA_ACTIVE;
3616 return error;
3617 }
3618
3619 static void
3620 ata_promise_dmareset(device_t dev)
3621 {
3622 struct ata_channel *ch = device_get_softc(dev);
3623
3624 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3625 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3626 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3627 ch->flags &= ~ATA_DMA_ACTIVE;
3628 }
3629
3630 static void
3631 ata_promise_dmainit(device_t dev)
3632 {
3633 struct ata_channel *ch = device_get_softc(dev);
3634
3635 ata_dmainit(dev);
3636 if (ch->dma) {
3637 ch->dma->start = ata_promise_dmastart;
3638 ch->dma->stop = ata_promise_dmastop;
3639 ch->dma->reset = ata_promise_dmareset;
3640 }
3641 }
3642
3643 static void
3644 ata_promise_setmode(device_t dev, int mode)
3645 {
3646 device_t gparent = GRANDPARENT(dev);
3647 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3648 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3649 struct ata_device *atadev = device_get_softc(dev);
3650 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3651 int error;
3652 u_int32_t timings[][2] = {
3653 /* PROLD PRNEW mode */
3654 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3655 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3656 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3657 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3658 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3659 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3660 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3661 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3662 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3663 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3664 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3665 { 0, 0x00424ef6 }, /* UDMA 3 */
3666 { 0, 0x004127f3 }, /* UDMA 4 */
3667 { 0, 0x004127f3 } /* UDMA 5 */
3668 };
3669
3670 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3671
3672 switch (ctlr->chip->cfg1) {
3673 case PROLD:
3674 case PRNEW:
3675 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3676 (ch->unit ? 1 << 11 : 1 << 10))) {
3677 ata_print_cable(dev, "controller");
3678 mode = ATA_UDMA2;
3679 }
3680 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3681 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3682 break;
3683
3684 case PRTX:
3685 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3686 if (mode > ATA_UDMA2 &&
3687 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3688 ata_print_cable(dev, "controller");
3689 mode = ATA_UDMA2;
3690 }
3691 break;
3692
3693 case PRMIO:
3694 if (mode > ATA_UDMA2 &&
3695 (ATA_INL(ctlr->r_res2,
3696 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3697 (ch->unit << 7)) & 0x01000000)) {
3698 ata_print_cable(dev, "controller");
3699 mode = ATA_UDMA2;
3700 }
3701 break;
3702 }
3703
3704 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3705
3706 if (bootverbose)
3707 device_printf(dev, "%ssetting %s on %s chip\n",
3708 (error) ? "FAILURE " : "",
3709 ata_mode2str(mode), ctlr->chip->text);
3710 if (!error) {
3711 if (ctlr->chip->cfg1 < PRTX)
3712 pci_write_config(gparent, 0x60 + (devno << 2),
3713 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3714 atadev->mode = mode;
3715 }
3716 return;
3717 }
3718
3719 static int
3720 ata_promise_tx2_allocate(device_t dev)
3721 {
3722 struct ata_channel *ch = device_get_softc(dev);
3723
3724 if (ata_pci_allocate(dev))
3725 return ENXIO;
3726
3727 ch->hw.status = ata_promise_tx2_status;
3728 return 0;
3729 }
3730
3731 static int
3732 ata_promise_tx2_status(device_t dev)
3733 {
3734 struct ata_channel *ch = device_get_softc(dev);
3735
3736 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3737 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3738 return ata_pci_status(dev);
3739 }
3740 return 0;
3741 }
3742
3743 static int
3744 ata_promise_mio_allocate(device_t dev)
3745 {
3746 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3747 struct ata_channel *ch = device_get_softc(dev);
3748 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3749 int i;
3750
3751 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3752 ch->r_io[i].res = ctlr->r_res2;
3753 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3754 }
3755 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3756 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3757 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3758 ata_default_registers(dev);
3759 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3760 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3761 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3762 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3763 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3764 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3765 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3766 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3767 ch->flags |= ATA_NO_SLAVE;
3768 }
3769 ch->flags |= ATA_USE_16BIT;
3770
3771 ata_generic_hw(dev);
3772 if (ctlr->chip->cfg2 & PRSX4X) {
3773 ch->hw.command = ata_promise_sx4_command;
3774 }
3775 else {
3776 ch->hw.command = ata_promise_mio_command;
3777 ch->hw.status = ata_promise_mio_status;
3778 }
3779 return 0;
3780 }
3781
3782 static void
3783 ata_promise_mio_intr(void *data)
3784 {
3785 struct ata_pci_controller *ctlr = data;
3786 struct ata_channel *ch;
3787 u_int32_t vector;
3788 int unit, fake_reg;
3789
3790 switch (ctlr->chip->cfg2) {
3791 case PRPATA:
3792 case PRCMBO:
3793 case PRSATA:
3794 fake_reg = 0x60;
3795 break;
3796 case PRCMBO2:
3797 case PRSATA2:
3798 default:
3799 fake_reg = 0x54;
3800 break;
3801 }
3802
3803 /*
3804 * since reading interrupt status register on early "mio" chips
3805 * clears the status bits we cannot read it for each channel later on
3806 * in the generic interrupt routine.
3807 * store the bits in an unused register in the chip so we can read
3808 * it from there safely to get around this "feature".
3809 */
3810 vector = ATA_INL(ctlr->r_res2, 0x040);
3811 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3812 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3813
3814 for (unit = 0; unit < ctlr->channels; unit++) {
3815 if ((ch = ctlr->interrupt[unit].argument))
3816 ctlr->interrupt[unit].function(ch);
3817 }
3818
3819 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3820 }
3821
3822 static int
3823 ata_promise_mio_status(device_t dev)
3824 {
3825 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3826 struct ata_channel *ch = device_get_softc(dev);
3827 struct ata_connect_task *tp;
3828 u_int32_t fake_reg, stat_reg, vector, status;
3829
3830 switch (ctlr->chip->cfg2) {
3831 case PRPATA:
3832 case PRCMBO:
3833 case PRSATA:
3834 fake_reg = 0x60;
3835 stat_reg = 0x6c;
3836 break;
3837 case PRCMBO2:
3838 case PRSATA2:
3839 default:
3840 fake_reg = 0x54;
3841 stat_reg = 0x60;
3842 break;
3843 }
3844
3845 /* read and acknowledge interrupt */
3846 vector = ATA_INL(ctlr->r_res2, fake_reg);
3847
3848 /* read and clear interface status */
3849 status = ATA_INL(ctlr->r_res2, stat_reg);
3850 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3851
3852 /* check for and handle disconnect events */
3853 if ((status & (0x00000001 << ch->unit)) &&
3854 (tp = (struct ata_connect_task *)
3855 kmalloc(sizeof(struct ata_connect_task),
3856 M_ATA, M_INTWAIT | M_ZERO))) {
3857
3858 if (bootverbose)
3859 device_printf(ch->dev, "DISCONNECT requested\n");
3860 tp->action = ATA_C_DETACH;
3861 tp->dev = ch->dev;
3862 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3863 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3864 }
3865
3866 /* check for and handle connect events */
3867 if ((status & (0x00000010 << ch->unit)) &&
3868 (tp = (struct ata_connect_task *)
3869 kmalloc(sizeof(struct ata_connect_task),
3870 M_ATA, M_INTWAIT | M_ZERO))) {
3871
3872 if (bootverbose)
3873 device_printf(ch->dev, "CONNECT requested\n");
3874 tp->action = ATA_C_ATTACH;
3875 tp->dev = ch->dev;
3876 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3877 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3878 }
3879
3880 /* do we have any device action ? */
3881 return (vector & (1 << (ch->unit + 1)));
3882 }
3883
3884 static int
3885 ata_promise_mio_command(struct ata_request *request)
3886 {
3887 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3888 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3889 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3890
3891 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3892
3893 /* XXX SOS add ATAPI commands support later */
3894 switch (request->u.ata.command) {
3895 default:
3896 return ata_generic_command(request);
3897
3898 case ATA_READ_DMA:
3899 case ATA_READ_DMA48:
3900 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3901 break;
3902
3903 case ATA_WRITE_DMA:
3904 case ATA_WRITE_DMA48:
3905 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3906 break;
3907 }
3908 wordp[1] = htole32(ch->dma->sg_bus);
3909 wordp[2] = 0;
3910 ata_promise_apkt((u_int8_t*)wordp, request);
3911
3912 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3913 return 0;
3914 }
3915
3916 static void
3917 ata_promise_mio_reset(device_t dev)
3918 {
3919 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3920 struct ata_channel *ch = device_get_softc(dev);
3921 struct ata_promise_sx4 *hpktp;
3922
3923 switch (ctlr->chip->cfg2) {
3924 case PRSX4X:
3925
3926 /* softreset channel ATA module */
3927 hpktp = device_get_ivars(ctlr->dev);
3928 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3929 ata_udelay(1000);
3930 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3931 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3932 ~0x00003f9f) | (ch->unit + 1));
3933
3934 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3935 spin_lock_wr(&hpktp->mtx);
3936 ATA_OUTL(ctlr->r_res2, 0xc012c,
3937 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3938 DELAY(10);
3939 ATA_OUTL(ctlr->r_res2, 0xc012c,
3940 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3941 hpktp->busy = 0;
3942 spin_unlock_wr(&hpktp->mtx);
3943 ata_generic_reset(dev);
3944 break;
3945
3946 case PRPATA:
3947 case PRCMBO:
3948 case PRSATA:
3949 if ((ctlr->chip->cfg2 == PRSATA) ||
3950 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3951
3952 /* mask plug/unplug intr */
3953 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3954 }
3955
3956 /* softreset channels ATA module */
3957 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3958 ata_udelay(10000);
3959 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3960 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3961 ~0x00003f9f) | (ch->unit + 1));
3962
3963 if ((ctlr->chip->cfg2 == PRSATA) ||
3964 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3965
3966 if (ata_sata_phy_reset(dev))
3967 ata_generic_reset(dev);
3968
3969 /* reset and enable plug/unplug intr */
3970 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3971 }
3972 else
3973 ata_generic_reset(dev);
3974 break;
3975
3976 case PRCMBO2:
3977 case PRSATA2:
3978 if ((ctlr->chip->cfg2 == PRSATA2) ||
3979 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3980 /* set portmultiplier port */
3981 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3982
3983 /* mask plug/unplug intr */
3984 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3985 }
3986
3987 /* softreset channels ATA module */
3988 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3989 ata_udelay(10000);
3990 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3991 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3992 ~0x00003f9f) | (ch->unit + 1));
3993
3994 if ((ctlr->chip->cfg2 == PRSATA2) ||
3995 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3996
3997 /* set PHY mode to "improved" */
3998 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3999 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
4000 ~0x00000003) | 0x00000001);
4001
4002 if (ata_sata_phy_reset(dev))
4003 ata_generic_reset(dev);
4004
4005 /* reset and enable plug/unplug intr */
4006 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
4007
4008 /* set portmultiplier port */
4009 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
4010 }
4011 else
4012 ata_generic_reset(dev);
4013 break;
4014
4015 }
4016 }
4017
4018 static void
4019 ata_promise_mio_dmainit(device_t dev)
4020 {
4021 /* note start and stop are not used here */
4022 ata_dmainit(dev);
4023 }
4024
4025 static void
4026 ata_promise_mio_setmode(device_t dev, int mode)
4027 {
4028 device_t gparent = GRANDPARENT(dev);
4029 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4030 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4031
4032 if ( (ctlr->chip->cfg2 == PRSATA) ||
4033 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
4034 (ctlr->chip->cfg2 == PRSATA2) ||
4035 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
4036 ata_sata_setmode(dev, mode);
4037 else
4038 ata_promise_setmode(dev, mode);
4039 }
4040
4041 static void
4042 ata_promise_sx4_intr(void *data)
4043 {
4044 struct ata_pci_controller *ctlr = data;
4045 struct ata_channel *ch;
4046 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
4047 int unit;
4048
4049 for (unit = 0; unit < ctlr->channels; unit++) {
4050 if (vector & (1 << (unit + 1)))
4051 if ((ch = ctlr->interrupt[unit].argument))
4052 ctlr->interrupt[unit].function(ch);
4053 if (vector & (1 << (unit + 5)))
4054 if ((ch = ctlr->interrupt[unit].argument))
4055 ata_promise_queue_hpkt(ctlr,
4056 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4057 ATA_PDC_HPKT_OFFSET));
4058 if (vector & (1 << (unit + 9))) {
4059 ata_promise_next_hpkt(ctlr);
4060 if ((ch = ctlr->interrupt[unit].argument))
4061 ctlr->interrupt[unit].function(ch);
4062 }
4063 if (vector & (1 << (unit + 13))) {
4064 ata_promise_next_hpkt(ctlr);
4065 if ((ch = ctlr->interrupt[unit].argument))
4066 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4067 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4068 ATA_PDC_APKT_OFFSET));
4069 }
4070 }
4071 }
4072
4073 static int
4074 ata_promise_sx4_command(struct ata_request *request)
4075 {
4076 device_t gparent = GRANDPARENT(request->dev);
4077 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4078 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4079 struct ata_dma_prdentry *prd = ch->dma->sg;
4080 caddr_t window = rman_get_virtual(ctlr->r_res1);
4081 u_int32_t *wordp;
4082 int i, idx, length = 0;
4083
4084 /* XXX SOS add ATAPI commands support later */
4085 switch (request->u.ata.command) {
4086
4087 default:
4088 return -1;
4089
4090 case ATA_ATA_IDENTIFY:
4091 case ATA_READ:
4092 case ATA_READ48:
4093 case ATA_READ_MUL:
4094 case ATA_READ_MUL48:
4095 case ATA_WRITE:
4096 case ATA_WRITE48:
4097 case ATA_WRITE_MUL:
4098 case ATA_WRITE_MUL48:
4099 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4100 return ata_generic_command(request);
4101
4102 case ATA_SETFEATURES:
4103 case ATA_FLUSHCACHE:
4104 case ATA_FLUSHCACHE48:
4105 case ATA_SLEEP:
4106 case ATA_SET_MULTI:
4107 wordp = (u_int32_t *)
4108 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4109 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4110 wordp[1] = 0;
4111 wordp[2] = 0;
4112 ata_promise_apkt((u_int8_t *)wordp, request);
4113 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4114 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4115 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4116 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4117 return 0;
4118
4119 case ATA_READ_DMA:
4120 case ATA_READ_DMA48:
4121 case ATA_WRITE_DMA:
4122 case ATA_WRITE_DMA48:
4123 wordp = (u_int32_t *)
4124 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4125 i = idx = 0;
4126 do {
4127 wordp[idx++] = prd[i].addr;
4128 wordp[idx++] = prd[i].count;
4129 length += (prd[i].count & ~ATA_DMA_EOT);
4130 } while (!(prd[i++].count & ATA_DMA_EOT));
4131
4132 wordp = (u_int32_t *)
4133 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4134 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4135 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4136
4137 wordp = (u_int32_t *)
4138 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4139 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4140 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4141
4142 wordp = (u_int32_t *)
4143 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4144 if (request->flags & ATA_R_READ)
4145 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4146 if (request->flags & ATA_R_WRITE)
4147 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4148 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4149 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4150 wordp[3] = 0;
4151
4152 wordp = (u_int32_t *)
4153 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4154 if (request->flags & ATA_R_READ)
4155 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4156 if (request->flags & ATA_R_WRITE)
4157 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4158 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4159 wordp[2] = 0;
4160 ata_promise_apkt((u_int8_t *)wordp, request);
4161 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4162
4163 if (request->flags & ATA_R_READ) {
4164 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4165 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4166 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4167 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4168 }
4169 if (request->flags & ATA_R_WRITE) {
4170 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4171 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4172 ata_promise_queue_hpkt(ctlr,
4173 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4174 }
4175 return 0;
4176 }
4177 }
4178
4179 static int
4180 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4181 {
4182 struct ata_device *atadev = device_get_softc(request->dev);
4183 int i = 12;
4184
4185 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4186 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4187 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4188 bytep[i++] = ATA_A_4BIT;
4189
4190 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4191 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4192 bytep[i++] = request->u.ata.feature >> 8;
4193 bytep[i++] = request->u.ata.feature;
4194 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4195 bytep[i++] = request->u.ata.count >> 8;
4196 bytep[i++] = request->u.ata.count;
4197 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4198 bytep[i++] = request->u.ata.lba >> 24;
4199 bytep[i++] = request->u.ata.lba;
4200 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4201 bytep[i++] = request->u.ata.lba >> 32;
4202 bytep[i++] = request->u.ata.lba >> 8;
4203 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4204 bytep[i++] = request->u.ata.lba >> 40;
4205 bytep[i++] = request->u.ata.lba >> 16;
4206 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4207 bytep[i++] = ATA_D_LBA | atadev->unit;
4208 }
4209 else {
4210 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4211 bytep[i++] = request->u.ata.feature;
4212 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4213 bytep[i++] = request->u.ata.count;
4214 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4215 bytep[i++] = request->u.ata.lba;
4216 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4217 bytep[i++] = request->u.ata.lba >> 8;
4218 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4219 bytep[i++] = request->u.ata.lba >> 16;
4220 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4221 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4222 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4223 }
4224 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4225 bytep[i++] = request->u.ata.command;
4226 return i;
4227 }
4228
4229 static void
4230 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4231 {
4232 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4233
4234 spin_lock_wr(&hpktp->mtx);
4235 if (hpktp->busy) {
4236 struct host_packet *hp =
4237 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO);
4238 hp->addr = hpkt;
4239 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4240 }
4241 else {
4242 hpktp->busy = 1;
4243 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4244 }
4245 spin_unlock_wr(&hpktp->mtx);
4246 }
4247
4248 static void
4249 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4250 {
4251 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4252 struct host_packet *hp;
4253
4254 spin_lock_wr(&hpktp->mtx);
4255 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4256 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4257 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4258 kfree(hp, M_TEMP);
4259 }
4260 else
4261 hpktp->busy = 0;
4262 spin_unlock_wr(&hpktp->mtx);
4263 }
4264
4265
4266 /*
4267 * ServerWorks chipset support functions
4268 */
4269 int
4270 ata_serverworks_ident(device_t dev)
4271 {
4272 struct ata_pci_controller *ctlr = device_get_softc(dev);
4273 struct ata_chip_id *idx;
4274 static struct ata_chip_id ids[] =
4275 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4276 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4277 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4278 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4279 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4280 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4281 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4282 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4283 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4284 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4285 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4286 { 0, 0, 0, 0, 0, 0}};
4287 char buffer[64];
4288
4289 if (!(idx = ata_match_chip(dev, ids)))
4290 return ENXIO;
4291
4292 ksprintf(buffer, "ServerWorks %s %s controller",
4293 idx->text, ata_mode2str(idx->max_dma));
4294 device_set_desc_copy(dev, buffer);
4295 ctlr->chip = idx;
4296 ctlr->chipinit = ata_serverworks_chipinit;
4297 return 0;
4298 }
4299
4300 static int
4301 ata_serverworks_chipinit(device_t dev)
4302 {
4303 struct ata_pci_controller *ctlr = device_get_softc(dev);
4304
4305 if (ata_setup_interrupt(dev))
4306 return ENXIO;
4307
4308 if (ctlr->chip->cfg1 == SWKSMIO) {
4309 ctlr->r_type2 = SYS_RES_MEMORY;
4310 ctlr->r_rid2 = PCIR_BAR(5);
4311 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4312 &ctlr->r_rid2, RF_ACTIVE)))
4313 return ENXIO;
4314
4315 ctlr->channels = ctlr->chip->cfg2;
4316 ctlr->allocate = ata_serverworks_allocate;
4317 ctlr->setmode = ata_sata_setmode;
4318 return 0;
4319 }
4320 else if (ctlr->chip->cfg1 == SWKS33) {
4321 device_t *children;
4322 int nchildren, i;
4323
4324 /* locate the ISA part in the southbridge and enable UDMA33 */
4325 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4326 for (i = 0; i < nchildren; i++) {
4327 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4328 pci_write_config(children[i], 0x64,
4329 (pci_read_config(children[i], 0x64, 4) &
4330 ~0x00002000) | 0x00004000, 4);
4331 break;
4332 }
4333 }
4334 kfree(children, M_TEMP);
4335 }
4336 }
4337 else {
4338 pci_write_config(dev, 0x5a,
4339 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4340 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4341 }
4342 ctlr->setmode = ata_serverworks_setmode;
4343 return 0;
4344 }
4345
4346 static int
4347 ata_serverworks_allocate(device_t dev)
4348 {
4349 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4350 struct ata_channel *ch = device_get_softc(dev);
4351 int ch_offset;
4352 int i;
4353
4354 ch_offset = ch->unit * 0x100;
4355
4356 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4357 ch->r_io[i].res = ctlr->r_res2;
4358
4359 /* setup ATA registers */
4360 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4361 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4362 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4363 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4364 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4365 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4366 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4367 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4368 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4369 ata_default_registers(dev);
4370
4371 /* setup DMA registers */
4372 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4373 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4374 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4375
4376 /* setup SATA registers */
4377 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4378 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4379 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4380
4381 ch->flags |= ATA_NO_SLAVE;
4382 ata_pci_hw(dev);
4383 return 0;
4384 }
4385
4386 static void
4387 ata_serverworks_setmode(device_t dev, int mode)
4388 {
4389 device_t gparent = GRANDPARENT(dev);
4390 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4391 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4392 struct ata_device *atadev = device_get_softc(dev);
4393 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4394 int offset = (devno ^ 0x01) << 3;
4395 int error;
4396 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4397 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4398 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4399
4400 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4401
4402 mode = ata_check_80pin(dev, mode);
4403
4404 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4405
4406 if (bootverbose)
4407 device_printf(dev, "%ssetting %s on %s chip\n",
4408 (error) ? "FAILURE " : "",
4409 ata_mode2str(mode), ctlr->chip->text);
4410 if (!error) {
4411 if (mode >= ATA_UDMA0) {
4412 pci_write_config(gparent, 0x56,
4413 (pci_read_config(gparent, 0x56, 2) &
4414 ~(0xf << (devno << 2))) |
4415 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4416 pci_write_config(gparent, 0x54,
4417 pci_read_config(gparent, 0x54, 1) |
4418 (0x01 << devno), 1);
4419 pci_write_config(gparent, 0x44,
4420 (pci_read_config(gparent, 0x44, 4) &
4421 ~(0xff << offset)) |
4422 (dmatimings[2] << offset), 4);
4423 }
4424 else if (mode >= ATA_WDMA0) {
4425 pci_write_config(gparent, 0x54,
4426 pci_read_config(gparent, 0x54, 1) &
4427 ~(0x01 << devno), 1);
4428 pci_write_config(gparent, 0x44,
4429 (pci_read_config(gparent, 0x44, 4) &
4430 ~(0xff << offset)) |
4431 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4432 }
4433 else
4434 pci_write_config(gparent, 0x54,
4435 pci_read_config(gparent, 0x54, 1) &
4436 ~(0x01 << devno), 1);
4437
4438 pci_write_config(gparent, 0x40,
4439 (pci_read_config(gparent, 0x40, 4) &
4440 ~(0xff << offset)) |
4441 (piotimings[ata_mode2idx(mode)] << offset), 4);
4442 atadev->mode = mode;
4443 }
4444 }
4445
4446
4447 /*
4448 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4449 */
4450 int
4451 ata_sii_ident(device_t dev)
4452 {
4453 struct ata_pci_controller *ctlr = device_get_softc(dev);
4454 struct ata_chip_id *idx;
4455 static struct ata_chip_id ids[] =
4456 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4457 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4458 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4459 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4460 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4461 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4462 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4463 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4464 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4465 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4466 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4467 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4468 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4469 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4470 { 0, 0, 0, 0, 0, 0}};
4471 char buffer[64];
4472
4473 if (!(idx = ata_match_chip(dev, ids)))
4474 return ENXIO;
4475
4476 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4477 device_set_desc_copy(dev, buffer);
4478 ctlr->chip = idx;
4479 ctlr->chipinit = ata_sii_chipinit;
4480 return 0;
4481 }
4482
4483 static int
4484 ata_sii_chipinit(device_t dev)
4485 {
4486 struct ata_pci_controller *ctlr = device_get_softc(dev);
4487
4488 if (ata_setup_interrupt(dev))
4489 return ENXIO;
4490
4491 switch (ctlr->chip->cfg1) {
4492 case SIIPRBIO:
4493 ctlr->r_type1 = SYS_RES_MEMORY;
4494 ctlr->r_rid1 = PCIR_BAR(0);
4495 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4496 &ctlr->r_rid1, RF_ACTIVE)))
4497 return ENXIO;
4498
4499 ctlr->r_rid2 = PCIR_BAR(2);
4500 ctlr->r_type2 = SYS_RES_MEMORY;
4501 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4502 &ctlr->r_rid2, RF_ACTIVE))){
4503 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4504 return ENXIO;
4505 }
4506 ctlr->allocate = ata_siiprb_allocate;
4507 ctlr->reset = ata_siiprb_reset;
4508 ctlr->dmainit = ata_siiprb_dmainit;
4509 ctlr->setmode = ata_sata_setmode;
4510 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4511
4512 /* reset controller */
4513 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4514 DELAY(10000);
4515 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4516
4517 /* enable PCI interrupt */
4518 pci_write_config(dev, PCIR_COMMAND,
4519 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4520 break;
4521
4522 case SIIMEMIO:
4523 ctlr->r_type2 = SYS_RES_MEMORY;
4524 ctlr->r_rid2 = PCIR_BAR(5);
4525 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4526 &ctlr->r_rid2, RF_ACTIVE)))
4527 return ENXIO;
4528
4529 if (ctlr->chip->cfg2 & SIISETCLK) {
4530 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4531 pci_write_config(dev, 0x8a,
4532 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4533 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4534 device_printf(dev, "%s could not set ATA133 clock\n",
4535 ctlr->chip->text);
4536 }
4537
4538 /* if we have 4 channels enable the second set */
4539 if (ctlr->chip->cfg2 & SII4CH) {
4540 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4541 ctlr->channels = 4;
4542 }
4543
4544 /* dont block interrupts from any channel */
4545 pci_write_config(dev, 0x48,
4546 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4547
4548 /* enable PCI interrupt as BIOS might not */
4549 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4550
4551 ctlr->allocate = ata_sii_allocate;
4552 if (ctlr->chip->max_dma >= ATA_SA150) {
4553 ctlr->reset = ata_sii_reset;
4554 ctlr->setmode = ata_sata_setmode;
4555 }
4556 else
4557 ctlr->setmode = ata_sii_setmode;
4558 break;
4559
4560 default:
4561 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4562 device_printf(dev, "HW has secondary channel disabled\n");
4563 ctlr->channels = 1;
4564 }
4565
4566 /* enable interrupt as BIOS might not */
4567 pci_write_config(dev, 0x71, 0x01, 1);
4568
4569 ctlr->allocate = ata_cmd_allocate;
4570 ctlr->setmode = ata_cmd_setmode;
4571 break;
4572 }
4573 return 0;
4574 }
4575
4576 static int
4577 ata_cmd_allocate(device_t dev)
4578 {
4579 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4580 struct ata_channel *ch = device_get_softc(dev);
4581
4582 /* setup the usual register normal pci style */
4583 if (ata_pci_allocate(dev))
4584 return ENXIO;
4585
4586 if (ctlr->chip->cfg2 & SIIINTR)
4587 ch->hw.status = ata_cmd_status;
4588
4589 return 0;
4590 }
4591
4592 static int
4593 ata_cmd_status(device_t dev)
4594 {
4595 struct ata_channel *ch = device_get_softc(dev);
4596 u_int8_t reg71;
4597
4598 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4599 (ch->unit ? 0x08 : 0x04))) {
4600 pci_write_config(device_get_parent(ch->dev), 0x71,
4601 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4602 return ata_pci_status(dev);
4603 }
4604 return 0;
4605 }
4606
4607 static void
4608 ata_cmd_setmode(device_t dev, int mode)
4609 {
4610 device_t gparent = GRANDPARENT(dev);
4611 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4612 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4613 struct ata_device *atadev = device_get_softc(dev);
4614 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4615 int error;
4616
4617 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4618
4619 mode = ata_check_80pin(dev, mode);
4620
4621 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4622
4623 if (bootverbose)
4624 device_printf(dev, "%ssetting %s on %s chip\n",
4625 (error) ? "FAILURE " : "",
4626 ata_mode2str(mode), ctlr->chip->text);
4627 if (!error) {
4628 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4629 int ureg = ch->unit ? 0x7b : 0x73;
4630
4631 if (mode >= ATA_UDMA0) {
4632 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4633 { 0x11, 0x42 }, { 0x25, 0x8a },
4634 { 0x15, 0x4a }, { 0x05, 0x0a } };
4635
4636 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4637
4638 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4639 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4640 pci_write_config(gparent, ureg, umode, 1);
4641 }
4642 else if (mode >= ATA_WDMA0) {
4643 int dmatimings[] = { 0x87, 0x32, 0x3f };
4644
4645 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4646 pci_write_config(gparent, ureg,
4647 pci_read_config(gparent, ureg, 1) &
4648 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4649 }
4650 else {
4651 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4652 pci_write_config(gparent, treg,
4653 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4654 pci_write_config(gparent, ureg,
4655 pci_read_config(gparent, ureg, 1) &
4656 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4657 }
4658 atadev->mode = mode;
4659 }
4660 }
4661
4662 static int
4663 ata_sii_allocate(device_t dev)
4664 {
4665 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4666 struct ata_channel *ch = device_get_softc(dev);
4667 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4668 int i;
4669
4670 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4671 ch->r_io[i].res = ctlr->r_res2;
4672 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4673 }
4674 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4675 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4676 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4677 ata_default_registers(dev);
4678
4679 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4680 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4681 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4682 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4683 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4684 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4685
4686 if (ctlr->chip->max_dma >= ATA_SA150) {
4687 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4688 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4689 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4690 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4691 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4692 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4693 ch->flags |= ATA_NO_SLAVE;
4694
4695 /* enable PHY state change interrupt */
4696 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4697 }
4698
4699 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4700 /* work around errata in early chips */
4701 ch->dma->boundary = 16 * DEV_BSIZE;
4702 ch->dma->segsize = 15 * DEV_BSIZE;
4703 }
4704
4705 ata_pci_hw(dev);
4706 ch->hw.status = ata_sii_status;
4707 return 0;
4708 }
4709
4710 static int
4711 ata_sii_status(device_t dev)
4712 {
4713 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4714 struct ata_channel *ch = device_get_softc(dev);
4715 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4716 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4717
4718 /* do we have any PHY events ? */
4719 if (ctlr->chip->max_dma >= ATA_SA150 &&
4720 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4721 ata_sata_phy_check_events(dev);
4722
4723 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4724 return ata_pci_status(dev);
4725 else
4726 return 0;
4727 }
4728
4729 static void
4730 ata_sii_reset(device_t dev)
4731 {
4732 if (ata_sata_phy_reset(dev))
4733 ata_generic_reset(dev);
4734 }
4735
4736 static void
4737 ata_sii_setmode(device_t dev, int mode)
4738 {
4739 device_t gparent = GRANDPARENT(dev);
4740 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4741 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4742 struct ata_device *atadev = device_get_softc(dev);
4743 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4744 int mreg = ch->unit ? 0x84 : 0x80;
4745 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4746 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4747 int error;
4748
4749 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4750
4751 if (ctlr->chip->cfg2 & SIISETCLK) {
4752 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4753 (ch->unit ? 0x02 : 0x01))) {
4754 ata_print_cable(dev, "controller");
4755 mode = ATA_UDMA2;
4756 }
4757 }
4758 else
4759 mode = ata_check_80pin(dev, mode);
4760
4761 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4762
4763 if (bootverbose)
4764 device_printf(dev, "%ssetting %s on %s chip\n",
4765 (error) ? "FAILURE " : "",
4766 ata_mode2str(mode), ctlr->chip->text);
4767 if (error)
4768 return;
4769
4770 if (mode >= ATA_UDMA0) {
4771 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4772 u_int8_t ureg = 0xac + rego;
4773
4774 pci_write_config(gparent, mreg,
4775 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4776 pci_write_config(gparent, ureg,
4777 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4778 udmatimings[mode & ATA_MODE_MASK], 1);
4779
4780 }
4781 else if (mode >= ATA_WDMA0) {
4782 u_int8_t dreg = 0xa8 + rego;
4783 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4784
4785 pci_write_config(gparent, mreg,
4786 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4787 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4788
4789 }
4790 else {
4791 u_int8_t preg = 0xa4 + rego;
4792 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4793
4794 pci_write_config(gparent, mreg,
4795 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4796 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4797 }
4798 atadev->mode = mode;
4799 }
4800
4801 struct ata_siiprb_dma_prdentry {
4802 u_int64_t addr;
4803 u_int32_t count;
4804 u_int32_t control;
4805 } __packed;
4806
4807 struct ata_siiprb_ata_command {
4808 u_int32_t reserved0;
4809 struct ata_siiprb_dma_prdentry prd[126];
4810 } __packed;
4811
4812 struct ata_siiprb_atapi_command {
4813 u_int8_t cdb[16];
4814 struct ata_siiprb_dma_prdentry prd[125];
4815 } __packed;
4816
4817 struct ata_siiprb_command {
4818 u_int16_t control;
4819 u_int16_t protocol_override;
4820 u_int32_t transfer_count;
4821 u_int8_t fis[20];
4822 union {
4823 struct ata_siiprb_ata_command ata;
4824 struct ata_siiprb_atapi_command atapi;
4825 } u;
4826 } __packed;
4827
4828 static int
4829 ata_siiprb_allocate(device_t dev)
4830 {
4831 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4832 struct ata_channel *ch = device_get_softc(dev);
4833 int offset = ch->unit * 0x2000;
4834
4835 /* set the SATA resources */
4836 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4837 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4838 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4839 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4840 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4841 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4842 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4843 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4844
4845 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4846 ch->hw.end_transaction = ata_siiprb_end_transaction;
4847 ch->hw.status = ata_siiprb_status;
4848 ch->hw.command = NULL; /* not used here */
4849 return 0;
4850 }
4851
4852 static int
4853 ata_siiprb_status(device_t dev)
4854 {
4855 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4856 struct ata_channel *ch = device_get_softc(dev);
4857 int offset = ch->unit * 0x2000;
4858
4859 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) {
4860 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4861
4862 /* do we have any PHY events ? */
4863 ata_sata_phy_check_events(dev);
4864
4865 /* clear interrupt(s) */
4866 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4867
4868 /* do we have any device action ? */
4869 return (istatus & 0x00000001);
4870 }
4871 return 0;
4872 }
4873
4874 static int
4875 ata_siiprb_begin_transaction(struct ata_request *request)
4876 {
4877 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4878 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4879 struct ata_siiprb_command *prb;
4880 int offset = ch->unit * 0x2000;
4881 u_int64_t prb_bus;
4882 int tag = 0, dummy;
4883
4884 /* check for 48 bit access and convert if needed */
4885 ata_modify_if_48bit(request);
4886
4887 /* get a piece of the workspace for this request */
4888 prb = (struct ata_siiprb_command *)
4889 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4890
4891 /* set basic prd options ata/atapi etc etc */
4892 bzero(prb, sizeof(struct ata_siiprb_command));
4893
4894 /* setup the FIS for this request */
4895 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4896 device_printf(request->dev, "setting up SATA FIS failed\n");
4897 request->result = EIO;
4898 return ATA_OP_FINISHED;
4899 }
4900
4901 /* if request moves data setup and load SG list */
4902 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4903 struct ata_siiprb_dma_prdentry *prd;
4904
4905 if (request->flags & ATA_R_ATAPI)
4906 prd = &prb->u.atapi.prd[0];
4907 else
4908 prd = &prb->u.ata.prd[0];
4909 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4910 request->flags & ATA_R_READ, prd, &dummy)) {
4911 device_printf(request->dev, "setting up DMA failed\n");
4912 request->result = EIO;
4913 return ATA_OP_FINISHED;
4914 }
4915 }
4916
4917 /* activate the prb */
4918 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4919 ATA_OUTL(ctlr->r_res2,
4920 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4921 ATA_OUTL(ctlr->r_res2,
4922 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4923
4924 /* start the timeout */
4925 callout_reset(&request->callout, request->timeout * hz,
4926 (timeout_t*)ata_timeout, request);
4927 return ATA_OP_CONTINUES;
4928 }
4929
4930 static int
4931 ata_siiprb_end_transaction(struct ata_request *request)
4932 {
4933 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4934 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4935 struct ata_siiprb_command *prb;
4936 int offset = ch->unit * 0x2000;
4937 int error, tag = 0;
4938
4939 /* kill the timeout */
4940 callout_stop(&request->callout);
4941
4942 prb = (struct ata_siiprb_command *)
4943 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4944
4945 /* if error status get details */
4946 request->status = prb->fis[2];
4947 if (request->status & ATA_S_ERROR)
4948 request->error = prb->fis[3];
4949
4950 /* update progress */
4951 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4952 if (request->flags & ATA_R_READ)
4953 request->donecount = prb->transfer_count;
4954 else
4955 request->donecount = request->bytecount;
4956 }
4957
4958 /* any controller errors flagged ? */
4959 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4960 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
4961 ata_cmd2str(request), error);
4962 }
4963
4964 /* release SG list etc */
4965 ch->dma->unload(ch->dev);
4966
4967 return ATA_OP_FINISHED;
4968 }
4969
4970 static void
4971 ata_siiprb_reset(device_t dev)
4972 {
4973 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4974 struct ata_channel *ch = device_get_softc(dev);
4975 int offset = ch->unit * 0x2000;
4976 struct ata_siiprb_command *prb;
4977 u_int64_t prb_bus;
4978 u_int32_t status, signature;
4979 int timeout, tag = 0;
4980
4981 /* reset channel HW */
4982 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
4983 DELAY(1000);
4984 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
4985 DELAY(10000);
4986
4987 /* poll for channel ready */
4988 for (timeout = 0; timeout < 1000; timeout++) {
4989 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000)
4990 break;
4991 DELAY(1000);
4992 }
4993 if (timeout >= 1000) {
4994 device_printf(ch->dev, "channel HW reset timeout reset failure\n");
4995 ch->devices = 0;
4996 goto finish;
4997 }
4998 if (bootverbose)
4999 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1);
5000
5001 /* reset phy */
5002 if (!ata_sata_phy_reset(dev)) {
5003 if (bootverbose)
5004 device_printf(ch->dev, "phy reset found no device\n");
5005 ch->devices = 0;
5006 goto finish;
5007 }
5008
5009 /* get a piece of the workspace for a soft reset request */
5010 prb = (struct ata_siiprb_command *)
5011 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5012 bzero(prb, sizeof(struct ata_siiprb_command));
5013 prb->control = htole16(0x0080);
5014
5015 /* activate the soft reset prb */
5016 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5017 ATA_OUTL(ctlr->r_res2,
5018 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5019 ATA_OUTL(ctlr->r_res2,
5020 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5021
5022 /* poll for channel ready */
5023 for (timeout = 0; timeout < 1000; timeout++) {
5024 DELAY(1000);
5025 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5026 break;
5027 }
5028 if (timeout >= 1000) {
5029 device_printf(ch->dev, "reset timeout - no device found\n");
5030 ch->devices = 0;
5031 goto finish;
5032 }
5033 if (bootverbose)
5034 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5035 timeout, status);
5036
5037 /* find out whats there */
5038 prb = (struct ata_siiprb_command *)
5039 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5040 signature =
5041 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5042 if (bootverbose)
5043 device_printf(ch->dev, "signature=%08x\n", signature);
5044 switch (signature) {
5045 case 0xeb140101:
5046 ch->devices = ATA_ATAPI_MASTER;
5047 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
5048 ch->devices = 0;
5049 break;
5050 case 0x96690101:
5051 ch->devices = ATA_PORTMULTIPLIER;
5052 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5053 ch->devices = 0;
5054 break;
5055 case 0x00000101:
5056 ch->devices = ATA_ATA_MASTER;
5057 break;
5058 default:
5059 ch->devices = 0;
5060 }
5061
5062 finish:
5063 /* clear interrupt(s) */
5064 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5065
5066 /* require explicit interrupt ack */
5067 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5068
5069 /* 64bit mode */
5070 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5071
5072 /* enable interrupts wanted */
5073 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5074 }
5075
5076 static void
5077 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5078 {
5079 struct ata_dmasetprd_args *args = xsc;
5080 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5081 int i;
5082
5083 if ((args->error = error))
5084 return;
5085
5086 for (i = 0; i < nsegs; i++) {
5087 prd[i].addr = htole64(segs[i].ds_addr);
5088 prd[i].count = htole32(segs[i].ds_len);
5089 }
5090 prd[i - 1].control = htole32(ATA_DMA_EOT);
5091 }
5092
5093 static void
5094 ata_siiprb_dmainit(device_t dev)
5095 {
5096 struct ata_channel *ch = device_get_softc(dev);
5097
5098 ata_dmainit(dev);
5099 if (ch->dma) {
5100 /* note start and stop are not used here */
5101 ch->dma->setprd = ata_siiprb_dmasetprd;
5102 ch->dma->max_address = BUS_SPACE_MAXADDR;
5103 }
5104 }
5105
5106
5107 /*
5108 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5109 */
5110 int
5111 ata_sis_ident(device_t dev)
5112 {
5113 struct ata_pci_controller *ctlr = device_get_softc(dev);
5114 struct ata_chip_id *idx;
5115 static struct ata_chip_id ids[] =
5116 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5117 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5118 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5119 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5120 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5121 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5122 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5123
5124 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5125 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5126 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5127 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5128
5129 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5130 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5131 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5132 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5133 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5134
5135 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5136 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5137 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5138
5139 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5140 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5141 { 0, 0, 0, 0, 0, 0 }};
5142 char buffer[64];
5143 int found = 0;
5144
5145 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5146 return ENXIO;
5147
5148 if (idx->cfg2 && !found) {
5149 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5150
5151 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5152 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5153 found = 1;
5154 idx->cfg1 = SIS133NEW;
5155 idx->max_dma = ATA_UDMA6;
5156 ksprintf(buffer, "SiS 962/963 %s controller",
5157 ata_mode2str(idx->max_dma));
5158 }
5159 pci_write_config(dev, 0x57, reg57, 1);
5160 }
5161 if (idx->cfg2 && !found) {
5162 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5163
5164 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5165 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5166 struct ata_chip_id id[] =
5167 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5168
5169 found = 1;
5170 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5171 idx->cfg1 = SIS133OLD;
5172 idx->max_dma = ATA_UDMA6;
5173 }
5174 else {
5175 idx->cfg1 = SIS100NEW;
5176 idx->max_dma = ATA_UDMA5;
5177 }
5178 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5179 }
5180 pci_write_config(dev, 0x4a, reg4a, 1);
5181 }
5182 if (!found)
5183 ksprintf(buffer,"SiS %s %s controller",
5184 idx->text, ata_mode2str(idx->max_dma));
5185
5186 device_set_desc_copy(dev, buffer);
5187 ctlr->chip = idx;
5188 ctlr->chipinit = ata_sis_chipinit;
5189 return 0;
5190 }
5191
5192 static int
5193 ata_sis_chipinit(device_t dev)
5194 {
5195 struct ata_pci_controller *ctlr = device_get_softc(dev);
5196
5197 if (ata_setup_interrupt(dev))
5198 return ENXIO;
5199
5200 switch (ctlr->chip->cfg1) {
5201 case SIS33:
5202 break;
5203 case SIS66:
5204 case SIS100OLD:
5205 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5206 break;
5207 case SIS100NEW:
5208 case SIS133OLD:
5209 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5210 break;
5211 case SIS133NEW:
5212 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5213 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5214 break;
5215 case SISSATA:
5216 ctlr->r_type2 = SYS_RES_IOPORT;
5217 ctlr->r_rid2 = PCIR_BAR(5);
5218 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5219 &ctlr->r_rid2, RF_ACTIVE))) {
5220 ctlr->allocate = ata_sis_allocate;
5221 ctlr->reset = ata_sis_reset;
5222
5223 /* enable PCI interrupt */
5224 pci_write_config(dev, PCIR_COMMAND,
5225 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5226 }
5227 ctlr->setmode = ata_sata_setmode;
5228 return 0;
5229 default:
5230 return ENXIO;
5231 }
5232 ctlr->setmode = ata_sis_setmode;
5233 return 0;
5234 }
5235
5236 static int
5237 ata_sis_allocate(device_t dev)
5238 {
5239 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5240 struct ata_channel *ch = device_get_softc(dev);
5241 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5242
5243 /* setup the usual register normal pci style */
5244 if (ata_pci_allocate(dev))
5245 return ENXIO;
5246
5247 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5248 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5249 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5250 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5251 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5252 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5253 ch->flags |= ATA_NO_SLAVE;
5254
5255 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5256 /* XXX SOS unknown how to enable PHY state change interrupt */
5257 return 0;
5258 }
5259
5260 static void
5261 ata_sis_reset(device_t dev)
5262 {
5263 if (ata_sata_phy_reset(dev))
5264 ata_generic_reset(dev);
5265 }
5266
5267 static void
5268 ata_sis_setmode(device_t dev, int mode)
5269 {
5270 device_t gparent = GRANDPARENT(dev);
5271 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5272 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5273 struct ata_device *atadev = device_get_softc(dev);
5274 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5275 int error;
5276
5277 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5278
5279 if (ctlr->chip->cfg1 == SIS133NEW) {
5280 if (mode > ATA_UDMA2 &&
5281 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5282 ata_print_cable(dev, "controller");
5283 mode = ATA_UDMA2;
5284 }
5285 }
5286 else {
5287 if (mode > ATA_UDMA2 &&
5288 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5289 ata_print_cable(dev, "controller");
5290 mode = ATA_UDMA2;
5291 }
5292 }
5293
5294 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5295
5296 if (bootverbose)
5297 device_printf(dev, "%ssetting %s on %s chip\n",
5298 (error) ? "FAILURE " : "",
5299 ata_mode2str(mode), ctlr->chip->text);
5300 if (!error) {
5301 switch (ctlr->chip->cfg1) {
5302 case SIS133NEW: {
5303 u_int32_t timings[] =
5304 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5305 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5306 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5307 u_int32_t reg;
5308
5309 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5310 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
5311 break;
5312 }
5313 case SIS133OLD: {
5314 u_int16_t timings[] =
5315 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
5316 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
5317
5318 u_int16_t reg = 0x40 + (devno << 1);
5319
5320 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5321 break;
5322 }
5323 case SIS100NEW: {
5324 u_int16_t timings[] =
5325 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
5326 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
5327 u_int16_t reg = 0x40 + (devno << 1);
5328
5329 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5330 break;
5331 }
5332 case SIS100OLD:
5333 case SIS66:
5334 case SIS33: {
5335 u_int16_t timings[] =
5336 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
5337 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
5338 u_int16_t reg = 0x40 + (devno << 1);
5339
5340 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5341 break;
5342 }
5343 }
5344 atadev->mode = mode;
5345 }
5346 }
5347
5348
5349 /* VIA Technologies Inc. chipset support functions */
5350 int
5351 ata_via_ident(device_t dev)
5352 {
5353 struct ata_pci_controller *ctlr = device_get_softc(dev);
5354 struct ata_chip_id *idx;
5355 static struct ata_chip_id ids[] =
5356 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
5357 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
5358 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
5359 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
5360 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
5361 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
5362 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
5363 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
5364 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
5365 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
5366 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
5367 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
5368 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
5369 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
5370 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
5371 { 0, 0, 0, 0, 0, 0 }};
5372 static struct ata_chip_id new_ids[] =
5373 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
5374 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
5375 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
5376 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
5377 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
5378 { 0, 0, 0, 0, 0, 0 }};
5379 char buffer[64];
5380
5381 if (pci_get_devid(dev) == ATA_VIA82C571) {
5382 if (!(idx = ata_find_chip(dev, ids, -99)))
5383 return ENXIO;
5384 }
5385 else {
5386 if (!(idx = ata_match_chip(dev, new_ids)))
5387 return ENXIO;
5388 }
5389
5390 ksprintf(buffer, "VIA %s %s controller",
5391 idx->text, ata_mode2str(idx->max_dma));
5392 device_set_desc_copy(dev, buffer);
5393 ctlr->chip = idx;
5394 ctlr->chipinit = ata_via_chipinit;
5395 return 0;
5396 }
5397
5398 static int
5399 ata_via_chipinit(device_t dev)
5400 {
5401 struct ata_pci_controller *ctlr = device_get_softc(dev);
5402
5403 if (ata_setup_interrupt(dev))
5404 return ENXIO;
5405
5406 if (ctlr->chip->max_dma >= ATA_SA150) {
5407 if (ctlr->chip->cfg2 == VIAAHCI) {
5408 ctlr->r_type2 = SYS_RES_MEMORY;
5409 ctlr->r_rid2 = PCIR_BAR(5);
5410 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5411 &ctlr->r_rid2,
5412 RF_ACTIVE))) {
5413 return ata_ahci_chipinit(dev);
5414 }
5415 }
5416 ctlr->r_type2 = SYS_RES_IOPORT;
5417 ctlr->r_rid2 = PCIR_BAR(5);
5418 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5419 &ctlr->r_rid2, RF_ACTIVE))) {
5420 ctlr->allocate = ata_via_allocate;
5421 ctlr->reset = ata_via_reset;
5422
5423 /* enable PCI interrupt */
5424 pci_write_config(dev, PCIR_COMMAND,
5425 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5426 }
5427
5428 if (ctlr->chip->cfg2 & VIABAR) {
5429 ctlr->channels = 3;
5430 ctlr->setmode = ata_via_setmode;
5431 }
5432 else
5433 ctlr->setmode = ata_sata_setmode;
5434 return 0;
5435 }
5436
5437 /* prepare for ATA-66 on the 82C686a and 82C596b */
5438 if (ctlr->chip->cfg2 & VIACLK)
5439 pci_write_config(dev, 0x50, 0x030b030b, 4);
5440
5441 /* the southbridge might need the data corruption fix */
5442 if (ctlr->chip->cfg2 & VIABUG)
5443 ata_via_southbridge_fixup(dev);
5444
5445 /* set fifo configuration half'n'half */
5446 pci_write_config(dev, 0x43,
5447 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
5448
5449 /* set status register read retry */
5450 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
5451
5452 /* set DMA read & end-of-sector fifo flush */
5453 pci_write_config(dev, 0x46,
5454 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
5455
5456 /* set sector size */
5457 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
5458 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
5459
5460 ctlr->setmode = ata_via_family_setmode;
5461 return 0;
5462 }
5463
5464 static int
5465 ata_via_allocate(device_t dev)
5466 {
5467 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5468 struct ata_channel *ch = device_get_softc(dev);
5469
5470 /* newer SATA chips has resources in one BAR for each channel */
5471 if (ctlr->chip->cfg2 & VIABAR) {
5472 struct resource *r_io;
5473 int i, rid;
5474
5475 rid = PCIR_BAR(ch->unit);
5476 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
5477 SYS_RES_IOPORT,
5478 &rid, RF_ACTIVE)))
5479 return ENXIO;
5480
5481 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
5482 ch->r_io[i].res = r_io;
5483 ch->r_io[i].offset = i;
5484 }
5485 ch->r_io[ATA_CONTROL].res = r_io;
5486 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
5487 ch->r_io[ATA_IDX_ADDR].res = r_io;
5488 ata_default_registers(dev);
5489 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
5490 ch->r_io[i].res = ctlr->r_res1;
5491 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
5492 }
5493 ata_pci_hw(dev);
5494 if (ch->unit > 1)
5495 return 0;
5496 }
5497 else {
5498 /* setup the usual register normal pci style */
5499 if (ata_pci_allocate(dev))
5500 return ENXIO;
5501 }
5502
5503 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5504 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
5505 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5506 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
5507 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5508 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
5509 ch->flags |= ATA_NO_SLAVE;
5510
5511 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
5512 /* XXX SOS unknown how to enable PHY state change interrupt */
5513 return 0;
5514 }
5515
5516 static void
5517 ata_via_reset(device_t dev)
5518 {
5519 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5520 struct ata_channel *ch = device_get_softc(dev);
5521
5522 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
5523 ata_generic_reset(dev);
5524 else
5525 if (ata_sata_phy_reset(dev))
5526 ata_generic_reset(dev);
5527 }
5528
5529 static void
5530 ata_via_setmode(device_t dev, int mode)
5531 {
5532 device_t gparent = GRANDPARENT(dev);
5533 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5534 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5535 struct ata_device *atadev = device_get_softc(dev);
5536 int error;
5537
5538 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
5539 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
5540 0x65, 0x32, 0x20,
5541 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5542 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
5543
5544 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
5545 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5546 if (bootverbose)
5547 device_printf(dev, "%ssetting %s on %s chip\n",
5548 (error) ? "FAILURE " : "", ata_mode2str(mode),
5549 ctlr->chip->text);
5550 if (!error) {
5551 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
5552 if (mode >= ATA_UDMA0)
5553 pci_write_config(gparent, 0xb3,
5554 dma_timings[mode & ATA_MODE_MASK], 1);
5555 atadev->mode = mode;
5556 }
5557 }
5558 else
5559 ata_sata_setmode(dev, mode);
5560 }
5561
5562 static void
5563 ata_via_southbridge_fixup(device_t dev)
5564 {
5565 device_t *children;
5566 int nchildren, i;
5567
5568 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5569 return;
5570
5571 for (i = 0; i < nchildren; i++) {
5572 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
5573 pci_get_devid(children[i]) == ATA_VIA8371 ||
5574 pci_get_devid(children[i]) == ATA_VIA8662 ||
5575 pci_get_devid(children[i]) == ATA_VIA8361) {
5576 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
5577
5578 if ((reg76 & 0xf0) != 0xd0) {
5579 device_printf(dev,
5580 "Correcting VIA config for southbridge data corruption bug\n");
5581 pci_write_config(children[i], 0x75, 0x80, 1);
5582 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
5583 }
5584 break;
5585 }
5586 }
5587 kfree(children, M_TEMP);
5588 }
5589
5590
5591 /* common code for VIA, AMD & nVidia */
5592 static void
5593 ata_via_family_setmode(device_t dev, int mode)
5594 {
5595 device_t gparent = GRANDPARENT(dev);
5596 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5597 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5598 struct ata_device *atadev = device_get_softc(dev);
5599 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
5600 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5601 int modes[][7] = {
5602 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
5603 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
5604 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
5605 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
5606 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
5607 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5608 int reg = 0x53 - devno;
5609 int error;
5610
5611 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5612
5613 if (ctlr->chip->cfg2 & AMDCABLE) {
5614 if (mode > ATA_UDMA2 &&
5615 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
5616 ata_print_cable(dev, "controller");
5617 mode = ATA_UDMA2;
5618 }
5619 }
5620 else
5621 mode = ata_check_80pin(dev, mode);
5622
5623 if (ctlr->chip->cfg2 & NVIDIA)
5624 reg += 0x10;
5625
5626 if (ctlr->chip->cfg1 != VIA133)
5627 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
5628
5629 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5630
5631 if (bootverbose)
5632 device_printf(dev, "%ssetting %s on %s chip\n",
5633 (error) ? "FAILURE " : "", ata_mode2str(mode),
5634 ctlr->chip->text);
5635 if (!error) {
5636 if (mode >= ATA_UDMA0)
5637 pci_write_config(gparent, reg,
5638 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
5639 else
5640 pci_write_config(gparent, reg, 0x8b, 1);
5641 atadev->mode = mode;
5642 }
5643 }
5644
5645
5646 /* misc functions */
5647 static struct ata_chip_id *
5648 ata_match_chip(device_t dev, struct ata_chip_id *index)
5649 {
5650 while (index->chipid != 0) {
5651 if (pci_get_devid(dev) == index->chipid &&
5652 pci_get_revid(dev) >= index->chiprev)
5653 return index;
5654 index++;
5655 }
5656 return NULL;
5657 }
5658
5659 static struct ata_chip_id *
5660 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5661 {
5662 device_t *children;
5663 int nchildren, i;
5664
5665 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5666 return 0;
5667
5668 while (index->chipid != 0) {
5669 for (i = 0; i < nchildren; i++) {
5670 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5671 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5672 pci_get_devid(children[i]) == index->chipid &&
5673 pci_get_revid(children[i]) >= index->chiprev) {
5674 kfree(children, M_TEMP);
5675 return index;
5676 }
5677 }
5678 index++;
5679 }
5680 kfree(children, M_TEMP);
5681 return NULL;
5682 }
5683
5684 static int
5685 ata_setup_interrupt(device_t dev)
5686 {
5687 struct ata_pci_controller *ctlr = device_get_softc(dev);
5688 int rid = ATA_IRQ_RID;
5689
5690 if (!ata_legacy(dev)) {
5691 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5692 RF_SHAREABLE | RF_ACTIVE))) {
5693 device_printf(dev, "unable to map interrupt\n");
5694 return ENXIO;
5695 }
5696 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5697 ata_generic_intr, ctlr, &ctlr->handle, NULL))) {
5698 device_printf(dev, "unable to setup interrupt\n");
5699 return ENXIO;
5700 }
5701 }
5702 return 0;
5703 }
5704
5705 struct ata_serialize {
5706 struct spinlock locked_mtx;
5707 int locked_ch;
5708 int restart_ch;
5709 };
5710
5711 static int
5712 ata_serialize(device_t dev, int flags)
5713 {
5714 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5715 struct ata_channel *ch = device_get_softc(dev);
5716 struct ata_serialize *serial;
5717 static int inited = 0;
5718 int res;
5719
5720 if (!inited) {
5721 serial = kmalloc(sizeof(struct ata_serialize),
5722 M_TEMP, M_INTWAIT | M_ZERO);
5723 spin_init(&serial->locked_mtx);
5724 serial->locked_ch = -1;
5725 serial->restart_ch = -1;
5726 device_set_ivars(ctlr->dev, serial);
5727 inited = 1;
5728 }
5729 else
5730 serial = device_get_ivars(ctlr->dev);
5731
5732 spin_lock_wr(&serial->locked_mtx);
5733 switch (flags) {
5734 case ATA_LF_LOCK:
5735 if (serial->locked_ch == -1)
5736 serial->locked_ch = ch->unit;
5737 if (serial->locked_ch != ch->unit)
5738 serial->restart_ch = ch->unit;
5739 break;
5740
5741 case ATA_LF_UNLOCK:
5742 if (serial->locked_ch == ch->unit) {
5743 serial->locked_ch = -1;
5744 if (serial->restart_ch != -1) {
5745 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5746 serial->restart_ch = -1;
5747 spin_unlock_wr(&serial->locked_mtx);
5748 ata_start(ch->dev);
5749 return -1;
5750 }
5751 }
5752 }
5753 break;
5754
5755 case ATA_LF_WHICH:
5756 break;
5757 }
5758 res = serial->locked_ch;
5759 spin_unlock_wr(&serial->locked_mtx);
5760 return res;
5761 }
5762
5763 static void
5764 ata_print_cable(device_t dev, u_int8_t *who)
5765 {
5766 device_printf(dev,
5767 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5768 }
5769
5770 static int
5771 ata_atapi(device_t dev)
5772 {
5773 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5774 struct ata_device *atadev = device_get_softc(dev);
5775
5776 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5777 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5778 }
5779
5780 static int
5781 ata_check_80pin(device_t dev, int mode)
5782 {
5783 struct ata_device *atadev = device_get_softc(dev);
5784
5785 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5786 ata_print_cable(dev, "device");
5787 mode = ATA_UDMA2;
5788 }
5789 return mode;
5790 }
5791
5792 static int
5793 ata_mode2idx(int mode)
5794 {
5795 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5796 return (mode & ATA_MODE_MASK) + 8;
5797 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5798 return (mode & ATA_MODE_MASK) + 5;
5799 return (mode & ATA_MODE_MASK) - ATA_PIO0;
5800 }
DragonFly BSD