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dhcpcd: update README.DRAGONFLY
[dragonfly.git] / sys / dev / disk / nata / ata-all.h
blob7ca5e3d536adf4311464765d37dd5a6485e79a98
1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.123 2007/04/08 19:18:51 sos Exp $
27 */
28
29 #include <sys/param.h>
30 #include <sys/bio.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/nata.h>
36 #include <sys/objcache.h>
37 #include <sys/queue.h>
38 #include <sys/rman.h>
39 #include <sys/systm.h>
40 #include <sys/taskqueue.h>
41
42 #include <machine/bus_dma.h>
43
44 /* ATA register defines */
45 #define ATA_DATA 0 /* (RW) data */
46
47 #define ATA_FEATURE 1 /* (W) feature */
48 #define ATA_F_DMA 0x01 /* enable DMA */
49 #define ATA_F_OVL 0x02 /* enable overlap */
50
51 #define ATA_COUNT 2 /* (W) sector count */
52
53 #define ATA_SECTOR 3 /* (RW) sector # */
54 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
55 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
56 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
57 #define ATA_D_LBA 0x40 /* use LBA addressing */
58 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60 #define ATA_COMMAND 7 /* (W) command */
61
62 #define ATA_ERROR 8 /* (R) error */
63 #define ATA_E_ILI 0x01 /* illegal length */
64 #define ATA_E_NM 0x02 /* no media */
65 #define ATA_E_ABORT 0x04 /* command aborted */
66 #define ATA_E_MCR 0x08 /* media change request */
67 #define ATA_E_IDNF 0x10 /* ID not found */
68 #define ATA_E_MC 0x20 /* media changed */
69 #define ATA_E_UNC 0x40 /* uncorrectable data */
70 #define ATA_E_ICRC 0x80 /* UDMA crc error */
71 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
72
73 #define ATA_IREASON 9 /* (R) interrupt reason */
74 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
75 #define ATA_I_IN 0x02 /* read (1) | write (0) */
76 #define ATA_I_RELEASE 0x04 /* released bus (1) */
77 #define ATA_I_TAGMASK 0xf8 /* tag mask */
78
79 #define ATA_STATUS 10 /* (R) status */
80 #define ATA_ALTSTAT 11 /* (R) alternate status */
81 #define ATA_S_ERROR 0x01 /* error */
82 #define ATA_S_INDEX 0x02 /* index */
83 #define ATA_S_CORR 0x04 /* data corrected */
84 #define ATA_S_DRQ 0x08 /* data request */
85 #define ATA_S_DSC 0x10 /* drive seek completed */
86 #define ATA_S_SERVICE 0x10 /* drive needs service */
87 #define ATA_S_DWF 0x20 /* drive write fault */
88 #define ATA_S_DMA 0x20 /* DMA ready */
89 #define ATA_S_READY 0x40 /* drive ready */
90 #define ATA_S_BUSY 0x80 /* busy */
91
92 #define ATA_CONTROL 12 /* (W) control */
93
94 #define ATA_CTLOFFSET 0x206 /* control register offset */
95 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
96 #define ATA_A_IDS 0x02 /* disable interrupts */
97 #define ATA_A_RESET 0x04 /* RESET controller */
98 #define ATA_A_4BIT 0x08 /* 4 head bits */
99 #define ATA_A_HOB 0x80 /* High Order Byte enable */
100
101 /* SATA register defines */
102 #define ATA_SSTATUS 13
103 #define ATA_SS_DET_MASK 0x0000000f
104 #define ATA_SS_DET_NO_DEVICE 0x00000000
105 #define ATA_SS_DET_DEV_PRESENT 0x00000001
106 #define ATA_SS_DET_PHY_ONLINE 0x00000003
107 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
108
109 #define ATA_SS_SPD_MASK 0x000000f0
110 #define ATA_SS_SPD_NO_SPEED 0x00000000
111 #define ATA_SS_SPD_GEN1 0x00000010
112 #define ATA_SS_SPD_GEN2 0x00000020
113
114 #define ATA_SS_IPM_MASK 0x00000f00
115 #define ATA_SS_IPM_NO_DEVICE 0x00000000
116 #define ATA_SS_IPM_ACTIVE 0x00000100
117 #define ATA_SS_IPM_PARTIAL 0x00000200
118 #define ATA_SS_IPM_SLUMBER 0x00000600
119
120 #define ATA_SS_CONWELL_MASK \
121 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
122 #define ATA_SS_CONWELL_GEN1 \
123 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
124 #define ATA_SS_CONWELL_GEN2 \
125 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
126
127 #define ATA_SERROR 14
128 #define ATA_SE_DATA_CORRECTED 0x00000001
129 #define ATA_SE_COMM_CORRECTED 0x00000002
130 #define ATA_SE_DATA_ERR 0x00000100
131 #define ATA_SE_COMM_ERR 0x00000200
132 #define ATA_SE_PROT_ERR 0x00000400
133 #define ATA_SE_HOST_ERR 0x00000800
134 #define ATA_SE_PHY_CHANGED 0x00010000
135 #define ATA_SE_PHY_IERROR 0x00020000
136 #define ATA_SE_COMM_WAKE 0x00040000
137 #define ATA_SE_DECODE_ERR 0x00080000
138 #define ATA_SE_PARITY_ERR 0x00100000
139 #define ATA_SE_CRC_ERR 0x00200000
140 #define ATA_SE_HANDSHAKE_ERR 0x00400000
141 #define ATA_SE_LINKSEQ_ERR 0x00800000
142 #define ATA_SE_TRANSPORT_ERR 0x01000000
143 #define ATA_SE_UNKNOWN_FIS 0x02000000
144
145 #define ATA_SCONTROL 15
146 #define ATA_SC_DET_MASK 0x0000000f
147 #define ATA_SC_DET_IDLE 0x00000000
148 #define ATA_SC_DET_RESET 0x00000001
149 #define ATA_SC_DET_DISABLE 0x00000004
150
151 #define ATA_SC_SPD_MASK 0x000000f0
152 #define ATA_SC_SPD_NO_SPEED 0x00000000
153 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
154 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
155
156 #define ATA_SC_IPM_MASK 0x00000f00
157 #define ATA_SC_IPM_NONE 0x00000000
158 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
159 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
160
161 #define ATA_SACTIVE 16
162
163 /* SATA AHCI v1.0 register defines */
164 #define ATA_AHCI_CAP 0x00
165 #define ATA_AHCI_NPMASK 0x1f
166 #define ATA_AHCI_CAP_CLO 0x01000000
167 #define ATA_AHCI_CAP_64BIT 0x80000000
168
169 #define ATA_AHCI_GHC 0x04
170 #define ATA_AHCI_GHC_AE 0x80000000
171 #define ATA_AHCI_GHC_IE 0x00000002
172 #define ATA_AHCI_GHC_HR 0x00000001
173
174 #define ATA_AHCI_IS 0x08
175 #define ATA_AHCI_PI 0x0c
176 #define ATA_AHCI_VS 0x10
177
178 #define ATA_AHCI_OFFSET 0x80
179
180 #define ATA_AHCI_P_CLB 0x100
181 #define ATA_AHCI_P_CLBU 0x104
182 #define ATA_AHCI_P_FB 0x108
183 #define ATA_AHCI_P_FBU 0x10c
184 #define ATA_AHCI_P_IS 0x110
185 #define ATA_AHCI_P_IE 0x114
186 #define ATA_AHCI_P_IX_DHR 0x00000001
187 #define ATA_AHCI_P_IX_PS 0x00000002
188 #define ATA_AHCI_P_IX_DS 0x00000004
189 #define ATA_AHCI_P_IX_SDB 0x00000008
190 #define ATA_AHCI_P_IX_UF 0x00000010
191 #define ATA_AHCI_P_IX_DP 0x00000020
192 #define ATA_AHCI_P_IX_PC 0x00000040
193 #define ATA_AHCI_P_IX_DI 0x00000080
194
195 #define ATA_AHCI_P_IX_PRC 0x00400000
196 #define ATA_AHCI_P_IX_IPM 0x00800000
197 #define ATA_AHCI_P_IX_OF 0x01000000
198 #define ATA_AHCI_P_IX_INF 0x04000000
199 #define ATA_AHCI_P_IX_IF 0x08000000
200 #define ATA_AHCI_P_IX_HBD 0x10000000
201 #define ATA_AHCI_P_IX_HBF 0x20000000
202 #define ATA_AHCI_P_IX_TFE 0x40000000
203 #define ATA_AHCI_P_IX_CPD 0x80000000
204
205 #define ATA_AHCI_P_CMD 0x118
206 #define ATA_AHCI_P_CMD_ST 0x00000001
207 #define ATA_AHCI_P_CMD_SUD 0x00000002
208 #define ATA_AHCI_P_CMD_POD 0x00000004
209 #define ATA_AHCI_P_CMD_CLO 0x00000008
210 #define ATA_AHCI_P_CMD_FRE 0x00000010
211 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
212 #define ATA_AHCI_P_CMD_ISS 0x00002000
213 #define ATA_AHCI_P_CMD_FR 0x00004000
214 #define ATA_AHCI_P_CMD_CR 0x00008000
215 #define ATA_AHCI_P_CMD_CPS 0x00010000
216 #define ATA_AHCI_P_CMD_PMA 0x00020000
217 #define ATA_AHCI_P_CMD_HPCP 0x00040000
218 #define ATA_AHCI_P_CMD_ISP 0x00080000
219 #define ATA_AHCI_P_CMD_CPD 0x00100000
220 #define ATA_AHCI_P_CMD_ATAPI 0x01000000
221 #define ATA_AHCI_P_CMD_DLAE 0x02000000
222 #define ATA_AHCI_P_CMD_ALPE 0x04000000
223 #define ATA_AHCI_P_CMD_ASP 0x08000000
224 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000
225
226 #define ATA_AHCI_P_TFD 0x120
227 #define ATA_AHCI_P_SIG 0x124
228 #define ATA_AHCI_P_SSTS 0x128
229 #define ATA_AHCI_P_SCTL 0x12c
230 #define ATA_AHCI_P_SERR 0x130
231 #define ATA_AHCI_P_SACT 0x134
232 #define ATA_AHCI_P_CI 0x138
233
234 #define ATA_AHCI_CL_SIZE 32
235 #define ATA_AHCI_CL_OFFSET 0
236 #define ATA_AHCI_FB_OFFSET 1024
237 #define ATA_AHCI_CT_OFFSET 1024+256
238 #define ATA_AHCI_CT_SG_OFFSET 128
239 #define ATA_AHCI_CT_SIZE 256
240
241 struct ata_ahci_dma_prd {
242 u_int64_t dba;
243 u_int32_t reserved;
244 u_int32_t dbc; /* 0 based */
245 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
246 #define ATA_AHCI_PRD_IPC (1<<31)
247 } __packed;
248
249 struct ata_ahci_cmd_tab {
250 u_int8_t cfis[64];
251 u_int8_t acmd[32];
252 u_int8_t reserved[32];
253 #define ATA_AHCI_DMA_ENTRIES 64
254 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES];
255 } __packed;
256
257 struct ata_ahci_cmd_list {
258 u_int16_t cmd_flags;
259 #define ATA_AHCI_CMD_ATAPI 0x0020
260 #define ATA_AHCI_CMD_WRITE 0x0040
261 #define ATA_AHCI_CMD_PREFETCH 0x0080
262
263 u_int16_t prd_length; /* PRD entries */
264 u_int32_t bytecount;
265 u_int64_t cmd_table_phys; /* 128byte aligned */
266 } __packed;
267
268
269 /* DMA register defines */
270 #define ATA_DMA_ENTRIES 256
271 #define ATA_DMA_EOT 0x80000000
272
273 #define ATA_BMCMD_PORT 17
274 #define ATA_BMCMD_START_STOP 0x01
275 #define ATA_BMCMD_WRITE_READ 0x08
276
277 #define ATA_BMDEVSPEC_0 18
278 #define ATA_BMSTAT_PORT 19
279 #define ATA_BMSTAT_ACTIVE 0x01
280 #define ATA_BMSTAT_ERROR 0x02
281 #define ATA_BMSTAT_INTERRUPT 0x04
282 #define ATA_BMSTAT_MASK 0x07
283 #define ATA_BMSTAT_DMA_MASTER 0x20
284 #define ATA_BMSTAT_DMA_SLAVE 0x40
285 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
286
287 #define ATA_BMDEVSPEC_1 20
288 #define ATA_BMDTP_PORT 21
289
290 #define ATA_IDX_ADDR 22
291 #define ATA_IDX_DATA 23
292 #define ATA_MAX_RES 24
293
294 /* misc defines */
295 #define ATA_PRIMARY 0x1f0
296 #define ATA_SECONDARY 0x170
297 #define ATA_IOSIZE 0x08
298 #define ATA_CTLIOSIZE 0x01
299 #define ATA_BMIOSIZE 0x08
300 #define ATA_IOADDR_RID 0
301 #define ATA_CTLADDR_RID 1
302 #define ATA_BMADDR_RID 0x20
303 #define ATA_IRQ_RID 0
304 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0)
305 #define ATA_CFA_MAGIC1 0x844A
306 #define ATA_CFA_MAGIC2 0x848A
307 #define ATA_CFA_MAGIC3 0x8400
308 #define ATAPI_MAGIC_LSB 0x14
309 #define ATAPI_MAGIC_MSB 0xeb
310 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
311 #define ATAPI_P_WRITE (ATA_S_DRQ)
312 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
313 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
314 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
315 #define ATAPI_P_ABORT 0
316 #define ATA_INTR_FLAGS (INTR_NOPOLL)
317 #define ATA_OP_CONTINUES 0
318 #define ATA_OP_FINISHED 1
319 #define ATA_MAX_28BIT_LBA 268435455UL
320
321 /* Dragonfly: Default request timeout increased from 5 to 10 */
322 #define ATA_DEFAULT_TIMEOUT 10
323
324 /* structure used for composite atomic operations */
325 #define MAX_COMPOSITES 32 /* u_int32_t bits */
326 struct ata_composite {
327 struct lock lock; /* control lock */
328 u_int32_t rd_needed; /* needed read subdisks */
329 u_int32_t rd_done; /* done read subdisks */
330 u_int32_t wr_needed; /* needed write subdisks */
331 u_int32_t wr_depend; /* write depends on subdisks */
332 u_int32_t wr_done; /* done write subdisks */
333 struct ata_request *request[MAX_COMPOSITES];
334 u_int32_t residual; /* bytes still to transfer */
335 caddr_t data_1;
336 caddr_t data_2;
337 };
338
339 /* structure used to queue an ATA/ATAPI request */
340 struct ata_request {
341 device_t dev; /* device handle */
342 device_t parent; /* channel handle */
343 union {
344 struct {
345 u_int8_t command; /* command reg */
346 u_int16_t feature; /* feature reg */
347 u_int16_t count; /* count reg */
348 u_int64_t lba; /* lba reg */
349 } ata;
350 struct {
351 u_int8_t ccb[16]; /* ATAPI command block */
352 struct atapi_sense sense; /* ATAPI request sense data */
353 u_int8_t saved_cmd; /* ATAPI saved command */
354 } atapi;
355 } u;
356 u_int32_t bytecount; /* bytes to transfer */
357 u_int32_t transfersize; /* bytes pr transfer */
358 caddr_t data; /* pointer to data buf */
359 int flags;
360 #define ATA_R_CONTROL 0x00000001
361 #define ATA_R_READ 0x00000002
362 #define ATA_R_WRITE 0x00000004
363 #define ATA_R_ATAPI 0x00000008
364 #define ATA_R_DMA 0x00000010
365 #define ATA_R_QUIET 0x00000020
366 #define ATA_R_TIMEOUT 0x00000040
367 #define ATA_R_COMPLETED 0x00000080
368
369 #define ATA_R_ORDERED 0x00000100
370 #define ATA_R_AT_HEAD 0x00000200
371 #define ATA_R_REQUEUE 0x00000400
372 #define ATA_R_THREAD 0x00000800
373 #define ATA_R_DIRECT 0x00001000
374
375 #define ATA_R_HWCMDQUEUED 0x00010000
376
377 #define ATA_R_DEBUG 0x10000000
378 #define ATA_R_DANGER1 0x20000000
379 #define ATA_R_DANGER2 0x40000000
380
381 u_int8_t status; /* ATA status */
382 u_int8_t error; /* ATA error */
383 u_int8_t dmastat; /* DMA status */
384 u_int32_t donecount; /* bytes transferred */
385 int result; /* result error code */
386 void (*callback)(struct ata_request *request);
387 struct lock done; /* request done sema */
388 int retries; /* retry count */
389 int timeout; /* timeout for this cmd */
390 int unused01;
391 struct callout callout; /* callout management */
392 struct task task; /* task management */
393 struct bio *bio; /* bio for this request */
394 int this; /* this request ID */
395 struct ata_composite *composite; /* for composite atomic ops */
396 void *driver; /* driver specific */
397 TAILQ_ENTRY(ata_request) chain; /* list management */
398 };
399
400 /* define this for debugging request processing */
401 #if 0
402 #define ATA_DEBUG_RQ(request, string) \
403 { \
404 if (request->flags & ATA_R_DEBUG) \
405 device_printf(request->dev, "req=%p %s " string "\n", \
406 request, ata_cmd2str(request)); \
407 }
408 #else
409 #define ATA_DEBUG_RQ(request, string)
410 #endif
411
412
413 /* structure describing an ATA/ATAPI device */
414 struct ata_device {
415 device_t dev; /* device handle */
416 int unit; /* physical unit */
417 #define ATA_MASTER 0x00
418 #define ATA_SLAVE 0x01
419 #define ATA_PM 0x0f
420
421 struct ata_params param; /* ata param structure */
422 int mode; /* current transfermode */
423 u_int32_t max_iosize; /* max IO size */
424 int spindown; /* idle spindown timeout */
425 struct callout spindown_timer;
426 int spindown_state;
427 int flags;
428 #define ATA_D_USE_CHS 0x0001
429 #define ATA_D_MEDIA_CHANGED 0x0002
430 #define ATA_D_ENC_PRESENT 0x0004
431 #define ATA_D_48BIT_ACTIVE 0x0008
432 int opencount; /* when tracking needed */
433 };
434
435 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
436 struct ata_dma_prdentry {
437 u_int32_t addr;
438 u_int32_t count;
439 };
440
441 /* structure used by the setprd function */
442 struct ata_dmasetprd_args {
443 void *dmatab;
444 int nsegs;
445 int error;
446 };
447
448 /* structure holding DMA related information */
449 struct ata_dma {
450 bus_dma_tag_t dmatag; /* parent DMA tag */
451 bus_dma_tag_t sg_tag; /* SG list DMA tag */
452 bus_dmamap_t sg_map; /* SG list DMA map */
453 void *sg; /* DMA transfer table */
454 bus_addr_t sg_bus; /* bus address of dmatab */
455 bus_dma_tag_t data_tag; /* data DMA tag */
456 bus_dmamap_t data_map; /* data DMA map */
457 bus_dma_tag_t work_tag; /* workspace DMA tag */
458 bus_dmamap_t work_map; /* workspace DMA map */
459 u_int8_t *work; /* workspace */
460 bus_addr_t work_bus; /* bus address of dmatab */
461
462 u_int32_t alignment; /* DMA SG list alignment */
463 u_int32_t boundary; /* DMA SG list boundary */
464 u_int32_t segsize; /* DMA SG list segment size */
465 u_int32_t max_iosize; /* DMA data max IO size */
466 u_int32_t cur_iosize; /* DMA data current IO size */
467 u_int64_t max_address; /* highest DMA'able address */
468 int flags;
469 #define ATA_DMA_READ 0x01 /* transaction is a read */
470 #define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */
471 #define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */
472
473 void (*alloc)(device_t dev);
474 void (*free)(device_t dev);
475 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
476 int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs);
477 int (*unload)(device_t dev);
478 int (*start)(device_t dev);
479 int (*stop)(device_t dev);
480 void (*reset)(device_t dev);
481 };
482
483 /* structure holding lowlevel functions */
484 struct ata_lowlevel {
485 u_int32_t (*softreset)(device_t dev, int pmport);
486 int (*status)(device_t dev);
487 int (*begin_transaction)(struct ata_request *request);
488 int (*end_transaction)(struct ata_request *request);
489 int (*command)(struct ata_request *request);
490 void (*tf_read)(struct ata_request *request);
491 void (*tf_write)(struct ata_request *request);
492 };
493
494 /* structure holding resources for an ATA channel */
495 struct ata_resource {
496 struct resource *res;
497 int offset;
498 };
499
500 /* structure describing an ATA channel */
501 struct ata_channel {
502 device_t dev; /* device handle */
503 int unit; /* physical channel */
504 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
505 struct resource *r_irq; /* interrupt of this channel */
506 void *ih; /* interrupt handle */
507 struct ata_lowlevel hw; /* lowlevel HW functions */
508 struct ata_dma *dma; /* DMA data / functions */
509 int flags; /* channel flags */
510 #define ATA_NO_SLAVE 0x01
511 #define ATA_USE_16BIT 0x02
512 #define ATA_ATAPI_DMA_RO 0x04
513 #define ATA_NO_48BIT_DMA 0x08
514 #define ATA_ALWAYS_DMASTAT 0x10
515
516 int devices; /* what is present */
517 #define ATA_ATA_MASTER 0x00000001
518 #define ATA_ATA_SLAVE 0x00000002
519 #define ATA_PORTMULTIPLIER 0x00008000
520 #define ATA_ATAPI_MASTER 0x00010000
521 #define ATA_ATAPI_SLAVE 0x00020000
522
523 struct lock state_mtx; /* state lock */
524 int state; /* ATA channel state */
525 #define ATA_IDLE 0x0000
526 #define ATA_ACTIVE 0x0001
527 #define ATA_STALL_QUEUE 0x0002
528
529 struct lock queue_mtx; /* queue lock */
530 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */
531 int reorder; /* limit sort reordering */
532 struct ata_request *transition;
533 struct ata_request *running; /* currently running request */
534 };
535
536 /* disk bay/enclosure related */
537 #define ATA_LED_OFF 0x00
538 #define ATA_LED_RED 0x01
539 #define ATA_LED_GREEN 0x02
540 #define ATA_LED_ORANGE 0x03
541 #define ATA_LED_MASK 0x03
542
543 /* externs */
544 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
545 extern devclass_t ata_devclass;
546 extern int ata_wc;
547
548 /* public prototypes */
549 /* ata-all.c: */
550 int ata_probe(device_t dev);
551 int ata_attach(device_t dev);
552 int ata_detach(device_t dev);
553 int ata_reinit(device_t dev);
554 int ata_suspend(device_t dev);
555 int ata_resume(device_t dev);
556 int ata_interrupt(void *data);
557 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data);
558 int ata_identify(device_t dev);
559 void ata_default_registers(device_t dev);
560 void ata_modify_if_48bit(struct ata_request *request);
561 void ata_udelay(int interval);
562 const char *ata_unit2str(struct ata_device *atadev);
563 const char *ata_mode2str(int mode);
564 void ata_print_cable(device_t dev, u_int8_t *who);
565 int ata_atapi(device_t dev);
566 int ata_pmode(struct ata_params *ap);
567 int ata_wmode(struct ata_params *ap);
568 int ata_umode(struct ata_params *ap);
569 int ata_limit_mode(device_t dev, int mode, int maxmode);
570
571 /* ata-queue.c: */
572 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
573 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
574 void ata_drop_requests(device_t dev);
575 void ata_queue_init(struct ata_channel *ch);
576 void ata_queue_request(struct ata_request *request);
577 void ata_start(device_t dev);
578 void ata_finish(struct ata_request *request);
579 void ata_timeout(struct ata_request *);
580 void ata_catch_inflight(device_t dev);
581 void ata_fail_requests(device_t dev);
582 const char *ata_cmd2str(struct ata_request *request);
583
584 /* ata-lowlevel.c: */
585 void ata_generic_hw(device_t dev);
586 int ata_begin_transaction(struct ata_request *);
587 int ata_end_transaction(struct ata_request *);
588 void ata_generic_reset(device_t dev);
589 int ata_generic_command(struct ata_request *request);
590
591 /* ata-dma.c: */
592 void ata_dmainit(device_t);
593
594 /* ata-sata.c: */
595 void ata_sata_phy_check_events(device_t dev);
596 void ata_sata_phy_event(void *context, int dummy);
597 int ata_sata_phy_reset(device_t dev);
598 void ata_sata_setmode(device_t dev, int mode);
599 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
600
601 /* macros for alloc/free of struct ata_request */
602 extern struct objcache *ata_request_cache;
603 #define ata_alloc_request() objcache_get(ata_request_cache, M_WAITOK)
604 /* zero the object so objects in the cache are guaranteed to be zero'ed */
605 #define ata_free_request(request) { \
606 if (!(request->flags & ATA_R_DANGER2)) { \
607 bzero(request, sizeof(struct ata_request)); \
608 objcache_put(ata_request_cache, request); \
609 } \
610 }
611 /* macros for alloc/free of struct ata_composite */
612 extern struct objcache *ata_composite_cache;
613 #define ata_alloc_composite() objcache_get(ata_composite_cache, M_WAITOK)
614 /* zero the object so objects in the cache are guaranteed to be zero'ed */
615 #define ata_free_composite(composite) { \
616 bzero(composite, sizeof(struct ata_composite)); \
617 objcache_put(ata_composite_cache, composite); \
618 }
619
620 MALLOC_DECLARE(M_ATA);
621
622 /* misc newbus defines */
623 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
624
625 /* macros to hide busspace uglyness */
626 #define ATA_INB(res, offset) \
627 bus_space_read_1(rman_get_bustag((res)), \
628 rman_get_bushandle((res)), (offset))
629
630 #define ATA_INW(res, offset) \
631 bus_space_read_2(rman_get_bustag((res)), \
632 rman_get_bushandle((res)), (offset))
633 #define ATA_INL(res, offset) \
634 bus_space_read_4(rman_get_bustag((res)), \
635 rman_get_bushandle((res)), (offset))
636 #define ATA_INSW(res, offset, addr, count) \
637 bus_space_read_multi_2(rman_get_bustag((res)), \
638 rman_get_bushandle((res)), \
639 (offset), (addr), (count))
640 #define ATA_INSW_STRM(res, offset, addr, count) \
641 bus_space_read_multi_stream_2(rman_get_bustag((res)), \
642 rman_get_bushandle((res)), \
643 (offset), (addr), (count))
644 #define ATA_INSL(res, offset, addr, count) \
645 bus_space_read_multi_4(rman_get_bustag((res)), \
646 rman_get_bushandle((res)), \
647 (offset), (addr), (count))
648 #define ATA_INSL_STRM(res, offset, addr, count) \
649 bus_space_read_multi_stream_4(rman_get_bustag((res)), \
650 rman_get_bushandle((res)), \
651 (offset), (addr), (count))
652 #define ATA_OUTB(res, offset, value) \
653 bus_space_write_1(rman_get_bustag((res)), \
654 rman_get_bushandle((res)), (offset), (value))
655 #define ATA_OUTW(res, offset, value) \
656 bus_space_write_2(rman_get_bustag((res)), \
657 rman_get_bushandle((res)), (offset), (value))
658 #define ATA_OUTL(res, offset, value) \
659 bus_space_write_4(rman_get_bustag((res)), \
660 rman_get_bushandle((res)), (offset), (value))
661 #define ATA_OUTSW(res, offset, addr, count) \
662 bus_space_write_multi_2(rman_get_bustag((res)), \
663 rman_get_bushandle((res)), \
664 (offset), (addr), (count))
665 #define ATA_OUTSW_STRM(res, offset, addr, count) \
666 bus_space_write_multi_stream_2(rman_get_bustag((res)), \
667 rman_get_bushandle((res)), \
668 (offset), (addr), (count))
669 #define ATA_OUTSL(res, offset, addr, count) \
670 bus_space_write_multi_4(rman_get_bustag((res)), \
671 rman_get_bushandle((res)), \
672 (offset), (addr), (count))
673 #define ATA_OUTSL_STRM(res, offset, addr, count) \
674 bus_space_write_multi_stream_4(rman_get_bustag((res)), \
675 rman_get_bushandle((res)), \
676 (offset), (addr), (count))
677
678 #define ATA_IDX_INB(ch, idx) \
679 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
680
681 #define ATA_IDX_INW(ch, idx) \
682 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
683
684 #define ATA_IDX_INL(ch, idx) \
685 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
686
687 #define ATA_IDX_INSW(ch, idx, addr, count) \
688 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
689
690 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
691 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
692
693 #define ATA_IDX_INSL(ch, idx, addr, count) \
694 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
695
696 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
697 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
698
699 #define ATA_IDX_OUTB(ch, idx, value) \
700 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
701
702 #define ATA_IDX_OUTW(ch, idx, value) \
703 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
704
705 #define ATA_IDX_OUTL(ch, idx, value) \
706 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
707
708 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
709 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
710
711 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
712 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
713
714 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
715 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
716
717 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
718 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
DragonFly BSD