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Rewrite the polling code. Instead of trying to do fancy polling enablement
[dragonfly.git] / sys / dev / netif / nge / if_nge.c
blob6d8e2890d497183c3ada8ab7a6865aaea436b9f6
1 /*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.24 2005/05/25 01:44:26 dillon Exp $
35 */
36
37 /*
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
40 *
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
43 *
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
48 *
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
52 * components:
53 *
54 * http://www.national.com/ds/DP/DP83861.pdf
55 *
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
58 */
59
60 /*
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
71 * descriptors.
72 *
73 * There are two bugs/misfeatures in the 83820/83821 that I have
74 * discovered so far:
75 *
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
78 * alignment.
79 *
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
86 *
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
89 */
90
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
94 #include <sys/mbuf.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98
99 #include <net/if.h>
100 #include <net/ifq_var.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
106 #include <net/vlan/if_vlan_var.h>
107
108 #include <net/bpf.h>
109
110 #include <vm/vm.h> /* for vtophys */
111 #include <vm/pmap.h> /* for vtophys */
112 #include <machine/bus.h>
113 #include <machine/resource.h>
114 #include <sys/bus.h>
115 #include <sys/rman.h>
116
117 #include <dev/netif/mii_layer/mii.h>
118 #include <dev/netif/mii_layer/miivar.h>
119
120 #include <bus/pci/pcireg.h>
121 #include <bus/pci/pcivar.h>
122
123 #define NGE_USEIOSPACE
124
125 #include "if_ngereg.h"
126
127
128 /* "controller miibus0" required. See GENERIC if you get errors here. */
129 #include "miibus_if.h"
130
131 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
132
133 /*
134 * Various supported device vendors/types and their names.
135 */
136 static struct nge_type nge_devs[] = {
137 { NGE_VENDORID, NGE_DEVICEID,
138 "National Semiconductor Gigabit Ethernet" },
139 { 0, 0, NULL }
140 };
141
142 static int nge_probe(device_t);
143 static int nge_attach(device_t);
144 static int nge_detach(device_t);
145
146 static int nge_alloc_jumbo_mem(struct nge_softc *);
147 static void nge_free_jumbo_mem(struct nge_softc *);
148 static void *nge_jalloc(struct nge_softc *);
149 static void nge_jfree(caddr_t, u_int);
150 static void nge_jref(caddr_t, u_int);
151
152 static int nge_newbuf(struct nge_softc *,
153 struct nge_desc *, struct mbuf *);
154 static int nge_encap(struct nge_softc *,
155 struct mbuf *, uint32_t *);
156 static void nge_rxeof(struct nge_softc *);
157 static void nge_txeof(struct nge_softc *);
158 static void nge_intr(void *);
159 static void nge_tick(void *);
160 static void nge_start(struct ifnet *);
161 static int nge_ioctl(struct ifnet *, u_long, caddr_t,
162 struct ucred *);
163 static void nge_init(void *);
164 static void nge_stop(struct nge_softc *);
165 static void nge_watchdog(struct ifnet *);
166 static void nge_shutdown(device_t);
167 static int nge_ifmedia_upd(struct ifnet *);
168 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
169
170 static void nge_delay(struct nge_softc *);
171 static void nge_eeprom_idle(struct nge_softc *);
172 static void nge_eeprom_putbyte(struct nge_softc *, int);
173 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
174 static void nge_read_eeprom(struct nge_softc *, void *, int, int);
175
176 static void nge_mii_sync(struct nge_softc *);
177 static void nge_mii_send(struct nge_softc *, uint32_t, int);
178 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
179 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
180
181 static int nge_miibus_readreg(device_t, int, int);
182 static int nge_miibus_writereg(device_t, int, int, int);
183 static void nge_miibus_statchg(device_t);
184
185 static void nge_setmulti(struct nge_softc *);
186 static void nge_reset(struct nge_softc *);
187 static int nge_list_rx_init(struct nge_softc *);
188 static int nge_list_tx_init(struct nge_softc *);
189 #ifdef DEVICE_POLLING
190 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
191 #endif
192
193 #ifdef NGE_USEIOSPACE
194 #define NGE_RES SYS_RES_IOPORT
195 #define NGE_RID NGE_PCI_LOIO
196 #else
197 #define NGE_RES SYS_RES_MEMORY
198 #define NGE_RID NGE_PCI_LOMEM
199 #endif
200
201 static device_method_t nge_methods[] = {
202 /* Device interface */
203 DEVMETHOD(device_probe, nge_probe),
204 DEVMETHOD(device_attach, nge_attach),
205 DEVMETHOD(device_detach, nge_detach),
206 DEVMETHOD(device_shutdown, nge_shutdown),
207
208 /* bus interface */
209 DEVMETHOD(bus_print_child, bus_generic_print_child),
210 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
211
212 /* MII interface */
213 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
214 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
215 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
216
217 { 0, 0 }
218 };
219
220 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
221 static devclass_t nge_devclass;
222
223 DECLARE_DUMMY_MODULE(if_nge);
224 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
225 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
226 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
227
228 #define NGE_SETBIT(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
230
231 #define NGE_CLRBIT(sc, reg, x) \
232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
233
234 #define SIO_SET(x) \
235 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
236
237 #define SIO_CLR(x) \
238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
239
240 static void
241 nge_delay(struct nge_softc *sc)
242 {
243 int idx;
244
245 for (idx = (300 / 33) + 1; idx > 0; idx--)
246 CSR_READ_4(sc, NGE_CSR);
247 }
248
249 static void
250 nge_eeprom_idle(struct nge_softc *sc)
251 {
252 int i;
253
254 SIO_SET(NGE_MEAR_EE_CSEL);
255 nge_delay(sc);
256 SIO_SET(NGE_MEAR_EE_CLK);
257 nge_delay(sc);
258
259 for (i = 0; i < 25; i++) {
260 SIO_CLR(NGE_MEAR_EE_CLK);
261 nge_delay(sc);
262 SIO_SET(NGE_MEAR_EE_CLK);
263 nge_delay(sc);
264 }
265
266 SIO_CLR(NGE_MEAR_EE_CLK);
267 nge_delay(sc);
268 SIO_CLR(NGE_MEAR_EE_CSEL);
269 nge_delay(sc);
270 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
271 }
272
273 /*
274 * Send a read command and address to the EEPROM, check for ACK.
275 */
276 static void
277 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
278 {
279 int d, i;
280
281 d = addr | NGE_EECMD_READ;
282
283 /*
284 * Feed in each bit and stobe the clock.
285 */
286 for (i = 0x400; i; i >>= 1) {
287 if (d & i)
288 SIO_SET(NGE_MEAR_EE_DIN);
289 else
290 SIO_CLR(NGE_MEAR_EE_DIN);
291 nge_delay(sc);
292 SIO_SET(NGE_MEAR_EE_CLK);
293 nge_delay(sc);
294 SIO_CLR(NGE_MEAR_EE_CLK);
295 nge_delay(sc);
296 }
297 }
298
299 /*
300 * Read a word of data stored in the EEPROM at address 'addr.'
301 */
302 static void
303 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
304 {
305 int i;
306 uint16_t word = 0;
307
308 /* Force EEPROM to idle state. */
309 nge_eeprom_idle(sc);
310
311 /* Enter EEPROM access mode. */
312 nge_delay(sc);
313 SIO_CLR(NGE_MEAR_EE_CLK);
314 nge_delay(sc);
315 SIO_SET(NGE_MEAR_EE_CSEL);
316 nge_delay(sc);
317
318 /*
319 * Send address of word we want to read.
320 */
321 nge_eeprom_putbyte(sc, addr);
322
323 /*
324 * Start reading bits from EEPROM.
325 */
326 for (i = 0x8000; i; i >>= 1) {
327 SIO_SET(NGE_MEAR_EE_CLK);
328 nge_delay(sc);
329 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
330 word |= i;
331 nge_delay(sc);
332 SIO_CLR(NGE_MEAR_EE_CLK);
333 nge_delay(sc);
334 }
335
336 /* Turn off EEPROM access mode. */
337 nge_eeprom_idle(sc);
338
339 *dest = word;
340 }
341
342 /*
343 * Read a sequence of words from the EEPROM.
344 */
345 static void
346 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
347 {
348 int i;
349 uint16_t word = 0, *ptr;
350
351 for (i = 0; i < cnt; i++) {
352 nge_eeprom_getword(sc, off + i, &word);
353 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
354 *ptr = word;
355 }
356 }
357
358 /*
359 * Sync the PHYs by setting data bit and strobing the clock 32 times.
360 */
361 static void
362 nge_mii_sync(struct nge_softc *sc)
363 {
364 int i;
365
366 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
367
368 for (i = 0; i < 32; i++) {
369 SIO_SET(NGE_MEAR_MII_CLK);
370 DELAY(1);
371 SIO_CLR(NGE_MEAR_MII_CLK);
372 DELAY(1);
373 }
374 }
375
376 /*
377 * Clock a series of bits through the MII.
378 */
379 static void
380 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
381 {
382 int i;
383
384 SIO_CLR(NGE_MEAR_MII_CLK);
385
386 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
387 if (bits & i)
388 SIO_SET(NGE_MEAR_MII_DATA);
389 else
390 SIO_CLR(NGE_MEAR_MII_DATA);
391 DELAY(1);
392 SIO_CLR(NGE_MEAR_MII_CLK);
393 DELAY(1);
394 SIO_SET(NGE_MEAR_MII_CLK);
395 }
396 }
397
398 /*
399 * Read an PHY register through the MII.
400 */
401 static int
402 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
403 {
404 int ack, i, s;
405
406 s = splimp();
407
408 /*
409 * Set up frame for RX.
410 */
411 frame->mii_stdelim = NGE_MII_STARTDELIM;
412 frame->mii_opcode = NGE_MII_READOP;
413 frame->mii_turnaround = 0;
414 frame->mii_data = 0;
415
416 CSR_WRITE_4(sc, NGE_MEAR, 0);
417
418 /*
419 * Turn on data xmit.
420 */
421 SIO_SET(NGE_MEAR_MII_DIR);
422
423 nge_mii_sync(sc);
424
425 /*
426 * Send command/address info.
427 */
428 nge_mii_send(sc, frame->mii_stdelim, 2);
429 nge_mii_send(sc, frame->mii_opcode, 2);
430 nge_mii_send(sc, frame->mii_phyaddr, 5);
431 nge_mii_send(sc, frame->mii_regaddr, 5);
432
433 /* Idle bit */
434 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
435 DELAY(1);
436 SIO_SET(NGE_MEAR_MII_CLK);
437 DELAY(1);
438
439 /* Turn off xmit. */
440 SIO_CLR(NGE_MEAR_MII_DIR);
441 /* Check for ack */
442 SIO_CLR(NGE_MEAR_MII_CLK);
443 DELAY(1);
444 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
445 SIO_SET(NGE_MEAR_MII_CLK);
446 DELAY(1);
447
448 /*
449 * Now try reading data bits. If the ack failed, we still
450 * need to clock through 16 cycles to keep the PHY(s) in sync.
451 */
452 if (ack) {
453 for(i = 0; i < 16; i++) {
454 SIO_CLR(NGE_MEAR_MII_CLK);
455 DELAY(1);
456 SIO_SET(NGE_MEAR_MII_CLK);
457 DELAY(1);
458 }
459 goto fail;
460 }
461
462 for (i = 0x8000; i; i >>= 1) {
463 SIO_CLR(NGE_MEAR_MII_CLK);
464 DELAY(1);
465 if (!ack) {
466 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
467 frame->mii_data |= i;
468 DELAY(1);
469 }
470 SIO_SET(NGE_MEAR_MII_CLK);
471 DELAY(1);
472 }
473
474 fail:
475 SIO_CLR(NGE_MEAR_MII_CLK);
476 DELAY(1);
477 SIO_SET(NGE_MEAR_MII_CLK);
478 DELAY(1);
479
480 splx(s);
481
482 if (ack)
483 return(1);
484 return(0);
485 }
486
487 /*
488 * Write to a PHY register through the MII.
489 */
490 static int
491 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
492 {
493 int s;
494
495 s = splimp();
496 /*
497 * Set up frame for TX.
498 */
499
500 frame->mii_stdelim = NGE_MII_STARTDELIM;
501 frame->mii_opcode = NGE_MII_WRITEOP;
502 frame->mii_turnaround = NGE_MII_TURNAROUND;
503
504 /*
505 * Turn on data output.
506 */
507 SIO_SET(NGE_MEAR_MII_DIR);
508
509 nge_mii_sync(sc);
510
511 nge_mii_send(sc, frame->mii_stdelim, 2);
512 nge_mii_send(sc, frame->mii_opcode, 2);
513 nge_mii_send(sc, frame->mii_phyaddr, 5);
514 nge_mii_send(sc, frame->mii_regaddr, 5);
515 nge_mii_send(sc, frame->mii_turnaround, 2);
516 nge_mii_send(sc, frame->mii_data, 16);
517
518 /* Idle bit. */
519 SIO_SET(NGE_MEAR_MII_CLK);
520 DELAY(1);
521 SIO_CLR(NGE_MEAR_MII_CLK);
522 DELAY(1);
523
524 /*
525 * Turn off xmit.
526 */
527 SIO_CLR(NGE_MEAR_MII_DIR);
528
529 splx(s);
530
531 return(0);
532 }
533
534 static int
535 nge_miibus_readreg(device_t dev, int phy, int reg)
536 {
537 struct nge_softc *sc = device_get_softc(dev);
538 struct nge_mii_frame frame;
539
540 bzero((char *)&frame, sizeof(frame));
541
542 frame.mii_phyaddr = phy;
543 frame.mii_regaddr = reg;
544 nge_mii_readreg(sc, &frame);
545
546 return(frame.mii_data);
547 }
548
549 static int
550 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
551 {
552 struct nge_softc *sc = device_get_softc(dev);
553 struct nge_mii_frame frame;
554
555 bzero((char *)&frame, sizeof(frame));
556
557 frame.mii_phyaddr = phy;
558 frame.mii_regaddr = reg;
559 frame.mii_data = data;
560 nge_mii_writereg(sc, &frame);
561
562 return(0);
563 }
564
565 static void
566 nge_miibus_statchg(device_t dev)
567 {
568 struct nge_softc *sc = device_get_softc(dev);
569 struct mii_data *mii;
570 int status;
571
572 if (sc->nge_tbi) {
573 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
574 == IFM_AUTO) {
575 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
576 if (status == 0 || status & NGE_TBIANAR_FDX) {
577 NGE_SETBIT(sc, NGE_TX_CFG,
578 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
579 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
580 } else {
581 NGE_CLRBIT(sc, NGE_TX_CFG,
582 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
583 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
584 }
585 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
586 != IFM_FDX) {
587 NGE_CLRBIT(sc, NGE_TX_CFG,
588 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
589 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
590 } else {
591 NGE_SETBIT(sc, NGE_TX_CFG,
592 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
593 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
594 }
595 } else {
596 mii = device_get_softc(sc->nge_miibus);
597
598 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
599 NGE_SETBIT(sc, NGE_TX_CFG,
600 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
601 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
602 } else {
603 NGE_CLRBIT(sc, NGE_TX_CFG,
604 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
605 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
606 }
607
608 /* If we have a 1000Mbps link, set the mode_1000 bit. */
609 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
610 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
611 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
612 } else {
613 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
614 }
615 }
616 }
617
618 static void
619 nge_setmulti(struct nge_softc *sc)
620 {
621 struct ifnet *ifp = &sc->arpcom.ac_if;
622 struct ifmultiaddr *ifma;
623 uint32_t filtsave, h = 0, i;
624 int bit, index;
625
626 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
627 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
628 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
629 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
630 return;
631 }
632
633 /*
634 * We have to explicitly enable the multicast hash table
635 * on the NatSemi chip if we want to use it, which we do.
636 * We also have to tell it that we don't want to use the
637 * hash table for matching unicast addresses.
638 */
639 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
640 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
641 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
642
643 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
644
645 /* first, zot all the existing hash bits */
646 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
647 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
648 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
649 }
650
651 /*
652 * From the 11 bits returned by the crc routine, the top 7
653 * bits represent the 16-bit word in the mcast hash table
654 * that needs to be updated, and the lower 4 bits represent
655 * which bit within that byte needs to be set.
656 */
657 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
658 if (ifma->ifma_addr->sa_family != AF_LINK)
659 continue;
660 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
661 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
662 index = (h >> 4) & 0x7F;
663 bit = h & 0xF;
664 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
665 NGE_FILTADDR_MCAST_LO + (index * 2));
666 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
667 }
668
669 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
670 }
671
672 static void
673 nge_reset(struct nge_softc *sc)
674 {
675 int i;
676
677 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
678
679 for (i = 0; i < NGE_TIMEOUT; i++) {
680 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
681 break;
682 }
683
684 if (i == NGE_TIMEOUT)
685 printf("nge%d: reset never completed\n", sc->nge_unit);
686
687 /* Wait a little while for the chip to get its brains in order. */
688 DELAY(1000);
689
690 /*
691 * If this is a NetSemi chip, make sure to clear
692 * PME mode.
693 */
694 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
695 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
696 }
697
698 /*
699 * Probe for an NatSemi chip. Check the PCI vendor and device
700 * IDs against our list and return a device name if we find a match.
701 */
702 static int
703 nge_probe(device_t dev)
704 {
705 struct nge_type *t;
706 uint16_t vendor, product;
707
708 vendor = pci_get_vendor(dev);
709 product = pci_get_device(dev);
710
711 for (t = nge_devs; t->nge_name != NULL; t++) {
712 if (vendor == t->nge_vid && product == t->nge_did) {
713 device_set_desc(dev, t->nge_name);
714 return(0);
715 }
716 }
717
718 return(ENXIO);
719 }
720
721 /*
722 * Attach the interface. Allocate softc structures, do ifmedia
723 * setup and ethernet/BPF attach.
724 */
725 static int
726 nge_attach(device_t dev)
727 {
728 struct nge_softc *sc;
729 struct ifnet *ifp;
730 uint8_t eaddr[ETHER_ADDR_LEN];
731 uint32_t command;
732 int error = 0, rid, s, unit;
733 const char *sep = "";
734
735 s = splimp();
736
737 sc = device_get_softc(dev);
738 unit = device_get_unit(dev);
739 callout_init(&sc->nge_stat_timer);
740
741 /*
742 * Handle power management nonsense.
743 */
744 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
745 if (command == 0x01) {
746 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
747 if (command & NGE_PSTATE_MASK) {
748 uint32_t iobase, membase, irq;
749
750 /* Save important PCI config data. */
751 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
752 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
753 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
754
755 /* Reset the power state. */
756 printf("nge%d: chip is in D%d power mode "
757 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
758 command &= 0xFFFFFFFC;
759 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
760
761 /* Restore PCI config data. */
762 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
763 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
764 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
765 }
766 }
767
768 /*
769 * Map control/status registers.
770 */
771 command = pci_read_config(dev, PCIR_COMMAND, 4);
772 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
773 pci_write_config(dev, PCIR_COMMAND, command, 4);
774 command = pci_read_config(dev, PCIR_COMMAND, 4);
775
776 #ifdef NGE_USEIOSPACE
777 if (!(command & PCIM_CMD_PORTEN)) {
778 printf("nge%d: failed to enable I/O ports!\n", unit);
779 error = ENXIO;;
780 goto fail;
781 }
782 #else
783 if (!(command & PCIM_CMD_MEMEN)) {
784 printf("nge%d: failed to enable memory mapping!\n", unit);
785 error = ENXIO;;
786 goto fail;
787 }
788 #endif
789
790 rid = NGE_RID;
791 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
792
793 if (sc->nge_res == NULL) {
794 printf("nge%d: couldn't map ports/memory\n", unit);
795 error = ENXIO;
796 goto fail;
797 }
798
799 sc->nge_btag = rman_get_bustag(sc->nge_res);
800 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
801
802 /* Allocate interrupt */
803 rid = 0;
804 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
805 RF_SHAREABLE | RF_ACTIVE);
806
807 if (sc->nge_irq == NULL) {
808 printf("nge%d: couldn't map interrupt\n", unit);
809 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
810 error = ENXIO;
811 goto fail;
812 }
813
814 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
815 nge_intr, sc, &sc->nge_intrhand, NULL);
816
817 if (error) {
818 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
819 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
820 printf("nge%d: couldn't set up irq\n", unit);
821 goto fail;
822 }
823
824 /* Reset the adapter. */
825 nge_reset(sc);
826
827 /*
828 * Get station address from the EEPROM.
829 */
830 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
831 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
832 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
833
834 sc->nge_unit = unit;
835
836 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
837 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
838
839 if (sc->nge_ldata == NULL) {
840 printf("nge%d: no memory for list buffers!\n", unit);
841 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
842 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
843 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
844 error = ENXIO;
845 goto fail;
846 }
847 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
848
849 /* Try to allocate memory for jumbo buffers. */
850 if (nge_alloc_jumbo_mem(sc)) {
851 printf("nge%d: jumbo buffer allocation failed\n",
852 sc->nge_unit);
853 contigfree(sc->nge_ldata,
854 sizeof(struct nge_list_data), M_DEVBUF);
855 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
856 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
857 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
858 error = ENXIO;
859 goto fail;
860 }
861
862 ifp = &sc->arpcom.ac_if;
863 ifp->if_softc = sc;
864 if_initname(ifp, "nge", unit);
865 ifp->if_mtu = ETHERMTU;
866 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
867 ifp->if_ioctl = nge_ioctl;
868 ifp->if_start = nge_start;
869 #ifdef DEVICE_POLLING
870 ifp->if_poll = nge_poll;
871 #endif
872 ifp->if_watchdog = nge_watchdog;
873 ifp->if_init = nge_init;
874 ifp->if_baudrate = 1000000000;
875 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
876 ifq_set_ready(&ifp->if_snd);
877 ifp->if_hwassist = NGE_CSUM_FEATURES;
878 ifp->if_capabilities = IFCAP_HWCSUM;
879 ifp->if_capenable = ifp->if_capabilities;
880
881 /*
882 * Do MII setup.
883 */
884 if (mii_phy_probe(dev, &sc->nge_miibus,
885 nge_ifmedia_upd, nge_ifmedia_sts)) {
886 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
887 sc->nge_tbi = 1;
888 device_printf(dev, "Using TBI\n");
889
890 sc->nge_miibus = dev;
891
892 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
893 nge_ifmedia_sts);
894 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
895 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
896 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
897 device_printf(dev, " ");
898 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
899 PRINT("1000baseSX");
900 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
901 PRINT("1000baseSX-FDX");
902 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
903 PRINT("auto");
904
905 printf("\n");
906 #undef ADD
907 #undef PRINT
908 ifmedia_set(&sc->nge_ifmedia,
909 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
910
911 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
912 | NGE_GPIO_GP4_OUT
913 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
914 | NGE_GPIO_GP3_OUTENB
915 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
916
917 } else {
918 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
919 nge_free_jumbo_mem(sc);
920 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
921 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
922 bus_release_resource(dev, NGE_RES, NGE_RID,
923 sc->nge_res);
924 error = ENXIO;
925 goto fail;
926 }
927 }
928
929 /*
930 * Call MI attach routine.
931 */
932 ether_ifattach(ifp, eaddr);
933
934 fail:
935
936 splx(s);
937 return(error);
938 }
939
940 static int
941 nge_detach(device_t dev)
942 {
943 struct nge_softc *sc;
944 struct ifnet *ifp;
945 int s;
946
947 s = splimp();
948
949 sc = device_get_softc(dev);
950 ifp = &sc->arpcom.ac_if;
951
952 nge_reset(sc);
953 nge_stop(sc);
954 ether_ifdetach(ifp);
955
956 bus_generic_detach(dev);
957 if (!sc->nge_tbi)
958 device_delete_child(dev, sc->nge_miibus);
959
960 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
961 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
962 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
963
964 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
965 nge_free_jumbo_mem(sc);
966
967 splx(s);
968
969 return(0);
970 }
971
972 /*
973 * Initialize the transmit descriptors.
974 */
975 static int
976 nge_list_tx_init(struct nge_softc *sc)
977 {
978 struct nge_list_data *ld;
979 struct nge_ring_data *cd;
980 int i;
981
982 cd = &sc->nge_cdata;
983 ld = sc->nge_ldata;
984
985 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
986 if (i == (NGE_TX_LIST_CNT - 1)) {
987 ld->nge_tx_list[i].nge_nextdesc =
988 &ld->nge_tx_list[0];
989 ld->nge_tx_list[i].nge_next =
990 vtophys(&ld->nge_tx_list[0]);
991 } else {
992 ld->nge_tx_list[i].nge_nextdesc =
993 &ld->nge_tx_list[i + 1];
994 ld->nge_tx_list[i].nge_next =
995 vtophys(&ld->nge_tx_list[i + 1]);
996 }
997 ld->nge_tx_list[i].nge_mbuf = NULL;
998 ld->nge_tx_list[i].nge_ptr = 0;
999 ld->nge_tx_list[i].nge_ctl = 0;
1000 }
1001
1002 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1003
1004 return(0);
1005 }
1006
1007
1008 /*
1009 * Initialize the RX descriptors and allocate mbufs for them. Note that
1010 * we arrange the descriptors in a closed ring, so that the last descriptor
1011 * points back to the first.
1012 */
1013 static int
1014 nge_list_rx_init(struct nge_softc *sc)
1015 {
1016 struct nge_list_data *ld;
1017 struct nge_ring_data *cd;
1018 int i;
1019
1020 ld = sc->nge_ldata;
1021 cd = &sc->nge_cdata;
1022
1023 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1024 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1025 return(ENOBUFS);
1026 if (i == (NGE_RX_LIST_CNT - 1)) {
1027 ld->nge_rx_list[i].nge_nextdesc =
1028 &ld->nge_rx_list[0];
1029 ld->nge_rx_list[i].nge_next =
1030 vtophys(&ld->nge_rx_list[0]);
1031 } else {
1032 ld->nge_rx_list[i].nge_nextdesc =
1033 &ld->nge_rx_list[i + 1];
1034 ld->nge_rx_list[i].nge_next =
1035 vtophys(&ld->nge_rx_list[i + 1]);
1036 }
1037 }
1038
1039 cd->nge_rx_prod = 0;
1040
1041 return(0);
1042 }
1043
1044 /*
1045 * Initialize an RX descriptor and attach an MBUF cluster.
1046 */
1047 static int
1048 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1049 {
1050 struct mbuf *m_new = NULL;
1051 caddr_t *buf = NULL;
1052
1053 if (m == NULL) {
1054 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1055 if (m_new == NULL) {
1056 printf("nge%d: no memory for rx list "
1057 "-- packet dropped!\n", sc->nge_unit);
1058 return(ENOBUFS);
1059 }
1060
1061 /* Allocate the jumbo buffer */
1062 buf = nge_jalloc(sc);
1063 if (buf == NULL) {
1064 #ifdef NGE_VERBOSE
1065 printf("nge%d: jumbo allocation failed "
1066 "-- packet dropped!\n", sc->nge_unit);
1067 #endif
1068 m_freem(m_new);
1069 return(ENOBUFS);
1070 }
1071 /* Attach the buffer to the mbuf */
1072 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
1073 m_new->m_flags |= M_EXT | M_EXT_OLD;
1074 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1075 m_new->m_len = NGE_MCLBYTES;
1076 m_new->m_ext.ext_nfree.old = nge_jfree;
1077 m_new->m_ext.ext_nref.old = nge_jref;
1078 } else {
1079 m_new = m;
1080 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES;
1081 m_new->m_data = m_new->m_ext.ext_buf;
1082 }
1083
1084 m_adj(m_new, sizeof(uint64_t));
1085
1086 c->nge_mbuf = m_new;
1087 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1088 c->nge_ctl = m_new->m_len;
1089 c->nge_extsts = 0;
1090
1091 return(0);
1092 }
1093
1094 static int
1095 nge_alloc_jumbo_mem(struct nge_softc *sc)
1096 {
1097 caddr_t ptr;
1098 int i;
1099 struct nge_jpool_entry *entry;
1100
1101 /* Grab a big chunk o' storage. */
1102 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1103 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1104
1105 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1106 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1107 return(ENOBUFS);
1108 }
1109
1110 SLIST_INIT(&sc->nge_jfree_listhead);
1111 SLIST_INIT(&sc->nge_jinuse_listhead);
1112
1113 /*
1114 * Now divide it up into 9K pieces and save the addresses
1115 * in an array.
1116 */
1117 ptr = sc->nge_cdata.nge_jumbo_buf;
1118 for (i = 0; i < NGE_JSLOTS; i++) {
1119 uint64_t **aptr;
1120 aptr = (uint64_t **)ptr;
1121 aptr[0] = (uint64_t *)sc;
1122 ptr += sizeof(uint64_t);
1123 sc->nge_cdata.nge_jslots[i].nge_buf = ptr;
1124 sc->nge_cdata.nge_jslots[i].nge_inuse = 0;
1125 ptr += NGE_MCLBYTES;
1126 entry = malloc(sizeof(struct nge_jpool_entry),
1127 M_DEVBUF, M_WAITOK);
1128 if (entry == NULL) {
1129 printf("nge%d: no memory for jumbo "
1130 "buffer queue!\n", sc->nge_unit);
1131 return(ENOBUFS);
1132 }
1133 entry->slot = i;
1134 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1135 entry, jpool_entries);
1136 }
1137
1138 return(0);
1139 }
1140
1141 static void
1142 nge_free_jumbo_mem(struct nge_softc *sc)
1143 {
1144 int i;
1145 struct nge_jpool_entry *entry;
1146
1147 for (i = 0; i < NGE_JSLOTS; i++) {
1148 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1149 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1150 free(entry, M_DEVBUF);
1151 }
1152
1153 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
1154 }
1155
1156 /*
1157 * Allocate a jumbo buffer.
1158 */
1159 static void *
1160 nge_jalloc(struct nge_softc *sc)
1161 {
1162 struct nge_jpool_entry *entry;
1163
1164 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1165
1166 if (entry == NULL) {
1167 #ifdef NGE_VERBOSE
1168 printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1169 #endif
1170 return(NULL);
1171 }
1172
1173 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1174 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries);
1175 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1;
1176 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf);
1177 }
1178
1179 /*
1180 * Adjust usage count on a jumbo buffer. In general this doesn't
1181 * get used much because our jumbo buffers don't get passed around
1182 * a lot, but it's implemented for correctness.
1183 */
1184 static void
1185 nge_jref(caddr_t buf, u_int size)
1186 {
1187 struct nge_softc *sc;
1188 uint64_t **aptr;
1189 int i;
1190
1191 /* Extract the softc struct pointer. */
1192 aptr = (uint64_t **)(buf - sizeof(uint64_t));
1193 sc = (struct nge_softc *)(aptr[0]);
1194
1195 if (sc == NULL)
1196 panic("nge_jref: can't find softc pointer!");
1197
1198 if (size != NGE_MCLBYTES)
1199 panic("nge_jref: adjusting refcount of buf of wrong size!");
1200
1201 /* calculate the slot this buffer belongs to */
1202
1203 i = ((vm_offset_t)aptr
1204 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
1205
1206 if ((i < 0) || (i >= NGE_JSLOTS))
1207 panic("nge_jref: asked to reference buffer "
1208 "that we don't manage!");
1209 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0)
1210 panic("nge_jref: buffer already free!");
1211 else
1212 sc->nge_cdata.nge_jslots[i].nge_inuse++;
1213 }
1214
1215 /*
1216 * Release a jumbo buffer.
1217 */
1218 static void
1219 nge_jfree(caddr_t buf, u_int size)
1220 {
1221 struct nge_softc *sc;
1222 uint64_t **aptr;
1223 int i;
1224 struct nge_jpool_entry *entry;
1225
1226 /* Extract the softc struct pointer. */
1227 aptr = (uint64_t **)(buf - sizeof(uint64_t));
1228 sc = (struct nge_softc *)(aptr[0]);
1229
1230 if (sc == NULL)
1231 panic("nge_jfree: can't find softc pointer!");
1232
1233 if (size != NGE_MCLBYTES)
1234 panic("nge_jfree: freeing buffer of wrong size!");
1235
1236 /* calculate the slot this buffer belongs to */
1237
1238 i = ((vm_offset_t)aptr
1239 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
1240
1241 if ((i < 0) || (i >= NGE_JSLOTS))
1242 panic("nge_jfree: asked to free buffer that we don't manage!");
1243 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0)
1244 panic("nge_jfree: buffer already free!");
1245 else {
1246 sc->nge_cdata.nge_jslots[i].nge_inuse--;
1247 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) {
1248 entry = SLIST_FIRST(&sc->nge_jinuse_listhead);
1249 if (entry == NULL)
1250 panic("nge_jfree: buffer not in use!");
1251 entry->slot = i;
1252 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead,
1253 jpool_entries);
1254 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1255 entry, jpool_entries);
1256 }
1257 }
1258 }
1259 /*
1260 * A frame has been uploaded: pass the resulting mbuf chain up to
1261 * the higher level protocols.
1262 */
1263 static void
1264 nge_rxeof(struct nge_softc *sc)
1265 {
1266 struct mbuf *m;
1267 struct ifnet *ifp = &sc->arpcom.ac_if;
1268 struct nge_desc *cur_rx;
1269 int i, total_len = 0;
1270 uint32_t rxstat;
1271
1272 i = sc->nge_cdata.nge_rx_prod;
1273
1274 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1275 struct mbuf *m0 = NULL;
1276 uint32_t extsts;
1277
1278 #ifdef DEVICE_POLLING
1279 if (ifp->if_flags & IFF_POLLING) {
1280 if (sc->rxcycles <= 0)
1281 break;
1282 sc->rxcycles--;
1283 }
1284 #endif /* DEVICE_POLLING */
1285
1286 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1287 rxstat = cur_rx->nge_rxstat;
1288 extsts = cur_rx->nge_extsts;
1289 m = cur_rx->nge_mbuf;
1290 cur_rx->nge_mbuf = NULL;
1291 total_len = NGE_RXBYTES(cur_rx);
1292 NGE_INC(i, NGE_RX_LIST_CNT);
1293 /*
1294 * If an error occurs, update stats, clear the
1295 * status word and leave the mbuf cluster in place:
1296 * it should simply get re-used next time this descriptor
1297 * comes up in the ring.
1298 */
1299 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1300 ifp->if_ierrors++;
1301 nge_newbuf(sc, cur_rx, m);
1302 continue;
1303 }
1304
1305 /*
1306 * Ok. NatSemi really screwed up here. This is the
1307 * only gigE chip I know of with alignment constraints
1308 * on receive buffers. RX buffers must be 64-bit aligned.
1309 */
1310 #ifdef __i386__
1311 /*
1312 * By popular demand, ignore the alignment problems
1313 * on the Intel x86 platform. The performance hit
1314 * incurred due to unaligned accesses is much smaller
1315 * than the hit produced by forcing buffer copies all
1316 * the time, especially with jumbo frames. We still
1317 * need to fix up the alignment everywhere else though.
1318 */
1319 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1320 #endif
1321 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1322 total_len + ETHER_ALIGN, 0, ifp, NULL);
1323 nge_newbuf(sc, cur_rx, m);
1324 if (m0 == NULL) {
1325 printf("nge%d: no receive buffers "
1326 "available -- packet dropped!\n",
1327 sc->nge_unit);
1328 ifp->if_ierrors++;
1329 continue;
1330 }
1331 m_adj(m0, ETHER_ALIGN);
1332 m = m0;
1333 #ifdef __i386__
1334 } else {
1335 m->m_pkthdr.rcvif = ifp;
1336 m->m_pkthdr.len = m->m_len = total_len;
1337 }
1338 #endif
1339
1340 ifp->if_ipackets++;
1341
1342 /* Do IP checksum checking. */
1343 if (extsts & NGE_RXEXTSTS_IPPKT)
1344 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1345 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1346 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1347 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1348 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1349 (extsts & NGE_RXEXTSTS_UDPPKT &&
1350 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1351 m->m_pkthdr.csum_flags |=
1352 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1353 m->m_pkthdr.csum_data = 0xffff;
1354 }
1355
1356 /*
1357 * If we received a packet with a vlan tag, pass it
1358 * to vlan_input() instead of ether_input().
1359 */
1360 if (extsts & NGE_RXEXTSTS_VLANPKT)
1361 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI);
1362 else
1363 (*ifp->if_input)(ifp, m);
1364 }
1365
1366 sc->nge_cdata.nge_rx_prod = i;
1367 }
1368
1369 /*
1370 * A frame was downloaded to the chip. It's safe for us to clean up
1371 * the list buffers.
1372 */
1373 static void
1374 nge_txeof(struct nge_softc *sc)
1375 {
1376 struct ifnet *ifp = &sc->arpcom.ac_if;
1377 struct nge_desc *cur_tx = NULL;
1378 uint32_t idx;
1379
1380 /* Clear the timeout timer. */
1381 ifp->if_timer = 0;
1382
1383 /*
1384 * Go through our tx list and free mbufs for those
1385 * frames that have been transmitted.
1386 */
1387 idx = sc->nge_cdata.nge_tx_cons;
1388 while (idx != sc->nge_cdata.nge_tx_prod) {
1389 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1390
1391 if (NGE_OWNDESC(cur_tx))
1392 break;
1393
1394 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1395 sc->nge_cdata.nge_tx_cnt--;
1396 NGE_INC(idx, NGE_TX_LIST_CNT);
1397 continue;
1398 }
1399
1400 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1401 ifp->if_oerrors++;
1402 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1403 ifp->if_collisions++;
1404 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1405 ifp->if_collisions++;
1406 }
1407
1408 ifp->if_collisions +=
1409 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1410
1411 ifp->if_opackets++;
1412 if (cur_tx->nge_mbuf != NULL) {
1413 m_freem(cur_tx->nge_mbuf);
1414 cur_tx->nge_mbuf = NULL;
1415 }
1416
1417 sc->nge_cdata.nge_tx_cnt--;
1418 NGE_INC(idx, NGE_TX_LIST_CNT);
1419 ifp->if_timer = 0;
1420 }
1421
1422 sc->nge_cdata.nge_tx_cons = idx;
1423
1424 if (cur_tx != NULL)
1425 ifp->if_flags &= ~IFF_OACTIVE;
1426 }
1427
1428 static void
1429 nge_tick(void *xsc)
1430 {
1431 struct nge_softc *sc = xsc;
1432 struct ifnet *ifp = &sc->arpcom.ac_if;
1433 struct mii_data *mii;
1434 int s;
1435
1436 s = splimp();
1437
1438 if (sc->nge_tbi) {
1439 if (sc->nge_link == 0) {
1440 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1441 & NGE_TBIBMSR_ANEG_DONE) {
1442 printf("nge%d: gigabit link up\n",
1443 sc->nge_unit);
1444 nge_miibus_statchg(sc->nge_miibus);
1445 sc->nge_link++;
1446 if (!ifq_is_empty(&ifp->if_snd))
1447 nge_start(ifp);
1448 }
1449 }
1450 } else {
1451 mii = device_get_softc(sc->nge_miibus);
1452 mii_tick(mii);
1453
1454 if (sc->nge_link == 0) {
1455 if (mii->mii_media_status & IFM_ACTIVE &&
1456 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1457 sc->nge_link++;
1458 if (IFM_SUBTYPE(mii->mii_media_active)
1459 == IFM_1000_T)
1460 printf("nge%d: gigabit link up\n",
1461 sc->nge_unit);
1462 if (!ifq_is_empty(&ifp->if_snd))
1463 nge_start(ifp);
1464 }
1465 }
1466 }
1467 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1468
1469 splx(s);
1470 }
1471
1472 #ifdef DEVICE_POLLING
1473
1474 static void
1475 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1476 {
1477 struct nge_softc *sc = ifp->if_softc;
1478
1479 switch(cmd) {
1480 case POLL_REGISTER:
1481 /* disable interrupts */
1482 CSR_WRITE_4(sc, NGE_IER, 0);
1483 break;
1484 case POLL_DEREGISTER:
1485 /* enable interrupts */
1486 CSR_WRITE_4(sc, NGE_IER, 1);
1487 break;
1488 default:
1489 /*
1490 * On the nge, reading the status register also clears it.
1491 * So before returning to intr mode we must make sure that all
1492 * possible pending sources of interrupts have been served.
1493 * In practice this means run to completion the *eof routines,
1494 * and then call the interrupt routine
1495 */
1496 sc->rxcycles = count;
1497 nge_rxeof(sc);
1498 nge_txeof(sc);
1499 if (!ifq_is_empty(&ifp->if_snd))
1500 nge_start(ifp);
1501
1502 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1503 uint32_t status;
1504
1505 /* Reading the ISR register clears all interrupts. */
1506 status = CSR_READ_4(sc, NGE_ISR);
1507
1508 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1509 nge_rxeof(sc);
1510
1511 if (status & (NGE_ISR_RX_IDLE))
1512 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1513
1514 if (status & NGE_ISR_SYSERR) {
1515 nge_reset(sc);
1516 nge_init(sc);
1517 }
1518 }
1519 break;
1520 }
1521 }
1522
1523 #endif /* DEVICE_POLLING */
1524
1525 static void
1526 nge_intr(void *arg)
1527 {
1528 struct nge_softc *sc = arg;
1529 struct ifnet *ifp = &sc->arpcom.ac_if;
1530 uint32_t status;
1531
1532 /* Supress unwanted interrupts */
1533 if (!(ifp->if_flags & IFF_UP)) {
1534 nge_stop(sc);
1535 return;
1536 }
1537
1538 /* Disable interrupts. */
1539 CSR_WRITE_4(sc, NGE_IER, 0);
1540
1541 /* Data LED on for TBI mode */
1542 if(sc->nge_tbi)
1543 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1544 | NGE_GPIO_GP3_OUT);
1545
1546 for (;;) {
1547 /* Reading the ISR register clears all interrupts. */
1548 status = CSR_READ_4(sc, NGE_ISR);
1549
1550 if ((status & NGE_INTRS) == 0)
1551 break;
1552
1553 if ((status & NGE_ISR_TX_DESC_OK) ||
1554 (status & NGE_ISR_TX_ERR) ||
1555 (status & NGE_ISR_TX_OK) ||
1556 (status & NGE_ISR_TX_IDLE))
1557 nge_txeof(sc);
1558
1559 if ((status & NGE_ISR_RX_DESC_OK) ||
1560 (status & NGE_ISR_RX_ERR) ||
1561 (status & NGE_ISR_RX_OFLOW) ||
1562 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1563 (status & NGE_ISR_RX_IDLE) ||
1564 (status & NGE_ISR_RX_OK))
1565 nge_rxeof(sc);
1566
1567 if ((status & NGE_ISR_RX_IDLE))
1568 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1569
1570 if (status & NGE_ISR_SYSERR) {
1571 nge_reset(sc);
1572 ifp->if_flags &= ~IFF_RUNNING;
1573 nge_init(sc);
1574 }
1575
1576 #ifdef notyet
1577 /* mii_tick should only be called once per second */
1578 if (status & NGE_ISR_PHY_INTR) {
1579 sc->nge_link = 0;
1580 nge_tick(sc);
1581 }
1582 #endif
1583 }
1584
1585 /* Re-enable interrupts. */
1586 CSR_WRITE_4(sc, NGE_IER, 1);
1587
1588 if (!ifq_is_empty(&ifp->if_snd))
1589 nge_start(ifp);
1590
1591 /* Data LED off for TBI mode */
1592
1593 if(sc->nge_tbi)
1594 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1595 & ~NGE_GPIO_GP3_OUT);
1596 }
1597
1598 /*
1599 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1600 * pointers to the fragment pointers.
1601 */
1602 static int
1603 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1604 {
1605 struct nge_desc *f = NULL;
1606 struct mbuf *m;
1607 int frag, cur, cnt = 0;
1608 struct ifvlan *ifv = NULL;
1609
1610 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1611 m_head->m_pkthdr.rcvif != NULL &&
1612 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1613 ifv = m_head->m_pkthdr.rcvif->if_softc;
1614
1615 /*
1616 * Start packing the mbufs in this chain into
1617 * the fragment pointers. Stop when we run out
1618 * of fragments or hit the end of the mbuf chain.
1619 */
1620 m = m_head;
1621 cur = frag = *txidx;
1622
1623 for (m = m_head; m != NULL; m = m->m_next) {
1624 if (m->m_len != 0) {
1625 if ((NGE_TX_LIST_CNT -
1626 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1627 return(ENOBUFS);
1628 f = &sc->nge_ldata->nge_tx_list[frag];
1629 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1630 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1631 if (cnt != 0)
1632 f->nge_ctl |= NGE_CMDSTS_OWN;
1633 cur = frag;
1634 NGE_INC(frag, NGE_TX_LIST_CNT);
1635 cnt++;
1636 }
1637 }
1638
1639 if (m != NULL)
1640 return(ENOBUFS);
1641
1642 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1643 if (m_head->m_pkthdr.csum_flags) {
1644 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1645 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1646 NGE_TXEXTSTS_IPCSUM;
1647 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1648 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1649 NGE_TXEXTSTS_TCPCSUM;
1650 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1651 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1652 NGE_TXEXTSTS_UDPCSUM;
1653 }
1654
1655 if (ifv != NULL) {
1656 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1657 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1658 }
1659
1660 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1661 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1662 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1663 sc->nge_cdata.nge_tx_cnt += cnt;
1664 *txidx = frag;
1665
1666 return(0);
1667 }
1668
1669 /*
1670 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1671 * to the mbuf data regions directly in the transmit lists. We also save a
1672 * copy of the pointers since the transmit list fragment pointers are
1673 * physical addresses.
1674 */
1675
1676 static void
1677 nge_start(struct ifnet *ifp)
1678 {
1679 struct nge_softc *sc = ifp->if_softc;
1680 struct mbuf *m_head = NULL;
1681 uint32_t idx;
1682
1683 if (!sc->nge_link)
1684 return;
1685
1686 idx = sc->nge_cdata.nge_tx_prod;
1687
1688 if (ifp->if_flags & IFF_OACTIVE)
1689 return;
1690
1691 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1692 m_head = ifq_poll(&ifp->if_snd);
1693 if (m_head == NULL)
1694 break;
1695
1696 if (nge_encap(sc, m_head, &idx)) {
1697 ifp->if_flags |= IFF_OACTIVE;
1698 break;
1699 }
1700 m_head = ifq_dequeue(&ifp->if_snd);
1701
1702 BPF_MTAP(ifp, m_head);
1703 }
1704
1705 /* Transmit */
1706 sc->nge_cdata.nge_tx_prod = idx;
1707 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1708
1709 /*
1710 * Set a timeout in case the chip goes out to lunch.
1711 */
1712 ifp->if_timer = 5;
1713 }
1714
1715 static void
1716 nge_init(void *xsc)
1717 {
1718 struct nge_softc *sc = xsc;
1719 struct ifnet *ifp = &sc->arpcom.ac_if;
1720 struct mii_data *mii;
1721 int s;
1722
1723 if (ifp->if_flags & IFF_RUNNING)
1724 return;
1725
1726 s = splimp();
1727
1728 /*
1729 * Cancel pending I/O and free all RX/TX buffers.
1730 */
1731 nge_stop(sc);
1732 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1733
1734 if (sc->nge_tbi)
1735 mii = NULL;
1736 else
1737 mii = device_get_softc(sc->nge_miibus);
1738
1739 /* Set MAC address */
1740 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1741 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1742 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1743 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1744 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1745 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1746 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1747 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1748 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1749
1750 /* Init circular RX list. */
1751 if (nge_list_rx_init(sc) == ENOBUFS) {
1752 printf("nge%d: initialization failed: no "
1753 "memory for rx buffers\n", sc->nge_unit);
1754 nge_stop(sc);
1755 splx(s);
1756 return;
1757 }
1758
1759 /*
1760 * Init tx descriptors.
1761 */
1762 nge_list_tx_init(sc);
1763
1764 /*
1765 * For the NatSemi chip, we have to explicitly enable the
1766 * reception of ARP frames, as well as turn on the 'perfect
1767 * match' filter where we store the station address, otherwise
1768 * we won't receive unicasts meant for this host.
1769 */
1770 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1771 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1772
1773 /* If we want promiscuous mode, set the allframes bit. */
1774 if (ifp->if_flags & IFF_PROMISC)
1775 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1776 else
1777 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1778
1779 /*
1780 * Set the capture broadcast bit to capture broadcast frames.
1781 */
1782 if (ifp->if_flags & IFF_BROADCAST)
1783 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1784 else
1785 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1786
1787 /*
1788 * Load the multicast filter.
1789 */
1790 nge_setmulti(sc);
1791
1792 /* Turn the receive filter on */
1793 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1794
1795 /*
1796 * Load the address of the RX and TX lists.
1797 */
1798 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1799 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1800 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1801 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1802
1803 /* Set RX configuration */
1804 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1805 /*
1806 * Enable hardware checksum validation for all IPv4
1807 * packets, do not reject packets with bad checksums.
1808 */
1809 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1810
1811 /*
1812 * Tell the chip to detect and strip VLAN tag info from
1813 * received frames. The tag will be provided in the extsts
1814 * field in the RX descriptors.
1815 */
1816 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1817 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1818
1819 /* Set TX configuration */
1820 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1821
1822 /*
1823 * Enable TX IPv4 checksumming on a per-packet basis.
1824 */
1825 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1826
1827 /*
1828 * Tell the chip to insert VLAN tags on a per-packet basis as
1829 * dictated by the code in the frame encapsulation routine.
1830 */
1831 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1832
1833 /* Set full/half duplex mode. */
1834 if (sc->nge_tbi) {
1835 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1836 == IFM_FDX) {
1837 NGE_SETBIT(sc, NGE_TX_CFG,
1838 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1839 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1840 } else {
1841 NGE_CLRBIT(sc, NGE_TX_CFG,
1842 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1843 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1844 }
1845 } else {
1846 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1847 NGE_SETBIT(sc, NGE_TX_CFG,
1848 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1849 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1850 } else {
1851 NGE_CLRBIT(sc, NGE_TX_CFG,
1852 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1853 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1854 }
1855 }
1856
1857 /*
1858 * Enable the delivery of PHY interrupts based on
1859 * link/speed/duplex status changes. Also enable the
1860 * extsts field in the DMA descriptors (needed for
1861 * TCP/IP checksum offload on transmit).
1862 */
1863 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1864 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1865
1866 /*
1867 * Configure interrupt holdoff (moderation). We can
1868 * have the chip delay interrupt delivery for a certain
1869 * period. Units are in 100us, and the max setting
1870 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1871 */
1872 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1873
1874 /*
1875 * Enable interrupts.
1876 */
1877 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1878 #ifdef DEVICE_POLLING
1879 /*
1880 * ... only enable interrupts if we are not polling, make sure
1881 * they are off otherwise.
1882 */
1883 if (ifp->if_flags & IFF_POLLING)
1884 CSR_WRITE_4(sc, NGE_IER, 0);
1885 else
1886 #endif /* DEVICE_POLLING */
1887 CSR_WRITE_4(sc, NGE_IER, 1);
1888
1889 /* Enable receiver and transmitter. */
1890 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1891 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1892
1893 nge_ifmedia_upd(ifp);
1894
1895 ifp->if_flags |= IFF_RUNNING;
1896 ifp->if_flags &= ~IFF_OACTIVE;
1897
1898 splx(s);
1899 }
1900
1901 /*
1902 * Set media options.
1903 */
1904 static int
1905 nge_ifmedia_upd(struct ifnet *ifp)
1906 {
1907 struct nge_softc *sc = ifp->if_softc;
1908 struct mii_data *mii;
1909
1910 if (sc->nge_tbi) {
1911 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1912 == IFM_AUTO) {
1913 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1914 CSR_READ_4(sc, NGE_TBI_ANAR)
1915 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1916 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1917 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1918 | NGE_TBIBMCR_RESTART_ANEG);
1919 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1920 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1921 & IFM_GMASK) == IFM_FDX) {
1922 NGE_SETBIT(sc, NGE_TX_CFG,
1923 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1924 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1925
1926 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1927 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1928 } else {
1929 NGE_CLRBIT(sc, NGE_TX_CFG,
1930 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1931 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1932
1933 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1934 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1935 }
1936
1937 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1938 & ~NGE_GPIO_GP3_OUT);
1939 } else {
1940 mii = device_get_softc(sc->nge_miibus);
1941 sc->nge_link = 0;
1942 if (mii->mii_instance) {
1943 struct mii_softc *miisc;
1944 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1945 miisc = LIST_NEXT(miisc, mii_list))
1946 mii_phy_reset(miisc);
1947 }
1948 mii_mediachg(mii);
1949 }
1950
1951 return(0);
1952 }
1953
1954 /*
1955 * Report current media status.
1956 */
1957 static void
1958 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1959 {
1960 struct nge_softc *sc = ifp->if_softc;
1961 struct mii_data *mii;
1962
1963 if (sc->nge_tbi) {
1964 ifmr->ifm_status = IFM_AVALID;
1965 ifmr->ifm_active = IFM_ETHER;
1966
1967 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1968 ifmr->ifm_status |= IFM_ACTIVE;
1969 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1970 ifmr->ifm_active |= IFM_LOOP;
1971 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1972 ifmr->ifm_active |= IFM_NONE;
1973 ifmr->ifm_status = 0;
1974 return;
1975 }
1976 ifmr->ifm_active |= IFM_1000_SX;
1977 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1978 == IFM_AUTO) {
1979 ifmr->ifm_active |= IFM_AUTO;
1980 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1981 & NGE_TBIANAR_FDX) {
1982 ifmr->ifm_active |= IFM_FDX;
1983 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1984 & NGE_TBIANAR_HDX) {
1985 ifmr->ifm_active |= IFM_HDX;
1986 }
1987 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1988 == IFM_FDX)
1989 ifmr->ifm_active |= IFM_FDX;
1990 else
1991 ifmr->ifm_active |= IFM_HDX;
1992
1993 } else {
1994 mii = device_get_softc(sc->nge_miibus);
1995 mii_pollstat(mii);
1996 ifmr->ifm_active = mii->mii_media_active;
1997 ifmr->ifm_status = mii->mii_media_status;
1998 }
1999 }
2000
2001 static int
2002 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2003 {
2004 struct nge_softc *sc = ifp->if_softc;
2005 struct ifreq *ifr = (struct ifreq *) data;
2006 struct mii_data *mii;
2007 int error = 0, s;
2008
2009 s = splimp();
2010
2011 switch(command) {
2012 case SIOCSIFADDR:
2013 case SIOCGIFADDR:
2014 error = ether_ioctl(ifp, command, data);
2015 break;
2016 case SIOCSIFMTU:
2017 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
2018 error = EINVAL;
2019 } else {
2020 ifp->if_mtu = ifr->ifr_mtu;
2021 /*
2022 * Workaround: if the MTU is larger than
2023 * 8152 (TX FIFO size minus 64 minus 18), turn off
2024 * TX checksum offloading.
2025 */
2026 if (ifr->ifr_mtu >= 8152)
2027 ifp->if_hwassist = 0;
2028 else
2029 ifp->if_hwassist = NGE_CSUM_FEATURES;
2030 }
2031 break;
2032 case SIOCSIFFLAGS:
2033 if (ifp->if_flags & IFF_UP) {
2034 if (ifp->if_flags & IFF_RUNNING &&
2035 ifp->if_flags & IFF_PROMISC &&
2036 !(sc->nge_if_flags & IFF_PROMISC)) {
2037 NGE_SETBIT(sc, NGE_RXFILT_CTL,
2038 NGE_RXFILTCTL_ALLPHYS|
2039 NGE_RXFILTCTL_ALLMULTI);
2040 } else if (ifp->if_flags & IFF_RUNNING &&
2041 !(ifp->if_flags & IFF_PROMISC) &&
2042 sc->nge_if_flags & IFF_PROMISC) {
2043 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2044 NGE_RXFILTCTL_ALLPHYS);
2045 if (!(ifp->if_flags & IFF_ALLMULTI))
2046 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2047 NGE_RXFILTCTL_ALLMULTI);
2048 } else {
2049 ifp->if_flags &= ~IFF_RUNNING;
2050 nge_init(sc);
2051 }
2052 } else {
2053 if (ifp->if_flags & IFF_RUNNING)
2054 nge_stop(sc);
2055 }
2056 sc->nge_if_flags = ifp->if_flags;
2057 error = 0;
2058 break;
2059 case SIOCADDMULTI:
2060 case SIOCDELMULTI:
2061 nge_setmulti(sc);
2062 error = 0;
2063 break;
2064 case SIOCGIFMEDIA:
2065 case SIOCSIFMEDIA:
2066 if (sc->nge_tbi) {
2067 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2068 command);
2069 } else {
2070 mii = device_get_softc(sc->nge_miibus);
2071 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2072 command);
2073 }
2074 break;
2075 default:
2076 error = EINVAL;
2077 break;
2078 }
2079
2080 splx(s);
2081
2082 return(error);
2083 }
2084
2085 static void
2086 nge_watchdog(struct ifnet *ifp)
2087 {
2088 struct nge_softc *sc = ifp->if_softc;
2089
2090 ifp->if_oerrors++;
2091 printf("nge%d: watchdog timeout\n", sc->nge_unit);
2092
2093 nge_stop(sc);
2094 nge_reset(sc);
2095 ifp->if_flags &= ~IFF_RUNNING;
2096 nge_init(sc);
2097
2098 if (!ifq_is_empty(&ifp->if_snd))
2099 nge_start(ifp);
2100 }
2101
2102 /*
2103 * Stop the adapter and free any mbufs allocated to the
2104 * RX and TX lists.
2105 */
2106 static void
2107 nge_stop(struct nge_softc *sc)
2108 {
2109 struct ifnet *ifp = &sc->arpcom.ac_if;
2110 struct ifmedia_entry *ifm;
2111 struct mii_data *mii;
2112 int i, itmp, mtmp;
2113
2114 ifp->if_timer = 0;
2115 if (sc->nge_tbi)
2116 mii = NULL;
2117 else
2118 mii = device_get_softc(sc->nge_miibus);
2119
2120 callout_stop(&sc->nge_stat_timer);
2121 CSR_WRITE_4(sc, NGE_IER, 0);
2122 CSR_WRITE_4(sc, NGE_IMR, 0);
2123 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2124 DELAY(1000);
2125 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2126 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2127
2128 /*
2129 * Isolate/power down the PHY, but leave the media selection
2130 * unchanged so that things will be put back to normal when
2131 * we bring the interface back up.
2132 */
2133 itmp = ifp->if_flags;
2134 ifp->if_flags |= IFF_UP;
2135
2136 if (sc->nge_tbi)
2137 ifm = sc->nge_ifmedia.ifm_cur;
2138 else
2139 ifm = mii->mii_media.ifm_cur;
2140
2141 mtmp = ifm->ifm_media;
2142 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2143
2144 if (!sc->nge_tbi)
2145 mii_mediachg(mii);
2146 ifm->ifm_media = mtmp;
2147 ifp->if_flags = itmp;
2148
2149 sc->nge_link = 0;
2150
2151 /*
2152 * Free data in the RX lists.
2153 */
2154 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2155 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2156 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2157 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2158 }
2159 }
2160 bzero(&sc->nge_ldata->nge_rx_list,
2161 sizeof(sc->nge_ldata->nge_rx_list));
2162
2163 /*
2164 * Free the TX list buffers.
2165 */
2166 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2167 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2168 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2169 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2170 }
2171 }
2172
2173 bzero(&sc->nge_ldata->nge_tx_list,
2174 sizeof(sc->nge_ldata->nge_tx_list));
2175
2176 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2177 }
2178
2179 /*
2180 * Stop all chip I/O so that the kernel's probe routines don't
2181 * get confused by errant DMAs when rebooting.
2182 */
2183 static void
2184 nge_shutdown(device_t dev)
2185 {
2186 struct nge_softc *sc = device_get_softc(dev);
2187
2188 nge_reset(sc);
2189 nge_stop(sc);
2190 }
DragonFly BSD