?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add SATA ATAPI support for AHCI controllers.
[dragonfly.git] / sys / dev / disk / nata / ata-chipset.c
blob9a976e0a18ef201f112c967ae80f0fab4b8fcad7
1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.10 2007/11/20 09:25:21 hasso Exp $
28 */
29
30 #include "opt_ata.h"
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/bus_dma.h>
35 #include <sys/bus_resource.h>
36 #include <sys/callout.h>
37 #include <sys/endian.h>
38 #include <sys/libkern.h>
39 #include <sys/lock.h> /* for {get,rel}_mplock() */
40 #include <sys/malloc.h>
41 #include <sys/nata.h>
42 #include <sys/queue.h>
43 #include <sys/rman.h>
44 #include <sys/spinlock.h>
45 #include <sys/spinlock2.h>
46 #include <sys/systm.h>
47 #include <sys/taskqueue.h>
48
49 #include <machine/bus_dma.h>
50
51 #include <bus/pci/pcireg.h>
52 #include <bus/pci/pcivar.h>
53
54 #include "ata-all.h"
55 #include "ata-pci.h"
56 #include "ata_if.h"
57
58 /* local prototypes */
59 /* ata-chipset.c */
60 static int ata_generic_chipinit(device_t dev);
61 static void ata_generic_intr(void *data);
62 static void ata_generic_setmode(device_t dev, int mode);
63 static void ata_sata_phy_check_events(device_t dev);
64 static void ata_sata_phy_event(void *context, int dummy);
65 static int ata_sata_phy_reset(device_t dev);
66 static int ata_sata_connect(struct ata_channel *ch);
67 static void ata_sata_setmode(device_t dev, int mode);
68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
69 static int ata_ahci_chipinit(device_t dev);
70 static int ata_ahci_allocate(device_t dev);
71 static int ata_ahci_status(device_t dev);
72 static int ata_ahci_begin_transaction(struct ata_request *request);
73 static int ata_ahci_end_transaction(struct ata_request *request);
74 static void ata_ahci_reset(device_t dev);
75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
76 static void ata_ahci_dmainit(device_t dev);
77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
78 static int ata_genahci_chipinit(device_t dev);
79 static int ata_acard_chipinit(device_t dev);
80 static int ata_acard_allocate(device_t dev);
81 static int ata_acard_status(device_t dev);
82 static void ata_acard_850_setmode(device_t dev, int mode);
83 static void ata_acard_86X_setmode(device_t dev, int mode);
84 static int ata_ali_chipinit(device_t dev);
85 static int ata_ali_allocate(device_t dev);
86 static int ata_ali_sata_allocate(device_t dev);
87 static void ata_ali_reset(device_t dev);
88 static void ata_ali_setmode(device_t dev, int mode);
89 static int ata_amd_chipinit(device_t dev);
90 static int ata_ati_chipinit(device_t dev);
91 static void ata_ati_setmode(device_t dev, int mode);
92 static int ata_cyrix_chipinit(device_t dev);
93 static void ata_cyrix_setmode(device_t dev, int mode);
94 static int ata_cypress_chipinit(device_t dev);
95 static void ata_cypress_setmode(device_t dev, int mode);
96 static int ata_highpoint_chipinit(device_t dev);
97 static int ata_highpoint_allocate(device_t dev);
98 static void ata_highpoint_setmode(device_t dev, int mode);
99 static int ata_highpoint_check_80pin(device_t dev, int mode);
100 static int ata_intel_chipinit(device_t dev);
101 static int ata_intel_allocate(device_t dev);
102 static void ata_intel_reset(device_t dev);
103 static void ata_intel_old_setmode(device_t dev, int mode);
104 static void ata_intel_new_setmode(device_t dev, int mode);
105 static int ata_intel_31244_allocate(device_t dev);
106 static int ata_intel_31244_status(device_t dev);
107 static int ata_intel_31244_command(struct ata_request *request);
108 static void ata_intel_31244_reset(device_t dev);
109 static int ata_ite_chipinit(device_t dev);
110 static void ata_ite_setmode(device_t dev, int mode);
111 static int ata_jmicron_chipinit(device_t dev);
112 static int ata_jmicron_allocate(device_t dev);
113 static void ata_jmicron_reset(device_t dev);
114 static void ata_jmicron_dmainit(device_t dev);
115 static void ata_jmicron_setmode(device_t dev, int mode);
116 static int ata_marvell_pata_chipinit(device_t dev);
117 static int ata_marvell_pata_allocate(device_t dev);
118 static void ata_marvell_pata_setmode(device_t dev, int mode);
119 static int ata_marvell_edma_chipinit(device_t dev);
120 static int ata_marvell_edma_allocate(device_t dev);
121 static int ata_marvell_edma_status(device_t dev);
122 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
123 static int ata_marvell_edma_end_transaction(struct ata_request *request);
124 static void ata_marvell_edma_reset(device_t dev);
125 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
126 static void ata_marvell_edma_dmainit(device_t dev);
127 static int ata_national_chipinit(device_t dev);
128 static void ata_national_setmode(device_t dev, int mode);
129 static int ata_netcell_chipinit(device_t dev);
130 static int ata_netcell_allocate(device_t dev);
131 static int ata_nvidia_chipinit(device_t dev);
132 static int ata_nvidia_allocate(device_t dev);
133 static int ata_nvidia_status(device_t dev);
134 static void ata_nvidia_reset(device_t dev);
135 static int ata_promise_chipinit(device_t dev);
136 static int ata_promise_allocate(device_t dev);
137 static int ata_promise_status(device_t dev);
138 static int ata_promise_dmastart(device_t dev);
139 static int ata_promise_dmastop(device_t dev);
140 static void ata_promise_dmareset(device_t dev);
141 static void ata_promise_dmainit(device_t dev);
142 static void ata_promise_setmode(device_t dev, int mode);
143 static int ata_promise_tx2_allocate(device_t dev);
144 static int ata_promise_tx2_status(device_t dev);
145 static int ata_promise_mio_allocate(device_t dev);
146 static void ata_promise_mio_intr(void *data);
147 static int ata_promise_mio_status(device_t dev);
148 static int ata_promise_mio_command(struct ata_request *request);
149 static void ata_promise_mio_reset(device_t dev);
150 static void ata_promise_mio_dmainit(device_t dev);
151 static void ata_promise_mio_setmode(device_t dev, int mode);
152 static void ata_promise_sx4_intr(void *data);
153 static int ata_promise_sx4_command(struct ata_request *request);
154 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
155 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
156 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
157 static int ata_serverworks_chipinit(device_t dev);
158 static int ata_serverworks_allocate(device_t dev);
159 static void ata_serverworks_setmode(device_t dev, int mode);
160 static int ata_sii_chipinit(device_t dev);
161 static int ata_cmd_allocate(device_t dev);
162 static int ata_cmd_status(device_t dev);
163 static void ata_cmd_setmode(device_t dev, int mode);
164 static int ata_sii_allocate(device_t dev);
165 static int ata_sii_status(device_t dev);
166 static void ata_sii_reset(device_t dev);
167 static void ata_sii_setmode(device_t dev, int mode);
168 static int ata_siiprb_allocate(device_t dev);
169 static int ata_siiprb_status(device_t dev);
170 static int ata_siiprb_begin_transaction(struct ata_request *request);
171 static int ata_siiprb_end_transaction(struct ata_request *request);
172 static void ata_siiprb_reset(device_t dev);
173 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
174 static void ata_siiprb_dmainit(device_t dev);
175 static int ata_sis_chipinit(device_t dev);
176 static int ata_sis_allocate(device_t dev);
177 static void ata_sis_reset(device_t dev);
178 static void ata_sis_setmode(device_t dev, int mode);
179 static int ata_via_chipinit(device_t dev);
180 static int ata_via_allocate(device_t dev);
181 static void ata_via_reset(device_t dev);
182 static void ata_via_setmode(device_t dev, int mode);
183 static void ata_via_southbridge_fixup(device_t dev);
184 static void ata_via_family_setmode(device_t dev, int mode);
185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
187 static int ata_setup_interrupt(device_t dev);
188 static int ata_serialize(device_t dev, int flags);
189 static void ata_print_cable(device_t dev, u_int8_t *who);
190 static int ata_atapi(device_t dev);
191 static int ata_check_80pin(device_t dev, int mode);
192 static int ata_mode2idx(int mode);
193
194
195 /*
196 * generic ATA support functions
197 */
198 int
199 ata_generic_ident(device_t dev)
200 {
201 struct ata_pci_controller *ctlr = device_get_softc(dev);
202
203 device_set_desc(dev, "GENERIC ATA controller");
204 ctlr->chipinit = ata_generic_chipinit;
205 return 0;
206 }
207
208 static int
209 ata_generic_chipinit(device_t dev)
210 {
211 struct ata_pci_controller *ctlr = device_get_softc(dev);
212
213 if (ata_setup_interrupt(dev))
214 return ENXIO;
215 ctlr->setmode = ata_generic_setmode;
216 return 0;
217 }
218
219 static void
220 ata_generic_intr(void *data)
221 {
222 struct ata_pci_controller *ctlr = data;
223 struct ata_channel *ch;
224 int unit;
225
226 for (unit = 0; unit < ctlr->channels; unit++) {
227 if ((ch = ctlr->interrupt[unit].argument))
228 ctlr->interrupt[unit].function(ch);
229 }
230 }
231
232 static void
233 ata_generic_setmode(device_t dev, int mode)
234 {
235 struct ata_device *atadev = device_get_softc(dev);
236
237 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
238 mode = ata_check_80pin(dev, mode);
239 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
240 atadev->mode = mode;
241 }
242
243
244 /*
245 * SATA support functions
246 */
247 static void
248 ata_sata_phy_check_events(device_t dev)
249 {
250 struct ata_channel *ch = device_get_softc(dev);
251 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
252
253 /* clear error bits/interrupt */
254 ATA_IDX_OUTL(ch, ATA_SERROR, error);
255
256 /* do we have any events flagged ? */
257 if (error) {
258 struct ata_connect_task *tp;
259 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
260
261 /* if we have a connection event deal with it */
262 if ((error & ATA_SE_PHY_CHANGED) &&
263 (tp = (struct ata_connect_task *)
264 kmalloc(sizeof(struct ata_connect_task),
265 M_ATA, M_INTWAIT | M_ZERO))) {
266
267 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
268 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
269 if (bootverbose)
270 device_printf(ch->dev, "CONNECT requested\n");
271 tp->action = ATA_C_ATTACH;
272 }
273 else {
274 if (bootverbose)
275 device_printf(ch->dev, "DISCONNECT requested\n");
276 tp->action = ATA_C_DETACH;
277 }
278 tp->dev = ch->dev;
279 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
280 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
281 }
282 }
283 }
284
285 static void
286 ata_sata_phy_event(void *context, int dummy)
287 {
288 struct ata_connect_task *tp = (struct ata_connect_task *)context;
289 struct ata_channel *ch = device_get_softc(tp->dev);
290 device_t *children;
291 int nchildren, i;
292
293 get_mplock();
294 if (tp->action == ATA_C_ATTACH) {
295 if (bootverbose)
296 device_printf(tp->dev, "CONNECTED\n");
297 ATA_RESET(tp->dev);
298 ata_identify(tp->dev);
299 }
300 if (tp->action == ATA_C_DETACH) {
301 if (!device_get_children(tp->dev, &children, &nchildren)) {
302 for (i = 0; i < nchildren; i++)
303 if (children[i])
304 device_delete_child(tp->dev, children[i]);
305 kfree(children, M_TEMP);
306 }
307 spin_lock_wr(&ch->state_mtx);
308 ch->state = ATA_IDLE;
309 spin_unlock_wr(&ch->state_mtx);
310 if (bootverbose)
311 device_printf(tp->dev, "DISCONNECTED\n");
312 }
313 rel_mplock();
314 kfree(tp, M_ATA);
315 }
316
317 static int
318 ata_sata_phy_reset(device_t dev)
319 {
320 struct ata_channel *ch = device_get_softc(dev);
321 int loop, retry;
322
323 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
324 return ata_sata_connect(ch);
325
326 for (retry = 0; retry < 10; retry++) {
327 for (loop = 0; loop < 10; loop++) {
328 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
329 ata_udelay(100);
330 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
331 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
332 break;
333 }
334 ata_udelay(5000);
335 for (loop = 0; loop < 10; loop++) {
336 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
337 ATA_SC_IPM_DIS_PARTIAL |
338 ATA_SC_IPM_DIS_SLUMBER);
339 ata_udelay(100);
340 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
341 return ata_sata_connect(ch);
342 }
343 }
344 return 0;
345 }
346
347 static int
348 ata_sata_connect(struct ata_channel *ch)
349 {
350 u_int32_t status;
351 int timeout;
352
353 /* wait up to 1 second for "connect well" */
354 for (timeout = 0; timeout < 100 ; timeout++) {
355 status = ATA_IDX_INL(ch, ATA_SSTATUS);
356 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
357 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
358 break;
359 ata_udelay(10000);
360 }
361 if (timeout >= 100) {
362 if (bootverbose)
363 device_printf(ch->dev, "SATA connect status=%08x\n", status);
364 return 0;
365 }
366
367 if (bootverbose)
368 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
369
370 /* clear SATA error register */
371 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
372
373 return 1;
374 }
375
376 static void
377 ata_sata_setmode(device_t dev, int mode)
378 {
379 struct ata_device *atadev = device_get_softc(dev);
380
381 /*
382 * if we detect that the device isn't a real SATA device we limit
383 * the transfer mode to UDMA5/ATA100.
384 * this works around the problems some devices has with the
385 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
386 */
387 if (atadev->param.satacapabilities != 0x0000 &&
388 atadev->param.satacapabilities != 0xffff) {
389 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
390
391 /* on some drives we need to set the transfer mode */
392 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
393 ata_limit_mode(dev, mode, ATA_UDMA6));
394
395 /* query SATA STATUS for the speed */
396 if (ch->r_io[ATA_SSTATUS].res &&
397 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
398 ATA_SS_CONWELL_GEN2))
399 atadev->mode = ATA_SA300;
400 else
401 atadev->mode = ATA_SA150;
402 }
403 else {
404 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
405 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
406 atadev->mode = mode;
407 }
408 }
409
410 static int
411 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
412 {
413 struct ata_device *atadev = device_get_softc(request->dev);
414
415 if (request->flags & ATA_R_ATAPI) {
416 fis[0] = 0x27; /* host to device */
417 fis[1] = 0x80; /* command FIS (note PM goes here) */
418 fis[2] = ATA_PACKET_CMD;
419 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
420 fis[3] = ATA_F_DMA;
421 else {
422 fis[5] = request->transfersize;
423 fis[6] = request->transfersize >> 8;
424 }
425 fis[7] = ATA_D_LBA | atadev->unit;
426 fis[15] = ATA_A_4BIT;
427 return 20;
428 }
429 else {
430 ata_modify_if_48bit(request);
431 fis[0] = 0x27; /* host to device */
432 fis[1] = 0x80; /* command FIS (note PM goes here) */
433 fis[2] = request->u.ata.command;
434 fis[3] = request->u.ata.feature;
435 fis[4] = request->u.ata.lba;
436 fis[5] = request->u.ata.lba >> 8;
437 fis[6] = request->u.ata.lba >> 16;
438 fis[7] = ATA_D_LBA | atadev->unit;
439 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
440 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
441 fis[8] = request->u.ata.lba >> 24;
442 fis[9] = request->u.ata.lba >> 32;
443 fis[10] = request->u.ata.lba >> 40;
444 fis[11] = request->u.ata.feature >> 8;
445 fis[12] = request->u.ata.count;
446 fis[13] = request->u.ata.count >> 8;
447 fis[15] = ATA_A_4BIT;
448 return 20;
449 }
450 return 0;
451 }
452
453 /*
454 * AHCI v1.x compliant SATA chipset support functions
455 */
456 static int
457 ata_ahci_chipinit(device_t dev)
458 {
459 struct ata_pci_controller *ctlr = device_get_softc(dev);
460 u_int32_t version;
461 int unit;
462
463 /* reset AHCI controller */
464 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
465 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
466 DELAY(1000000);
467 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
468 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
469 device_printf(dev, "AHCI controller reset failure\n");
470 return ENXIO;
471 }
472
473 /* enable AHCI mode */
474 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
475 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE);
476
477 /* get the number of HW channels */
478 ctlr->channels =
479 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
480 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
481
482 /* disable interrupt sources and clear interrupts */
483 for (unit = 0; unit < ctlr->channels; unit++) {
484 int offset = unit << 7;
485 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
486 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1);
487 }
488 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
489
490 /* enable AHCI interrupts */
491 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
492 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
493
494 ctlr->reset = ata_ahci_reset;
495 ctlr->dmainit = ata_ahci_dmainit;
496 ctlr->allocate = ata_ahci_allocate;
497 ctlr->setmode = ata_sata_setmode;
498
499 /* enable PCI interrupt */
500 pci_write_config(dev, PCIR_COMMAND,
501 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
502
503 /* announce we support the HW */
504 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
505 device_printf(dev,
506 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
507 (version >> 24) & 0xff, (version >> 16) & 0xff,
508 (version >> 8) & 0xff, version & 0xff,
509 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
510 return 0;
511 }
512
513 static int
514 ata_ahci_allocate(device_t dev)
515 {
516 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
517 struct ata_channel *ch = device_get_softc(dev);
518 u_int64_t work;
519 int offset = ch->unit << 7;
520
521 /* set the SATA resources */
522 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
523 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
524 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
525 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
526 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
527 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
528 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
529 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
530
531 ch->hw.status = ata_ahci_status;
532 ch->hw.begin_transaction = ata_ahci_begin_transaction;
533 ch->hw.end_transaction = ata_ahci_end_transaction;
534 ch->hw.command = NULL; /* not used here */
535
536 /* setup work areas */
537 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
538 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
539 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
540
541 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
542 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
543 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
544
545 /* enable wanted port interrupts */
546 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
547 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
548 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
549 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
550 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
551 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
552
553 /* start operations on this channel */
554 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
555 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
556 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
557 return 0;
558 }
559
560 static int
561 ata_ahci_status(device_t dev)
562 {
563 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
564 struct ata_channel *ch = device_get_softc(dev);
565 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
566 int offset = ch->unit << 7;
567 int tag = 0;
568
569 if (action & (1 << ch->unit)) {
570 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
571 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
572
573 /* clear interrupt(s) */
574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
575 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
576
577 /* do we have any PHY events ? */
578 /* XXX SOS check istatus phy bits */
579 ata_sata_phy_check_events(dev);
580
581 /* do we have a potentially hanging engine to take care of? */
582 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
583
584 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
585 int timeout = 0;
586
587 /* kill off all activity on this channel */
588 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
589 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
590
591 /* XXX SOS this is not entirely wrong */
592 do {
593 DELAY(1000);
594 if (timeout++ > 500) {
595 device_printf(dev, "stopping AHCI engine failed\n");
596 break;
597 }
598 } while (ATA_INL(ctlr->r_res2,
599 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
600
601 /* start operations on this channel */
602 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
603 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
604
605 return 1;
606 }
607 else
608 return (!(cstatus & (1 << tag)));
609 }
610 return 0;
611 }
612
613 /* must be called with ATA channel locked and state_mtx held */
614 static int
615 ata_ahci_begin_transaction(struct ata_request *request)
616 {
617 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
618 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
619 struct ata_ahci_cmd_tab *ctp;
620 struct ata_ahci_cmd_list *clp;
621 int offset = ch->unit << 7;
622 int tag = 0, entries = 0;
623 int fis_size;
624
625 /* get a piece of the workspace for this request */
626 ctp = (struct ata_ahci_cmd_tab *)
627 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
628
629 /* setup the FIS for this request */
630 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
631 device_printf(request->dev, "setting up SATA FIS failed\n");
632 request->result = EIO;
633 return ATA_OP_FINISHED;
634 }
635
636 /* if request moves data setup and load SG list */
637 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
638 if (ch->dma->load(ch->dev, request->data, request->bytecount,
639 request->flags & ATA_R_READ,
640 ctp->prd_tab, &entries)) {
641 device_printf(request->dev, "setting up DMA failed\n");
642 request->result = EIO;
643 return ATA_OP_FINISHED;
644 }
645 }
646
647 /* setup the command list entry */
648 clp = (struct ata_ahci_cmd_list *)
649 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
650
651 clp->prd_length = entries;
652 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
653 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
654 (fis_size / sizeof(u_int32_t));
655 clp->bytecount = 0;
656 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
657 (ATA_AHCI_CT_SIZE * tag));
658
659 /* clear eventual ACTIVE bit */
660 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
661
662 /* set command type bit */
663 if (request->flags & ATA_R_ATAPI)
664 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
665 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
666 ATA_AHCI_P_CMD_ATAPI);
667 else
668 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
669 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
670 ~ATA_AHCI_P_CMD_ATAPI);
671
672 /* issue command to controller */
673 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
674
675 if (!(request->flags & ATA_R_ATAPI)) {
676 /* device reset doesn't interrupt */
677 if (request->u.ata.command == ATA_DEVICE_RESET) {
678 u_int32_t tf_data;
679 int timeout = 1000000;
680
681 do {
682 DELAY(10);
683 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
684 } while ((tf_data & ATA_S_BUSY) && timeout--);
685 if (bootverbose)
686 device_printf(ch->dev, "device_reset timeout=%dus\n",
687 (1000000-timeout)*10);
688 request->status = tf_data;
689 if (request->status & ATA_S_ERROR)
690 request->error = tf_data >> 8;
691 return ATA_OP_FINISHED;
692 }
693 }
694
695 /* start the timeout */
696 callout_reset(&request->callout, request->timeout * hz,
697 (timeout_t*)ata_timeout, request);
698 return ATA_OP_CONTINUES;
699 }
700
701 /* must be called with ATA channel locked and state_mtx held */
702 static int
703 ata_ahci_end_transaction(struct ata_request *request)
704 {
705 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
706 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
707 struct ata_ahci_cmd_list *clp;
708 u_int32_t tf_data;
709 int offset = ch->unit << 7;
710 int tag = 0;
711
712 /* kill the timeout */
713 callout_stop(&request->callout);
714
715 /* get status */
716 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
717 request->status = tf_data;
718
719 /* if error status get details */
720 if (request->status & ATA_S_ERROR)
721 request->error = tf_data >> 8;
722
723 /* record how much data we actually moved */
724 clp = (struct ata_ahci_cmd_list *)
725 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
726 request->donecount = clp->bytecount;
727
728 /* release SG list etc */
729 ch->dma->unload(ch->dev);
730
731 return ATA_OP_FINISHED;
732 }
733
734 static void
735 ata_ahci_reset(device_t dev)
736 {
737 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
738 struct ata_channel *ch = device_get_softc(dev);
739 u_int32_t cmd, signature;
740 int offset = ch->unit << 7;
741 int timeout;
742
743 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
744 device_printf(dev, "port not implemented\n");
745 return;
746 }
747 ch->devices = 0;
748
749 /* kill off all activity on this channel */
750 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
751 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
752 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
753
754 /* XXX SOS this is not entirely wrong */
755 timeout = 0;
756 do {
757 DELAY(1000);
758 if (timeout++ > 500) {
759 device_printf(dev, "stopping AHCI engine failed\n");
760 break;
761 }
762 }
763 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
764
765 /* issue Command List Override if supported */
766 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
767 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
768 cmd |= ATA_AHCI_P_CMD_CLO;
769 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
770 timeout = 0;
771 do {
772 DELAY(1000);
773 if (timeout++ > 500) {
774 device_printf(dev, "executing CLO failed\n");
775 break;
776 }
777 }
778 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
779 }
780
781 /* reset PHY and decide what is present */
782 if (ata_sata_phy_reset(dev)) {
783
784 /* clear any interrupts pending on this channel */
785 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
786 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
787
788 /* clear SATA error register */
789 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
790
791 /* start operations on this channel */
792 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
793 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
794 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
795
796 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
797 switch (signature) {
798 case 0x00000101:
799 ch->devices = ATA_ATA_MASTER;
800 break;
801 case 0x96690101:
802 ch->devices = ATA_PORTMULTIPLIER;
803 device_printf(ch->dev, "Portmultipliers not supported yet\n");
804 ch->devices = 0;
805 break;
806 case 0xeb140101:
807 ch->devices = ATA_ATAPI_MASTER;
808 break;
809 default: /* SOS XXX */
810 if (bootverbose)
811 device_printf(ch->dev, "No signature, assuming disk device\n");
812 ch->devices = ATA_ATA_MASTER;
813 }
814 }
815 if (bootverbose)
816 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
817 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
818 }
819
820 static void
821 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
822 {
823 struct ata_dmasetprd_args *args = xsc;
824 struct ata_ahci_dma_prd *prd = args->dmatab;
825 int i;
826
827 if (!(args->error = error)) {
828 for (i = 0; i < nsegs; i++) {
829 prd[i].dba = htole64(segs[i].ds_addr);
830 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
831 }
832 }
833 args->nsegs = nsegs;
834 }
835
836 static void
837 ata_ahci_dmainit(device_t dev)
838 {
839 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
840 struct ata_channel *ch = device_get_softc(dev);
841
842 ata_dmainit(dev);
843 if (ch->dma) {
844 /* note start and stop are not used here */
845 ch->dma->setprd = ata_ahci_dmasetprd;
846 ch->dma->max_iosize = 8192 * DEV_BSIZE;
847 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
848 ch->dma->max_address = BUS_SPACE_MAXADDR;
849 }
850 }
851
852 static int
853 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
854 {
855 bzero(ctp->cfis, 64);
856 if (request->flags & ATA_R_ATAPI) {
857 bzero(ctp->acmd, 32);
858 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
859 }
860 return ata_request2fis_h2d(request, &ctp->cfis[0]);
861 }
862
863 /*
864 * Generic AHCI part support functions.
865 */
866 int
867 ata_genahci_ident(device_t dev)
868 {
869 struct ata_pci_controller *ctlr = device_get_softc(dev);
870 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"};
871 char buffer[64];
872
873 if(!(pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) {
874 return ENXIO;
875 }
876
877 ksprintf(buffer, "GENERIC %s %s controller", id.text, ata_mode2str(id.max_dma));
878 device_set_desc_copy(dev, buffer);
879 ctlr->chip = &id;
880 ctlr->chipinit = ata_genahci_chipinit;
881 return 0;
882 }
883
884 static int
885 ata_genahci_chipinit(device_t dev)
886 {
887 struct ata_pci_controller *ctlr = device_get_softc(dev);
888
889 if (ata_setup_interrupt(dev))
890 return ENXIO;
891
892 /* Check if the chip has PCI BAR 5 as memory resource. */
893 ctlr->r_type2 = SYS_RES_MEMORY;
894 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */
895 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
896 &ctlr->r_rid2, RF_ACTIVE))) {
897 return ata_ahci_chipinit(dev);
898 } else
899 return ENXIO;
900 }
901
902 /*
903 * Acard chipset support functions
904 */
905 int
906 ata_acard_ident(device_t dev)
907 {
908 struct ata_pci_controller *ctlr = device_get_softc(dev);
909 struct ata_chip_id *idx;
910 static struct ata_chip_id ids[] =
911 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
912 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
913 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
914 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
915 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
916 { 0, 0, 0, 0, 0, 0}};
917 char buffer[64];
918
919 if (!(idx = ata_match_chip(dev, ids)))
920 return ENXIO;
921
922 ksprintf(buffer, "Acard %s %s controller",
923 idx->text, ata_mode2str(idx->max_dma));
924 device_set_desc_copy(dev, buffer);
925 ctlr->chip = idx;
926 ctlr->chipinit = ata_acard_chipinit;
927 return 0;
928 }
929
930 static int
931 ata_acard_chipinit(device_t dev)
932 {
933 struct ata_pci_controller *ctlr = device_get_softc(dev);
934
935 if (ata_setup_interrupt(dev))
936 return ENXIO;
937
938 ctlr->allocate = ata_acard_allocate;
939 if (ctlr->chip->cfg1 == ATPOLD) {
940 ctlr->setmode = ata_acard_850_setmode;
941 ctlr->locking = ata_serialize;
942 }
943 else
944 ctlr->setmode = ata_acard_86X_setmode;
945 return 0;
946 }
947
948 static int
949 ata_acard_allocate(device_t dev)
950 {
951 struct ata_channel *ch = device_get_softc(dev);
952
953 /* setup the usual register normal pci style */
954 if (ata_pci_allocate(dev))
955 return ENXIO;
956
957 ch->hw.status = ata_acard_status;
958 return 0;
959 }
960
961 static int
962 ata_acard_status(device_t dev)
963 {
964 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
965 struct ata_channel *ch = device_get_softc(dev);
966
967 if (ctlr->chip->cfg1 == ATPOLD &&
968 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
969 return 0;
970 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
971 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
972
973 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
974 ATA_BMSTAT_INTERRUPT)
975 return 0;
976 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
977 DELAY(1);
978 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
979 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
980 DELAY(1);
981 }
982 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
983 DELAY(100);
984 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
985 return 0;
986 }
987 return 1;
988 }
989
990 static void
991 ata_acard_850_setmode(device_t dev, int mode)
992 {
993 device_t gparent = GRANDPARENT(dev);
994 struct ata_pci_controller *ctlr = device_get_softc(gparent);
995 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
996 struct ata_device *atadev = device_get_softc(dev);
997 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
998 int error;
999
1000 mode = ata_limit_mode(dev, mode,
1001 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1002
1003 /* XXX SOS missing WDMA0+1 + PIO modes */
1004 if (mode >= ATA_WDMA2) {
1005 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1006 if (bootverbose)
1007 device_printf(dev, "%ssetting %s on %s chip\n",
1008 (error) ? "FAILURE " : "",
1009 ata_mode2str(mode), ctlr->chip->text);
1010 if (!error) {
1011 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1012
1013 reg54 &= ~(0x03 << (devno << 1));
1014 if (mode >= ATA_UDMA0)
1015 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1016 pci_write_config(gparent, 0x54, reg54, 1);
1017 pci_write_config(gparent, 0x4a, 0xa6, 1);
1018 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1019 atadev->mode = mode;
1020 return;
1021 }
1022 }
1023 /* we could set PIO mode timings, but we assume the BIOS did that */
1024 }
1025
1026 static void
1027 ata_acard_86X_setmode(device_t dev, int mode)
1028 {
1029 device_t gparent = GRANDPARENT(dev);
1030 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1031 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1032 struct ata_device *atadev = device_get_softc(dev);
1033 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1034 int error;
1035
1036
1037 mode = ata_limit_mode(dev, mode,
1038 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1039
1040 mode = ata_check_80pin(dev, mode);
1041
1042 /* XXX SOS missing WDMA0+1 + PIO modes */
1043 if (mode >= ATA_WDMA2) {
1044 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1045 if (bootverbose)
1046 device_printf(dev, "%ssetting %s on %s chip\n",
1047 (error) ? "FAILURE " : "",
1048 ata_mode2str(mode), ctlr->chip->text);
1049 if (!error) {
1050 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1051
1052 reg44 &= ~(0x000f << (devno << 2));
1053 if (mode >= ATA_UDMA0)
1054 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1055 pci_write_config(gparent, 0x44, reg44, 2);
1056 pci_write_config(gparent, 0x4a, 0xa6, 1);
1057 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1058 atadev->mode = mode;
1059 return;
1060 }
1061 }
1062 /* we could set PIO mode timings, but we assume the BIOS did that */
1063 }
1064
1065
1066 /*
1067 * Acer Labs Inc (ALI) chipset support functions
1068 */
1069 int
1070 ata_ali_ident(device_t dev)
1071 {
1072 struct ata_pci_controller *ctlr = device_get_softc(dev);
1073 struct ata_chip_id *idx;
1074 static struct ata_chip_id ids[] =
1075 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1076 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1077 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1078 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1079 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1080 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1081 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1082 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1083 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1084 { 0, 0, 0, 0, 0, 0}};
1085 char buffer[64];
1086
1087 if (!(idx = ata_match_chip(dev, ids)))
1088 return ENXIO;
1089
1090 ksprintf(buffer, "AcerLabs %s %s controller",
1091 idx->text, ata_mode2str(idx->max_dma));
1092 device_set_desc_copy(dev, buffer);
1093 ctlr->chip = idx;
1094 ctlr->chipinit = ata_ali_chipinit;
1095 return 0;
1096 }
1097
1098 static int
1099 ata_ali_chipinit(device_t dev)
1100 {
1101 struct ata_pci_controller *ctlr = device_get_softc(dev);
1102
1103 if (ata_setup_interrupt(dev))
1104 return ENXIO;
1105
1106 switch (ctlr->chip->cfg2) {
1107 case ALISATA:
1108 ctlr->channels = ctlr->chip->cfg1;
1109 ctlr->allocate = ata_ali_sata_allocate;
1110 ctlr->setmode = ata_sata_setmode;
1111
1112 /* if we have a memory resource we can likely do AHCI */
1113 ctlr->r_type2 = SYS_RES_MEMORY;
1114 ctlr->r_rid2 = PCIR_BAR(5);
1115 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1116 &ctlr->r_rid2, RF_ACTIVE)))
1117 return ata_ahci_chipinit(dev);
1118
1119 /* enable PCI interrupt */
1120 pci_write_config(dev, PCIR_COMMAND,
1121 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1122 break;
1123
1124 case ALINEW:
1125 /* use device interrupt as byte count end */
1126 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1127
1128 /* enable cable detection and UDMA support on newer chips */
1129 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1130
1131 /* enable ATAPI UDMA mode */
1132 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1133
1134 /* only chips with revision > 0xc4 can do 48bit DMA */
1135 if (ctlr->chip->chiprev <= 0xc4)
1136 device_printf(dev,
1137 "using PIO transfers above 137GB as workaround for "
1138 "48bit DMA access bug, expect reduced performance\n");
1139 ctlr->allocate = ata_ali_allocate;
1140 ctlr->reset = ata_ali_reset;
1141 ctlr->setmode = ata_ali_setmode;
1142 break;
1143
1144 case ALIOLD:
1145 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1146 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1147 ctlr->setmode = ata_ali_setmode;
1148 break;
1149 }
1150 return 0;
1151 }
1152
1153 static int
1154 ata_ali_allocate(device_t dev)
1155 {
1156 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1157 struct ata_channel *ch = device_get_softc(dev);
1158
1159 /* setup the usual register normal pci style */
1160 if (ata_pci_allocate(dev))
1161 return ENXIO;
1162
1163 /* older chips can't do 48bit DMA transfers */
1164 if (ctlr->chip->chiprev <= 0xc4)
1165 ch->flags |= ATA_NO_48BIT_DMA;
1166
1167 return 0;
1168 }
1169
1170 static int
1171 ata_ali_sata_allocate(device_t dev)
1172 {
1173 device_t parent = device_get_parent(dev);
1174 struct ata_pci_controller *ctlr = device_get_softc(parent);
1175 struct ata_channel *ch = device_get_softc(dev);
1176 struct resource *io = NULL, *ctlio = NULL;
1177 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1178 int i, rid;
1179
1180 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1181 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1182 if (!io)
1183 return ENXIO;
1184
1185 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1186 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1187 if (!ctlio) {
1188 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1189 return ENXIO;
1190 }
1191
1192 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1193 ch->r_io[i].res = io;
1194 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1195 }
1196 ch->r_io[ATA_CONTROL].res = ctlio;
1197 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1198 ch->r_io[ATA_IDX_ADDR].res = io;
1199 ata_default_registers(dev);
1200 if (ctlr->r_res1) {
1201 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1202 ch->r_io[i].res = ctlr->r_res1;
1203 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1204 }
1205 }
1206 ch->flags |= ATA_NO_SLAVE;
1207
1208 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1209 ata_pci_hw(dev);
1210 return 0;
1211 }
1212
1213 static void
1214 ata_ali_reset(device_t dev)
1215 {
1216 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1217 struct ata_channel *ch = device_get_softc(dev);
1218 device_t *children;
1219 int nchildren, i;
1220
1221 ata_generic_reset(dev);
1222
1223 /*
1224 * workaround for datacorruption bug found on at least SUN Blade-100
1225 * find the ISA function on the southbridge and disable then enable
1226 * the ATA channel tristate buffer
1227 */
1228 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1229 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1230 for (i = 0; i < nchildren; i++) {
1231 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1232 pci_write_config(children[i], 0x58,
1233 pci_read_config(children[i], 0x58, 1) &
1234 ~(0x04 << ch->unit), 1);
1235 pci_write_config(children[i], 0x58,
1236 pci_read_config(children[i], 0x58, 1) |
1237 (0x04 << ch->unit), 1);
1238 break;
1239 }
1240 }
1241 kfree(children, M_TEMP);
1242 }
1243 }
1244 }
1245
1246 static void
1247 ata_ali_setmode(device_t dev, int mode)
1248 {
1249 device_t gparent = GRANDPARENT(dev);
1250 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1251 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1252 struct ata_device *atadev = device_get_softc(dev);
1253 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1254 int error;
1255
1256 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1257
1258 if (ctlr->chip->cfg2 & ALINEW) {
1259 if (mode > ATA_UDMA2 &&
1260 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1261 ata_print_cable(dev, "controller");
1262 mode = ATA_UDMA2;
1263 }
1264 }
1265 else
1266 mode = ata_check_80pin(dev, mode);
1267
1268 if (ctlr->chip->cfg2 & ALIOLD) {
1269 /* doesn't support ATAPI DMA on write */
1270 ch->flags |= ATA_ATAPI_DMA_RO;
1271 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1272 /* doesn't support ATAPI DMA on two ATAPI devices */
1273 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1274 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1275 }
1276 }
1277
1278 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1279
1280 if (bootverbose)
1281 device_printf(dev, "%ssetting %s on %s chip\n",
1282 (error) ? "FAILURE " : "",
1283 ata_mode2str(mode), ctlr->chip->text);
1284 if (!error) {
1285 if (mode >= ATA_UDMA0) {
1286 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1287 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1288
1289 word54 &= ~(0x000f000f << (devno << 2));
1290 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1291 pci_write_config(gparent, 0x54, word54, 4);
1292 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1293 0x00310001, 4);
1294 }
1295 else {
1296 u_int32_t piotimings[] =
1297 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1298 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1299
1300 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1301 ~(0x0008000f << (devno << 2)), 4);
1302 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1303 piotimings[ata_mode2idx(mode)], 4);
1304 }
1305 atadev->mode = mode;
1306 }
1307 }
1308
1309
1310 /*
1311 * American Micro Devices (AMD) chipset support functions
1312 */
1313 int
1314 ata_amd_ident(device_t dev)
1315 {
1316 struct ata_pci_controller *ctlr = device_get_softc(dev);
1317 struct ata_chip_id *idx;
1318 static struct ata_chip_id ids[] =
1319 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1320 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1321 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1322 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1323 { 0, 0, 0, 0, 0, 0}};
1324 char buffer[64];
1325
1326 if (!(idx = ata_match_chip(dev, ids)))
1327 return ENXIO;
1328
1329 ksprintf(buffer, "AMD %s %s controller",
1330 idx->text, ata_mode2str(idx->max_dma));
1331 device_set_desc_copy(dev, buffer);
1332 ctlr->chip = idx;
1333 ctlr->chipinit = ata_amd_chipinit;
1334 return 0;
1335 }
1336
1337 static int
1338 ata_amd_chipinit(device_t dev)
1339 {
1340 struct ata_pci_controller *ctlr = device_get_softc(dev);
1341
1342 if (ata_setup_interrupt(dev))
1343 return ENXIO;
1344
1345 /* disable/set prefetch, postwrite */
1346 if (ctlr->chip->cfg2 & AMDBUG)
1347 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1348 else
1349 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1350
1351 ctlr->setmode = ata_via_family_setmode;
1352 return 0;
1353 }
1354
1355
1356 /*
1357 * ATI chipset support functions
1358 */
1359 int
1360 ata_ati_ident(device_t dev)
1361 {
1362 struct ata_pci_controller *ctlr = device_get_softc(dev);
1363 struct ata_chip_id *idx;
1364 static struct ata_chip_id ids[] =
1365 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1366 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1367 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1368 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" },
1369 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1370 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1371 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1372 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1373 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1374 { 0, 0, 0, 0, 0, 0}};
1375 char buffer[64];
1376
1377 if (!(idx = ata_match_chip(dev, ids)))
1378 return ENXIO;
1379
1380 ksprintf(buffer, "ATI %s %s controller",
1381 idx->text, ata_mode2str(idx->max_dma));
1382 device_set_desc_copy(dev, buffer);
1383 ctlr->chip = idx;
1384
1385 /*
1386 * The ATI SATA controllers are actually a SiI 3112 controller, except
1387 * for the SB600.
1388 */
1389 if (ctlr->chip->cfg1 & SIIMEMIO)
1390 ctlr->chipinit = ata_sii_chipinit;
1391 else
1392 ctlr->chipinit = ata_ati_chipinit;
1393 return 0;
1394 }
1395
1396 static int
1397 ata_ati_chipinit(device_t dev)
1398 {
1399 struct ata_pci_controller *ctlr = device_get_softc(dev);
1400
1401 if (ata_setup_interrupt(dev))
1402 return ENXIO;
1403
1404 /* The SB600 needs special treatment. */
1405 if (ctlr->chip->cfg1 & ATIAHCI) {
1406 /* Check if the chip is configured as an AHCI part. */
1407 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) &&
1408 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) {
1409 /* Check if the chip has PCI BAR 5 as memory resource. */
1410 ctlr->r_type2 = SYS_RES_MEMORY;
1411 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */
1412 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1413 &ctlr->r_rid2,
1414 RF_ACTIVE))) {
1415 return ata_ahci_chipinit(dev);
1416 }
1417 }
1418 }
1419
1420 ctlr->setmode = ata_ati_setmode;
1421 return 0;
1422 }
1423
1424 static void
1425 ata_ati_setmode(device_t dev, int mode)
1426 {
1427 device_t gparent = GRANDPARENT(dev);
1428 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1429 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1430 struct ata_device *atadev = device_get_softc(dev);
1431 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1432 int offset = (devno ^ 0x01) << 3;
1433 int error;
1434 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1435 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1436 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1437
1438 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1439
1440 mode = ata_check_80pin(dev, mode);
1441
1442 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1443
1444 if (bootverbose)
1445 device_printf(dev, "%ssetting %s on %s chip\n",
1446 (error) ? "FAILURE " : "",
1447 ata_mode2str(mode), ctlr->chip->text);
1448 if (!error) {
1449 if (mode >= ATA_UDMA0) {
1450 pci_write_config(gparent, 0x56,
1451 (pci_read_config(gparent, 0x56, 2) &
1452 ~(0xf << (devno << 2))) |
1453 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1454 pci_write_config(gparent, 0x54,
1455 pci_read_config(gparent, 0x54, 1) |
1456 (0x01 << devno), 1);
1457 pci_write_config(gparent, 0x44,
1458 (pci_read_config(gparent, 0x44, 4) &
1459 ~(0xff << offset)) |
1460 (dmatimings[2] << offset), 4);
1461 }
1462 else if (mode >= ATA_WDMA0) {
1463 pci_write_config(gparent, 0x54,
1464 pci_read_config(gparent, 0x54, 1) &
1465 ~(0x01 << devno), 1);
1466 pci_write_config(gparent, 0x44,
1467 (pci_read_config(gparent, 0x44, 4) &
1468 ~(0xff << offset)) |
1469 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1470 }
1471 else
1472 pci_write_config(gparent, 0x54,
1473 pci_read_config(gparent, 0x54, 1) &
1474 ~(0x01 << devno), 1);
1475
1476 pci_write_config(gparent, 0x4a,
1477 (pci_read_config(gparent, 0x4a, 2) &
1478 ~(0xf << (devno << 2))) |
1479 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1480 pci_write_config(gparent, 0x40,
1481 (pci_read_config(gparent, 0x40, 4) &
1482 ~(0xff << offset)) |
1483 (piotimings[ata_mode2idx(mode)] << offset), 4);
1484 atadev->mode = mode;
1485 }
1486 }
1487
1488 /*
1489 * Cyrix chipset support functions
1490 */
1491 int
1492 ata_cyrix_ident(device_t dev)
1493 {
1494 struct ata_pci_controller *ctlr = device_get_softc(dev);
1495
1496 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1497 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1498 ctlr->chipinit = ata_cyrix_chipinit;
1499 return 0;
1500 }
1501 return ENXIO;
1502 }
1503
1504 static int
1505 ata_cyrix_chipinit(device_t dev)
1506 {
1507 struct ata_pci_controller *ctlr = device_get_softc(dev);
1508
1509 if (ata_setup_interrupt(dev))
1510 return ENXIO;
1511
1512 if (ctlr->r_res1)
1513 ctlr->setmode = ata_cyrix_setmode;
1514 else
1515 ctlr->setmode = ata_generic_setmode;
1516 return 0;
1517 }
1518
1519 static void
1520 ata_cyrix_setmode(device_t dev, int mode)
1521 {
1522 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1523 struct ata_device *atadev = device_get_softc(dev);
1524 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1525 u_int32_t piotiming[] =
1526 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1527 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1528 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1529 int error;
1530
1531 ch->dma->alignment = 16;
1532 ch->dma->max_iosize = 126 * DEV_BSIZE;
1533
1534 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1535
1536 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1537
1538 if (bootverbose)
1539 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1540 (error) ? "FAILURE " : "", ata_mode2str(mode));
1541 if (!error) {
1542 if (mode >= ATA_UDMA0) {
1543 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1544 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1545 }
1546 else if (mode >= ATA_WDMA0) {
1547 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1548 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1549 }
1550 else {
1551 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1552 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1553 }
1554 atadev->mode = mode;
1555 }
1556 }
1557
1558
1559 /*
1560 * Cypress chipset support functions
1561 */
1562 int
1563 ata_cypress_ident(device_t dev)
1564 {
1565 struct ata_pci_controller *ctlr = device_get_softc(dev);
1566
1567 /*
1568 * the Cypress chip is a mess, it contains two ATA functions, but
1569 * both channels are visible on the first one.
1570 * simply ignore the second function for now, as the right
1571 * solution (ignoring the second channel on the first function)
1572 * doesn't work with the crappy ATA interrupt setup on the alpha.
1573 */
1574 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1575 pci_get_function(dev) == 1 &&
1576 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1577 device_set_desc(dev, "Cypress 82C693 ATA controller");
1578 ctlr->chipinit = ata_cypress_chipinit;
1579 return 0;
1580 }
1581 return ENXIO;
1582 }
1583
1584 static int
1585 ata_cypress_chipinit(device_t dev)
1586 {
1587 struct ata_pci_controller *ctlr = device_get_softc(dev);
1588
1589 if (ata_setup_interrupt(dev))
1590 return ENXIO;
1591
1592 ctlr->setmode = ata_cypress_setmode;
1593 return 0;
1594 }
1595
1596 static void
1597 ata_cypress_setmode(device_t dev, int mode)
1598 {
1599 device_t gparent = GRANDPARENT(dev);
1600 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1601 struct ata_device *atadev = device_get_softc(dev);
1602 int error;
1603
1604 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1605
1606 /* XXX SOS missing WDMA0+1 + PIO modes */
1607 if (mode == ATA_WDMA2) {
1608 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1609 if (bootverbose)
1610 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1611 error ? "FAILURE " : "");
1612 if (!error) {
1613 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1614 atadev->mode = mode;
1615 return;
1616 }
1617 }
1618 /* we could set PIO mode timings, but we assume the BIOS did that */
1619 }
1620
1621
1622 /*
1623 * HighPoint chipset support functions
1624 */
1625 int
1626 ata_highpoint_ident(device_t dev)
1627 {
1628 struct ata_pci_controller *ctlr = device_get_softc(dev);
1629 struct ata_chip_id *idx;
1630 static struct ata_chip_id ids[] =
1631 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1632 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1633 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1634 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1635 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1636 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1637 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1638 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1639 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1640 { 0, 0, 0, 0, 0, 0}};
1641 char buffer[64];
1642
1643 if (!(idx = ata_match_chip(dev, ids)))
1644 return ENXIO;
1645
1646 strcpy(buffer, "HighPoint ");
1647 strcat(buffer, idx->text);
1648 if (idx->cfg1 == HPT374) {
1649 if (pci_get_function(dev) == 0)
1650 strcat(buffer, " (channel 0+1)");
1651 if (pci_get_function(dev) == 1)
1652 strcat(buffer, " (channel 2+3)");
1653 }
1654 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1655 device_set_desc_copy(dev, buffer);
1656 ctlr->chip = idx;
1657 ctlr->chipinit = ata_highpoint_chipinit;
1658 return 0;
1659 }
1660
1661 static int
1662 ata_highpoint_chipinit(device_t dev)
1663 {
1664 struct ata_pci_controller *ctlr = device_get_softc(dev);
1665
1666 if (ata_setup_interrupt(dev))
1667 return ENXIO;
1668
1669 if (ctlr->chip->cfg2 == HPTOLD) {
1670 /* disable interrupt prediction */
1671 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1672 }
1673 else {
1674 /* disable interrupt prediction */
1675 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1676 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1677
1678 /* enable interrupts */
1679 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1680
1681 /* set clocks etc */
1682 if (ctlr->chip->cfg1 < HPT372)
1683 pci_write_config(dev, 0x5b, 0x22, 1);
1684 else
1685 pci_write_config(dev, 0x5b,
1686 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1687 }
1688 ctlr->allocate = ata_highpoint_allocate;
1689 ctlr->setmode = ata_highpoint_setmode;
1690 return 0;
1691 }
1692
1693 static int
1694 ata_highpoint_allocate(device_t dev)
1695 {
1696 struct ata_channel *ch = device_get_softc(dev);
1697
1698 /* setup the usual register normal pci style */
1699 if (ata_pci_allocate(dev))
1700 return ENXIO;
1701
1702 ch->flags |= ATA_ALWAYS_DMASTAT;
1703 return 0;
1704 }
1705
1706 static void
1707 ata_highpoint_setmode(device_t dev, int mode)
1708 {
1709 device_t gparent = GRANDPARENT(dev);
1710 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1711 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1712 struct ata_device *atadev = device_get_softc(dev);
1713 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1714 int error;
1715 u_int32_t timings33[][4] = {
1716 /* HPT366 HPT370 HPT372 HPT374 mode */
1717 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1718 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1719 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1720 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1721 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1722 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1723 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1724 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1725 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1726 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1727 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1728 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1729 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1730 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1731 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1732 };
1733
1734 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1735
1736 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1737 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1738
1739 mode = ata_highpoint_check_80pin(dev, mode);
1740
1741 /*
1742 * most if not all HPT chips cant really handle that the device is
1743 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1744 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1745 */
1746 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1747 ata_limit_mode(dev, mode, ATA_UDMA5));
1748 if (bootverbose)
1749 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1750 (error) ? "FAILURE " : "", ata_mode2str(mode));
1751 if (!error)
1752 pci_write_config(gparent, 0x40 + (devno << 2),
1753 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1754 atadev->mode = mode;
1755 }
1756
1757 static int
1758 ata_highpoint_check_80pin(device_t dev, int mode)
1759 {
1760 device_t gparent = GRANDPARENT(dev);
1761 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1762 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1763 u_int8_t reg, val, res;
1764
1765 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1766 reg = ch->unit ? 0x57 : 0x53;
1767 val = pci_read_config(gparent, reg, 1);
1768 pci_write_config(gparent, reg, val | 0x80, 1);
1769 }
1770 else {
1771 reg = 0x5b;
1772 val = pci_read_config(gparent, reg, 1);
1773 pci_write_config(gparent, reg, val & 0xfe, 1);
1774 }
1775 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1776 pci_write_config(gparent, reg, val, 1);
1777
1778 if (mode > ATA_UDMA2 && res) {
1779 ata_print_cable(dev, "controller");
1780 mode = ATA_UDMA2;
1781 }
1782 return mode;
1783 }
1784
1785
1786 /*
1787 * Intel chipset support functions
1788 */
1789 int
1790 ata_intel_ident(device_t dev)
1791 {
1792 struct ata_pci_controller *ctlr = device_get_softc(dev);
1793 struct ata_chip_id *idx;
1794 static struct ata_chip_id ids[] =
1795 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1796 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1797 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1798 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1799 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1800 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1801 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1802 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1803 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1804 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1805 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1806 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1807 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1808 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1809 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1810 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1811 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1812 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1813 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1814 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1815 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1816 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1817 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1818 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1819 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1820 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1821 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1822 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1823 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1824 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1825 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1826 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1827 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1828 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1829 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1830 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1831 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1832 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1833 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1834 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1835 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1836 { ATA_I82801HBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1837 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1838 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1839 { 0, 0, 0, 0, 0, 0}};
1840 char buffer[64];
1841
1842 if (!(idx = ata_match_chip(dev, ids)))
1843 return ENXIO;
1844
1845 ksprintf(buffer, "Intel %s %s controller",
1846 idx->text, ata_mode2str(idx->max_dma));
1847 device_set_desc_copy(dev, buffer);
1848 ctlr->chip = idx;
1849 ctlr->chipinit = ata_intel_chipinit;
1850 return 0;
1851 }
1852
1853 static int
1854 ata_intel_chipinit(device_t dev)
1855 {
1856 struct ata_pci_controller *ctlr = device_get_softc(dev);
1857
1858 if (ata_setup_interrupt(dev))
1859 return ENXIO;
1860
1861 /* good old PIIX needs special treatment (not implemented) */
1862 if (ctlr->chip->chipid == ATA_I82371FB) {
1863 ctlr->setmode = ata_intel_old_setmode;
1864 }
1865
1866 /* the intel 31244 needs special care if in DPA mode */
1867 else if (ctlr->chip->chipid == ATA_I31244) {
1868 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1869 ctlr->r_type2 = SYS_RES_MEMORY;
1870 ctlr->r_rid2 = PCIR_BAR(0);
1871 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1872 &ctlr->r_rid2,
1873 RF_ACTIVE)))
1874 return ENXIO;
1875 ctlr->channels = 4;
1876 ctlr->allocate = ata_intel_31244_allocate;
1877 ctlr->reset = ata_intel_31244_reset;
1878 }
1879 ctlr->setmode = ata_sata_setmode;
1880 }
1881
1882 /* non SATA intel chips goes here */
1883 else if (ctlr->chip->max_dma < ATA_SA150) {
1884 ctlr->allocate = ata_intel_allocate;
1885 ctlr->setmode = ata_intel_new_setmode;
1886 }
1887
1888 /* SATA parts can be either compat or AHCI */
1889 else {
1890 /* force all ports active "the legacy way" */
1891 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1892
1893 ctlr->allocate = ata_intel_allocate;
1894 ctlr->reset = ata_intel_reset;
1895
1896 /*
1897 * if we have AHCI capability and BAR(5) as a memory resource
1898 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode
1899 */
1900 if ((ctlr->chip->cfg1 == AHCI) &&
1901 (pci_read_config(dev, 0x90, 1) & 0xc0)) {
1902 ctlr->r_type2 = SYS_RES_MEMORY;
1903 ctlr->r_rid2 = PCIR_BAR(5);
1904 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1905 &ctlr->r_rid2,
1906 RF_ACTIVE)))
1907 return ata_ahci_chipinit(dev);
1908 }
1909 ctlr->setmode = ata_sata_setmode;
1910
1911 /* enable PCI interrupt */
1912 pci_write_config(dev, PCIR_COMMAND,
1913 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1914 }
1915 return 0;
1916 }
1917
1918 static int
1919 ata_intel_allocate(device_t dev)
1920 {
1921 struct ata_channel *ch = device_get_softc(dev);
1922
1923 /* setup the usual register normal pci style */
1924 if (ata_pci_allocate(dev))
1925 return ENXIO;
1926
1927 ch->flags |= ATA_ALWAYS_DMASTAT;
1928 return 0;
1929 }
1930
1931 static void
1932 ata_intel_reset(device_t dev)
1933 {
1934 device_t parent = device_get_parent(dev);
1935 struct ata_pci_controller *ctlr = device_get_softc(parent);
1936 struct ata_channel *ch = device_get_softc(dev);
1937 int mask, timeout;
1938
1939 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1940 if (ctlr->chip->cfg1) {
1941 mask = (0x0005 << ch->unit);
1942 }
1943 else {
1944 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1945 if (pci_read_config(parent, 0x90, 1) & 0x04)
1946 mask = 0x0003;
1947 else {
1948 mask = (0x0001 << ch->unit);
1949 /* XXX SOS should be in intel_allocate if we grow it */
1950 ch->flags |= ATA_NO_SLAVE;
1951 }
1952 }
1953 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1954 DELAY(10);
1955 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1956
1957 /* wait up to 1 sec for "connect well" */
1958 for (timeout = 0; timeout < 100 ; timeout++) {
1959 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1960 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1961 break;
1962 ata_udelay(10000);
1963 }
1964 ata_generic_reset(dev);
1965 }
1966
1967 static void
1968 ata_intel_old_setmode(device_t dev, int mode)
1969 {
1970 /* NOT YET */
1971 }
1972
1973 static void
1974 ata_intel_new_setmode(device_t dev, int mode)
1975 {
1976 device_t gparent = GRANDPARENT(dev);
1977 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1978 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1979 struct ata_device *atadev = device_get_softc(dev);
1980 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1981 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1982 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1983 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1984 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1985 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1986 u_int32_t mask40 = 0, new40 = 0;
1987 u_int8_t mask44 = 0, new44 = 0;
1988 int error;
1989 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1990 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1991 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */
1992 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */
1993
1994 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1995
1996 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1997 ata_print_cable(dev, "controller");
1998 mode = ATA_UDMA2;
1999 }
2000
2001 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2002
2003 if (bootverbose)
2004 device_printf(dev, "%ssetting %s on %s chip\n",
2005 (error) ? "FAILURE " : "",
2006 ata_mode2str(mode), ctlr->chip->text);
2007 if (error)
2008 return;
2009
2010 /*
2011 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary
2012 * drive 0, secondary drive 1)
2013 *
2014 * 0 Disable Ultra DMA mode
2015 * 1 Enable Ultra DMA mode
2016 *
2017 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary
2018 * drive 0, secondary drive 1).
2019 * 0000 UDMA mode 0
2020 * 0001 UDMA mode 1, 3, 5
2021 * 0010 UDMA mode 2, 4, reserved
2022 * 0011 reserved
2023 * (top two bits for each drive reserved)
2024 */
2025 #if 0
2026 device_printf(dev,
2027 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2028 reg40, reg44, reg48 ,reg4a, reg54);
2029 #endif
2030 reg48 &= ~(0x0001 << devno);
2031 reg4a &= ~(0x3 << (devno << 2));
2032 if (mode >= ATA_UDMA0) {
2033 reg48 |= 0x0001 << devno;
2034 if (mode > ATA_UDMA0)
2035 reg4a |= (1 + !(mode & 0x01)) << (devno << 2);
2036 }
2037 pci_write_config(gparent, 0x48, reg48, 2);
2038 pci_write_config(gparent, 0x4a, reg4a, 2);
2039
2040 /*
2041 * reg54:
2042 *
2043 * 32:20 reserved
2044 * 19:18 Secondary ATA signal mode
2045 * 17:16 Primary ATA signal mode
2046 * 00 = Normal (enabled)
2047 * 01 = Tri-state (disabled)
2048 * 10 = Drive Low (disabled)
2049 * 11 = Reserved
2050 *
2051 * 15 Secondary drive 1 - Base Clock
2052 * 14 Secondary drive 0 - Base Clock
2053 * 13 Primary drive 1 - Base Clock
2054 * 12 Primary drive 0 - Base Clock
2055 * 0 = Select 33 MHz clock
2056 * 1 = Select 100 Mhz clock
2057 *
2058 * 11 Reserved
2059 * 10 Vendor specific (set by BIOS?)
2060 * 09:08 Reserved
2061 *
2062 * 07 Secondary drive 1 - Cable Type
2063 * 06 Secondary drive 0 - Cable Type
2064 * 05 Primary drive 1 - Cable Type
2065 * 04 Primary drive 0 - Cable Type
2066 * 0 = 40 Conductor
2067 * 1 = 80 Conductor (or high speed cable)
2068 *
2069 * 03 Secondary drive 1 - Select 33/66 clock
2070 * 02 Secondary drive 0 - Select 33/66 clock
2071 * 01 Primary drive 1 - Select 33/66 clock
2072 * 00 Primary drive 0 - Select 33/66 clock
2073 * 0 = Select 33 MHz
2074 * 1 = Select 66 MHz
2075 *
2076 * It is unclear what this should be set to when operating
2077 * in 100MHz mode.
2078 *
2079 * NOTE: UDMA2 = 33 MHz
2080 * UDMA3 = 40 MHz (?) - unsupported
2081 * UDMA4 = 66 MHz
2082 * UDMA5 = 100 MHz
2083 * UDMA6 = 133 Mhz
2084 */
2085 reg54 |= 0x0400; /* set vendor specific bit */
2086 reg54 &= ~((0x1 << devno) | (0x1000 << devno));
2087
2088 if (mode >= ATA_UDMA5)
2089 reg54 |= (0x1000 << devno);
2090 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */
2091 reg54 |= (0x1 << devno);
2092
2093 pci_write_config(gparent, 0x54, reg54, 2);
2094
2095 /*
2096 * Reg40 (32 bits... well, actually two 16 bit registers)
2097 *
2098 * Primary channel bits 15:00, Secondary channel bits 31:00. Note
2099 * that slave timings are handled in register 44.
2100 *
2101 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges
2102 *
2103 * 14 Slave ATA Timing Register Enable (R/W)
2104 *
2105 * 13:12 IORDY Sample Mode
2106 * 00 PIO-0
2107 * 01 PIO-2, SW-2
2108 * 10 PIO-3, PIO-4, MW-1, MW-2
2109 * 11 Reserved
2110 *
2111 * 11:10 Reserved
2112 *
2113 * 09:08 Recovery Mode
2114 * 00 PIO-0, PIO-2, SW-2
2115 * 01 PIO-3, MW-1
2116 * 10 Reserved
2117 * 11 PIO-4, MW-2
2118 *
2119 * 07:04 Secondary Device Control Bits
2120 * 03:00 Primary Device Control Bits
2121 *
2122 * bit 3 DMA Timing Enable
2123 *
2124 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device
2125 *
2126 * bit 1 Enable IORDY sample point capability for PIO
2127 * xfers. Always enabled for PIO4 and PIO3, enabled
2128 * for PIO2 if indicated by the device, and otherwise
2129 * probably should be 0.
2130 *
2131 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0
2132 * timing modes.
2133 */
2134
2135 /*
2136 * Modify reg40 according to the table
2137 */
2138 if (atadev->unit == ATA_MASTER) {
2139 mask40 = 0x3300;
2140 new40 = timings[ata_mode2idx(mode)] << 8;
2141 }
2142 else {
2143 mask44 = 0x0f;
2144 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2145 (timings[ata_mode2idx(mode)] & 0x03);
2146 }
2147
2148 /*
2149 * Slave ATA timing register enable
2150 */
2151 mask40 |= 0x4000;
2152 new40 |= 0x4000;
2153
2154 /*
2155 * Device control bits 3:0 for master, 7:4 for slave.
2156 *
2157 * bit3 DMA Timing enable.
2158 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly
2159 * bit1 Enable IORDY sample point capability for PIO xfers. Always
2160 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by
2161 * the device, and otherwise should be 0.
2162 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes.
2163 *
2164 * Set to: 0 x 1 1
2165 */
2166
2167 if (atadev->unit == ATA_MASTER) {
2168 mask40 |= 0x0F;
2169 new40 |= 0x03;
2170 if (!ata_atapi(dev))
2171 new40 |= 0x04;
2172 } else {
2173 mask40 |= 0xF0;
2174 new40 |= 0x30;
2175 if (!ata_atapi(dev))
2176 new40 |= 0x40;
2177 }
2178 /*
2179 reg40 &= ~0x00ff00ff;
2180 reg40 |= 0x40774077;
2181 */
2182
2183 /*
2184 * Primary or Secondary controller
2185 */
2186 if (ch->unit) {
2187 mask40 <<= 16;
2188 new40 <<= 16;
2189 mask44 <<= 4;
2190 new44 <<= 4;
2191 }
2192 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2193 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2194
2195 #if 0
2196 reg40 = pci_read_config(gparent, 0x40, 4);
2197 reg44 = pci_read_config(gparent, 0x44, 1);
2198 reg48 = pci_read_config(gparent, 0x48, 1);
2199 reg4a = pci_read_config(gparent, 0x4a, 2);
2200 reg54 = pci_read_config(gparent, 0x54, 2);
2201 device_printf(dev,
2202 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2203 reg40, reg44, reg48 ,reg4a, reg54);
2204 #endif
2205
2206 atadev->mode = mode;
2207 }
2208
2209 static int
2210 ata_intel_31244_allocate(device_t dev)
2211 {
2212 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2213 struct ata_channel *ch = device_get_softc(dev);
2214 int i;
2215 int ch_offset;
2216
2217 ch_offset = 0x200 + ch->unit * 0x200;
2218
2219 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2220 ch->r_io[i].res = ctlr->r_res2;
2221
2222 /* setup ATA registers */
2223 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2224 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2225 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2226 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2227 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2228 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2229 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2230 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2231 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2232 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2233 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2234 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2235
2236 /* setup DMA registers */
2237 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2238 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2239 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2240
2241 /* setup SATA registers */
2242 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2243 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2244 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2245
2246 ch->flags |= ATA_NO_SLAVE;
2247 ata_pci_hw(dev);
2248 ch->hw.status = ata_intel_31244_status;
2249 ch->hw.command = ata_intel_31244_command;
2250
2251 /* enable PHY state change interrupt */
2252 ATA_OUTL(ctlr->r_res2, 0x4,
2253 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2254 return 0;
2255 }
2256
2257 static int
2258 ata_intel_31244_status(device_t dev)
2259 {
2260 /* do we have any PHY events ? */
2261 ata_sata_phy_check_events(dev);
2262
2263 /* any drive action to take care of ? */
2264 return ata_pci_status(dev);
2265 }
2266
2267 static int
2268 ata_intel_31244_command(struct ata_request *request)
2269 {
2270 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2271 struct ata_device *atadev = device_get_softc(request->dev);
2272 u_int64_t lba;
2273
2274 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2275 return (ata_generic_command(request));
2276
2277 lba = request->u.ata.lba;
2278 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2279 /* enable interrupt */
2280 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2281 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2282 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2283 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2284 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2285 ((lba >> 8) & 0x00ff));
2286 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2287 ((lba >> 16) & 0x00ff));
2288
2289 /* issue command to controller */
2290 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2291
2292 return 0;
2293 }
2294
2295 static void
2296 ata_intel_31244_reset(device_t dev)
2297 {
2298 if (ata_sata_phy_reset(dev))
2299 ata_generic_reset(dev);
2300 }
2301
2302
2303 /*
2304 * Integrated Technology Express Inc. (ITE) chipset support functions
2305 */
2306 int
2307 ata_ite_ident(device_t dev)
2308 {
2309 struct ata_pci_controller *ctlr = device_get_softc(dev);
2310 struct ata_chip_id *idx;
2311 static struct ata_chip_id ids[] =
2312 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2313 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2314 { 0, 0, 0, 0, 0, 0}};
2315 char buffer[64];
2316
2317 if (!(idx = ata_match_chip(dev, ids)))
2318 return ENXIO;
2319
2320 ksprintf(buffer, "ITE %s %s controller",
2321 idx->text, ata_mode2str(idx->max_dma));
2322 device_set_desc_copy(dev, buffer);
2323 ctlr->chip = idx;
2324 ctlr->chipinit = ata_ite_chipinit;
2325 return 0;
2326 }
2327
2328 static int
2329 ata_ite_chipinit(device_t dev)
2330 {
2331 struct ata_pci_controller *ctlr = device_get_softc(dev);
2332
2333 if (ata_setup_interrupt(dev))
2334 return ENXIO;
2335
2336 ctlr->setmode = ata_ite_setmode;
2337
2338 /* set PCI mode and 66Mhz reference clock */
2339 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2340
2341 /* set default active & recover timings */
2342 pci_write_config(dev, 0x54, 0x31, 1);
2343 pci_write_config(dev, 0x56, 0x31, 1);
2344 return 0;
2345 }
2346
2347 static void
2348 ata_ite_setmode(device_t dev, int mode)
2349 {
2350 device_t gparent = GRANDPARENT(dev);
2351 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2352 struct ata_device *atadev = device_get_softc(dev);
2353 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2354 int error;
2355
2356 /* correct the mode for what the HW supports */
2357 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2358
2359 /* check the CBLID bits for 80 conductor cable detection */
2360 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2361 (ch->unit ? (1<<3) : (1<<2)))) {
2362 ata_print_cable(dev, "controller");
2363 mode = ATA_UDMA2;
2364 }
2365
2366 /* set the wanted mode on the device */
2367 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2368
2369 if (bootverbose)
2370 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2371 (error) ? "failed" : "success", ata_mode2str(mode));
2372
2373 /* if the device accepted the mode change, setup the HW accordingly */
2374 if (!error) {
2375 if (mode >= ATA_UDMA0) {
2376 u_int8_t udmatiming[] =
2377 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2378
2379 /* enable UDMA mode */
2380 pci_write_config(gparent, 0x50,
2381 pci_read_config(gparent, 0x50, 1) &
2382 ~(1 << (devno + 3)), 1);
2383
2384 /* set UDMA timing */
2385 pci_write_config(gparent,
2386 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2387 udmatiming[mode & ATA_MODE_MASK], 1);
2388 }
2389 else {
2390 u_int8_t chtiming[] =
2391 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2392
2393 /* disable UDMA mode */
2394 pci_write_config(gparent, 0x50,
2395 pci_read_config(gparent, 0x50, 1) |
2396 (1 << (devno + 3)), 1);
2397
2398 /* set active and recover timing (shared between master & slave) */
2399 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2400 chtiming[ata_mode2idx(mode)])
2401 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2402 chtiming[ata_mode2idx(mode)], 1);
2403 }
2404 atadev->mode = mode;
2405 }
2406 }
2407
2408
2409 /*
2410 * JMicron chipset support functions
2411 */
2412 int
2413 ata_jmicron_ident(device_t dev)
2414 {
2415 struct ata_pci_controller *ctlr = device_get_softc(dev);
2416 struct ata_chip_id *idx;
2417 static struct ata_chip_id ids[] =
2418 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2419 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2420 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2421 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2422 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2423 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2424 { 0, 0, 0, 0, 0, 0}};
2425 char buffer[64];
2426
2427 if (!(idx = ata_match_chip(dev, ids)))
2428 return ENXIO;
2429
2430 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2431 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2432 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2433 idx->text, ata_mode2str(ATA_UDMA6));
2434 else
2435 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2436 idx->text, ata_mode2str(idx->max_dma));
2437 device_set_desc_copy(dev, buffer);
2438 ctlr->chip = idx;
2439 ctlr->chipinit = ata_jmicron_chipinit;
2440 return 0;
2441 }
2442
2443 static int
2444 ata_jmicron_chipinit(device_t dev)
2445 {
2446 struct ata_pci_controller *ctlr = device_get_softc(dev);
2447 int error;
2448
2449 if (ata_setup_interrupt(dev))
2450 return ENXIO;
2451
2452 /* do we have multiple PCI functions ? */
2453 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2454 /* if we have a memory BAR(5) we are on the AHCI part */
2455 ctlr->r_type2 = SYS_RES_MEMORY;
2456 ctlr->r_rid2 = PCIR_BAR(5);
2457 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2458 &ctlr->r_rid2, RF_ACTIVE)))
2459 return ata_ahci_chipinit(dev);
2460
2461 /* otherwise we are on the PATA part */
2462 ctlr->allocate = ata_pci_allocate;
2463 ctlr->reset = ata_generic_reset;
2464 ctlr->dmainit = ata_pci_dmainit;
2465 ctlr->setmode = ata_jmicron_setmode;
2466 ctlr->channels = ctlr->chip->cfg2;
2467 }
2468 else {
2469 /* set controller configuration to a combined setup we support */
2470 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2471 pci_write_config(dev, 0x80, 0x01200000, 4);
2472
2473 ctlr->r_type2 = SYS_RES_MEMORY;
2474 ctlr->r_rid2 = PCIR_BAR(5);
2475 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2476 &ctlr->r_rid2, RF_ACTIVE))) {
2477 if ((error = ata_ahci_chipinit(dev)))
2478 return error;
2479 }
2480
2481 ctlr->allocate = ata_jmicron_allocate;
2482 ctlr->reset = ata_jmicron_reset;
2483 ctlr->dmainit = ata_jmicron_dmainit;
2484 ctlr->setmode = ata_jmicron_setmode;
2485
2486 /* set the number of HW channels */
2487 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2488 }
2489 return 0;
2490 }
2491
2492 static int
2493 ata_jmicron_allocate(device_t dev)
2494 {
2495 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2496 struct ata_channel *ch = device_get_softc(dev);
2497 int error;
2498
2499 if (ch->unit >= ctlr->chip->cfg1) {
2500 ch->unit -= ctlr->chip->cfg1;
2501 error = ata_pci_allocate(dev);
2502 ch->unit += ctlr->chip->cfg1;
2503 }
2504 else
2505 error = ata_ahci_allocate(dev);
2506 return error;
2507 }
2508
2509 static void
2510 ata_jmicron_reset(device_t dev)
2511 {
2512 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2513 struct ata_channel *ch = device_get_softc(dev);
2514
2515 if (ch->unit >= ctlr->chip->cfg1)
2516 ata_generic_reset(dev);
2517 else
2518 ata_ahci_reset(dev);
2519 }
2520
2521 static void
2522 ata_jmicron_dmainit(device_t dev)
2523 {
2524 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2525 struct ata_channel *ch = device_get_softc(dev);
2526
2527 if (ch->unit >= ctlr->chip->cfg1)
2528 ata_pci_dmainit(dev);
2529 else
2530 ata_ahci_dmainit(dev);
2531 }
2532
2533 static void
2534 ata_jmicron_setmode(device_t dev, int mode)
2535 {
2536 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2537 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2538
2539 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2540 struct ata_device *atadev = device_get_softc(dev);
2541
2542 /* check for 80pin cable present */
2543 if (pci_read_config(dev, 0x40, 1) & 0x08)
2544 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2545 else
2546 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2547
2548 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2549 atadev->mode = mode;
2550 }
2551 else
2552 ata_sata_setmode(dev, mode);
2553 }
2554
2555
2556 /*
2557 * Marvell chipset support functions
2558 */
2559 #define ATA_MV_HOST_BASE(ch) \
2560 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2561 #define ATA_MV_EDMA_BASE(ch) \
2562 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2563
2564 struct ata_marvell_response {
2565 u_int16_t tag;
2566 u_int8_t edma_status;
2567 u_int8_t dev_status;
2568 u_int32_t timestamp;
2569 };
2570
2571 struct ata_marvell_dma_prdentry {
2572 u_int32_t addrlo;
2573 u_int32_t count;
2574 u_int32_t addrhi;
2575 u_int32_t reserved;
2576 };
2577
2578 int
2579 ata_marvell_ident(device_t dev)
2580 {
2581 struct ata_pci_controller *ctlr = device_get_softc(dev);
2582 struct ata_chip_id *idx;
2583 static struct ata_chip_id ids[] =
2584 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2585 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2586 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2587 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2588 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2589 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2590 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2591 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2592 { 0, 0, 0, 0, 0, 0}};
2593 char buffer[64];
2594
2595 if (!(idx = ata_match_chip(dev, ids)))
2596 return ENXIO;
2597
2598 ksprintf(buffer, "Marvell %s %s controller",
2599 idx->text, ata_mode2str(idx->max_dma));
2600 device_set_desc_copy(dev, buffer);
2601 ctlr->chip = idx;
2602 switch (ctlr->chip->cfg2) {
2603 case MV50XX:
2604 case MV60XX:
2605 ctlr->chipinit = ata_marvell_edma_chipinit;
2606 break;
2607 case MV61XX:
2608 ctlr->chipinit = ata_marvell_pata_chipinit;
2609 break;
2610 }
2611 return 0;
2612 }
2613
2614 static int
2615 ata_marvell_pata_chipinit(device_t dev)
2616 {
2617 struct ata_pci_controller *ctlr = device_get_softc(dev);
2618
2619 if (ata_setup_interrupt(dev))
2620 return ENXIO;
2621
2622 ctlr->allocate = ata_marvell_pata_allocate;
2623 ctlr->setmode = ata_marvell_pata_setmode;
2624 ctlr->channels = ctlr->chip->cfg1;
2625 return 0;
2626 }
2627
2628 static int
2629 ata_marvell_pata_allocate(device_t dev)
2630 {
2631 struct ata_channel *ch = device_get_softc(dev);
2632
2633 /* setup the usual register normal pci style */
2634 if (ata_pci_allocate(dev))
2635 return ENXIO;
2636
2637 /* dont use 32 bit PIO transfers */
2638 ch->flags |= ATA_USE_16BIT;
2639
2640 return 0;
2641 }
2642
2643 static void
2644 ata_marvell_pata_setmode(device_t dev, int mode)
2645 {
2646 device_t gparent = GRANDPARENT(dev);
2647 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2648 struct ata_device *atadev = device_get_softc(dev);
2649
2650 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2651 mode = ata_check_80pin(dev, mode);
2652 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2653 atadev->mode = mode;
2654 }
2655
2656 static int
2657 ata_marvell_edma_chipinit(device_t dev)
2658 {
2659 struct ata_pci_controller *ctlr = device_get_softc(dev);
2660
2661 if (ata_setup_interrupt(dev))
2662 return ENXIO;
2663
2664 ctlr->r_type1 = SYS_RES_MEMORY;
2665 ctlr->r_rid1 = PCIR_BAR(0);
2666 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2667 &ctlr->r_rid1, RF_ACTIVE)))
2668 return ENXIO;
2669
2670 /* mask all host controller interrupts */
2671 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2672
2673 /* mask all PCI interrupts */
2674 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2675
2676 ctlr->allocate = ata_marvell_edma_allocate;
2677 ctlr->reset = ata_marvell_edma_reset;
2678 ctlr->dmainit = ata_marvell_edma_dmainit;
2679 ctlr->setmode = ata_sata_setmode;
2680 ctlr->channels = ctlr->chip->cfg1;
2681
2682 /* clear host controller interrupts */
2683 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2684 if (ctlr->chip->cfg1 > 4)
2685 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2686
2687 /* clear PCI interrupts */
2688 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2689
2690 /* unmask PCI interrupts we want */
2691 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2692
2693 /* unmask host controller interrupts we want */
2694 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2695 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2696
2697 /* enable PCI interrupt */
2698 pci_write_config(dev, PCIR_COMMAND,
2699 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2700 return 0;
2701 }
2702
2703 static int
2704 ata_marvell_edma_allocate(device_t dev)
2705 {
2706 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2707 struct ata_channel *ch = device_get_softc(dev);
2708 u_int64_t work = ch->dma->work_bus;
2709 int i;
2710
2711 /* clear work area */
2712 bzero(ch->dma->work, 1024+256);
2713
2714 /* set legacy ATA resources */
2715 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2716 ch->r_io[i].res = ctlr->r_res1;
2717 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2718 }
2719 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2720 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2721 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2722 ata_default_registers(dev);
2723
2724 /* set SATA resources */
2725 switch (ctlr->chip->cfg2) {
2726 case MV50XX:
2727 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2728 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2729 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2730 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2731 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2732 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2733 break;
2734 case MV60XX:
2735 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2736 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2737 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2738 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2739 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2740 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2741 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2742 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2743 break;
2744 }
2745
2746 ch->flags |= ATA_NO_SLAVE;
2747 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2748 ata_generic_hw(dev);
2749 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2750 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2751 ch->hw.status = ata_marvell_edma_status;
2752
2753 /* disable the EDMA machinery */
2754 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2755 DELAY(100000); /* SOS should poll for disabled */
2756
2757 /* set configuration to non-queued 128b read transfers stop on error */
2758 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2759
2760 /* request queue base high */
2761 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2762
2763 /* request queue in ptr */
2764 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2765
2766 /* request queue out ptr */
2767 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2768
2769 /* response queue base high */
2770 work += 1024;
2771 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2772
2773 /* response queue in ptr */
2774 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2775
2776 /* response queue out ptr */
2777 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2778
2779 /* clear SATA error register */
2780 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2781
2782 /* clear any outstanding error interrupts */
2783 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2784
2785 /* unmask all error interrupts */
2786 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2787
2788 /* enable EDMA machinery */
2789 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2790 return 0;
2791 }
2792
2793 static int
2794 ata_marvell_edma_status(device_t dev)
2795 {
2796 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2797 struct ata_channel *ch = device_get_softc(dev);
2798 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2799 int shift = (ch->unit << 1) + (ch->unit > 3);
2800
2801 if (cause & (1 << shift)) {
2802
2803 /* clear interrupt(s) */
2804 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2805
2806 /* do we have any PHY events ? */
2807 ata_sata_phy_check_events(dev);
2808 }
2809
2810 /* do we have any device action ? */
2811 return (cause & (2 << shift));
2812 }
2813
2814 /* must be called with ATA channel locked and state_mtx held */
2815 static int
2816 ata_marvell_edma_begin_transaction(struct ata_request *request)
2817 {
2818 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2819 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2820 u_int32_t req_in;
2821 u_int8_t *bytep;
2822 u_int16_t *wordp;
2823 u_int32_t *quadp;
2824 int i, tag = 0x07;
2825 int dummy, error, slot;
2826
2827 /* only DMA R/W goes through the EMDA machine */
2828 if (request->u.ata.command != ATA_READ_DMA &&
2829 request->u.ata.command != ATA_WRITE_DMA) {
2830
2831 /* disable the EDMA machinery */
2832 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2833 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2834 return ata_begin_transaction(request);
2835 }
2836
2837 /* check for 48 bit access and convert if needed */
2838 ata_modify_if_48bit(request);
2839
2840 /* check sanity, setup SG list and DMA engine */
2841 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2842 request->flags & ATA_R_READ, ch->dma->sg,
2843 &dummy))) {
2844 device_printf(request->dev, "setting up DMA failed\n");
2845 request->result = error;
2846 return ATA_OP_FINISHED;
2847 }
2848
2849 /* get next free request queue slot */
2850 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2851 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2852 bytep = (u_int8_t *)(ch->dma->work);
2853 bytep += (slot << 5);
2854 wordp = (u_int16_t *)bytep;
2855 quadp = (u_int32_t *)bytep;
2856
2857 /* fill in this request */
2858 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2859 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2860 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2861
2862 i = 10;
2863 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2864 bytep[i++] = 0x10 | ATA_COUNT;
2865 bytep[i++] = request->u.ata.count & 0xff;
2866 bytep[i++] = 0x10 | ATA_COUNT;
2867
2868 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2869 bytep[i++] = 0x10 | ATA_SECTOR;
2870 bytep[i++] = request->u.ata.lba & 0xff;
2871 bytep[i++] = 0x10 | ATA_SECTOR;
2872
2873 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2874 bytep[i++] = 0x10 | ATA_CYL_LSB;
2875 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2876 bytep[i++] = 0x10 | ATA_CYL_LSB;
2877
2878 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2879 bytep[i++] = 0x10 | ATA_CYL_MSB;
2880 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2881 bytep[i++] = 0x10 | ATA_CYL_MSB;
2882
2883 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2884 bytep[i++] = 0x10 | ATA_DRIVE;
2885
2886 bytep[i++] = request->u.ata.command;
2887 bytep[i++] = 0x90 | ATA_COMMAND;
2888
2889 /* enable EDMA machinery if needed */
2890 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2891 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2892 while (!(ATA_INL(ctlr->r_res1,
2893 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2894 DELAY(10);
2895 }
2896
2897 /* tell EDMA it has a new request */
2898 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2899 req_in &= 0xfffffc00;
2900 req_in += (slot << 5);
2901 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2902
2903 return ATA_OP_CONTINUES;
2904 }
2905
2906 /* must be called with ATA channel locked and state_mtx held */
2907 static int
2908 ata_marvell_edma_end_transaction(struct ata_request *request)
2909 {
2910 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2911 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2912 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2913 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2914 int res;
2915
2916 /* EDMA interrupt */
2917 if ((icr & (0x0001 << (ch->unit & 3)))) {
2918 struct ata_marvell_response *response;
2919 u_int32_t rsp_in, rsp_out;
2920 int slot;
2921
2922 /* stop timeout */
2923 callout_stop(&request->callout);
2924
2925 /* get response ptr's */
2926 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2927 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2928 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2929 rsp_out &= 0xffffff00;
2930 rsp_out += (slot << 3);
2931 response = (struct ata_marvell_response *)
2932 (ch->dma->work + 1024 + (slot << 3));
2933
2934 /* record status for this request */
2935 request->status = response->dev_status;
2936 request->error = 0;
2937
2938 /* ack response */
2939 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2940
2941 /* update progress */
2942 if (!(request->status & ATA_S_ERROR) &&
2943 !(request->flags & ATA_R_TIMEOUT))
2944 request->donecount = request->bytecount;
2945
2946 /* unload SG list */
2947 ch->dma->unload(ch->dev);
2948
2949 res = ATA_OP_FINISHED;
2950 }
2951
2952 /* legacy ATA interrupt */
2953 else {
2954 res = ata_end_transaction(request);
2955 }
2956
2957 /* ack interrupt */
2958 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2959 return res;
2960 }
2961
2962 static void
2963 ata_marvell_edma_reset(device_t dev)
2964 {
2965 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2966 struct ata_channel *ch = device_get_softc(dev);
2967
2968 /* disable the EDMA machinery */
2969 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2970 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2971 DELAY(10);
2972
2973 /* clear SATA error register */
2974 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2975
2976 /* clear any outstanding error interrupts */
2977 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2978
2979 /* unmask all error interrupts */
2980 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2981
2982 /* enable channel and test for devices */
2983 if (ata_sata_phy_reset(dev))
2984 ata_generic_reset(dev);
2985
2986 /* enable EDMA machinery */
2987 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2988 }
2989
2990 static void
2991 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2992 int error)
2993 {
2994 struct ata_dmasetprd_args *args = xsc;
2995 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2996 int i;
2997
2998 if ((args->error = error))
2999 return;
3000
3001 for (i = 0; i < nsegs; i++) {
3002 prd[i].addrlo = htole32(segs[i].ds_addr);
3003 prd[i].count = htole32(segs[i].ds_len);
3004 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
3005 }
3006 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3007 }
3008
3009 static void
3010 ata_marvell_edma_dmainit(device_t dev)
3011 {
3012 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3013 struct ata_channel *ch = device_get_softc(dev);
3014
3015 ata_dmainit(dev);
3016 if (ch->dma) {
3017 /* note start and stop are not used here */
3018 ch->dma->setprd = ata_marvell_edma_dmasetprd;
3019
3020 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
3021 ch->dma->max_address = BUS_SPACE_MAXADDR;
3022 }
3023 }
3024
3025
3026 /*
3027 * National chipset support functions
3028 */
3029 int
3030 ata_national_ident(device_t dev)
3031 {
3032 struct ata_pci_controller *ctlr = device_get_softc(dev);
3033
3034 /* this chip is a clone of the Cyrix chip, bugs and all */
3035 if (pci_get_devid(dev) == ATA_SC1100) {
3036 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
3037 ctlr->chipinit = ata_national_chipinit;
3038 return 0;
3039 }
3040 return ENXIO;
3041 }
3042
3043 static int
3044 ata_national_chipinit(device_t dev)
3045 {
3046 struct ata_pci_controller *ctlr = device_get_softc(dev);
3047
3048 if (ata_setup_interrupt(dev))
3049 return ENXIO;
3050
3051 ctlr->setmode = ata_national_setmode;
3052 return 0;
3053 }
3054
3055 static void
3056 ata_national_setmode(device_t dev, int mode)
3057 {
3058 device_t gparent = GRANDPARENT(dev);
3059 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3060 struct ata_device *atadev = device_get_softc(dev);
3061 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3062 u_int32_t piotiming[] =
3063 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
3064 0x00803020, 0x20102010, 0x00100010,
3065 0x00100010, 0x00100010, 0x00100010 };
3066 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
3067 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
3068 int error;
3069
3070 ch->dma->alignment = 16;
3071 ch->dma->max_iosize = 126 * DEV_BSIZE;
3072
3073 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
3074
3075 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3076
3077 if (bootverbose)
3078 device_printf(dev, "%s setting %s on National chip\n",
3079 (error) ? "failed" : "success", ata_mode2str(mode));
3080 if (!error) {
3081 if (mode >= ATA_UDMA0) {
3082 pci_write_config(gparent, 0x44 + (devno << 3),
3083 udmatiming[mode & ATA_MODE_MASK], 4);
3084 }
3085 else if (mode >= ATA_WDMA0) {
3086 pci_write_config(gparent, 0x44 + (devno << 3),
3087 dmatiming[mode & ATA_MODE_MASK], 4);
3088 }
3089 else {
3090 pci_write_config(gparent, 0x44 + (devno << 3),
3091 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
3092 0x80000000, 4);
3093 }
3094 pci_write_config(gparent, 0x40 + (devno << 3),
3095 piotiming[ata_mode2idx(mode)], 4);
3096 atadev->mode = mode;
3097 }
3098 }
3099
3100 /*
3101 * NetCell chipset support functions
3102 */
3103 int
3104 ata_netcell_ident(device_t dev)
3105 {
3106 struct ata_pci_controller *ctlr = device_get_softc(dev);
3107
3108 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
3109 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
3110 ctlr->chipinit = ata_netcell_chipinit;
3111 return 0;
3112 }
3113 return ENXIO;
3114 }
3115
3116 static int
3117 ata_netcell_chipinit(device_t dev)
3118 {
3119 struct ata_pci_controller *ctlr = device_get_softc(dev);
3120
3121 if (ata_generic_chipinit(dev))
3122 return ENXIO;
3123
3124 ctlr->allocate = ata_netcell_allocate;
3125 return 0;
3126 }
3127
3128 static int
3129 ata_netcell_allocate(device_t dev)
3130 {
3131 struct ata_channel *ch = device_get_softc(dev);
3132
3133 /* setup the usual register normal pci style */
3134 if (ata_pci_allocate(dev))
3135 return ENXIO;
3136
3137 /* the NetCell only supports 16 bit PIO transfers */
3138 ch->flags |= ATA_USE_16BIT;
3139
3140 return 0;
3141 }
3142
3143
3144 /*
3145 * nVidia chipset support functions
3146 */
3147 int
3148 ata_nvidia_ident(device_t dev)
3149 {
3150 struct ata_pci_controller *ctlr = device_get_softc(dev);
3151 struct ata_chip_id *idx;
3152 static struct ata_chip_id ids[] =
3153 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3154 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3155 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3156 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3157 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3158 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3159 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3160 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3161 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3162 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3163 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3164 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3165 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3166 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3167 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3168 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3169 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3170 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3171 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3172 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3173 { 0, 0, 0, 0, 0, 0}} ;
3174 char buffer[64] ;
3175
3176 if (!(idx = ata_match_chip(dev, ids)))
3177 return ENXIO;
3178
3179 ksprintf(buffer, "nVidia %s %s controller",
3180 idx->text, ata_mode2str(idx->max_dma));
3181 device_set_desc_copy(dev, buffer);
3182 ctlr->chip = idx;
3183 ctlr->chipinit = ata_nvidia_chipinit;
3184 return 0;
3185 }
3186
3187 static int
3188 ata_nvidia_chipinit(device_t dev)
3189 {
3190 struct ata_pci_controller *ctlr = device_get_softc(dev);
3191
3192 if (ata_setup_interrupt(dev))
3193 return ENXIO;
3194
3195 if (ctlr->chip->max_dma >= ATA_SA150) {
3196 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3197 ctlr->r_type2 = SYS_RES_IOPORT;
3198 else
3199 ctlr->r_type2 = SYS_RES_MEMORY;
3200 ctlr->r_rid2 = PCIR_BAR(5);
3201 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3202 &ctlr->r_rid2, RF_ACTIVE))) {
3203 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3204
3205 ctlr->allocate = ata_nvidia_allocate;
3206 ctlr->reset = ata_nvidia_reset;
3207
3208 /* enable control access */
3209 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3210
3211 if (ctlr->chip->cfg2 & NVQ) {
3212 /* clear interrupt status */
3213 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3214
3215 /* enable device and PHY state change interrupts */
3216 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3217
3218 /* disable NCQ support */
3219 ATA_OUTL(ctlr->r_res2, 0x0400,
3220 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3221 }
3222 else {
3223 /* clear interrupt status */
3224 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3225
3226 /* enable device and PHY state change interrupts */
3227 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3228 }
3229
3230 /* enable PCI interrupt */
3231 pci_write_config(dev, PCIR_COMMAND,
3232 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3233
3234 }
3235 ctlr->setmode = ata_sata_setmode;
3236 }
3237 else {
3238 /* disable prefetch, postwrite */
3239 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3240 ctlr->setmode = ata_via_family_setmode;
3241 }
3242 return 0;
3243 }
3244
3245 static int
3246 ata_nvidia_allocate(device_t dev)
3247 {
3248 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3249 struct ata_channel *ch = device_get_softc(dev);
3250
3251 /* setup the usual register normal pci style */
3252 if (ata_pci_allocate(dev))
3253 return ENXIO;
3254
3255 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3256 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3257 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3258 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3259 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3260 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3261
3262 ch->hw.status = ata_nvidia_status;
3263 ch->flags |= ATA_NO_SLAVE;
3264
3265 return 0;
3266 }
3267
3268 static int
3269 ata_nvidia_status(device_t dev)
3270 {
3271 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3272 struct ata_channel *ch = device_get_softc(dev);
3273 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3274 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3275 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3276
3277 /* do we have any PHY events ? */
3278 if (istatus & (0x0c << shift))
3279 ata_sata_phy_check_events(dev);
3280
3281 /* clear interrupt(s) */
3282 ATA_OUTB(ctlr->r_res2, offset,
3283 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3284
3285 /* do we have any device action ? */
3286 return (istatus & (0x01 << shift));
3287 }
3288
3289 static void
3290 ata_nvidia_reset(device_t dev)
3291 {
3292 if (ata_sata_phy_reset(dev))
3293 ata_generic_reset(dev);
3294 }
3295
3296
3297 /*
3298 * Promise chipset support functions
3299 */
3300 #define ATA_PDC_APKT_OFFSET 0x00000010
3301 #define ATA_PDC_HPKT_OFFSET 0x00000040
3302 #define ATA_PDC_ASG_OFFSET 0x00000080
3303 #define ATA_PDC_LSG_OFFSET 0x000000c0
3304 #define ATA_PDC_HSG_OFFSET 0x00000100
3305 #define ATA_PDC_CHN_OFFSET 0x00000400
3306 #define ATA_PDC_BUF_BASE 0x00400000
3307 #define ATA_PDC_BUF_OFFSET 0x00100000
3308 #define ATA_PDC_MAX_HPKT 8
3309 #define ATA_PDC_WRITE_REG 0x00
3310 #define ATA_PDC_WRITE_CTL 0x0e
3311 #define ATA_PDC_WRITE_END 0x08
3312 #define ATA_PDC_WAIT_NBUSY 0x10
3313 #define ATA_PDC_WAIT_READY 0x18
3314 #define ATA_PDC_1B 0x20
3315 #define ATA_PDC_2B 0x40
3316
3317 struct host_packet {
3318 u_int32_t addr;
3319 TAILQ_ENTRY(host_packet) chain;
3320 };
3321
3322 struct ata_promise_sx4 {
3323 struct spinlock mtx;
3324 TAILQ_HEAD(, host_packet) queue;
3325 int busy;
3326 };
3327
3328 int
3329 ata_promise_ident(device_t dev)
3330 {
3331 struct ata_pci_controller *ctlr = device_get_softc(dev);
3332 struct ata_chip_id *idx;
3333 static struct ata_chip_id ids[] =
3334 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3335 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3336 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3337 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3338 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3339 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3340 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3341 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3342 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3343 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3344 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3345 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3346 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3347 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3348 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3349 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3350 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3351 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3352 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3353 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3354 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3355 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3356 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3357 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3358 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3359 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3360 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3361 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3362 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3363 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3364 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3365 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3366 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3367 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3368 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3369 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3370 { 0, 0, 0, 0, 0, 0}};
3371 char buffer[64];
3372 uintptr_t devid = 0;
3373
3374 if (!(idx = ata_match_chip(dev, ids)))
3375 return ENXIO;
3376
3377 /* if we are on a SuperTrak SX6000 dont attach */
3378 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3379 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3380 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3381 devid == ATA_I960RM)
3382 return ENXIO;
3383
3384 strcpy(buffer, "Promise ");
3385 strcat(buffer, idx->text);
3386
3387 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3388 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3389 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3390 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3391 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3392 static long start = 0, end = 0;
3393
3394 if (pci_get_slot(dev) == 1) {
3395 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3396 strcat(buffer, " (channel 0+1)");
3397 }
3398 else if (pci_get_slot(dev) == 2 && start && end) {
3399 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3400 strcat(buffer, " (channel 2+3)");
3401 }
3402 else {
3403 start = end = 0;
3404 }
3405 }
3406 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3407 device_set_desc_copy(dev, buffer);
3408 ctlr->chip = idx;
3409 ctlr->chipinit = ata_promise_chipinit;
3410 return 0;
3411 }
3412
3413 static int
3414 ata_promise_chipinit(device_t dev)
3415 {
3416 struct ata_pci_controller *ctlr = device_get_softc(dev);
3417 int fake_reg, stat_reg;
3418
3419 if (ata_setup_interrupt(dev))
3420 return ENXIO;
3421
3422 switch (ctlr->chip->cfg1) {
3423 case PRNEW:
3424 /* setup clocks */
3425 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3426
3427 ctlr->dmainit = ata_promise_dmainit;
3428 /* FALLTHROUGH */
3429
3430 case PROLD:
3431 /* enable burst mode */
3432 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3433 ctlr->allocate = ata_promise_allocate;
3434 ctlr->setmode = ata_promise_setmode;
3435 return 0;
3436
3437 case PRTX:
3438 ctlr->allocate = ata_promise_tx2_allocate;
3439 ctlr->setmode = ata_promise_setmode;
3440 return 0;
3441
3442 case PRMIO:
3443 ctlr->r_type1 = SYS_RES_MEMORY;
3444 ctlr->r_rid1 = PCIR_BAR(4);
3445 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3446 &ctlr->r_rid1, RF_ACTIVE)))
3447 goto failnfree;
3448
3449 ctlr->r_type2 = SYS_RES_MEMORY;
3450 ctlr->r_rid2 = PCIR_BAR(3);
3451 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3452 &ctlr->r_rid2, RF_ACTIVE)))
3453 goto failnfree;
3454
3455 if (ctlr->chip->cfg2 == PRSX4X) {
3456 struct ata_promise_sx4 *hpkt;
3457 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3458
3459 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3460 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3461 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) {
3462 device_printf(dev, "unable to setup interrupt\n");
3463 goto failnfree;
3464 }
3465
3466 /* print info about cache memory */
3467 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3468 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3469 ((dimm >> 24) & 0xff),
3470 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3471 " ECC enabled" : "" );
3472
3473 /* adjust cache memory parameters */
3474 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3475 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3476
3477 /* setup host packet controls */
3478 hpkt = kmalloc(sizeof(struct ata_promise_sx4),
3479 M_TEMP, M_INTWAIT | M_ZERO);
3480 spin_init(&hpkt->mtx);
3481 TAILQ_INIT(&hpkt->queue);
3482 hpkt->busy = 0;
3483 device_set_ivars(dev, hpkt);
3484 ctlr->allocate = ata_promise_mio_allocate;
3485 ctlr->reset = ata_promise_mio_reset;
3486 ctlr->dmainit = ata_promise_mio_dmainit;
3487 ctlr->setmode = ata_promise_setmode;
3488 ctlr->channels = 4;
3489 return 0;
3490 }
3491
3492 /* mio type controllers need an interrupt intercept */
3493 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3494 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3495 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) {
3496 device_printf(dev, "unable to setup interrupt\n");
3497 goto failnfree;
3498 }
3499
3500 switch (ctlr->chip->cfg2) {
3501 case PRPATA:
3502 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3503 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3504 goto sata150;
3505 case PRCMBO:
3506 ctlr->channels = 3;
3507 goto sata150;
3508 case PRSATA:
3509 ctlr->channels = 4;
3510 sata150:
3511 fake_reg = 0x60;
3512 stat_reg = 0x6c;
3513 break;
3514
3515 case PRCMBO2:
3516 ctlr->channels = 3;
3517 goto sataii;
3518 case PRSATA2:
3519 default:
3520 ctlr->channels = 4;
3521 sataii:
3522 fake_reg = 0x54;
3523 stat_reg = 0x60;
3524 break;
3525 }
3526
3527 /* prime fake interrupt register */
3528 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3529
3530 /* clear SATA status */
3531 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3532
3533 ctlr->allocate = ata_promise_mio_allocate;
3534 ctlr->reset = ata_promise_mio_reset;
3535 ctlr->dmainit = ata_promise_mio_dmainit;
3536 ctlr->setmode = ata_promise_mio_setmode;
3537
3538 return 0;
3539 }
3540
3541 failnfree:
3542 if (ctlr->r_res2)
3543 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3544 if (ctlr->r_res1)
3545 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3546 return ENXIO;
3547 }
3548
3549 static int
3550 ata_promise_allocate(device_t dev)
3551 {
3552 struct ata_channel *ch = device_get_softc(dev);
3553
3554 if (ata_pci_allocate(dev))
3555 return ENXIO;
3556
3557 ch->hw.status = ata_promise_status;
3558 return 0;
3559 }
3560
3561 static int
3562 ata_promise_status(device_t dev)
3563 {
3564 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3565 struct ata_channel *ch = device_get_softc(dev);
3566
3567 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3568 return ata_pci_status(dev);
3569 }
3570 return 0;
3571 }
3572
3573 static int
3574 ata_promise_dmastart(device_t dev)
3575 {
3576 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3577 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3578 struct ata_device *atadev = device_get_softc(dev);
3579
3580 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3581 ATA_OUTB(ctlr->r_res1, 0x11,
3582 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3583 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3584 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3585 (ch->dma->cur_iosize >> 1));
3586 }
3587 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3588 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3589 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3590 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3591 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3592 ATA_BMCMD_START_STOP);
3593 ch->flags |= ATA_DMA_ACTIVE;
3594 return 0;
3595 }
3596
3597 static int
3598 ata_promise_dmastop(device_t dev)
3599 {
3600 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3601 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3602 struct ata_device *atadev = device_get_softc(dev);
3603 int error;
3604
3605 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3606 ATA_OUTB(ctlr->r_res1, 0x11,
3607 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3608 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3609 }
3610 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3611 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3612 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3613 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3614 ch->flags &= ~ATA_DMA_ACTIVE;
3615 return error;
3616 }
3617
3618 static void
3619 ata_promise_dmareset(device_t dev)
3620 {
3621 struct ata_channel *ch = device_get_softc(dev);
3622
3623 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3624 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3625 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3626 ch->flags &= ~ATA_DMA_ACTIVE;
3627 }
3628
3629 static void
3630 ata_promise_dmainit(device_t dev)
3631 {
3632 struct ata_channel *ch = device_get_softc(dev);
3633
3634 ata_dmainit(dev);
3635 if (ch->dma) {
3636 ch->dma->start = ata_promise_dmastart;
3637 ch->dma->stop = ata_promise_dmastop;
3638 ch->dma->reset = ata_promise_dmareset;
3639 }
3640 }
3641
3642 static void
3643 ata_promise_setmode(device_t dev, int mode)
3644 {
3645 device_t gparent = GRANDPARENT(dev);
3646 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3647 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3648 struct ata_device *atadev = device_get_softc(dev);
3649 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3650 int error;
3651 u_int32_t timings[][2] = {
3652 /* PROLD PRNEW mode */
3653 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3654 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3655 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3656 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3657 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3658 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3659 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3660 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3661 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3662 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3663 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3664 { 0, 0x00424ef6 }, /* UDMA 3 */
3665 { 0, 0x004127f3 }, /* UDMA 4 */
3666 { 0, 0x004127f3 } /* UDMA 5 */
3667 };
3668
3669 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3670
3671 switch (ctlr->chip->cfg1) {
3672 case PROLD:
3673 case PRNEW:
3674 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3675 (ch->unit ? 1 << 11 : 1 << 10))) {
3676 ata_print_cable(dev, "controller");
3677 mode = ATA_UDMA2;
3678 }
3679 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3680 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3681 break;
3682
3683 case PRTX:
3684 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3685 if (mode > ATA_UDMA2 &&
3686 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3687 ata_print_cable(dev, "controller");
3688 mode = ATA_UDMA2;
3689 }
3690 break;
3691
3692 case PRMIO:
3693 if (mode > ATA_UDMA2 &&
3694 (ATA_INL(ctlr->r_res2,
3695 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3696 (ch->unit << 7)) & 0x01000000)) {
3697 ata_print_cable(dev, "controller");
3698 mode = ATA_UDMA2;
3699 }
3700 break;
3701 }
3702
3703 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3704
3705 if (bootverbose)
3706 device_printf(dev, "%ssetting %s on %s chip\n",
3707 (error) ? "FAILURE " : "",
3708 ata_mode2str(mode), ctlr->chip->text);
3709 if (!error) {
3710 if (ctlr->chip->cfg1 < PRTX)
3711 pci_write_config(gparent, 0x60 + (devno << 2),
3712 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3713 atadev->mode = mode;
3714 }
3715 return;
3716 }
3717
3718 static int
3719 ata_promise_tx2_allocate(device_t dev)
3720 {
3721 struct ata_channel *ch = device_get_softc(dev);
3722
3723 if (ata_pci_allocate(dev))
3724 return ENXIO;
3725
3726 ch->hw.status = ata_promise_tx2_status;
3727 return 0;
3728 }
3729
3730 static int
3731 ata_promise_tx2_status(device_t dev)
3732 {
3733 struct ata_channel *ch = device_get_softc(dev);
3734
3735 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3736 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3737 return ata_pci_status(dev);
3738 }
3739 return 0;
3740 }
3741
3742 static int
3743 ata_promise_mio_allocate(device_t dev)
3744 {
3745 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3746 struct ata_channel *ch = device_get_softc(dev);
3747 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3748 int i;
3749
3750 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3751 ch->r_io[i].res = ctlr->r_res2;
3752 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3753 }
3754 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3755 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3756 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3757 ata_default_registers(dev);
3758 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3759 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3760 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3761 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3762 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3763 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3764 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3765 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3766 ch->flags |= ATA_NO_SLAVE;
3767 }
3768 ch->flags |= ATA_USE_16BIT;
3769
3770 ata_generic_hw(dev);
3771 if (ctlr->chip->cfg2 & PRSX4X) {
3772 ch->hw.command = ata_promise_sx4_command;
3773 }
3774 else {
3775 ch->hw.command = ata_promise_mio_command;
3776 ch->hw.status = ata_promise_mio_status;
3777 }
3778 return 0;
3779 }
3780
3781 static void
3782 ata_promise_mio_intr(void *data)
3783 {
3784 struct ata_pci_controller *ctlr = data;
3785 struct ata_channel *ch;
3786 u_int32_t vector;
3787 int unit, fake_reg;
3788
3789 switch (ctlr->chip->cfg2) {
3790 case PRPATA:
3791 case PRCMBO:
3792 case PRSATA:
3793 fake_reg = 0x60;
3794 break;
3795 case PRCMBO2:
3796 case PRSATA2:
3797 default:
3798 fake_reg = 0x54;
3799 break;
3800 }
3801
3802 /*
3803 * since reading interrupt status register on early "mio" chips
3804 * clears the status bits we cannot read it for each channel later on
3805 * in the generic interrupt routine.
3806 * store the bits in an unused register in the chip so we can read
3807 * it from there safely to get around this "feature".
3808 */
3809 vector = ATA_INL(ctlr->r_res2, 0x040);
3810 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3811 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3812
3813 for (unit = 0; unit < ctlr->channels; unit++) {
3814 if ((ch = ctlr->interrupt[unit].argument))
3815 ctlr->interrupt[unit].function(ch);
3816 }
3817
3818 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3819 }
3820
3821 static int
3822 ata_promise_mio_status(device_t dev)
3823 {
3824 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3825 struct ata_channel *ch = device_get_softc(dev);
3826 struct ata_connect_task *tp;
3827 u_int32_t fake_reg, stat_reg, vector, status;
3828
3829 switch (ctlr->chip->cfg2) {
3830 case PRPATA:
3831 case PRCMBO:
3832 case PRSATA:
3833 fake_reg = 0x60;
3834 stat_reg = 0x6c;
3835 break;
3836 case PRCMBO2:
3837 case PRSATA2:
3838 default:
3839 fake_reg = 0x54;
3840 stat_reg = 0x60;
3841 break;
3842 }
3843
3844 /* read and acknowledge interrupt */
3845 vector = ATA_INL(ctlr->r_res2, fake_reg);
3846
3847 /* read and clear interface status */
3848 status = ATA_INL(ctlr->r_res2, stat_reg);
3849 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3850
3851 /* check for and handle disconnect events */
3852 if ((status & (0x00000001 << ch->unit)) &&
3853 (tp = (struct ata_connect_task *)
3854 kmalloc(sizeof(struct ata_connect_task),
3855 M_ATA, M_INTWAIT | M_ZERO))) {
3856
3857 if (bootverbose)
3858 device_printf(ch->dev, "DISCONNECT requested\n");
3859 tp->action = ATA_C_DETACH;
3860 tp->dev = ch->dev;
3861 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3862 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3863 }
3864
3865 /* check for and handle connect events */
3866 if ((status & (0x00000010 << ch->unit)) &&
3867 (tp = (struct ata_connect_task *)
3868 kmalloc(sizeof(struct ata_connect_task),
3869 M_ATA, M_INTWAIT | M_ZERO))) {
3870
3871 if (bootverbose)
3872 device_printf(ch->dev, "CONNECT requested\n");
3873 tp->action = ATA_C_ATTACH;
3874 tp->dev = ch->dev;
3875 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3876 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3877 }
3878
3879 /* do we have any device action ? */
3880 return (vector & (1 << (ch->unit + 1)));
3881 }
3882
3883 static int
3884 ata_promise_mio_command(struct ata_request *request)
3885 {
3886 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3887 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3888 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3889
3890 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3891
3892 /* XXX SOS add ATAPI commands support later */
3893 switch (request->u.ata.command) {
3894 default:
3895 return ata_generic_command(request);
3896
3897 case ATA_READ_DMA:
3898 case ATA_READ_DMA48:
3899 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3900 break;
3901
3902 case ATA_WRITE_DMA:
3903 case ATA_WRITE_DMA48:
3904 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3905 break;
3906 }
3907 wordp[1] = htole32(ch->dma->sg_bus);
3908 wordp[2] = 0;
3909 ata_promise_apkt((u_int8_t*)wordp, request);
3910
3911 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3912 return 0;
3913 }
3914
3915 static void
3916 ata_promise_mio_reset(device_t dev)
3917 {
3918 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3919 struct ata_channel *ch = device_get_softc(dev);
3920 struct ata_promise_sx4 *hpktp;
3921
3922 switch (ctlr->chip->cfg2) {
3923 case PRSX4X:
3924
3925 /* softreset channel ATA module */
3926 hpktp = device_get_ivars(ctlr->dev);
3927 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3928 ata_udelay(1000);
3929 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3930 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3931 ~0x00003f9f) | (ch->unit + 1));
3932
3933 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3934 spin_lock_wr(&hpktp->mtx);
3935 ATA_OUTL(ctlr->r_res2, 0xc012c,
3936 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3937 DELAY(10);
3938 ATA_OUTL(ctlr->r_res2, 0xc012c,
3939 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3940 hpktp->busy = 0;
3941 spin_unlock_wr(&hpktp->mtx);
3942 ata_generic_reset(dev);
3943 break;
3944
3945 case PRPATA:
3946 case PRCMBO:
3947 case PRSATA:
3948 if ((ctlr->chip->cfg2 == PRSATA) ||
3949 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3950
3951 /* mask plug/unplug intr */
3952 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3953 }
3954
3955 /* softreset channels ATA module */
3956 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3957 ata_udelay(10000);
3958 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3959 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3960 ~0x00003f9f) | (ch->unit + 1));
3961
3962 if ((ctlr->chip->cfg2 == PRSATA) ||
3963 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3964
3965 if (ata_sata_phy_reset(dev))
3966 ata_generic_reset(dev);
3967
3968 /* reset and enable plug/unplug intr */
3969 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3970 }
3971 else
3972 ata_generic_reset(dev);
3973 break;
3974
3975 case PRCMBO2:
3976 case PRSATA2:
3977 if ((ctlr->chip->cfg2 == PRSATA2) ||
3978 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3979 /* set portmultiplier port */
3980 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3981
3982 /* mask plug/unplug intr */
3983 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3984 }
3985
3986 /* softreset channels ATA module */
3987 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3988 ata_udelay(10000);
3989 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3990 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3991 ~0x00003f9f) | (ch->unit + 1));
3992
3993 if ((ctlr->chip->cfg2 == PRSATA2) ||
3994 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3995
3996 /* set PHY mode to "improved" */
3997 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3998 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
3999 ~0x00000003) | 0x00000001);
4000
4001 if (ata_sata_phy_reset(dev))
4002 ata_generic_reset(dev);
4003
4004 /* reset and enable plug/unplug intr */
4005 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
4006
4007 /* set portmultiplier port */
4008 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
4009 }
4010 else
4011 ata_generic_reset(dev);
4012 break;
4013
4014 }
4015 }
4016
4017 static void
4018 ata_promise_mio_dmainit(device_t dev)
4019 {
4020 /* note start and stop are not used here */
4021 ata_dmainit(dev);
4022 }
4023
4024 static void
4025 ata_promise_mio_setmode(device_t dev, int mode)
4026 {
4027 device_t gparent = GRANDPARENT(dev);
4028 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4029 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4030
4031 if ( (ctlr->chip->cfg2 == PRSATA) ||
4032 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
4033 (ctlr->chip->cfg2 == PRSATA2) ||
4034 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
4035 ata_sata_setmode(dev, mode);
4036 else
4037 ata_promise_setmode(dev, mode);
4038 }
4039
4040 static void
4041 ata_promise_sx4_intr(void *data)
4042 {
4043 struct ata_pci_controller *ctlr = data;
4044 struct ata_channel *ch;
4045 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
4046 int unit;
4047
4048 for (unit = 0; unit < ctlr->channels; unit++) {
4049 if (vector & (1 << (unit + 1)))
4050 if ((ch = ctlr->interrupt[unit].argument))
4051 ctlr->interrupt[unit].function(ch);
4052 if (vector & (1 << (unit + 5)))
4053 if ((ch = ctlr->interrupt[unit].argument))
4054 ata_promise_queue_hpkt(ctlr,
4055 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4056 ATA_PDC_HPKT_OFFSET));
4057 if (vector & (1 << (unit + 9))) {
4058 ata_promise_next_hpkt(ctlr);
4059 if ((ch = ctlr->interrupt[unit].argument))
4060 ctlr->interrupt[unit].function(ch);
4061 }
4062 if (vector & (1 << (unit + 13))) {
4063 ata_promise_next_hpkt(ctlr);
4064 if ((ch = ctlr->interrupt[unit].argument))
4065 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4066 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4067 ATA_PDC_APKT_OFFSET));
4068 }
4069 }
4070 }
4071
4072 static int
4073 ata_promise_sx4_command(struct ata_request *request)
4074 {
4075 device_t gparent = GRANDPARENT(request->dev);
4076 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4077 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4078 struct ata_dma_prdentry *prd = ch->dma->sg;
4079 caddr_t window = rman_get_virtual(ctlr->r_res1);
4080 u_int32_t *wordp;
4081 int i, idx, length = 0;
4082
4083 /* XXX SOS add ATAPI commands support later */
4084 switch (request->u.ata.command) {
4085
4086 default:
4087 return -1;
4088
4089 case ATA_ATA_IDENTIFY:
4090 case ATA_READ:
4091 case ATA_READ48:
4092 case ATA_READ_MUL:
4093 case ATA_READ_MUL48:
4094 case ATA_WRITE:
4095 case ATA_WRITE48:
4096 case ATA_WRITE_MUL:
4097 case ATA_WRITE_MUL48:
4098 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4099 return ata_generic_command(request);
4100
4101 case ATA_SETFEATURES:
4102 case ATA_FLUSHCACHE:
4103 case ATA_FLUSHCACHE48:
4104 case ATA_SLEEP:
4105 case ATA_SET_MULTI:
4106 wordp = (u_int32_t *)
4107 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4108 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4109 wordp[1] = 0;
4110 wordp[2] = 0;
4111 ata_promise_apkt((u_int8_t *)wordp, request);
4112 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4113 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4114 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4115 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4116 return 0;
4117
4118 case ATA_READ_DMA:
4119 case ATA_READ_DMA48:
4120 case ATA_WRITE_DMA:
4121 case ATA_WRITE_DMA48:
4122 wordp = (u_int32_t *)
4123 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4124 i = idx = 0;
4125 do {
4126 wordp[idx++] = prd[i].addr;
4127 wordp[idx++] = prd[i].count;
4128 length += (prd[i].count & ~ATA_DMA_EOT);
4129 } while (!(prd[i++].count & ATA_DMA_EOT));
4130
4131 wordp = (u_int32_t *)
4132 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4133 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4134 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4135
4136 wordp = (u_int32_t *)
4137 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4138 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4139 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4140
4141 wordp = (u_int32_t *)
4142 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4143 if (request->flags & ATA_R_READ)
4144 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4145 if (request->flags & ATA_R_WRITE)
4146 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4147 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4148 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4149 wordp[3] = 0;
4150
4151 wordp = (u_int32_t *)
4152 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4153 if (request->flags & ATA_R_READ)
4154 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4155 if (request->flags & ATA_R_WRITE)
4156 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4157 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4158 wordp[2] = 0;
4159 ata_promise_apkt((u_int8_t *)wordp, request);
4160 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4161
4162 if (request->flags & ATA_R_READ) {
4163 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4164 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4165 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4166 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4167 }
4168 if (request->flags & ATA_R_WRITE) {
4169 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4170 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4171 ata_promise_queue_hpkt(ctlr,
4172 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4173 }
4174 return 0;
4175 }
4176 }
4177
4178 static int
4179 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4180 {
4181 struct ata_device *atadev = device_get_softc(request->dev);
4182 int i = 12;
4183
4184 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4185 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4186 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4187 bytep[i++] = ATA_A_4BIT;
4188
4189 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4190 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4191 bytep[i++] = request->u.ata.feature >> 8;
4192 bytep[i++] = request->u.ata.feature;
4193 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4194 bytep[i++] = request->u.ata.count >> 8;
4195 bytep[i++] = request->u.ata.count;
4196 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4197 bytep[i++] = request->u.ata.lba >> 24;
4198 bytep[i++] = request->u.ata.lba;
4199 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4200 bytep[i++] = request->u.ata.lba >> 32;
4201 bytep[i++] = request->u.ata.lba >> 8;
4202 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4203 bytep[i++] = request->u.ata.lba >> 40;
4204 bytep[i++] = request->u.ata.lba >> 16;
4205 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4206 bytep[i++] = ATA_D_LBA | atadev->unit;
4207 }
4208 else {
4209 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4210 bytep[i++] = request->u.ata.feature;
4211 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4212 bytep[i++] = request->u.ata.count;
4213 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4214 bytep[i++] = request->u.ata.lba;
4215 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4216 bytep[i++] = request->u.ata.lba >> 8;
4217 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4218 bytep[i++] = request->u.ata.lba >> 16;
4219 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4220 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4221 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4222 }
4223 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4224 bytep[i++] = request->u.ata.command;
4225 return i;
4226 }
4227
4228 static void
4229 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4230 {
4231 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4232
4233 spin_lock_wr(&hpktp->mtx);
4234 if (hpktp->busy) {
4235 struct host_packet *hp =
4236 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO);
4237 hp->addr = hpkt;
4238 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4239 }
4240 else {
4241 hpktp->busy = 1;
4242 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4243 }
4244 spin_unlock_wr(&hpktp->mtx);
4245 }
4246
4247 static void
4248 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4249 {
4250 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4251 struct host_packet *hp;
4252
4253 spin_lock_wr(&hpktp->mtx);
4254 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4255 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4256 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4257 kfree(hp, M_TEMP);
4258 }
4259 else
4260 hpktp->busy = 0;
4261 spin_unlock_wr(&hpktp->mtx);
4262 }
4263
4264
4265 /*
4266 * ServerWorks chipset support functions
4267 */
4268 int
4269 ata_serverworks_ident(device_t dev)
4270 {
4271 struct ata_pci_controller *ctlr = device_get_softc(dev);
4272 struct ata_chip_id *idx;
4273 static struct ata_chip_id ids[] =
4274 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4275 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4276 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4277 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4278 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4279 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4280 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4281 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4282 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4283 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4284 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4285 { 0, 0, 0, 0, 0, 0}};
4286 char buffer[64];
4287
4288 if (!(idx = ata_match_chip(dev, ids)))
4289 return ENXIO;
4290
4291 ksprintf(buffer, "ServerWorks %s %s controller",
4292 idx->text, ata_mode2str(idx->max_dma));
4293 device_set_desc_copy(dev, buffer);
4294 ctlr->chip = idx;
4295 ctlr->chipinit = ata_serverworks_chipinit;
4296 return 0;
4297 }
4298
4299 static int
4300 ata_serverworks_chipinit(device_t dev)
4301 {
4302 struct ata_pci_controller *ctlr = device_get_softc(dev);
4303
4304 if (ata_setup_interrupt(dev))
4305 return ENXIO;
4306
4307 if (ctlr->chip->cfg1 == SWKSMIO) {
4308 ctlr->r_type2 = SYS_RES_MEMORY;
4309 ctlr->r_rid2 = PCIR_BAR(5);
4310 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4311 &ctlr->r_rid2, RF_ACTIVE)))
4312 return ENXIO;
4313
4314 ctlr->channels = ctlr->chip->cfg2;
4315 ctlr->allocate = ata_serverworks_allocate;
4316 ctlr->setmode = ata_sata_setmode;
4317 return 0;
4318 }
4319 else if (ctlr->chip->cfg1 == SWKS33) {
4320 device_t *children;
4321 int nchildren, i;
4322
4323 /* locate the ISA part in the southbridge and enable UDMA33 */
4324 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4325 for (i = 0; i < nchildren; i++) {
4326 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4327 pci_write_config(children[i], 0x64,
4328 (pci_read_config(children[i], 0x64, 4) &
4329 ~0x00002000) | 0x00004000, 4);
4330 break;
4331 }
4332 }
4333 kfree(children, M_TEMP);
4334 }
4335 }
4336 else {
4337 pci_write_config(dev, 0x5a,
4338 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4339 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4340 }
4341 ctlr->setmode = ata_serverworks_setmode;
4342 return 0;
4343 }
4344
4345 static int
4346 ata_serverworks_allocate(device_t dev)
4347 {
4348 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4349 struct ata_channel *ch = device_get_softc(dev);
4350 int ch_offset;
4351 int i;
4352
4353 ch_offset = ch->unit * 0x100;
4354
4355 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4356 ch->r_io[i].res = ctlr->r_res2;
4357
4358 /* setup ATA registers */
4359 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4360 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4361 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4362 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4363 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4364 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4365 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4366 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4367 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4368 ata_default_registers(dev);
4369
4370 /* setup DMA registers */
4371 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4372 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4373 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4374
4375 /* setup SATA registers */
4376 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4377 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4378 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4379
4380 ch->flags |= ATA_NO_SLAVE;
4381 ata_pci_hw(dev);
4382 return 0;
4383 }
4384
4385 static void
4386 ata_serverworks_setmode(device_t dev, int mode)
4387 {
4388 device_t gparent = GRANDPARENT(dev);
4389 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4390 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4391 struct ata_device *atadev = device_get_softc(dev);
4392 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4393 int offset = (devno ^ 0x01) << 3;
4394 int error;
4395 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4396 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4397 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4398
4399 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4400
4401 mode = ata_check_80pin(dev, mode);
4402
4403 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4404
4405 if (bootverbose)
4406 device_printf(dev, "%ssetting %s on %s chip\n",
4407 (error) ? "FAILURE " : "",
4408 ata_mode2str(mode), ctlr->chip->text);
4409 if (!error) {
4410 if (mode >= ATA_UDMA0) {
4411 pci_write_config(gparent, 0x56,
4412 (pci_read_config(gparent, 0x56, 2) &
4413 ~(0xf << (devno << 2))) |
4414 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4415 pci_write_config(gparent, 0x54,
4416 pci_read_config(gparent, 0x54, 1) |
4417 (0x01 << devno), 1);
4418 pci_write_config(gparent, 0x44,
4419 (pci_read_config(gparent, 0x44, 4) &
4420 ~(0xff << offset)) |
4421 (dmatimings[2] << offset), 4);
4422 }
4423 else if (mode >= ATA_WDMA0) {
4424 pci_write_config(gparent, 0x54,
4425 pci_read_config(gparent, 0x54, 1) &
4426 ~(0x01 << devno), 1);
4427 pci_write_config(gparent, 0x44,
4428 (pci_read_config(gparent, 0x44, 4) &
4429 ~(0xff << offset)) |
4430 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4431 }
4432 else
4433 pci_write_config(gparent, 0x54,
4434 pci_read_config(gparent, 0x54, 1) &
4435 ~(0x01 << devno), 1);
4436
4437 pci_write_config(gparent, 0x40,
4438 (pci_read_config(gparent, 0x40, 4) &
4439 ~(0xff << offset)) |
4440 (piotimings[ata_mode2idx(mode)] << offset), 4);
4441 atadev->mode = mode;
4442 }
4443 }
4444
4445
4446 /*
4447 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4448 */
4449 int
4450 ata_sii_ident(device_t dev)
4451 {
4452 struct ata_pci_controller *ctlr = device_get_softc(dev);
4453 struct ata_chip_id *idx;
4454 static struct ata_chip_id ids[] =
4455 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4456 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4457 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4458 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4459 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4460 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4461 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4462 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4463 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4464 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4465 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4466 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4467 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4468 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4469 { 0, 0, 0, 0, 0, 0}};
4470 char buffer[64];
4471
4472 if (!(idx = ata_match_chip(dev, ids)))
4473 return ENXIO;
4474
4475 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4476 device_set_desc_copy(dev, buffer);
4477 ctlr->chip = idx;
4478 ctlr->chipinit = ata_sii_chipinit;
4479 return 0;
4480 }
4481
4482 static int
4483 ata_sii_chipinit(device_t dev)
4484 {
4485 struct ata_pci_controller *ctlr = device_get_softc(dev);
4486
4487 if (ata_setup_interrupt(dev))
4488 return ENXIO;
4489
4490 switch (ctlr->chip->cfg1) {
4491 case SIIPRBIO:
4492 ctlr->r_type1 = SYS_RES_MEMORY;
4493 ctlr->r_rid1 = PCIR_BAR(0);
4494 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4495 &ctlr->r_rid1, RF_ACTIVE)))
4496 return ENXIO;
4497
4498 ctlr->r_rid2 = PCIR_BAR(2);
4499 ctlr->r_type2 = SYS_RES_MEMORY;
4500 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4501 &ctlr->r_rid2, RF_ACTIVE))){
4502 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4503 return ENXIO;
4504 }
4505 ctlr->allocate = ata_siiprb_allocate;
4506 ctlr->reset = ata_siiprb_reset;
4507 ctlr->dmainit = ata_siiprb_dmainit;
4508 ctlr->setmode = ata_sata_setmode;
4509 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4510
4511 /* reset controller */
4512 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4513 DELAY(10000);
4514 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4515
4516 /* enable PCI interrupt */
4517 pci_write_config(dev, PCIR_COMMAND,
4518 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4519 break;
4520
4521 case SIIMEMIO:
4522 ctlr->r_type2 = SYS_RES_MEMORY;
4523 ctlr->r_rid2 = PCIR_BAR(5);
4524 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4525 &ctlr->r_rid2, RF_ACTIVE)))
4526 return ENXIO;
4527
4528 if (ctlr->chip->cfg2 & SIISETCLK) {
4529 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4530 pci_write_config(dev, 0x8a,
4531 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4532 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4533 device_printf(dev, "%s could not set ATA133 clock\n",
4534 ctlr->chip->text);
4535 }
4536
4537 /* if we have 4 channels enable the second set */
4538 if (ctlr->chip->cfg2 & SII4CH) {
4539 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4540 ctlr->channels = 4;
4541 }
4542
4543 /* dont block interrupts from any channel */
4544 pci_write_config(dev, 0x48,
4545 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4546
4547 /* enable PCI interrupt as BIOS might not */
4548 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4549
4550 ctlr->allocate = ata_sii_allocate;
4551 if (ctlr->chip->max_dma >= ATA_SA150) {
4552 ctlr->reset = ata_sii_reset;
4553 ctlr->setmode = ata_sata_setmode;
4554 }
4555 else
4556 ctlr->setmode = ata_sii_setmode;
4557 break;
4558
4559 default:
4560 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4561 device_printf(dev, "HW has secondary channel disabled\n");
4562 ctlr->channels = 1;
4563 }
4564
4565 /* enable interrupt as BIOS might not */
4566 pci_write_config(dev, 0x71, 0x01, 1);
4567
4568 ctlr->allocate = ata_cmd_allocate;
4569 ctlr->setmode = ata_cmd_setmode;
4570 break;
4571 }
4572 return 0;
4573 }
4574
4575 static int
4576 ata_cmd_allocate(device_t dev)
4577 {
4578 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4579 struct ata_channel *ch = device_get_softc(dev);
4580
4581 /* setup the usual register normal pci style */
4582 if (ata_pci_allocate(dev))
4583 return ENXIO;
4584
4585 if (ctlr->chip->cfg2 & SIIINTR)
4586 ch->hw.status = ata_cmd_status;
4587
4588 return 0;
4589 }
4590
4591 static int
4592 ata_cmd_status(device_t dev)
4593 {
4594 struct ata_channel *ch = device_get_softc(dev);
4595 u_int8_t reg71;
4596
4597 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4598 (ch->unit ? 0x08 : 0x04))) {
4599 pci_write_config(device_get_parent(ch->dev), 0x71,
4600 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4601 return ata_pci_status(dev);
4602 }
4603 return 0;
4604 }
4605
4606 static void
4607 ata_cmd_setmode(device_t dev, int mode)
4608 {
4609 device_t gparent = GRANDPARENT(dev);
4610 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4611 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4612 struct ata_device *atadev = device_get_softc(dev);
4613 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4614 int error;
4615
4616 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4617
4618 mode = ata_check_80pin(dev, mode);
4619
4620 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4621
4622 if (bootverbose)
4623 device_printf(dev, "%ssetting %s on %s chip\n",
4624 (error) ? "FAILURE " : "",
4625 ata_mode2str(mode), ctlr->chip->text);
4626 if (!error) {
4627 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4628 int ureg = ch->unit ? 0x7b : 0x73;
4629
4630 if (mode >= ATA_UDMA0) {
4631 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4632 { 0x11, 0x42 }, { 0x25, 0x8a },
4633 { 0x15, 0x4a }, { 0x05, 0x0a } };
4634
4635 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4636
4637 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4638 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4639 pci_write_config(gparent, ureg, umode, 1);
4640 }
4641 else if (mode >= ATA_WDMA0) {
4642 int dmatimings[] = { 0x87, 0x32, 0x3f };
4643
4644 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4645 pci_write_config(gparent, ureg,
4646 pci_read_config(gparent, ureg, 1) &
4647 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4648 }
4649 else {
4650 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4651 pci_write_config(gparent, treg,
4652 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4653 pci_write_config(gparent, ureg,
4654 pci_read_config(gparent, ureg, 1) &
4655 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4656 }
4657 atadev->mode = mode;
4658 }
4659 }
4660
4661 static int
4662 ata_sii_allocate(device_t dev)
4663 {
4664 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4665 struct ata_channel *ch = device_get_softc(dev);
4666 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4667 int i;
4668
4669 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4670 ch->r_io[i].res = ctlr->r_res2;
4671 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4672 }
4673 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4674 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4675 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4676 ata_default_registers(dev);
4677
4678 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4679 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4680 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4681 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4682 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4683 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4684
4685 if (ctlr->chip->max_dma >= ATA_SA150) {
4686 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4687 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4688 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4689 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4690 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4691 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4692 ch->flags |= ATA_NO_SLAVE;
4693
4694 /* enable PHY state change interrupt */
4695 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4696 }
4697
4698 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4699 /* work around errata in early chips */
4700 ch->dma->boundary = 16 * DEV_BSIZE;
4701 ch->dma->segsize = 15 * DEV_BSIZE;
4702 }
4703
4704 ata_pci_hw(dev);
4705 ch->hw.status = ata_sii_status;
4706 return 0;
4707 }
4708
4709 static int
4710 ata_sii_status(device_t dev)
4711 {
4712 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4713 struct ata_channel *ch = device_get_softc(dev);
4714 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4715 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4716
4717 /* do we have any PHY events ? */
4718 if (ctlr->chip->max_dma >= ATA_SA150 &&
4719 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4720 ata_sata_phy_check_events(dev);
4721
4722 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4723 return ata_pci_status(dev);
4724 else
4725 return 0;
4726 }
4727
4728 static void
4729 ata_sii_reset(device_t dev)
4730 {
4731 if (ata_sata_phy_reset(dev))
4732 ata_generic_reset(dev);
4733 }
4734
4735 static void
4736 ata_sii_setmode(device_t dev, int mode)
4737 {
4738 device_t gparent = GRANDPARENT(dev);
4739 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4740 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4741 struct ata_device *atadev = device_get_softc(dev);
4742 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4743 int mreg = ch->unit ? 0x84 : 0x80;
4744 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4745 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4746 int error;
4747
4748 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4749
4750 if (ctlr->chip->cfg2 & SIISETCLK) {
4751 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4752 (ch->unit ? 0x02 : 0x01))) {
4753 ata_print_cable(dev, "controller");
4754 mode = ATA_UDMA2;
4755 }
4756 }
4757 else
4758 mode = ata_check_80pin(dev, mode);
4759
4760 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4761
4762 if (bootverbose)
4763 device_printf(dev, "%ssetting %s on %s chip\n",
4764 (error) ? "FAILURE " : "",
4765 ata_mode2str(mode), ctlr->chip->text);
4766 if (error)
4767 return;
4768
4769 if (mode >= ATA_UDMA0) {
4770 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4771 u_int8_t ureg = 0xac + rego;
4772
4773 pci_write_config(gparent, mreg,
4774 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4775 pci_write_config(gparent, ureg,
4776 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4777 udmatimings[mode & ATA_MODE_MASK], 1);
4778
4779 }
4780 else if (mode >= ATA_WDMA0) {
4781 u_int8_t dreg = 0xa8 + rego;
4782 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4783
4784 pci_write_config(gparent, mreg,
4785 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4786 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4787
4788 }
4789 else {
4790 u_int8_t preg = 0xa4 + rego;
4791 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4792
4793 pci_write_config(gparent, mreg,
4794 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4795 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4796 }
4797 atadev->mode = mode;
4798 }
4799
4800 struct ata_siiprb_dma_prdentry {
4801 u_int64_t addr;
4802 u_int32_t count;
4803 u_int32_t control;
4804 } __packed;
4805
4806 struct ata_siiprb_ata_command {
4807 u_int32_t reserved0;
4808 struct ata_siiprb_dma_prdentry prd[126];
4809 } __packed;
4810
4811 struct ata_siiprb_atapi_command {
4812 u_int8_t cdb[16];
4813 struct ata_siiprb_dma_prdentry prd[125];
4814 } __packed;
4815
4816 struct ata_siiprb_command {
4817 u_int16_t control;
4818 u_int16_t protocol_override;
4819 u_int32_t transfer_count;
4820 u_int8_t fis[20];
4821 union {
4822 struct ata_siiprb_ata_command ata;
4823 struct ata_siiprb_atapi_command atapi;
4824 } u;
4825 } __packed;
4826
4827 static int
4828 ata_siiprb_allocate(device_t dev)
4829 {
4830 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4831 struct ata_channel *ch = device_get_softc(dev);
4832 int offset = ch->unit * 0x2000;
4833
4834 /* set the SATA resources */
4835 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4836 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4837 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4838 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4839 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4840 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4841 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4842 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4843
4844 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4845 ch->hw.end_transaction = ata_siiprb_end_transaction;
4846 ch->hw.status = ata_siiprb_status;
4847 ch->hw.command = NULL; /* not used here */
4848 return 0;
4849 }
4850
4851 static int
4852 ata_siiprb_status(device_t dev)
4853 {
4854 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4855 struct ata_channel *ch = device_get_softc(dev);
4856 int offset = ch->unit * 0x2000;
4857
4858 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) {
4859 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4860
4861 /* do we have any PHY events ? */
4862 ata_sata_phy_check_events(dev);
4863
4864 /* clear interrupt(s) */
4865 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4866
4867 /* do we have any device action ? */
4868 return (istatus & 0x00000001);
4869 }
4870 return 0;
4871 }
4872
4873 static int
4874 ata_siiprb_begin_transaction(struct ata_request *request)
4875 {
4876 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4877 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4878 struct ata_siiprb_command *prb;
4879 int offset = ch->unit * 0x2000;
4880 u_int64_t prb_bus;
4881 int tag = 0, dummy;
4882
4883 /* check for 48 bit access and convert if needed */
4884 ata_modify_if_48bit(request);
4885
4886 /* get a piece of the workspace for this request */
4887 prb = (struct ata_siiprb_command *)
4888 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4889
4890 /* set basic prd options ata/atapi etc etc */
4891 bzero(prb, sizeof(struct ata_siiprb_command));
4892
4893 /* setup the FIS for this request */
4894 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4895 device_printf(request->dev, "setting up SATA FIS failed\n");
4896 request->result = EIO;
4897 return ATA_OP_FINISHED;
4898 }
4899
4900 /* if request moves data setup and load SG list */
4901 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4902 struct ata_siiprb_dma_prdentry *prd;
4903
4904 if (request->flags & ATA_R_ATAPI)
4905 prd = &prb->u.atapi.prd[0];
4906 else
4907 prd = &prb->u.ata.prd[0];
4908 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4909 request->flags & ATA_R_READ, prd, &dummy)) {
4910 device_printf(request->dev, "setting up DMA failed\n");
4911 request->result = EIO;
4912 return ATA_OP_FINISHED;
4913 }
4914 }
4915
4916 /* activate the prb */
4917 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4918 ATA_OUTL(ctlr->r_res2,
4919 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4920 ATA_OUTL(ctlr->r_res2,
4921 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4922
4923 /* start the timeout */
4924 callout_reset(&request->callout, request->timeout * hz,
4925 (timeout_t*)ata_timeout, request);
4926 return ATA_OP_CONTINUES;
4927 }
4928
4929 static int
4930 ata_siiprb_end_transaction(struct ata_request *request)
4931 {
4932 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4933 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4934 struct ata_siiprb_command *prb;
4935 int offset = ch->unit * 0x2000;
4936 int error, tag = 0;
4937
4938 /* kill the timeout */
4939 callout_stop(&request->callout);
4940
4941 prb = (struct ata_siiprb_command *)
4942 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4943
4944 /* if error status get details */
4945 request->status = prb->fis[2];
4946 if (request->status & ATA_S_ERROR)
4947 request->error = prb->fis[3];
4948
4949 /* update progress */
4950 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4951 if (request->flags & ATA_R_READ)
4952 request->donecount = prb->transfer_count;
4953 else
4954 request->donecount = request->bytecount;
4955 }
4956
4957 /* any controller errors flagged ? */
4958 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4959 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
4960 ata_cmd2str(request), error);
4961 }
4962
4963 /* release SG list etc */
4964 ch->dma->unload(ch->dev);
4965
4966 return ATA_OP_FINISHED;
4967 }
4968
4969 static void
4970 ata_siiprb_reset(device_t dev)
4971 {
4972 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4973 struct ata_channel *ch = device_get_softc(dev);
4974 int offset = ch->unit * 0x2000;
4975 struct ata_siiprb_command *prb;
4976 u_int64_t prb_bus;
4977 u_int32_t status, signature;
4978 int timeout, tag = 0;
4979
4980 /* reset channel HW */
4981 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
4982 DELAY(1000);
4983 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
4984 DELAY(10000);
4985
4986 /* poll for channel ready */
4987 for (timeout = 0; timeout < 1000; timeout++) {
4988 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000)
4989 break;
4990 DELAY(1000);
4991 }
4992 if (timeout >= 1000) {
4993 device_printf(ch->dev, "channel HW reset timeout reset failure\n");
4994 ch->devices = 0;
4995 goto finish;
4996 }
4997 if (bootverbose)
4998 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1);
4999
5000 /* reset phy */
5001 if (!ata_sata_phy_reset(dev)) {
5002 if (bootverbose)
5003 device_printf(ch->dev, "phy reset found no device\n");
5004 ch->devices = 0;
5005 goto finish;
5006 }
5007
5008 /* get a piece of the workspace for a soft reset request */
5009 prb = (struct ata_siiprb_command *)
5010 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5011 bzero(prb, sizeof(struct ata_siiprb_command));
5012 prb->control = htole16(0x0080);
5013
5014 /* activate the soft reset prb */
5015 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5016 ATA_OUTL(ctlr->r_res2,
5017 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5018 ATA_OUTL(ctlr->r_res2,
5019 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5020
5021 /* poll for channel ready */
5022 for (timeout = 0; timeout < 1000; timeout++) {
5023 DELAY(1000);
5024 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5025 break;
5026 }
5027 if (timeout >= 1000) {
5028 device_printf(ch->dev, "reset timeout - no device found\n");
5029 ch->devices = 0;
5030 goto finish;
5031 }
5032 if (bootverbose)
5033 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5034 timeout, status);
5035
5036 /* find out whats there */
5037 prb = (struct ata_siiprb_command *)
5038 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5039 signature =
5040 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5041 if (bootverbose)
5042 device_printf(ch->dev, "signature=%08x\n", signature);
5043 switch (signature) {
5044 case 0xeb140101:
5045 ch->devices = ATA_ATAPI_MASTER;
5046 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
5047 ch->devices = 0;
5048 break;
5049 case 0x96690101:
5050 ch->devices = ATA_PORTMULTIPLIER;
5051 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5052 ch->devices = 0;
5053 break;
5054 case 0x00000101:
5055 ch->devices = ATA_ATA_MASTER;
5056 break;
5057 default:
5058 ch->devices = 0;
5059 }
5060
5061 finish:
5062 /* clear interrupt(s) */
5063 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5064
5065 /* require explicit interrupt ack */
5066 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5067
5068 /* 64bit mode */
5069 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5070
5071 /* enable interrupts wanted */
5072 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5073 }
5074
5075 static void
5076 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5077 {
5078 struct ata_dmasetprd_args *args = xsc;
5079 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5080 int i;
5081
5082 if ((args->error = error))
5083 return;
5084
5085 for (i = 0; i < nsegs; i++) {
5086 prd[i].addr = htole64(segs[i].ds_addr);
5087 prd[i].count = htole32(segs[i].ds_len);
5088 }
5089 prd[i - 1].control = htole32(ATA_DMA_EOT);
5090 }
5091
5092 static void
5093 ata_siiprb_dmainit(device_t dev)
5094 {
5095 struct ata_channel *ch = device_get_softc(dev);
5096
5097 ata_dmainit(dev);
5098 if (ch->dma) {
5099 /* note start and stop are not used here */
5100 ch->dma->setprd = ata_siiprb_dmasetprd;
5101 ch->dma->max_address = BUS_SPACE_MAXADDR;
5102 }
5103 }
5104
5105
5106 /*
5107 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5108 */
5109 int
5110 ata_sis_ident(device_t dev)
5111 {
5112 struct ata_pci_controller *ctlr = device_get_softc(dev);
5113 struct ata_chip_id *idx;
5114 static struct ata_chip_id ids[] =
5115 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5116 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5117 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5118 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5119 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5120 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5121 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5122
5123 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5124 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5125 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5126 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5127
5128 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5129 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5130 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5131 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5132 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5133
5134 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5135 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5136 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5137
5138 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5139 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5140 { 0, 0, 0, 0, 0, 0 }};
5141 char buffer[64];
5142 int found = 0;
5143
5144 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5145 return ENXIO;
5146
5147 if (idx->cfg2 && !found) {
5148 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5149
5150 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5151 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5152 found = 1;
5153 idx->cfg1 = SIS133NEW;
5154 idx->max_dma = ATA_UDMA6;
5155 ksprintf(buffer, "SiS 962/963 %s controller",
5156 ata_mode2str(idx->max_dma));
5157 }
5158 pci_write_config(dev, 0x57, reg57, 1);
5159 }
5160 if (idx->cfg2 && !found) {
5161 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5162
5163 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5164 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5165 struct ata_chip_id id[] =
5166 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5167
5168 found = 1;
5169 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5170 idx->cfg1 = SIS133OLD;
5171 idx->max_dma = ATA_UDMA6;
5172 }
5173 else {
5174 idx->cfg1 = SIS100NEW;
5175 idx->max_dma = ATA_UDMA5;
5176 }
5177 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5178 }
5179 pci_write_config(dev, 0x4a, reg4a, 1);
5180 }
5181 if (!found)
5182 ksprintf(buffer,"SiS %s %s controller",
5183 idx->text, ata_mode2str(idx->max_dma));
5184
5185 device_set_desc_copy(dev, buffer);
5186 ctlr->chip = idx;
5187 ctlr->chipinit = ata_sis_chipinit;
5188 return 0;
5189 }
5190
5191 static int
5192 ata_sis_chipinit(device_t dev)
5193 {
5194 struct ata_pci_controller *ctlr = device_get_softc(dev);
5195
5196 if (ata_setup_interrupt(dev))
5197 return ENXIO;
5198
5199 switch (ctlr->chip->cfg1) {
5200 case SIS33:
5201 break;
5202 case SIS66:
5203 case SIS100OLD:
5204 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5205 break;
5206 case SIS100NEW:
5207 case SIS133OLD:
5208 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5209 break;
5210 case SIS133NEW:
5211 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5212 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5213 break;
5214 case SISSATA:
5215 ctlr->r_type2 = SYS_RES_IOPORT;
5216 ctlr->r_rid2 = PCIR_BAR(5);
5217 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5218 &ctlr->r_rid2, RF_ACTIVE))) {
5219 ctlr->allocate = ata_sis_allocate;
5220 ctlr->reset = ata_sis_reset;
5221
5222 /* enable PCI interrupt */
5223 pci_write_config(dev, PCIR_COMMAND,
5224 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5225 }
5226 ctlr->setmode = ata_sata_setmode;
5227 return 0;
5228 default:
5229 return ENXIO;
5230 }
5231 ctlr->setmode = ata_sis_setmode;
5232 return 0;
5233 }
5234
5235 static int
5236 ata_sis_allocate(device_t dev)
5237 {
5238 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5239 struct ata_channel *ch = device_get_softc(dev);
5240 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5241
5242 /* setup the usual register normal pci style */
5243 if (ata_pci_allocate(dev))
5244 return ENXIO;
5245
5246 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5247 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5248 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5249 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5250 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5251 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5252 ch->flags |= ATA_NO_SLAVE;
5253
5254 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5255 /* XXX SOS unknown how to enable PHY state change interrupt */
5256 return 0;
5257 }
5258
5259 static void
5260 ata_sis_reset(device_t dev)
5261 {
5262 if (ata_sata_phy_reset(dev))
5263 ata_generic_reset(dev);
5264 }
5265
5266 static void
5267 ata_sis_setmode(device_t dev, int mode)
5268 {
5269 device_t gparent = GRANDPARENT(dev);
5270 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5271 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5272 struct ata_device *atadev = device_get_softc(dev);
5273 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5274 int error;
5275
5276 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5277
5278 if (ctlr->chip->cfg1 == SIS133NEW) {
5279 if (mode > ATA_UDMA2 &&
5280 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5281 ata_print_cable(dev, "controller");
5282 mode = ATA_UDMA2;
5283 }
5284 }
5285 else {
5286 if (mode > ATA_UDMA2 &&
5287 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5288 ata_print_cable(dev, "controller");
5289 mode = ATA_UDMA2;
5290 }
5291 }
5292
5293 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5294
5295 if (bootverbose)
5296 device_printf(dev, "%ssetting %s on %s chip\n",
5297 (error) ? "FAILURE " : "",
5298 ata_mode2str(mode), ctlr->chip->text);
5299 if (!error) {
5300 switch (ctlr->chip->cfg1) {
5301 case SIS133NEW: {
5302 u_int32_t timings[] =
5303 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5304 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5305 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5306 u_int32_t reg;
5307
5308 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5309 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
5310 break;
5311 }
5312 case SIS133OLD: {
5313 u_int16_t timings[] =
5314 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
5315 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
5316
5317 u_int16_t reg = 0x40 + (devno << 1);
5318
5319 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5320 break;
5321 }
5322 case SIS100NEW: {
5323 u_int16_t timings[] =
5324 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
5325 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
5326 u_int16_t reg = 0x40 + (devno << 1);
5327
5328 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5329 break;
5330 }
5331 case SIS100OLD:
5332 case SIS66:
5333 case SIS33: {
5334 u_int16_t timings[] =
5335 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
5336 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
5337 u_int16_t reg = 0x40 + (devno << 1);
5338
5339 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5340 break;
5341 }
5342 }
5343 atadev->mode = mode;
5344 }
5345 }
5346
5347
5348 /* VIA Technologies Inc. chipset support functions */
5349 int
5350 ata_via_ident(device_t dev)
5351 {
5352 struct ata_pci_controller *ctlr = device_get_softc(dev);
5353 struct ata_chip_id *idx;
5354 static struct ata_chip_id ids[] =
5355 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
5356 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
5357 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
5358 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
5359 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
5360 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
5361 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
5362 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
5363 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
5364 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
5365 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
5366 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
5367 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
5368 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
5369 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
5370 { 0, 0, 0, 0, 0, 0 }};
5371 static struct ata_chip_id new_ids[] =
5372 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
5373 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
5374 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
5375 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
5376 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
5377 { 0, 0, 0, 0, 0, 0 }};
5378 char buffer[64];
5379
5380 if (pci_get_devid(dev) == ATA_VIA82C571) {
5381 if (!(idx = ata_find_chip(dev, ids, -99)))
5382 return ENXIO;
5383 }
5384 else {
5385 if (!(idx = ata_match_chip(dev, new_ids)))
5386 return ENXIO;
5387 }
5388
5389 ksprintf(buffer, "VIA %s %s controller",
5390 idx->text, ata_mode2str(idx->max_dma));
5391 device_set_desc_copy(dev, buffer);
5392 ctlr->chip = idx;
5393 ctlr->chipinit = ata_via_chipinit;
5394 return 0;
5395 }
5396
5397 static int
5398 ata_via_chipinit(device_t dev)
5399 {
5400 struct ata_pci_controller *ctlr = device_get_softc(dev);
5401
5402 if (ata_setup_interrupt(dev))
5403 return ENXIO;
5404
5405 if (ctlr->chip->max_dma >= ATA_SA150) {
5406 if (ctlr->chip->cfg2 == VIAAHCI) {
5407 ctlr->r_type2 = SYS_RES_MEMORY;
5408 ctlr->r_rid2 = PCIR_BAR(5);
5409 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5410 &ctlr->r_rid2,
5411 RF_ACTIVE))) {
5412 return ata_ahci_chipinit(dev);
5413 }
5414 }
5415 ctlr->r_type2 = SYS_RES_IOPORT;
5416 ctlr->r_rid2 = PCIR_BAR(5);
5417 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5418 &ctlr->r_rid2, RF_ACTIVE))) {
5419 ctlr->allocate = ata_via_allocate;
5420 ctlr->reset = ata_via_reset;
5421
5422 /* enable PCI interrupt */
5423 pci_write_config(dev, PCIR_COMMAND,
5424 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5425 }
5426
5427 if (ctlr->chip->cfg2 & VIABAR) {
5428 ctlr->channels = 3;
5429 ctlr->setmode = ata_via_setmode;
5430 }
5431 else
5432 ctlr->setmode = ata_sata_setmode;
5433 return 0;
5434 }
5435
5436 /* prepare for ATA-66 on the 82C686a and 82C596b */
5437 if (ctlr->chip->cfg2 & VIACLK)
5438 pci_write_config(dev, 0x50, 0x030b030b, 4);
5439
5440 /* the southbridge might need the data corruption fix */
5441 if (ctlr->chip->cfg2 & VIABUG)
5442 ata_via_southbridge_fixup(dev);
5443
5444 /* set fifo configuration half'n'half */
5445 pci_write_config(dev, 0x43,
5446 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
5447
5448 /* set status register read retry */
5449 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
5450
5451 /* set DMA read & end-of-sector fifo flush */
5452 pci_write_config(dev, 0x46,
5453 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
5454
5455 /* set sector size */
5456 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
5457 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
5458
5459 ctlr->setmode = ata_via_family_setmode;
5460 return 0;
5461 }
5462
5463 static int
5464 ata_via_allocate(device_t dev)
5465 {
5466 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5467 struct ata_channel *ch = device_get_softc(dev);
5468
5469 /* newer SATA chips has resources in one BAR for each channel */
5470 if (ctlr->chip->cfg2 & VIABAR) {
5471 struct resource *r_io;
5472 int i, rid;
5473
5474 rid = PCIR_BAR(ch->unit);
5475 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
5476 SYS_RES_IOPORT,
5477 &rid, RF_ACTIVE)))
5478 return ENXIO;
5479
5480 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
5481 ch->r_io[i].res = r_io;
5482 ch->r_io[i].offset = i;
5483 }
5484 ch->r_io[ATA_CONTROL].res = r_io;
5485 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
5486 ch->r_io[ATA_IDX_ADDR].res = r_io;
5487 ata_default_registers(dev);
5488 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
5489 ch->r_io[i].res = ctlr->r_res1;
5490 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
5491 }
5492 ata_pci_hw(dev);
5493 if (ch->unit > 1)
5494 return 0;
5495 }
5496 else {
5497 /* setup the usual register normal pci style */
5498 if (ata_pci_allocate(dev))
5499 return ENXIO;
5500 }
5501
5502 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5503 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
5504 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5505 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
5506 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5507 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
5508 ch->flags |= ATA_NO_SLAVE;
5509
5510 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
5511 /* XXX SOS unknown how to enable PHY state change interrupt */
5512 return 0;
5513 }
5514
5515 static void
5516 ata_via_reset(device_t dev)
5517 {
5518 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5519 struct ata_channel *ch = device_get_softc(dev);
5520
5521 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
5522 ata_generic_reset(dev);
5523 else
5524 if (ata_sata_phy_reset(dev))
5525 ata_generic_reset(dev);
5526 }
5527
5528 static void
5529 ata_via_setmode(device_t dev, int mode)
5530 {
5531 device_t gparent = GRANDPARENT(dev);
5532 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5533 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5534 struct ata_device *atadev = device_get_softc(dev);
5535 int error;
5536
5537 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
5538 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
5539 0x65, 0x32, 0x20,
5540 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5541 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
5542
5543 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
5544 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5545 if (bootverbose)
5546 device_printf(dev, "%ssetting %s on %s chip\n",
5547 (error) ? "FAILURE " : "", ata_mode2str(mode),
5548 ctlr->chip->text);
5549 if (!error) {
5550 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
5551 if (mode >= ATA_UDMA0)
5552 pci_write_config(gparent, 0xb3,
5553 dma_timings[mode & ATA_MODE_MASK], 1);
5554 atadev->mode = mode;
5555 }
5556 }
5557 else
5558 ata_sata_setmode(dev, mode);
5559 }
5560
5561 static void
5562 ata_via_southbridge_fixup(device_t dev)
5563 {
5564 device_t *children;
5565 int nchildren, i;
5566
5567 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5568 return;
5569
5570 for (i = 0; i < nchildren; i++) {
5571 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
5572 pci_get_devid(children[i]) == ATA_VIA8371 ||
5573 pci_get_devid(children[i]) == ATA_VIA8662 ||
5574 pci_get_devid(children[i]) == ATA_VIA8361) {
5575 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
5576
5577 if ((reg76 & 0xf0) != 0xd0) {
5578 device_printf(dev,
5579 "Correcting VIA config for southbridge data corruption bug\n");
5580 pci_write_config(children[i], 0x75, 0x80, 1);
5581 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
5582 }
5583 break;
5584 }
5585 }
5586 kfree(children, M_TEMP);
5587 }
5588
5589
5590 /* common code for VIA, AMD & nVidia */
5591 static void
5592 ata_via_family_setmode(device_t dev, int mode)
5593 {
5594 device_t gparent = GRANDPARENT(dev);
5595 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5596 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5597 struct ata_device *atadev = device_get_softc(dev);
5598 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
5599 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5600 int modes[][7] = {
5601 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
5602 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
5603 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
5604 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
5605 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
5606 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5607 int reg = 0x53 - devno;
5608 int error;
5609
5610 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5611
5612 if (ctlr->chip->cfg2 & AMDCABLE) {
5613 if (mode > ATA_UDMA2 &&
5614 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
5615 ata_print_cable(dev, "controller");
5616 mode = ATA_UDMA2;
5617 }
5618 }
5619 else
5620 mode = ata_check_80pin(dev, mode);
5621
5622 if (ctlr->chip->cfg2 & NVIDIA)
5623 reg += 0x10;
5624
5625 if (ctlr->chip->cfg1 != VIA133)
5626 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
5627
5628 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5629
5630 if (bootverbose)
5631 device_printf(dev, "%ssetting %s on %s chip\n",
5632 (error) ? "FAILURE " : "", ata_mode2str(mode),
5633 ctlr->chip->text);
5634 if (!error) {
5635 if (mode >= ATA_UDMA0)
5636 pci_write_config(gparent, reg,
5637 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
5638 else
5639 pci_write_config(gparent, reg, 0x8b, 1);
5640 atadev->mode = mode;
5641 }
5642 }
5643
5644
5645 /* misc functions */
5646 static struct ata_chip_id *
5647 ata_match_chip(device_t dev, struct ata_chip_id *index)
5648 {
5649 while (index->chipid != 0) {
5650 if (pci_get_devid(dev) == index->chipid &&
5651 pci_get_revid(dev) >= index->chiprev)
5652 return index;
5653 index++;
5654 }
5655 return NULL;
5656 }
5657
5658 static struct ata_chip_id *
5659 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5660 {
5661 device_t *children;
5662 int nchildren, i;
5663
5664 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5665 return 0;
5666
5667 while (index->chipid != 0) {
5668 for (i = 0; i < nchildren; i++) {
5669 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5670 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5671 pci_get_devid(children[i]) == index->chipid &&
5672 pci_get_revid(children[i]) >= index->chiprev) {
5673 kfree(children, M_TEMP);
5674 return index;
5675 }
5676 }
5677 index++;
5678 }
5679 kfree(children, M_TEMP);
5680 return NULL;
5681 }
5682
5683 static int
5684 ata_setup_interrupt(device_t dev)
5685 {
5686 struct ata_pci_controller *ctlr = device_get_softc(dev);
5687 int rid = ATA_IRQ_RID;
5688
5689 if (!ata_legacy(dev)) {
5690 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5691 RF_SHAREABLE | RF_ACTIVE))) {
5692 device_printf(dev, "unable to map interrupt\n");
5693 return ENXIO;
5694 }
5695 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5696 ata_generic_intr, ctlr, &ctlr->handle, NULL))) {
5697 device_printf(dev, "unable to setup interrupt\n");
5698 return ENXIO;
5699 }
5700 }
5701 return 0;
5702 }
5703
5704 struct ata_serialize {
5705 struct spinlock locked_mtx;
5706 int locked_ch;
5707 int restart_ch;
5708 };
5709
5710 static int
5711 ata_serialize(device_t dev, int flags)
5712 {
5713 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5714 struct ata_channel *ch = device_get_softc(dev);
5715 struct ata_serialize *serial;
5716 static int inited = 0;
5717 int res;
5718
5719 if (!inited) {
5720 serial = kmalloc(sizeof(struct ata_serialize),
5721 M_TEMP, M_INTWAIT | M_ZERO);
5722 spin_init(&serial->locked_mtx);
5723 serial->locked_ch = -1;
5724 serial->restart_ch = -1;
5725 device_set_ivars(ctlr->dev, serial);
5726 inited = 1;
5727 }
5728 else
5729 serial = device_get_ivars(ctlr->dev);
5730
5731 spin_lock_wr(&serial->locked_mtx);
5732 switch (flags) {
5733 case ATA_LF_LOCK:
5734 if (serial->locked_ch == -1)
5735 serial->locked_ch = ch->unit;
5736 if (serial->locked_ch != ch->unit)
5737 serial->restart_ch = ch->unit;
5738 break;
5739
5740 case ATA_LF_UNLOCK:
5741 if (serial->locked_ch == ch->unit) {
5742 serial->locked_ch = -1;
5743 if (serial->restart_ch != -1) {
5744 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5745 serial->restart_ch = -1;
5746 spin_unlock_wr(&serial->locked_mtx);
5747 ata_start(ch->dev);
5748 return -1;
5749 }
5750 }
5751 }
5752 break;
5753
5754 case ATA_LF_WHICH:
5755 break;
5756 }
5757 res = serial->locked_ch;
5758 spin_unlock_wr(&serial->locked_mtx);
5759 return res;
5760 }
5761
5762 static void
5763 ata_print_cable(device_t dev, u_int8_t *who)
5764 {
5765 device_printf(dev,
5766 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5767 }
5768
5769 static int
5770 ata_atapi(device_t dev)
5771 {
5772 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5773 struct ata_device *atadev = device_get_softc(dev);
5774
5775 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5776 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5777 }
5778
5779 static int
5780 ata_check_80pin(device_t dev, int mode)
5781 {
5782 struct ata_device *atadev = device_get_softc(dev);
5783
5784 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5785 ata_print_cable(dev, "device");
5786 mode = ATA_UDMA2;
5787 }
5788 return mode;
5789 }
5790
5791 static int
5792 ata_mode2idx(int mode)
5793 {
5794 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5795 return (mode & ATA_MODE_MASK) + 8;
5796 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5797 return (mode & ATA_MODE_MASK) + 5;
5798 return (mode & ATA_MODE_MASK) - ATA_PIO0;
5799 }
DragonFly BSD