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kernel - Add NUMA awareness to vm_page_alloc() and related functions (2)
[dragonfly.git] / sys / platform / pc64 / x86_64 / machdep.c
blob854c24cdbeed7bffe1387fe12842101cf714ea4c
1 /*-
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
41 */
42
43 //#include "use_npx.h"
44 #include "use_isa.h"
45 #include "opt_cpu.h"
46 #include "opt_ddb.h"
47 #include "opt_directio.h"
48 #include "opt_inet.h"
49 #include "opt_msgbuf.h"
50 #include "opt_swap.h"
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysproto.h>
55 #include <sys/signalvar.h>
56 #include <sys/kernel.h>
57 #include <sys/linker.h>
58 #include <sys/malloc.h>
59 #include <sys/proc.h>
60 #include <sys/priv.h>
61 #include <sys/buf.h>
62 #include <sys/reboot.h>
63 #include <sys/mbuf.h>
64 #include <sys/msgbuf.h>
65 #include <sys/sysent.h>
66 #include <sys/sysctl.h>
67 #include <sys/vmmeter.h>
68 #include <sys/bus.h>
69 #include <sys/usched.h>
70 #include <sys/reg.h>
71 #include <sys/sbuf.h>
72 #include <sys/ctype.h>
73 #include <sys/serialize.h>
74 #include <sys/systimer.h>
75
76 #include <vm/vm.h>
77 #include <vm/vm_param.h>
78 #include <sys/lock.h>
79 #include <vm/vm_kern.h>
80 #include <vm/vm_object.h>
81 #include <vm/vm_page.h>
82 #include <vm/vm_map.h>
83 #include <vm/vm_pager.h>
84 #include <vm/vm_extern.h>
85
86 #include <sys/thread2.h>
87 #include <sys/mplock2.h>
88 #include <sys/mutex2.h>
89
90 #include <sys/user.h>
91 #include <sys/exec.h>
92 #include <sys/cons.h>
93
94 #include <sys/efi.h>
95
96 #include <ddb/ddb.h>
97
98 #include <machine/cpu.h>
99 #include <machine/clock.h>
100 #include <machine/specialreg.h>
101 #if 0 /* JG */
102 #include <machine/bootinfo.h>
103 #endif
104 #include <machine/md_var.h>
105 #include <machine/metadata.h>
106 #include <machine/pc/bios.h>
107 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
108 #include <machine/globaldata.h> /* CPU_prvspace */
109 #include <machine/smp.h>
110 #include <machine/cputypes.h>
111 #include <machine/intr_machdep.h>
112 #include <machine/framebuffer.h>
113
114 #ifdef OLD_BUS_ARCH
115 #include <bus/isa/isa_device.h>
116 #endif
117 #include <machine_base/isa/isa_intr.h>
118 #include <bus/isa/rtc.h>
119 #include <sys/random.h>
120 #include <sys/ptrace.h>
121 #include <machine/sigframe.h>
122
123 #include <sys/machintr.h>
124 #include <machine_base/icu/icu_abi.h>
125 #include <machine_base/icu/elcr_var.h>
126 #include <machine_base/apic/lapic.h>
127 #include <machine_base/apic/ioapic.h>
128 #include <machine_base/apic/ioapic_abi.h>
129 #include <machine/mptable.h>
130
131 #define PHYSMAP_ENTRIES 10
132
133 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
134
135 extern void printcpuinfo(void); /* XXX header file */
136 extern void identify_cpu(void);
137 #if 0 /* JG */
138 extern void finishidentcpu(void);
139 #endif
140 extern void panicifcpuunsupported(void);
141
142 static void cpu_startup(void *);
143 static void pic_finish(void *);
144 static void cpu_finish(void *);
145
146 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
147 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
148 #ifdef DIRECTIO
149 extern void ffs_rawread_setup(void);
150 #endif /* DIRECTIO */
151 static void init_locks(void);
152
153 extern void pcpu_timer_always(struct intrframe *);
154
155 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
156 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL);
157 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL);
158
159 #ifdef DDB
160 extern vm_offset_t ksym_start, ksym_end;
161 #endif
162
163 struct privatespace CPU_prvspace_bsp __aligned(4096);
164 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp };
165
166 vm_paddr_t efi_systbl_phys;
167 int _udatasel, _ucodesel, _ucode32sel;
168 u_long atdevbase;
169 int64_t tsc_offsets[MAXCPU];
170 cpumask_t smp_idleinvl_mask;
171 cpumask_t smp_idleinvl_reqs;
172
173 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
174
175 #if defined(SWTCH_OPTIM_STATS)
176 extern int swtch_optim_stats;
177 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
178 CTLFLAG_RD, &swtch_optim_stats, 0, "");
179 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
180 CTLFLAG_RD, &tlb_flush_count, 0, "");
181 #endif
182 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
183 CTLFLAG_RD, &cpu_mwait_halt_global, 0, "");
184 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
185 "monitor/mwait target state");
186
187 #define CPU_MWAIT_HAS_CX \
188 ((cpu_feature2 & CPUID2_MON) && \
189 (cpu_mwait_feature & CPUID_MWAIT_EXT))
190
191 #define CPU_MWAIT_CX_NAMELEN 16
192
193 #define CPU_MWAIT_C1 1
194 #define CPU_MWAIT_C2 2
195 #define CPU_MWAIT_C3 3
196 #define CPU_MWAIT_CX_MAX 8
197
198 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
199 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
200
201 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
202 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
203
204 struct cpu_mwait_cx {
205 int subcnt;
206 char name[4];
207 struct sysctl_ctx_list sysctl_ctx;
208 struct sysctl_oid *sysctl_tree;
209 };
210 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
211 static char cpu_mwait_cx_supported[256];
212
213 static int cpu_mwait_c1_hints_cnt;
214 static int cpu_mwait_hints_cnt;
215 static int *cpu_mwait_hints;
216
217 static int cpu_mwait_deep_hints_cnt;
218 static int *cpu_mwait_deep_hints;
219
220 #define CPU_IDLE_REPEAT_DEFAULT 750
221
222 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
223 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
224 static u_int cpu_mwait_repeat_shift = 1;
225
226 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
227 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
228
229 static int cpu_mwait_c3_preamble =
230 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
231 CPU_MWAIT_C3_PREAMBLE_BM_STS;
232
233 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
234 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
235 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD,
236 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask");
237
238 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
239 int *, boolean_t);
240 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
241 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS);
242 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
243
244 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
245 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
246 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
247 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
248 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
249 &cpu_mwait_repeat_shift, 0, "");
250
251 long physmem = 0;
252
253 u_long ebda_addr = 0;
254
255 int imcr_present = 0;
256
257 int naps = 0; /* # of Applications processors */
258
259 u_int base_memory;
260 struct mtx dt_lock; /* lock for GDT and LDT */
261
262 static int
263 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
264 {
265 u_long pmem = ctob(physmem);
266
267 int error = sysctl_handle_long(oidp, &pmem, 0, req);
268 return (error);
269 }
270
271 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
272 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
273
274 static int
275 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
276 {
277 int error = sysctl_handle_int(oidp, 0,
278 ctob(physmem - vmstats.v_wire_count), req);
279 return (error);
280 }
281
282 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
283 0, 0, sysctl_hw_usermem, "IU", "");
284
285 static int
286 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
287 {
288 int error = sysctl_handle_int(oidp, 0,
289 x86_64_btop(avail_end - avail_start), req);
290 return (error);
291 }
292
293 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
294 0, 0, sysctl_hw_availpages, "I", "");
295
296 vm_paddr_t Maxmem;
297 vm_paddr_t Realmem;
298
299 /*
300 * The number of PHYSMAP entries must be one less than the number of
301 * PHYSSEG entries because the PHYSMAP entry that spans the largest
302 * physical address that is accessible by ISA DMA is split into two
303 * PHYSSEG entries.
304 */
305 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1];
306 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1];
307
308 /* must be 1 less so 0 0 can signal end of chunks */
309 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1)
310 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1)
311
312 static vm_offset_t buffer_sva, buffer_eva;
313 vm_offset_t clean_sva, clean_eva;
314 static vm_offset_t pager_sva, pager_eva;
315 static struct trapframe proc0_tf;
316
317 static void
318 cpu_startup(void *dummy)
319 {
320 caddr_t v;
321 vm_size_t size = 0;
322 vm_offset_t firstaddr;
323
324 /*
325 * Good {morning,afternoon,evening,night}.
326 */
327 kprintf("%s", version);
328 startrtclock();
329 printcpuinfo();
330 panicifcpuunsupported();
331 kprintf("real memory = %ju (%ju MB)\n",
332 (intmax_t)Realmem,
333 (intmax_t)Realmem / 1024 / 1024);
334 /*
335 * Display any holes after the first chunk of extended memory.
336 */
337 if (bootverbose) {
338 int indx;
339
340 kprintf("Physical memory chunk(s):\n");
341 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) {
342 vm_paddr_t size1;
343
344 size1 = phys_avail[indx].phys_end -
345 phys_avail[indx].phys_beg;
346
347 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
348 (intmax_t)phys_avail[indx].phys_beg,
349 (intmax_t)phys_avail[indx].phys_end - 1,
350 (intmax_t)size1,
351 (intmax_t)(size1 / PAGE_SIZE));
352 }
353 }
354
355 /*
356 * Allocate space for system data structures.
357 * The first available kernel virtual address is in "v".
358 * As pages of kernel virtual memory are allocated, "v" is incremented.
359 * As pages of memory are allocated and cleared,
360 * "firstaddr" is incremented.
361 * An index into the kernel page table corresponding to the
362 * virtual memory address maintained in "v" is kept in "mapaddr".
363 */
364
365 /*
366 * Make two passes. The first pass calculates how much memory is
367 * needed and allocates it. The second pass assigns virtual
368 * addresses to the various data structures.
369 */
370 firstaddr = 0;
371 again:
372 v = (caddr_t)firstaddr;
373
374 #define valloc(name, type, num) \
375 (name) = (type *)v; v = (caddr_t)((name)+(num))
376 #define valloclim(name, type, num, lim) \
377 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
378
379 /*
380 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE.
381 * For the first 64MB of ram nominally allocate sufficient buffers to
382 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
383 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
384 * the buffer cache we limit the eventual kva reservation to
385 * maxbcache bytes.
386 *
387 * factor represents the 1/4 x ram conversion.
388 */
389 if (nbuf == 0) {
390 long factor = 4 * NBUFCALCSIZE / 1024;
391 long kbytes = physmem * (PAGE_SIZE / 1024);
392
393 nbuf = 50;
394 if (kbytes > 4096)
395 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
396 if (kbytes > 65536)
397 nbuf += (kbytes - 65536) * 2 / (factor * 5);
398 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE)
399 nbuf = maxbcache / NBUFCALCSIZE;
400 }
401
402 /*
403 * Do not allow the buffer_map to be more then 1/2 the size of the
404 * kernel_map.
405 */
406 if (nbuf > (virtual_end - virtual_start +
407 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) {
408 nbuf = (virtual_end - virtual_start +
409 virtual2_end - virtual2_start) / (MAXBSIZE * 2);
410 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
411 }
412
413 /*
414 * Do not allow the buffer_map to use more than 50% of available
415 * physical-equivalent memory. Since the VM pages which back
416 * individual buffers are typically wired, having too many bufs
417 * can prevent the system from paging properly.
418 */
419 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) {
420 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2);
421 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
422 }
423
424 /*
425 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
426 * the valloc space which is just the virtual_end - virtual_start
427 * section. We use valloc() to allocate the buf header array.
428 */
429 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
430 nbuf = (virtual_end - virtual_start) /
431 sizeof(struct buf) / 2;
432 kprintf("Warning: nbufs capped at %ld due to valloc "
433 "considerations\n", nbuf);
434 }
435
436 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8);
437 #ifdef NSWBUF_MIN
438 if (nswbuf_mem < NSWBUF_MIN)
439 nswbuf_mem = NSWBUF_MIN;
440 #endif
441 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16);
442 #ifdef NSWBUF_MIN
443 if (nswbuf_kva < NSWBUF_MIN)
444 nswbuf_kva = NSWBUF_MIN;
445 #endif
446 #ifdef DIRECTIO
447 ffs_rawread_setup();
448 #endif
449
450 valloc(swbuf_mem, struct buf, nswbuf_mem);
451 valloc(swbuf_kva, struct buf, nswbuf_kva);
452 valloc(buf, struct buf, nbuf);
453
454 /*
455 * End of first pass, size has been calculated so allocate memory
456 */
457 if (firstaddr == 0) {
458 size = (vm_size_t)(v - firstaddr);
459 firstaddr = kmem_alloc(&kernel_map, round_page(size),
460 VM_SUBSYS_BUF);
461 if (firstaddr == 0)
462 panic("startup: no room for tables");
463 goto again;
464 }
465
466 /*
467 * End of second pass, addresses have been assigned
468 *
469 * nbuf is an int, make sure we don't overflow the field.
470 *
471 * On 64-bit systems we always reserve maximal allocations for
472 * buffer cache buffers and there are no fragmentation issues,
473 * so the KVA segment does not have to be excessively oversized.
474 */
475 if ((vm_size_t)(v - firstaddr) != size)
476 panic("startup: table size inconsistency");
477
478 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
479 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) +
480 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size);
481 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
482 ((vm_offset_t)(nbuf + 16) * MAXBSIZE));
483 buffer_map.system_map = 1;
484 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
485 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) +
486 pager_map_size);
487 pager_map.system_map = 1;
488 kprintf("avail memory = %ju (%ju MB)\n",
489 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
490 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
491 1024 / 1024);
492 }
493
494 struct cpu_idle_stat {
495 int hint;
496 int reserved;
497 u_long halt;
498 u_long spin;
499 u_long repeat;
500 u_long repeat_last;
501 u_long repeat_delta;
502 u_long mwait_cx[CPU_MWAIT_CX_MAX];
503 } __cachealign;
504
505 #define CPU_IDLE_STAT_HALT -1
506 #define CPU_IDLE_STAT_SPIN -2
507
508 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
509
510 static int
511 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
512 {
513 int idx = arg2, cpu, error;
514 u_long val = 0;
515
516 if (idx == CPU_IDLE_STAT_HALT) {
517 for (cpu = 0; cpu < ncpus; ++cpu)
518 val += cpu_idle_stats[cpu].halt;
519 } else if (idx == CPU_IDLE_STAT_SPIN) {
520 for (cpu = 0; cpu < ncpus; ++cpu)
521 val += cpu_idle_stats[cpu].spin;
522 } else {
523 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
524 ("invalid index %d", idx));
525 for (cpu = 0; cpu < ncpus; ++cpu)
526 val += cpu_idle_stats[cpu].mwait_cx[idx];
527 }
528
529 error = sysctl_handle_quad(oidp, &val, 0, req);
530 if (error || req->newptr == NULL)
531 return error;
532
533 if (idx == CPU_IDLE_STAT_HALT) {
534 for (cpu = 0; cpu < ncpus; ++cpu)
535 cpu_idle_stats[cpu].halt = 0;
536 cpu_idle_stats[0].halt = val;
537 } else if (idx == CPU_IDLE_STAT_SPIN) {
538 for (cpu = 0; cpu < ncpus; ++cpu)
539 cpu_idle_stats[cpu].spin = 0;
540 cpu_idle_stats[0].spin = val;
541 } else {
542 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
543 ("invalid index %d", idx));
544 for (cpu = 0; cpu < ncpus; ++cpu)
545 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
546 cpu_idle_stats[0].mwait_cx[idx] = val;
547 }
548 return 0;
549 }
550
551 static void
552 cpu_mwait_attach(void)
553 {
554 struct sbuf sb;
555 int hint_idx, i;
556
557 if (!CPU_MWAIT_HAS_CX)
558 return;
559
560 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
561 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
562 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
563 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
564 int bm_sts = 1;
565
566 /*
567 * Pentium dual-core, Core 2 and beyond do not need any
568 * additional activities to enter deep C-state, i.e. C3(+).
569 */
570 cpu_mwait_cx_no_bmarb();
571
572 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
573 if (!bm_sts)
574 cpu_mwait_cx_no_bmsts();
575 }
576
577 sbuf_new(&sb, cpu_mwait_cx_supported,
578 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
579
580 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
581 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
582 int sub;
583
584 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
585
586 sysctl_ctx_init(&cx->sysctl_ctx);
587 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
588 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
589 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
590 if (cx->sysctl_tree == NULL)
591 continue;
592
593 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
594 SYSCTL_ADD_INT(&cx->sysctl_ctx,
595 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
596 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
597 "sub-state count");
598 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
599 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
600 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
601 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
602
603 for (sub = 0; sub < cx->subcnt; ++sub)
604 sbuf_printf(&sb, "C%d/%d ", i, sub);
605 }
606 sbuf_trim(&sb);
607 sbuf_finish(&sb);
608
609 /*
610 * Non-deep C-states
611 */
612 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
613 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
614 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
615 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
616 M_DEVBUF, M_WAITOK);
617
618 hint_idx = 0;
619 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
620 int j, subcnt;
621
622 subcnt = cpu_mwait_cx_info[i].subcnt;
623 for (j = 0; j < subcnt; ++j) {
624 KASSERT(hint_idx < cpu_mwait_hints_cnt,
625 ("invalid mwait hint index %d", hint_idx));
626 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
627 ++hint_idx;
628 }
629 }
630 KASSERT(hint_idx == cpu_mwait_hints_cnt,
631 ("mwait hint count %d != index %d",
632 cpu_mwait_hints_cnt, hint_idx));
633
634 if (bootverbose) {
635 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
636 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
637 int hint = cpu_mwait_hints[i];
638
639 kprintf(" C%d/%d hint 0x%04x\n",
640 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
641 hint);
642 }
643 }
644
645 /*
646 * Deep C-states
647 */
648 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
649 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
650 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
651 M_DEVBUF, M_WAITOK);
652
653 hint_idx = 0;
654 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
655 int j, subcnt;
656
657 subcnt = cpu_mwait_cx_info[i].subcnt;
658 for (j = 0; j < subcnt; ++j) {
659 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
660 ("invalid mwait deep hint index %d", hint_idx));
661 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
662 ++hint_idx;
663 }
664 }
665 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
666 ("mwait deep hint count %d != index %d",
667 cpu_mwait_deep_hints_cnt, hint_idx));
668
669 if (bootverbose) {
670 kprintf("MWAIT deep hints:\n");
671 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
672 int hint = cpu_mwait_deep_hints[i];
673
674 kprintf(" C%d/%d hint 0x%04x\n",
675 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
676 hint);
677 }
678 }
679 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
680
681 for (i = 0; i < ncpus; ++i) {
682 char name[16];
683
684 ksnprintf(name, sizeof(name), "idle%d", i);
685 SYSCTL_ADD_PROC(NULL,
686 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO,
687 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i],
688 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", "");
689 }
690 }
691
692 static void
693 cpu_finish(void *dummy __unused)
694 {
695 cpu_setregs();
696 cpu_mwait_attach();
697 }
698
699 static void
700 pic_finish(void *dummy __unused)
701 {
702 /* Log ELCR information */
703 elcr_dump();
704
705 /* Log MPTABLE information */
706 mptable_pci_int_dump();
707
708 /* Finalize PCI */
709 MachIntrABI.finalize();
710 }
711
712 /*
713 * Send an interrupt to process.
714 *
715 * Stack is set up to allow sigcode stored
716 * at top to call routine, followed by kcall
717 * to sigreturn routine below. After sigreturn
718 * resets the signal mask, the stack, and the
719 * frame pointer, it returns to the user
720 * specified pc, psl.
721 */
722 void
723 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
724 {
725 struct lwp *lp = curthread->td_lwp;
726 struct proc *p = lp->lwp_proc;
727 struct trapframe *regs;
728 struct sigacts *psp = p->p_sigacts;
729 struct sigframe sf, *sfp;
730 int oonstack;
731 char *sp;
732
733 regs = lp->lwp_md.md_regs;
734 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
735
736 /* Save user context */
737 bzero(&sf, sizeof(struct sigframe));
738 sf.sf_uc.uc_sigmask = *mask;
739 sf.sf_uc.uc_stack = lp->lwp_sigstk;
740 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
741 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
742 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
743
744 /* Make the size of the saved context visible to userland */
745 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
746
747 /* Allocate and validate space for the signal handler context. */
748 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
749 SIGISMEMBER(psp->ps_sigonstack, sig)) {
750 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
751 sizeof(struct sigframe));
752 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
753 } else {
754 /* We take red zone into account */
755 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
756 }
757
758 /*
759 * XXX AVX needs 64-byte alignment but sigframe has other fields and
760 * the embedded ucontext is not at the front, so aligning this won't
761 * help us. Fortunately we bcopy in/out of the sigframe, so the
762 * kernel is ok.
763 *
764 * The problem though is if userland winds up trying to use the
765 * context directly.
766 */
767 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
768
769 /* Translate the signal is appropriate */
770 if (p->p_sysent->sv_sigtbl) {
771 if (sig <= p->p_sysent->sv_sigsize)
772 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
773 }
774
775 /*
776 * Build the argument list for the signal handler.
777 *
778 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
779 */
780 regs->tf_rdi = sig; /* argument 1 */
781 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
782
783 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
784 /*
785 * Signal handler installed with SA_SIGINFO.
786 *
787 * action(signo, siginfo, ucontext)
788 */
789 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
790 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
791 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
792
793 /* fill siginfo structure */
794 sf.sf_si.si_signo = sig;
795 sf.sf_si.si_code = code;
796 sf.sf_si.si_addr = (void *)regs->tf_addr;
797 } else {
798 /*
799 * Old FreeBSD-style arguments.
800 *
801 * handler (signo, code, [uc], addr)
802 */
803 regs->tf_rsi = (register_t)code; /* argument 2 */
804 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
805 sf.sf_ahu.sf_handler = catcher;
806 }
807
808 /*
809 * If we're a vm86 process, we want to save the segment registers.
810 * We also change eflags to be our emulated eflags, not the actual
811 * eflags.
812 */
813 #if 0 /* JG */
814 if (regs->tf_eflags & PSL_VM) {
815 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
816 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
817
818 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
819 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
820 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
821 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
822
823 if (vm86->vm86_has_vme == 0)
824 sf.sf_uc.uc_mcontext.mc_eflags =
825 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
826 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
827
828 /*
829 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
830 * syscalls made by the signal handler. This just avoids
831 * wasting time for our lazy fixup of such faults. PSL_NT
832 * does nothing in vm86 mode, but vm86 programs can set it
833 * almost legitimately in probes for old cpu types.
834 */
835 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
836 }
837 #endif
838
839 /*
840 * Save the FPU state and reinit the FP unit
841 */
842 npxpush(&sf.sf_uc.uc_mcontext);
843
844 /*
845 * Copy the sigframe out to the user's stack.
846 */
847 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
848 /*
849 * Something is wrong with the stack pointer.
850 * ...Kill the process.
851 */
852 sigexit(lp, SIGILL);
853 }
854
855 regs->tf_rsp = (register_t)sfp;
856 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
857
858 /*
859 * i386 abi specifies that the direction flag must be cleared
860 * on function entry
861 */
862 regs->tf_rflags &= ~(PSL_T|PSL_D);
863
864 /*
865 * 64 bit mode has a code and stack selector but
866 * no data or extra selector. %fs and %gs are not
867 * stored in-context.
868 */
869 regs->tf_cs = _ucodesel;
870 regs->tf_ss = _udatasel;
871 clear_quickret();
872 }
873
874 /*
875 * Sanitize the trapframe for a virtual kernel passing control to a custom
876 * VM context. Remove any items that would otherwise create a privilage
877 * issue.
878 *
879 * XXX at the moment we allow userland to set the resume flag. Is this a
880 * bad idea?
881 */
882 int
883 cpu_sanitize_frame(struct trapframe *frame)
884 {
885 frame->tf_cs = _ucodesel;
886 frame->tf_ss = _udatasel;
887 /* XXX VM (8086) mode not supported? */
888 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
889 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
890
891 return(0);
892 }
893
894 /*
895 * Sanitize the tls so loading the descriptor does not blow up
896 * on us. For x86_64 we don't have to do anything.
897 */
898 int
899 cpu_sanitize_tls(struct savetls *tls)
900 {
901 return(0);
902 }
903
904 /*
905 * sigreturn(ucontext_t *sigcntxp)
906 *
907 * System call to cleanup state after a signal
908 * has been taken. Reset signal mask and
909 * stack state from context left by sendsig (above).
910 * Return to previous pc and psl as specified by
911 * context left by sendsig. Check carefully to
912 * make sure that the user has not modified the
913 * state to gain improper privileges.
914 *
915 * MPSAFE
916 */
917 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
918 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
919
920 int
921 sys_sigreturn(struct sigreturn_args *uap)
922 {
923 struct lwp *lp = curthread->td_lwp;
924 struct trapframe *regs;
925 ucontext_t uc;
926 ucontext_t *ucp;
927 register_t rflags;
928 int cs;
929 int error;
930
931 /*
932 * We have to copy the information into kernel space so userland
933 * can't modify it while we are sniffing it.
934 */
935 regs = lp->lwp_md.md_regs;
936 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
937 if (error)
938 return (error);
939 ucp = &uc;
940 rflags = ucp->uc_mcontext.mc_rflags;
941
942 /* VM (8086) mode not supported */
943 rflags &= ~PSL_VM_UNSUPP;
944
945 #if 0 /* JG */
946 if (eflags & PSL_VM) {
947 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
948 struct vm86_kernel *vm86;
949
950 /*
951 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
952 * set up the vm86 area, and we can't enter vm86 mode.
953 */
954 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
955 return (EINVAL);
956 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
957 if (vm86->vm86_inited == 0)
958 return (EINVAL);
959
960 /* go back to user mode if both flags are set */
961 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
962 trapsignal(lp, SIGBUS, 0);
963
964 if (vm86->vm86_has_vme) {
965 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
966 (eflags & VME_USERCHANGE) | PSL_VM;
967 } else {
968 vm86->vm86_eflags = eflags; /* save VIF, VIP */
969 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
970 (eflags & VM_USERCHANGE) | PSL_VM;
971 }
972 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
973 tf->tf_eflags = eflags;
974 tf->tf_vm86_ds = tf->tf_ds;
975 tf->tf_vm86_es = tf->tf_es;
976 tf->tf_vm86_fs = tf->tf_fs;
977 tf->tf_vm86_gs = tf->tf_gs;
978 tf->tf_ds = _udatasel;
979 tf->tf_es = _udatasel;
980 tf->tf_fs = _udatasel;
981 tf->tf_gs = _udatasel;
982 } else
983 #endif
984 {
985 /*
986 * Don't allow users to change privileged or reserved flags.
987 */
988 /*
989 * XXX do allow users to change the privileged flag PSL_RF.
990 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
991 * should sometimes set it there too. tf_eflags is kept in
992 * the signal context during signal handling and there is no
993 * other place to remember it, so the PSL_RF bit may be
994 * corrupted by the signal handler without us knowing.
995 * Corruption of the PSL_RF bit at worst causes one more or
996 * one less debugger trap, so allowing it is fairly harmless.
997 */
998 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
999 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
1000 return(EINVAL);
1001 }
1002
1003 /*
1004 * Don't allow users to load a valid privileged %cs. Let the
1005 * hardware check for invalid selectors, excess privilege in
1006 * other selectors, invalid %eip's and invalid %esp's.
1007 */
1008 cs = ucp->uc_mcontext.mc_cs;
1009 if (!CS_SECURE(cs)) {
1010 kprintf("sigreturn: cs = 0x%x\n", cs);
1011 trapsignal(lp, SIGBUS, T_PROTFLT);
1012 return(EINVAL);
1013 }
1014 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
1015 }
1016
1017 /*
1018 * Restore the FPU state from the frame
1019 */
1020 crit_enter();
1021 npxpop(&ucp->uc_mcontext);
1022
1023 if (ucp->uc_mcontext.mc_onstack & 1)
1024 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1025 else
1026 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1027
1028 lp->lwp_sigmask = ucp->uc_sigmask;
1029 SIG_CANTMASK(lp->lwp_sigmask);
1030 clear_quickret();
1031 crit_exit();
1032 return(EJUSTRETURN);
1033 }
1034
1035 /*
1036 * Machine dependent boot() routine
1037 *
1038 * I haven't seen anything to put here yet
1039 * Possibly some stuff might be grafted back here from boot()
1040 */
1041 void
1042 cpu_boot(int howto)
1043 {
1044 }
1045
1046 /*
1047 * Shutdown the CPU as much as possible
1048 */
1049 void
1050 cpu_halt(void)
1051 {
1052 for (;;)
1053 __asm__ __volatile("hlt");
1054 }
1055
1056 /*
1057 * cpu_idle() represents the idle LWKT. You cannot return from this function
1058 * (unless you want to blow things up!). Instead we look for runnable threads
1059 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1060 *
1061 * The main loop is entered with a critical section held, we must release
1062 * the critical section before doing anything else. lwkt_switch() will
1063 * check for pending interrupts due to entering and exiting its own
1064 * critical section.
1065 *
1066 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1067 * However, there are cases where the idlethread will be entered with
1068 * the possibility that no IPI will occur and in such cases
1069 * lwkt_switch() sets TDF_IDLE_NOHLT.
1070 *
1071 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1072 * must occur before it starts using ACPI halt.
1073 *
1074 * NOTE: Value overridden in hammer_time().
1075 */
1076 static int cpu_idle_hlt = 2;
1077 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1078 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1079 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1080 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1081
1082 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1083 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1084 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1085 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1086
1087 static void
1088 cpu_idle_default_hook(void)
1089 {
1090 /*
1091 * We must guarentee that hlt is exactly the instruction
1092 * following the sti.
1093 */
1094 __asm __volatile("sti; hlt");
1095 }
1096
1097 /* Other subsystems (e.g., ACPI) can hook this later. */
1098 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1099
1100 static __inline int
1101 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1102 {
1103 int hint, cx_idx;
1104 u_int idx;
1105
1106 hint = stat->hint;
1107 if (hint >= 0)
1108 goto done;
1109
1110 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1111 cpu_mwait_repeat_shift;
1112 if (idx >= cpu_mwait_c1_hints_cnt) {
1113 /* Step up faster, once we walked through all C1 states */
1114 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1115 }
1116 if (hint == CPU_MWAIT_HINT_AUTODEEP) {
1117 if (idx >= cpu_mwait_deep_hints_cnt)
1118 idx = cpu_mwait_deep_hints_cnt - 1;
1119 hint = cpu_mwait_deep_hints[idx];
1120 } else {
1121 if (idx >= cpu_mwait_hints_cnt)
1122 idx = cpu_mwait_hints_cnt - 1;
1123 hint = cpu_mwait_hints[idx];
1124 }
1125 done:
1126 cx_idx = MWAIT_EAX_TO_CX(hint);
1127 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1128 stat->mwait_cx[cx_idx]++;
1129 return hint;
1130 }
1131
1132 void
1133 cpu_idle(void)
1134 {
1135 globaldata_t gd = mycpu;
1136 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1137 struct thread *td __debugvar = gd->gd_curthread;
1138 int reqflags;
1139 int quick;
1140
1141 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1142
1143 crit_exit();
1144 KKASSERT(td->td_critcount == 0);
1145
1146 for (;;) {
1147 /*
1148 * See if there are any LWKTs ready to go.
1149 */
1150 lwkt_switch();
1151
1152 /*
1153 * When halting inside a cli we must check for reqflags
1154 * races, particularly [re]schedule requests. Running
1155 * splz() does the job.
1156 *
1157 * cpu_idle_hlt:
1158 * 0 Never halt, just spin
1159 *
1160 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1161 *
1162 * Better default for modern (Haswell+) Intel
1163 * cpus.
1164 *
1165 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1166 * use the ACPI halt (default). This is a hybrid
1167 * approach. See machdep.cpu_idle_repeat.
1168 *
1169 * Better default for modern AMD cpus and older
1170 * Intel cpus.
1171 *
1172 * 3 Always use the ACPI halt. This typically
1173 * eats the least amount of power but the cpu
1174 * will be slow waking up. Slows down e.g.
1175 * compiles and other pipe/event oriented stuff.
1176 *
1177 * 4 Always use HLT.
1178 *
1179 * NOTE: Interrupts are enabled and we are not in a critical
1180 * section.
1181 *
1182 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1183 * don't bother capping gd_idle_repeat, it is ok if
1184 * it overflows.
1185 *
1186 * Implement optimized invltlb operations when halted
1187 * in idle. By setting the bit in smp_idleinvl_mask
1188 * we inform other cpus that they can set _reqs to
1189 * request an invltlb. Current the code to do that
1190 * sets the bits in _reqs anyway, but then check _mask
1191 * to determine if they can assume the invltlb will execute.
1192 *
1193 * A critical section is required to ensure that interrupts
1194 * do not fully run until after we've had a chance to execute
1195 * the request.
1196 */
1197 if (gd->gd_idle_repeat == 0) {
1198 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1199 if (stat->repeat > cpu_idle_repeat_max)
1200 stat->repeat = cpu_idle_repeat_max;
1201 stat->repeat_last = 0;
1202 stat->repeat_delta = 0;
1203 }
1204 ++stat->repeat_last;
1205
1206 ++gd->gd_idle_repeat;
1207 reqflags = gd->gd_reqflags;
1208 quick = (cpu_idle_hlt == 1) ||
1209 (cpu_idle_hlt < 3 &&
1210 gd->gd_idle_repeat < cpu_idle_repeat);
1211
1212 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1213 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1214 splz(); /* XXX */
1215 crit_enter_gd(gd);
1216 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid);
1217 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1218 cpu_mwait_cx_hint(stat), 0);
1219 stat->halt++;
1220 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid);
1221 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs,
1222 gd->gd_cpuid)) {
1223 cpu_invltlb();
1224 cpu_mfence();
1225 }
1226 crit_exit_gd(gd);
1227 } else if (cpu_idle_hlt) {
1228 __asm __volatile("cli");
1229 splz();
1230 crit_enter_gd(gd);
1231 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid);
1232 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1233 if (quick)
1234 cpu_idle_default_hook();
1235 else
1236 cpu_idle_hook();
1237 }
1238 __asm __volatile("sti");
1239 stat->halt++;
1240 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid);
1241 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs,
1242 gd->gd_cpuid)) {
1243 cpu_invltlb();
1244 cpu_mfence();
1245 }
1246 crit_exit_gd(gd);
1247 } else {
1248 splz();
1249 __asm __volatile("sti");
1250 stat->spin++;
1251 }
1252 }
1253 }
1254
1255 /*
1256 * Called in a loop indirectly via Xcpustop
1257 */
1258 void
1259 cpu_smp_stopped(void)
1260 {
1261 globaldata_t gd = mycpu;
1262 volatile __uint64_t *ptr;
1263 __uint64_t ovalue;
1264
1265 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid);
1266 ovalue = *ptr;
1267 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) {
1268 if (cpu_mi_feature & CPU_MI_MONITOR) {
1269 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), ovalue,
1270 cpu_mwait_hints[CPU_MWAIT_C1], 0);
1271 } else {
1272 cpu_halt(); /* depend on lapic timer */
1273 }
1274 }
1275 }
1276
1277 /*
1278 * This routine is called if a spinlock has been held through the
1279 * exponential backoff period and is seriously contested. On a real cpu
1280 * we let it spin.
1281 */
1282 void
1283 cpu_spinlock_contested(void)
1284 {
1285 cpu_pause();
1286 }
1287
1288 /*
1289 * Clear registers on exec
1290 */
1291 void
1292 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1293 {
1294 struct thread *td = curthread;
1295 struct lwp *lp = td->td_lwp;
1296 struct pcb *pcb = td->td_pcb;
1297 struct trapframe *regs = lp->lwp_md.md_regs;
1298
1299 /* was i386_user_cleanup() in NetBSD */
1300 user_ldt_free(pcb);
1301
1302 clear_quickret();
1303 bzero((char *)regs, sizeof(struct trapframe));
1304 regs->tf_rip = entry;
1305 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1306 regs->tf_rdi = stack; /* argv */
1307 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1308 regs->tf_ss = _udatasel;
1309 regs->tf_cs = _ucodesel;
1310 regs->tf_rbx = ps_strings;
1311
1312 /*
1313 * Reset the hardware debug registers if they were in use.
1314 * They won't have any meaning for the newly exec'd process.
1315 */
1316 if (pcb->pcb_flags & PCB_DBREGS) {
1317 pcb->pcb_dr0 = 0;
1318 pcb->pcb_dr1 = 0;
1319 pcb->pcb_dr2 = 0;
1320 pcb->pcb_dr3 = 0;
1321 pcb->pcb_dr6 = 0;
1322 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1323 if (pcb == td->td_pcb) {
1324 /*
1325 * Clear the debug registers on the running
1326 * CPU, otherwise they will end up affecting
1327 * the next process we switch to.
1328 */
1329 reset_dbregs();
1330 }
1331 pcb->pcb_flags &= ~PCB_DBREGS;
1332 }
1333
1334 /*
1335 * Initialize the math emulator (if any) for the current process.
1336 * Actually, just clear the bit that says that the emulator has
1337 * been initialized. Initialization is delayed until the process
1338 * traps to the emulator (if it is done at all) mainly because
1339 * emulators don't provide an entry point for initialization.
1340 */
1341 pcb->pcb_flags &= ~FP_SOFTFP;
1342
1343 /*
1344 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1345 * gd_npxthread. Otherwise a preemptive interrupt thread
1346 * may panic in npxdna().
1347 */
1348 crit_enter();
1349 load_cr0(rcr0() | CR0_MP);
1350
1351 /*
1352 * NOTE: The MSR values must be correct so we can return to
1353 * userland. gd_user_fs/gs must be correct so the switch
1354 * code knows what the current MSR values are.
1355 */
1356 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1357 pcb->pcb_gsbase = 0;
1358 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1359 mdcpu->gd_user_gs = 0;
1360 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1361 wrmsr(MSR_KGSBASE, 0);
1362
1363 /* Initialize the npx (if any) for the current process. */
1364 npxinit();
1365 crit_exit();
1366
1367 pcb->pcb_ds = _udatasel;
1368 pcb->pcb_es = _udatasel;
1369 pcb->pcb_fs = _udatasel;
1370 pcb->pcb_gs = _udatasel;
1371 }
1372
1373 void
1374 cpu_setregs(void)
1375 {
1376 register_t cr0;
1377
1378 cr0 = rcr0();
1379 cr0 |= CR0_NE; /* Done by npxinit() */
1380 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1381 cr0 |= CR0_WP | CR0_AM;
1382 load_cr0(cr0);
1383 load_gs(_udatasel);
1384 }
1385
1386 static int
1387 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1388 {
1389 int error;
1390 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1391 req);
1392 if (!error && req->newptr)
1393 resettodr();
1394 return (error);
1395 }
1396
1397 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1398 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1399
1400 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1401 CTLFLAG_RW, &disable_rtc_set, 0, "");
1402
1403 #if 0 /* JG */
1404 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1405 CTLFLAG_RD, &bootinfo, bootinfo, "");
1406 #endif
1407
1408 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1409 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1410
1411 extern u_long bootdev; /* not a cdev_t - encoding is different */
1412 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1413 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1414
1415 static int
1416 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS)
1417 {
1418 struct efi_map_header *efihdr;
1419 caddr_t kmdp;
1420 uint32_t efisize;
1421
1422 kmdp = preload_search_by_type("elf kernel");
1423 if (kmdp == NULL)
1424 kmdp = preload_search_by_type("elf64 kernel");
1425 efihdr = (struct efi_map_header *)preload_search_info(kmdp,
1426 MODINFO_METADATA | MODINFOMD_EFI_MAP);
1427 if (efihdr == NULL)
1428 return (0);
1429 efisize = *((uint32_t *)efihdr - 1);
1430 return (SYSCTL_OUT(req, efihdr, efisize));
1431 }
1432 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0,
1433 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map");
1434
1435 /*
1436 * Initialize 386 and configure to run kernel
1437 */
1438
1439 /*
1440 * Initialize segments & interrupt table
1441 */
1442
1443 int _default_ldt;
1444 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1445 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1446 #if 0 /* JG */
1447 union descriptor ldt[NLDT]; /* local descriptor table */
1448 #endif
1449
1450 /* table descriptors - used to load tables by cpu */
1451 struct region_descriptor r_gdt;
1452 struct region_descriptor r_idt_arr[MAXCPU];
1453
1454 /* JG proc0paddr is a virtual address */
1455 void *proc0paddr;
1456 /* JG alignment? */
1457 char proc0paddr_buff[LWKT_THREAD_STACK];
1458
1459
1460 /* software prototypes -- in more palatable form */
1461 struct soft_segment_descriptor gdt_segs[] = {
1462 /* GNULL_SEL 0 Null Descriptor */
1463 { 0x0, /* segment base address */
1464 0x0, /* length */
1465 0, /* segment type */
1466 0, /* segment descriptor priority level */
1467 0, /* segment descriptor present */
1468 0, /* long */
1469 0, /* default 32 vs 16 bit size */
1470 0 /* limit granularity (byte/page units)*/ },
1471 /* GCODE_SEL 1 Code Descriptor for kernel */
1472 { 0x0, /* segment base address */
1473 0xfffff, /* length - all address space */
1474 SDT_MEMERA, /* segment type */
1475 SEL_KPL, /* segment descriptor priority level */
1476 1, /* segment descriptor present */
1477 1, /* long */
1478 0, /* default 32 vs 16 bit size */
1479 1 /* limit granularity (byte/page units)*/ },
1480 /* GDATA_SEL 2 Data Descriptor for kernel */
1481 { 0x0, /* segment base address */
1482 0xfffff, /* length - all address space */
1483 SDT_MEMRWA, /* segment type */
1484 SEL_KPL, /* segment descriptor priority level */
1485 1, /* segment descriptor present */
1486 1, /* long */
1487 0, /* default 32 vs 16 bit size */
1488 1 /* limit granularity (byte/page units)*/ },
1489 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1490 { 0x0, /* segment base address */
1491 0xfffff, /* length - all address space */
1492 SDT_MEMERA, /* segment type */
1493 SEL_UPL, /* segment descriptor priority level */
1494 1, /* segment descriptor present */
1495 0, /* long */
1496 1, /* default 32 vs 16 bit size */
1497 1 /* limit granularity (byte/page units)*/ },
1498 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1499 { 0x0, /* segment base address */
1500 0xfffff, /* length - all address space */
1501 SDT_MEMRWA, /* segment type */
1502 SEL_UPL, /* segment descriptor priority level */
1503 1, /* segment descriptor present */
1504 0, /* long */
1505 1, /* default 32 vs 16 bit size */
1506 1 /* limit granularity (byte/page units)*/ },
1507 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1508 { 0x0, /* segment base address */
1509 0xfffff, /* length - all address space */
1510 SDT_MEMERA, /* segment type */
1511 SEL_UPL, /* segment descriptor priority level */
1512 1, /* segment descriptor present */
1513 1, /* long */
1514 0, /* default 32 vs 16 bit size */
1515 1 /* limit granularity (byte/page units)*/ },
1516 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1517 {
1518 0x0, /* segment base address */
1519 sizeof(struct x86_64tss)-1,/* length - all address space */
1520 SDT_SYSTSS, /* segment type */
1521 SEL_KPL, /* segment descriptor priority level */
1522 1, /* segment descriptor present */
1523 0, /* long */
1524 0, /* unused - default 32 vs 16 bit size */
1525 0 /* limit granularity (byte/page units)*/ },
1526 /* Actually, the TSS is a system descriptor which is double size */
1527 { 0x0, /* segment base address */
1528 0x0, /* length */
1529 0, /* segment type */
1530 0, /* segment descriptor priority level */
1531 0, /* segment descriptor present */
1532 0, /* long */
1533 0, /* default 32 vs 16 bit size */
1534 0 /* limit granularity (byte/page units)*/ },
1535 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1536 { 0x0, /* segment base address */
1537 0xfffff, /* length - all address space */
1538 SDT_MEMRWA, /* segment type */
1539 SEL_UPL, /* segment descriptor priority level */
1540 1, /* segment descriptor present */
1541 0, /* long */
1542 1, /* default 32 vs 16 bit size */
1543 1 /* limit granularity (byte/page units)*/ },
1544 };
1545
1546 void
1547 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1548 {
1549 int cpu;
1550
1551 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1552 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1553
1554 ip->gd_looffset = (uintptr_t)func;
1555 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1556 ip->gd_ist = ist;
1557 ip->gd_xx = 0;
1558 ip->gd_type = typ;
1559 ip->gd_dpl = dpl;
1560 ip->gd_p = 1;
1561 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1562 }
1563 }
1564
1565 void
1566 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1567 {
1568 struct gate_descriptor *ip;
1569
1570 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1571
1572 ip = &idt_arr[cpu][idx];
1573 ip->gd_looffset = (uintptr_t)func;
1574 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1575 ip->gd_ist = ist;
1576 ip->gd_xx = 0;
1577 ip->gd_type = typ;
1578 ip->gd_dpl = dpl;
1579 ip->gd_p = 1;
1580 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1581 }
1582
1583 #define IDTVEC(name) __CONCAT(X,name)
1584
1585 extern inthand_t
1586 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1587 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1588 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1589 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1590 IDTVEC(xmm), IDTVEC(dblfault),
1591 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1592
1593 void
1594 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1595 {
1596 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1597 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1598 ssd->ssd_type = sd->sd_type;
1599 ssd->ssd_dpl = sd->sd_dpl;
1600 ssd->ssd_p = sd->sd_p;
1601 ssd->ssd_def32 = sd->sd_def32;
1602 ssd->ssd_gran = sd->sd_gran;
1603 }
1604
1605 void
1606 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1607 {
1608
1609 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1610 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1611 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1612 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1613 sd->sd_type = ssd->ssd_type;
1614 sd->sd_dpl = ssd->ssd_dpl;
1615 sd->sd_p = ssd->ssd_p;
1616 sd->sd_long = ssd->ssd_long;
1617 sd->sd_def32 = ssd->ssd_def32;
1618 sd->sd_gran = ssd->ssd_gran;
1619 }
1620
1621 void
1622 ssdtosyssd(struct soft_segment_descriptor *ssd,
1623 struct system_segment_descriptor *sd)
1624 {
1625
1626 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1627 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1628 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1629 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1630 sd->sd_type = ssd->ssd_type;
1631 sd->sd_dpl = ssd->ssd_dpl;
1632 sd->sd_p = ssd->ssd_p;
1633 sd->sd_gran = ssd->ssd_gran;
1634 }
1635
1636 /*
1637 * Populate the (physmap) array with base/bound pairs describing the
1638 * available physical memory in the system, then test this memory and
1639 * build the phys_avail array describing the actually-available memory.
1640 *
1641 * If we cannot accurately determine the physical memory map, then use
1642 * value from the 0xE801 call, and failing that, the RTC.
1643 *
1644 * Total memory size may be set by the kernel environment variable
1645 * hw.physmem or the compile-time define MAXMEM.
1646 *
1647 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1648 * of PAGE_SIZE. This also greatly reduces the memory test time
1649 * which would otherwise be excessive on machines with > 8G of ram.
1650 *
1651 * XXX first should be vm_paddr_t.
1652 */
1653
1654 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1655 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1656 #define PHYSMAP_SIZE VM_PHYSSEG_MAX
1657
1658 vm_paddr_t physmap[PHYSMAP_SIZE];
1659 struct bios_smap *smapbase, *smap, *smapend;
1660 struct efi_map_header *efihdrbase;
1661 u_int32_t smapsize;
1662
1663 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024)
1664 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1)
1665
1666 static void
1667 add_smap_entries(int *physmap_idx)
1668 {
1669 int i;
1670
1671 smapsize = *((u_int32_t *)smapbase - 1);
1672 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1673
1674 for (smap = smapbase; smap < smapend; smap++) {
1675 if (boothowto & RB_VERBOSE)
1676 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1677 smap->type, smap->base, smap->length);
1678
1679 if (smap->type != SMAP_TYPE_MEMORY)
1680 continue;
1681
1682 if (smap->length == 0)
1683 continue;
1684
1685 for (i = 0; i <= *physmap_idx; i += 2) {
1686 if (smap->base < physmap[i + 1]) {
1687 if (boothowto & RB_VERBOSE) {
1688 kprintf("Overlapping or non-monotonic "
1689 "memory region, ignoring "
1690 "second region\n");
1691 }
1692 break;
1693 }
1694 }
1695 if (i <= *physmap_idx)
1696 continue;
1697
1698 Realmem += smap->length;
1699
1700 if (smap->base == physmap[*physmap_idx + 1]) {
1701 physmap[*physmap_idx + 1] += smap->length;
1702 continue;
1703 }
1704
1705 *physmap_idx += 2;
1706 if (*physmap_idx == PHYSMAP_SIZE) {
1707 kprintf("Too many segments in the physical "
1708 "address map, giving up\n");
1709 break;
1710 }
1711 physmap[*physmap_idx] = smap->base;
1712 physmap[*physmap_idx + 1] = smap->base + smap->length;
1713 }
1714 }
1715
1716 static void
1717 add_efi_map_entries(int *physmap_idx)
1718 {
1719 struct efi_md *map, *p;
1720 const char *type;
1721 size_t efisz;
1722 int i, ndesc;
1723
1724 static const char *types[] = {
1725 "Reserved",
1726 "LoaderCode",
1727 "LoaderData",
1728 "BootServicesCode",
1729 "BootServicesData",
1730 "RuntimeServicesCode",
1731 "RuntimeServicesData",
1732 "ConventionalMemory",
1733 "UnusableMemory",
1734 "ACPIReclaimMemory",
1735 "ACPIMemoryNVS",
1736 "MemoryMappedIO",
1737 "MemoryMappedIOPortSpace",
1738 "PalCode"
1739 };
1740
1741 /*
1742 * Memory map data provided by UEFI via the GetMemoryMap
1743 * Boot Services API.
1744 */
1745 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf;
1746 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz);
1747
1748 if (efihdrbase->descriptor_size == 0)
1749 return;
1750 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size;
1751
1752 if (boothowto & RB_VERBOSE)
1753 kprintf("%23s %12s %12s %8s %4s\n",
1754 "Type", "Physical", "Virtual", "#Pages", "Attr");
1755
1756 for (i = 0, p = map; i < ndesc; i++,
1757 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) {
1758 if (boothowto & RB_VERBOSE) {
1759 if (p->md_type <= EFI_MD_TYPE_PALCODE)
1760 type = types[p->md_type];
1761 else
1762 type = "<INVALID>";
1763 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys,
1764 p->md_virt, p->md_pages);
1765 if (p->md_attr & EFI_MD_ATTR_UC)
1766 kprintf("UC ");
1767 if (p->md_attr & EFI_MD_ATTR_WC)
1768 kprintf("WC ");
1769 if (p->md_attr & EFI_MD_ATTR_WT)
1770 kprintf("WT ");
1771 if (p->md_attr & EFI_MD_ATTR_WB)
1772 kprintf("WB ");
1773 if (p->md_attr & EFI_MD_ATTR_UCE)
1774 kprintf("UCE ");
1775 if (p->md_attr & EFI_MD_ATTR_WP)
1776 kprintf("WP ");
1777 if (p->md_attr & EFI_MD_ATTR_RP)
1778 kprintf("RP ");
1779 if (p->md_attr & EFI_MD_ATTR_XP)
1780 kprintf("XP ");
1781 if (p->md_attr & EFI_MD_ATTR_RT)
1782 kprintf("RUNTIME");
1783 kprintf("\n");
1784 }
1785
1786 switch (p->md_type) {
1787 case EFI_MD_TYPE_CODE:
1788 case EFI_MD_TYPE_DATA:
1789 case EFI_MD_TYPE_BS_CODE:
1790 case EFI_MD_TYPE_BS_DATA:
1791 case EFI_MD_TYPE_FREE:
1792 /*
1793 * We're allowed to use any entry with these types.
1794 */
1795 break;
1796 default:
1797 continue;
1798 }
1799
1800 Realmem += p->md_pages * PAGE_SIZE;
1801
1802 if (p->md_phys == physmap[*physmap_idx + 1]) {
1803 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE;
1804 continue;
1805 }
1806
1807 *physmap_idx += 2;
1808 if (*physmap_idx == PHYSMAP_SIZE) {
1809 kprintf("Too many segments in the physical "
1810 "address map, giving up\n");
1811 break;
1812 }
1813 physmap[*physmap_idx] = p->md_phys;
1814 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE;
1815 }
1816 }
1817
1818 struct fb_info efi_fb_info;
1819 static int have_efi_framebuffer = 0;
1820
1821 static void
1822 efi_fb_init_vaddr(int direct_map)
1823 {
1824 uint64_t sz;
1825 vm_offset_t addr, v;
1826
1827 v = efi_fb_info.vaddr;
1828 sz = efi_fb_info.stride * efi_fb_info.height;
1829
1830 if (direct_map) {
1831 addr = PHYS_TO_DMAP(efi_fb_info.paddr);
1832 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS)
1833 efi_fb_info.vaddr = addr;
1834 } else {
1835 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr(
1836 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING);
1837 }
1838 }
1839
1840 int
1841 probe_efi_fb(int early)
1842 {
1843 struct efi_fb *efifb;
1844 caddr_t kmdp;
1845
1846 if (have_efi_framebuffer) {
1847 if (!early &&
1848 (efi_fb_info.vaddr == 0 ||
1849 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr)))
1850 efi_fb_init_vaddr(0);
1851 return 0;
1852 }
1853
1854 kmdp = preload_search_by_type("elf kernel");
1855 if (kmdp == NULL)
1856 kmdp = preload_search_by_type("elf64 kernel");
1857 efifb = (struct efi_fb *)preload_search_info(kmdp,
1858 MODINFO_METADATA | MODINFOMD_EFI_FB);
1859 if (efifb == NULL)
1860 return 1;
1861
1862 have_efi_framebuffer = 1;
1863
1864 efi_fb_info.is_vga_boot_display = 1;
1865 efi_fb_info.width = efifb->fb_width;
1866 efi_fb_info.height = efifb->fb_height;
1867 efi_fb_info.stride = efifb->fb_stride * 4;
1868 efi_fb_info.depth = 32;
1869 efi_fb_info.paddr = efifb->fb_addr;
1870 if (early) {
1871 efi_fb_info.vaddr = 0;
1872 } else {
1873 efi_fb_init_vaddr(0);
1874 }
1875 efi_fb_info.fbops.fb_set_par = NULL;
1876 efi_fb_info.fbops.fb_blank = NULL;
1877 efi_fb_info.fbops.fb_debug_enter = NULL;
1878 efi_fb_info.device = NULL;
1879
1880 return 0;
1881 }
1882
1883 static void
1884 efifb_startup(void *arg)
1885 {
1886 probe_efi_fb(0);
1887 }
1888
1889 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL);
1890
1891 static void
1892 getmemsize(caddr_t kmdp, u_int64_t first)
1893 {
1894 int off, physmap_idx, pa_indx, da_indx;
1895 int i, j;
1896 vm_paddr_t pa;
1897 vm_paddr_t msgbuf_size;
1898 u_long physmem_tunable;
1899 pt_entry_t *pte;
1900 quad_t dcons_addr, dcons_size;
1901
1902 bzero(physmap, sizeof(physmap));
1903 physmap_idx = 0;
1904
1905 /*
1906 * get memory map from INT 15:E820, kindly supplied by the loader.
1907 *
1908 * subr_module.c says:
1909 * "Consumer may safely assume that size value precedes data."
1910 * ie: an int32_t immediately precedes smap.
1911 */
1912 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp,
1913 MODINFO_METADATA | MODINFOMD_EFI_MAP);
1914 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1915 MODINFO_METADATA | MODINFOMD_SMAP);
1916 if (smapbase == NULL && efihdrbase == NULL)
1917 panic("No BIOS smap or EFI map info from loader!");
1918
1919 if (efihdrbase == NULL)
1920 add_smap_entries(&physmap_idx);
1921 else
1922 add_efi_map_entries(&physmap_idx);
1923
1924 base_memory = physmap[1] / 1024;
1925 /* make hole for AP bootstrap code */
1926 physmap[1] = mp_bootaddress(base_memory);
1927
1928 /* Save EBDA address, if any */
1929 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1930 ebda_addr <<= 4;
1931
1932 /*
1933 * Maxmem isn't the "maximum memory", it's one larger than the
1934 * highest page of the physical address space. It should be
1935 * called something like "Maxphyspage". We may adjust this
1936 * based on ``hw.physmem'' and the results of the memory test.
1937 */
1938 Maxmem = atop(physmap[physmap_idx + 1]);
1939
1940 #ifdef MAXMEM
1941 Maxmem = MAXMEM / 4;
1942 #endif
1943
1944 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1945 Maxmem = atop(physmem_tunable);
1946
1947 /*
1948 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1949 * in the system.
1950 */
1951 if (Maxmem > atop(physmap[physmap_idx + 1]))
1952 Maxmem = atop(physmap[physmap_idx + 1]);
1953
1954 /*
1955 * Blowing out the DMAP will blow up the system.
1956 */
1957 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1958 kprintf("Limiting Maxmem due to DMAP size\n");
1959 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1960 }
1961
1962 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1963 (boothowto & RB_VERBOSE)) {
1964 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1965 }
1966
1967 /*
1968 * Call pmap initialization to make new kernel address space
1969 *
1970 * Mask off page 0.
1971 */
1972 pmap_bootstrap(&first);
1973 physmap[0] = PAGE_SIZE;
1974
1975 /*
1976 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1977 * exceeding Maxmem.
1978 */
1979 for (i = j = 0; i <= physmap_idx; i += 2) {
1980 if (physmap[i+1] > ptoa(Maxmem))
1981 physmap[i+1] = ptoa(Maxmem);
1982 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1983 ~PHYSMAP_ALIGN_MASK;
1984 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1985
1986 physmap[j] = physmap[i];
1987 physmap[j+1] = physmap[i+1];
1988
1989 if (physmap[i] < physmap[i+1])
1990 j += 2;
1991 }
1992 physmap_idx = j - 2;
1993
1994 /*
1995 * Align anything else used in the validation loop.
1996 */
1997 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1998
1999 /*
2000 * Size up each available chunk of physical memory.
2001 */
2002 pa_indx = 0;
2003 da_indx = 0;
2004 phys_avail[pa_indx].phys_beg = physmap[0];
2005 phys_avail[pa_indx].phys_end = physmap[0];
2006 dump_avail[da_indx].phys_beg = 0;
2007 dump_avail[da_indx].phys_end = physmap[0];
2008 pte = CMAP1;
2009
2010 /*
2011 * Get dcons buffer address
2012 */
2013 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
2014 kgetenv_quad("dcons.size", &dcons_size) == 0)
2015 dcons_addr = 0;
2016
2017 /*
2018 * Validate the physical memory. The physical memory segments
2019 * have already been aligned to PHYSMAP_ALIGN which is a multiple
2020 * of PAGE_SIZE.
2021 */
2022 for (i = 0; i <= physmap_idx; i += 2) {
2023 vm_paddr_t end;
2024 vm_paddr_t incr = PHYSMAP_ALIGN;
2025
2026 end = physmap[i + 1];
2027
2028 for (pa = physmap[i]; pa < end; pa += incr) {
2029 int page_bad, full;
2030 volatile uint64_t *ptr = (uint64_t *)CADDR1;
2031 uint64_t tmp;
2032
2033 incr = PHYSMAP_ALIGN;
2034 full = FALSE;
2035
2036 /*
2037 * block out kernel memory as not available.
2038 */
2039 if (pa >= 0x200000 && pa < first)
2040 goto do_dump_avail;
2041
2042 /*
2043 * block out dcons buffer
2044 */
2045 if (dcons_addr > 0
2046 && pa >= trunc_page(dcons_addr)
2047 && pa < dcons_addr + dcons_size) {
2048 goto do_dump_avail;
2049 }
2050
2051 page_bad = FALSE;
2052
2053 /*
2054 * Always test the first and last block supplied in
2055 * the map entry, but it just takes too long to run
2056 * the test these days and we already have to skip
2057 * pages. Handwave it on PHYSMAP_HANDWAVE boundaries.
2058 */
2059 if (pa != physmap[i]) {
2060 vm_paddr_t bytes = end - pa;
2061 if ((pa & PHYSMAP_HANDWAVE_MASK) == 0 &&
2062 bytes >= PHYSMAP_HANDWAVE + PHYSMAP_ALIGN) {
2063 incr = PHYSMAP_HANDWAVE;
2064 goto handwaved;
2065 }
2066 }
2067
2068 /*
2069 * map page into kernel: valid, read/write,non-cacheable
2070 */
2071 *pte = pa |
2072 kernel_pmap.pmap_bits[PG_V_IDX] |
2073 kernel_pmap.pmap_bits[PG_RW_IDX] |
2074 kernel_pmap.pmap_bits[PG_N_IDX];
2075 cpu_invlpg(__DEVOLATILE(void *, ptr));
2076 cpu_mfence();
2077
2078 tmp = *ptr;
2079 /*
2080 * Test for alternating 1's and 0's
2081 */
2082 *ptr = 0xaaaaaaaaaaaaaaaaLLU;
2083 cpu_mfence();
2084 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU)
2085 page_bad = TRUE;
2086 /*
2087 * Test for alternating 0's and 1's
2088 */
2089 *ptr = 0x5555555555555555LLU;
2090 cpu_mfence();
2091 if (*ptr != 0x5555555555555555LLU)
2092 page_bad = TRUE;
2093 /*
2094 * Test for all 1's
2095 */
2096 *ptr = 0xffffffffffffffffLLU;
2097 cpu_mfence();
2098 if (*ptr != 0xffffffffffffffffLLU)
2099 page_bad = TRUE;
2100 /*
2101 * Test for all 0's
2102 */
2103 *ptr = 0x0;
2104 cpu_mfence();
2105 if (*ptr != 0x0)
2106 page_bad = TRUE;
2107 /*
2108 * Restore original value.
2109 */
2110 *ptr = tmp;
2111 handwaved:
2112
2113 /*
2114 * Adjust array of valid/good pages.
2115 */
2116 if (page_bad == TRUE)
2117 continue;
2118
2119 /*
2120 * If this good page is a continuation of the
2121 * previous set of good pages, then just increase
2122 * the end pointer. Otherwise start a new chunk.
2123 * Note that "end" points one higher than end,
2124 * making the range >= start and < end.
2125 * If we're also doing a speculative memory
2126 * test and we at or past the end, bump up Maxmem
2127 * so that we keep going. The first bad page
2128 * will terminate the loop.
2129 */
2130 if (phys_avail[pa_indx].phys_end == pa) {
2131 phys_avail[pa_indx].phys_end += incr;
2132 } else {
2133 ++pa_indx;
2134 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
2135 kprintf(
2136 "Too many holes in the physical address space, giving up\n");
2137 --pa_indx;
2138 full = TRUE;
2139 goto do_dump_avail;
2140 }
2141 phys_avail[pa_indx].phys_beg = pa;
2142 phys_avail[pa_indx].phys_end = pa + incr;
2143 }
2144 physmem += incr / PAGE_SIZE;
2145 do_dump_avail:
2146 if (dump_avail[da_indx].phys_end == pa) {
2147 dump_avail[da_indx].phys_end += incr;
2148 } else {
2149 ++da_indx;
2150 if (da_indx == DUMP_AVAIL_ARRAY_END) {
2151 --da_indx;
2152 goto do_next;
2153 }
2154 dump_avail[da_indx].phys_beg = pa;
2155 dump_avail[da_indx].phys_end = pa + incr;
2156 }
2157 do_next:
2158 if (full)
2159 break;
2160 }
2161 }
2162 *pte = 0;
2163 cpu_invltlb();
2164 cpu_mfence();
2165
2166 /*
2167 * The last chunk must contain at least one page plus the message
2168 * buffer to avoid complicating other code (message buffer address
2169 * calculation, etc.).
2170 */
2171 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
2172
2173 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >=
2174 phys_avail[pa_indx].phys_end) {
2175 physmem -= atop(phys_avail[pa_indx].phys_end -
2176 phys_avail[pa_indx].phys_beg);
2177 phys_avail[pa_indx].phys_beg = 0;
2178 phys_avail[pa_indx].phys_end = 0;
2179 --pa_indx;
2180 }
2181
2182 Maxmem = atop(phys_avail[pa_indx].phys_end);
2183
2184 /* Trim off space for the message buffer. */
2185 phys_avail[pa_indx].phys_end -= msgbuf_size;
2186
2187 avail_end = phys_avail[pa_indx].phys_end;
2188
2189 /* Map the message buffer. */
2190 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
2191 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2192 }
2193 /* Try to get EFI framebuffer working as early as possible */
2194 if (have_efi_framebuffer)
2195 efi_fb_init_vaddr(1);
2196 }
2197
2198 struct machintr_abi MachIntrABI;
2199
2200 /*
2201 * IDT VECTORS:
2202 * 0 Divide by zero
2203 * 1 Debug
2204 * 2 NMI
2205 * 3 BreakPoint
2206 * 4 OverFlow
2207 * 5 Bound-Range
2208 * 6 Invalid OpCode
2209 * 7 Device Not Available (x87)
2210 * 8 Double-Fault
2211 * 9 Coprocessor Segment overrun (unsupported, reserved)
2212 * 10 Invalid-TSS
2213 * 11 Segment not present
2214 * 12 Stack
2215 * 13 General Protection
2216 * 14 Page Fault
2217 * 15 Reserved
2218 * 16 x87 FP Exception pending
2219 * 17 Alignment Check
2220 * 18 Machine Check
2221 * 19 SIMD floating point
2222 * 20-31 reserved
2223 * 32-255 INTn/external sources
2224 */
2225 u_int64_t
2226 hammer_time(u_int64_t modulep, u_int64_t physfree)
2227 {
2228 caddr_t kmdp;
2229 int gsel_tss, x, cpu;
2230 #if 0 /* JG */
2231 int metadata_missing, off;
2232 #endif
2233 struct mdglobaldata *gd;
2234 u_int64_t msr;
2235
2236 /*
2237 * Prevent lowering of the ipl if we call tsleep() early.
2238 */
2239 gd = &CPU_prvspace[0]->mdglobaldata;
2240 bzero(gd, sizeof(*gd));
2241
2242 /*
2243 * Note: on both UP and SMP curthread must be set non-NULL
2244 * early in the boot sequence because the system assumes
2245 * that 'curthread' is never NULL.
2246 */
2247
2248 gd->mi.gd_curthread = &thread0;
2249 thread0.td_gd = &gd->mi;
2250
2251 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
2252
2253 #if 0 /* JG */
2254 metadata_missing = 0;
2255 if (bootinfo.bi_modulep) {
2256 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
2257 preload_bootstrap_relocate(KERNBASE);
2258 } else {
2259 metadata_missing = 1;
2260 }
2261 if (bootinfo.bi_envp)
2262 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
2263 #endif
2264
2265 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
2266 preload_bootstrap_relocate(PTOV_OFFSET);
2267 kmdp = preload_search_by_type("elf kernel");
2268 if (kmdp == NULL)
2269 kmdp = preload_search_by_type("elf64 kernel");
2270 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
2271 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
2272 #ifdef DDB
2273 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
2274 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
2275 #endif
2276 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t);
2277
2278 if (boothowto & RB_VERBOSE)
2279 bootverbose++;
2280
2281 /*
2282 * Default MachIntrABI to ICU
2283 */
2284 MachIntrABI = MachIntrABI_ICU;
2285
2286 /*
2287 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
2288 * and ncpus_fit_mask remain 0.
2289 */
2290 ncpus = 1;
2291 ncpus2 = 1;
2292 ncpus_fit = 1;
2293 /* Init basic tunables, hz etc */
2294 init_param1();
2295
2296 /*
2297 * make gdt memory segments
2298 */
2299 gdt_segs[GPROC0_SEL].ssd_base =
2300 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss;
2301
2302 gd->mi.gd_prvspace = CPU_prvspace[0];
2303
2304 for (x = 0; x < NGDT; x++) {
2305 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
2306 ssdtosd(&gdt_segs[x], &gdt[x]);
2307 }
2308 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2309 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
2310
2311 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2312 r_gdt.rd_base = (long) gdt;
2313 lgdt(&r_gdt);
2314
2315 wrmsr(MSR_FSBASE, 0); /* User value */
2316 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
2317 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
2318
2319 mi_gdinit(&gd->mi, 0);
2320 cpu_gdinit(gd, 0);
2321 proc0paddr = proc0paddr_buff;
2322 mi_proc0init(&gd->mi, proc0paddr);
2323 safepri = TDPRI_MAX;
2324
2325 /* spinlocks and the BGL */
2326 init_locks();
2327
2328 /* exceptions */
2329 for (x = 0; x < NIDT; x++)
2330 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2331 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2332 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2333 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2334 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2335 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2336 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2337 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2338 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2339 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2340 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2341 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2342 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2343 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2344 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2345 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2346 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2347 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2348 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2349 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2350
2351 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2352 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2353 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2354 }
2355
2356 lidt(&r_idt_arr[0]);
2357
2358 /*
2359 * Initialize the console before we print anything out.
2360 */
2361 cninit();
2362
2363 #if 0 /* JG */
2364 if (metadata_missing)
2365 kprintf("WARNING: loader(8) metadata is missing!\n");
2366 #endif
2367
2368 #if NISA >0
2369 elcr_probe();
2370 isa_defaultirq();
2371 #endif
2372 rand_initialize();
2373
2374 /*
2375 * Initialize IRQ mapping
2376 *
2377 * NOTE:
2378 * SHOULD be after elcr_probe()
2379 */
2380 MachIntrABI_ICU.initmap();
2381 MachIntrABI_IOAPIC.initmap();
2382
2383 #ifdef DDB
2384 kdb_init();
2385 if (boothowto & RB_KDB)
2386 Debugger("Boot flags requested debugger");
2387 #endif
2388
2389 #if 0 /* JG */
2390 finishidentcpu(); /* Final stage of CPU initialization */
2391 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2392 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2393 #endif
2394 identify_cpu(); /* Final stage of CPU initialization */
2395 initializecpu(0); /* Initialize CPU registers */
2396
2397 /*
2398 * On modern intel cpus, haswell or later, cpu_idle_hlt=1 is better
2399 * because the cpu does significant power management in MWAIT
2400 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP).
2401 *
2402 * On modern amd cpus cpu_idle_hlt=3 is better, because the cpu does
2403 * significant power management in HLT or ACPI (but cpu_idle_hlt=1
2404 * would try to use MWAIT).
2405 *
2406 * On older amd or intel cpus, cpu_idle_hlt=2 is better because ACPI
2407 * is needed to reduce power consumption, but wakeup times are often
2408 * longer.
2409 */
2410 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
2411 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */
2412 cpu_idle_hlt = 1;
2413 }
2414 if (cpu_vendor_id == CPU_VENDOR_AMD &&
2415 CPUID_TO_FAMILY(cpu_id) >= 0x14) { /* Bobcat or later */
2416 cpu_idle_hlt = 3;
2417 }
2418
2419 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2420 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2421 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2422 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt);
2423
2424 /*
2425 * Some of the virtual machines do not work w/ I/O APIC
2426 * enabled. If the user does not explicitly enable or
2427 * disable the I/O APIC (ioapic_enable < 0), then we
2428 * disable I/O APIC on all virtual machines.
2429 *
2430 * NOTE:
2431 * This must be done after identify_cpu(), which sets
2432 * 'cpu_feature2'
2433 */
2434 if (ioapic_enable < 0) {
2435 if (cpu_feature2 & CPUID2_VMM)
2436 ioapic_enable = 0;
2437 else
2438 ioapic_enable = 1;
2439 }
2440
2441 /* make an initial tss so cpu can get interrupt stack on syscall! */
2442 gd->gd_common_tss.tss_rsp0 =
2443 (register_t)(thread0.td_kstack +
2444 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2445 /* Ensure the stack is aligned to 16 bytes */
2446 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2447
2448 /* double fault stack */
2449 gd->gd_common_tss.tss_ist1 =
2450 (long)&gd->mi.gd_prvspace->idlestack[
2451 sizeof(gd->mi.gd_prvspace->idlestack)];
2452
2453 /* Set the IO permission bitmap (empty due to tss seg limit) */
2454 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2455
2456 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2457 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2458 gd->gd_common_tssd = *gd->gd_tss_gdt;
2459 ltr(gsel_tss);
2460
2461 /* Set up the fast syscall stuff */
2462 msr = rdmsr(MSR_EFER) | EFER_SCE;
2463 wrmsr(MSR_EFER, msr);
2464 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2465 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2466 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2467 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2468 wrmsr(MSR_STAR, msr);
2469 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2470
2471 getmemsize(kmdp, physfree);
2472 init_param2(physmem);
2473
2474 /* now running on new page tables, configured,and u/iom is accessible */
2475
2476 /* Map the message buffer. */
2477 #if 0 /* JG */
2478 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2479 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2480 #endif
2481
2482 msgbufinit(msgbufp, MSGBUF_SIZE);
2483
2484
2485 /* transfer to user mode */
2486
2487 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2488 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2489 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2490
2491 load_ds(_udatasel);
2492 load_es(_udatasel);
2493 load_fs(_udatasel);
2494
2495 /* setup proc 0's pcb */
2496 thread0.td_pcb->pcb_flags = 0;
2497 thread0.td_pcb->pcb_cr3 = KPML4phys;
2498 thread0.td_pcb->pcb_ext = NULL;
2499 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2500
2501 /* Location of kernel stack for locore */
2502 return ((u_int64_t)thread0.td_pcb);
2503 }
2504
2505 /*
2506 * Initialize machine-dependant portions of the global data structure.
2507 * Note that the global data area and cpu0's idlestack in the private
2508 * data space were allocated in locore.
2509 *
2510 * Note: the idlethread's cpl is 0
2511 *
2512 * WARNING! Called from early boot, 'mycpu' may not work yet.
2513 */
2514 void
2515 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2516 {
2517 if (cpu)
2518 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2519
2520 lwkt_init_thread(&gd->mi.gd_idlethread,
2521 gd->mi.gd_prvspace->idlestack,
2522 sizeof(gd->mi.gd_prvspace->idlestack),
2523 0, &gd->mi);
2524 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2525 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2526 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2527 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2528 }
2529
2530 /*
2531 * We only have to check for DMAP bounds, the globaldata space is
2532 * actually part of the kernel_map so we don't have to waste time
2533 * checking CPU_prvspace[*].
2534 */
2535 int
2536 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2537 {
2538 #if 0
2539 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2540 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2541 return (TRUE);
2542 }
2543 #endif
2544 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2545 return (TRUE);
2546 return (FALSE);
2547 }
2548
2549 struct globaldata *
2550 globaldata_find(int cpu)
2551 {
2552 KKASSERT(cpu >= 0 && cpu < ncpus);
2553 return(&CPU_prvspace[cpu]->mdglobaldata.mi);
2554 }
2555
2556 /*
2557 * This path should be safe from the SYSRET issue because only stopped threads
2558 * can have their %rip adjusted this way (and all heavy weight thread switches
2559 * clear QUICKREF and thus do not use SYSRET). However, the code path is
2560 * convoluted so add a safety by forcing %rip to be cannonical.
2561 */
2562 int
2563 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2564 {
2565 if (addr & 0x0000800000000000LLU)
2566 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU;
2567 else
2568 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU;
2569 return (0);
2570 }
2571
2572 int
2573 ptrace_single_step(struct lwp *lp)
2574 {
2575 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2576 return (0);
2577 }
2578
2579 int
2580 fill_regs(struct lwp *lp, struct reg *regs)
2581 {
2582 struct trapframe *tp;
2583
2584 if ((tp = lp->lwp_md.md_regs) == NULL)
2585 return EINVAL;
2586 bcopy(&tp->tf_rdi, &regs->r_rdi, sizeof(*regs));
2587 return (0);
2588 }
2589
2590 int
2591 set_regs(struct lwp *lp, struct reg *regs)
2592 {
2593 struct trapframe *tp;
2594
2595 tp = lp->lwp_md.md_regs;
2596 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2597 !CS_SECURE(regs->r_cs))
2598 return (EINVAL);
2599 bcopy(&regs->r_rdi, &tp->tf_rdi, sizeof(*regs));
2600 clear_quickret();
2601 return (0);
2602 }
2603
2604 static void
2605 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2606 {
2607 struct env87 *penv_87 = &sv_87->sv_env;
2608 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2609 int i;
2610
2611 /* FPU control/status */
2612 penv_87->en_cw = penv_xmm->en_cw;
2613 penv_87->en_sw = penv_xmm->en_sw;
2614 penv_87->en_tw = penv_xmm->en_tw;
2615 penv_87->en_fip = penv_xmm->en_fip;
2616 penv_87->en_fcs = penv_xmm->en_fcs;
2617 penv_87->en_opcode = penv_xmm->en_opcode;
2618 penv_87->en_foo = penv_xmm->en_foo;
2619 penv_87->en_fos = penv_xmm->en_fos;
2620
2621 /* FPU registers */
2622 for (i = 0; i < 8; ++i)
2623 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2624 }
2625
2626 static void
2627 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2628 {
2629 struct env87 *penv_87 = &sv_87->sv_env;
2630 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2631 int i;
2632
2633 /* FPU control/status */
2634 penv_xmm->en_cw = penv_87->en_cw;
2635 penv_xmm->en_sw = penv_87->en_sw;
2636 penv_xmm->en_tw = penv_87->en_tw;
2637 penv_xmm->en_fip = penv_87->en_fip;
2638 penv_xmm->en_fcs = penv_87->en_fcs;
2639 penv_xmm->en_opcode = penv_87->en_opcode;
2640 penv_xmm->en_foo = penv_87->en_foo;
2641 penv_xmm->en_fos = penv_87->en_fos;
2642
2643 /* FPU registers */
2644 for (i = 0; i < 8; ++i)
2645 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2646 }
2647
2648 int
2649 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2650 {
2651 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2652 return EINVAL;
2653 if (cpu_fxsr) {
2654 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2655 (struct save87 *)fpregs);
2656 return (0);
2657 }
2658 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2659 return (0);
2660 }
2661
2662 int
2663 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2664 {
2665 if (cpu_fxsr) {
2666 set_fpregs_xmm((struct save87 *)fpregs,
2667 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2668 return (0);
2669 }
2670 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2671 return (0);
2672 }
2673
2674 int
2675 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2676 {
2677 struct pcb *pcb;
2678
2679 if (lp == NULL) {
2680 dbregs->dr[0] = rdr0();
2681 dbregs->dr[1] = rdr1();
2682 dbregs->dr[2] = rdr2();
2683 dbregs->dr[3] = rdr3();
2684 dbregs->dr[4] = rdr4();
2685 dbregs->dr[5] = rdr5();
2686 dbregs->dr[6] = rdr6();
2687 dbregs->dr[7] = rdr7();
2688 return (0);
2689 }
2690 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2691 return EINVAL;
2692 dbregs->dr[0] = pcb->pcb_dr0;
2693 dbregs->dr[1] = pcb->pcb_dr1;
2694 dbregs->dr[2] = pcb->pcb_dr2;
2695 dbregs->dr[3] = pcb->pcb_dr3;
2696 dbregs->dr[4] = 0;
2697 dbregs->dr[5] = 0;
2698 dbregs->dr[6] = pcb->pcb_dr6;
2699 dbregs->dr[7] = pcb->pcb_dr7;
2700 return (0);
2701 }
2702
2703 int
2704 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2705 {
2706 if (lp == NULL) {
2707 load_dr0(dbregs->dr[0]);
2708 load_dr1(dbregs->dr[1]);
2709 load_dr2(dbregs->dr[2]);
2710 load_dr3(dbregs->dr[3]);
2711 load_dr4(dbregs->dr[4]);
2712 load_dr5(dbregs->dr[5]);
2713 load_dr6(dbregs->dr[6]);
2714 load_dr7(dbregs->dr[7]);
2715 } else {
2716 struct pcb *pcb;
2717 struct ucred *ucred;
2718 int i;
2719 uint64_t mask1, mask2;
2720
2721 /*
2722 * Don't let an illegal value for dr7 get set. Specifically,
2723 * check for undefined settings. Setting these bit patterns
2724 * result in undefined behaviour and can lead to an unexpected
2725 * TRCTRAP.
2726 */
2727 /* JG this loop looks unreadable */
2728 /* Check 4 2-bit fields for invalid patterns.
2729 * These fields are R/Wi, for i = 0..3
2730 */
2731 /* Is 10 in LENi allowed when running in compatibility mode? */
2732 /* Pattern 10 in R/Wi might be used to indicate
2733 * breakpoint on I/O. Further analysis should be
2734 * carried to decide if it is safe and useful to
2735 * provide access to that capability
2736 */
2737 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2738 i++, mask1 <<= 4, mask2 <<= 4)
2739 if ((dbregs->dr[7] & mask1) == mask2)
2740 return (EINVAL);
2741
2742 pcb = lp->lwp_thread->td_pcb;
2743 ucred = lp->lwp_proc->p_ucred;
2744
2745 /*
2746 * Don't let a process set a breakpoint that is not within the
2747 * process's address space. If a process could do this, it
2748 * could halt the system by setting a breakpoint in the kernel
2749 * (if ddb was enabled). Thus, we need to check to make sure
2750 * that no breakpoints are being enabled for addresses outside
2751 * process's address space, unless, perhaps, we were called by
2752 * uid 0.
2753 *
2754 * XXX - what about when the watched area of the user's
2755 * address space is written into from within the kernel
2756 * ... wouldn't that still cause a breakpoint to be generated
2757 * from within kernel mode?
2758 */
2759
2760 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2761 if (dbregs->dr[7] & 0x3) {
2762 /* dr0 is enabled */
2763 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2764 return (EINVAL);
2765 }
2766
2767 if (dbregs->dr[7] & (0x3<<2)) {
2768 /* dr1 is enabled */
2769 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2770 return (EINVAL);
2771 }
2772
2773 if (dbregs->dr[7] & (0x3<<4)) {
2774 /* dr2 is enabled */
2775 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2776 return (EINVAL);
2777 }
2778
2779 if (dbregs->dr[7] & (0x3<<6)) {
2780 /* dr3 is enabled */
2781 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2782 return (EINVAL);
2783 }
2784 }
2785
2786 pcb->pcb_dr0 = dbregs->dr[0];
2787 pcb->pcb_dr1 = dbregs->dr[1];
2788 pcb->pcb_dr2 = dbregs->dr[2];
2789 pcb->pcb_dr3 = dbregs->dr[3];
2790 pcb->pcb_dr6 = dbregs->dr[6];
2791 pcb->pcb_dr7 = dbregs->dr[7];
2792
2793 pcb->pcb_flags |= PCB_DBREGS;
2794 }
2795
2796 return (0);
2797 }
2798
2799 /*
2800 * Return > 0 if a hardware breakpoint has been hit, and the
2801 * breakpoint was in user space. Return 0, otherwise.
2802 */
2803 int
2804 user_dbreg_trap(void)
2805 {
2806 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2807 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2808 int nbp; /* number of breakpoints that triggered */
2809 caddr_t addr[4]; /* breakpoint addresses */
2810 int i;
2811
2812 dr7 = rdr7();
2813 if ((dr7 & 0xff) == 0) {
2814 /*
2815 * all GE and LE bits in the dr7 register are zero,
2816 * thus the trap couldn't have been caused by the
2817 * hardware debug registers
2818 */
2819 return 0;
2820 }
2821
2822 nbp = 0;
2823 dr6 = rdr6();
2824 bp = dr6 & 0xf;
2825
2826 if (bp == 0) {
2827 /*
2828 * None of the breakpoint bits are set meaning this
2829 * trap was not caused by any of the debug registers
2830 */
2831 return 0;
2832 }
2833
2834 /*
2835 * at least one of the breakpoints were hit, check to see
2836 * which ones and if any of them are user space addresses
2837 */
2838
2839 if (bp & 0x01) {
2840 addr[nbp++] = (caddr_t)rdr0();
2841 }
2842 if (bp & 0x02) {
2843 addr[nbp++] = (caddr_t)rdr1();
2844 }
2845 if (bp & 0x04) {
2846 addr[nbp++] = (caddr_t)rdr2();
2847 }
2848 if (bp & 0x08) {
2849 addr[nbp++] = (caddr_t)rdr3();
2850 }
2851
2852 for (i=0; i<nbp; i++) {
2853 if (addr[i] <
2854 (caddr_t)VM_MAX_USER_ADDRESS) {
2855 /*
2856 * addr[i] is in user space
2857 */
2858 return nbp;
2859 }
2860 }
2861
2862 /*
2863 * None of the breakpoints are in user space.
2864 */
2865 return 0;
2866 }
2867
2868
2869 #ifndef DDB
2870 void
2871 Debugger(const char *msg)
2872 {
2873 kprintf("Debugger(\"%s\") called.\n", msg);
2874 }
2875 #endif /* no DDB */
2876
2877 #ifdef DDB
2878
2879 /*
2880 * Provide inb() and outb() as functions. They are normally only
2881 * available as macros calling inlined functions, thus cannot be
2882 * called inside DDB.
2883 *
2884 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2885 */
2886
2887 #undef inb
2888 #undef outb
2889
2890 /* silence compiler warnings */
2891 u_char inb(u_int);
2892 void outb(u_int, u_char);
2893
2894 u_char
2895 inb(u_int port)
2896 {
2897 u_char data;
2898 /*
2899 * We use %%dx and not %1 here because i/o is done at %dx and not at
2900 * %edx, while gcc generates inferior code (movw instead of movl)
2901 * if we tell it to load (u_short) port.
2902 */
2903 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2904 return (data);
2905 }
2906
2907 void
2908 outb(u_int port, u_char data)
2909 {
2910 u_char al;
2911 /*
2912 * Use an unnecessary assignment to help gcc's register allocator.
2913 * This make a large difference for gcc-1.40 and a tiny difference
2914 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2915 * best results. gcc-2.6.0 can't handle this.
2916 */
2917 al = data;
2918 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2919 }
2920
2921 #endif /* DDB */
2922
2923
2924
2925 /*
2926 * initialize all the SMP locks
2927 */
2928
2929 /* critical region when masking or unmasking interupts */
2930 struct spinlock_deprecated imen_spinlock;
2931
2932 /* lock region used by kernel profiling */
2933 struct spinlock_deprecated mcount_spinlock;
2934
2935 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2936 struct spinlock_deprecated com_spinlock;
2937
2938 /* lock regions around the clock hardware */
2939 struct spinlock_deprecated clock_spinlock;
2940
2941 static void
2942 init_locks(void)
2943 {
2944 /*
2945 * Get the initial mplock with a count of 1 for the BSP.
2946 * This uses a LOGICAL cpu ID, ie BSP == 0.
2947 */
2948 cpu_get_initial_mplock();
2949 /* DEPRECATED */
2950 spin_init_deprecated(&mcount_spinlock);
2951 spin_init_deprecated(&imen_spinlock);
2952 spin_init_deprecated(&com_spinlock);
2953 spin_init_deprecated(&clock_spinlock);
2954
2955 /* our token pool needs to work early */
2956 lwkt_token_pool_init();
2957 }
2958
2959 boolean_t
2960 cpu_mwait_hint_valid(uint32_t hint)
2961 {
2962 int cx_idx, sub;
2963
2964 cx_idx = MWAIT_EAX_TO_CX(hint);
2965 if (cx_idx >= CPU_MWAIT_CX_MAX)
2966 return FALSE;
2967
2968 sub = MWAIT_EAX_TO_CX_SUB(hint);
2969 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2970 return FALSE;
2971
2972 return TRUE;
2973 }
2974
2975 void
2976 cpu_mwait_cx_no_bmsts(void)
2977 {
2978 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2979 }
2980
2981 void
2982 cpu_mwait_cx_no_bmarb(void)
2983 {
2984 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB);
2985 }
2986
2987 static int
2988 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto)
2989 {
2990 int old_cx_idx, sub = 0;
2991
2992 if (hint >= 0) {
2993 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2994 sub = MWAIT_EAX_TO_CX_SUB(hint);
2995 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2996 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2997 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2998 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2999 } else {
3000 old_cx_idx = CPU_MWAIT_CX_MAX;
3001 }
3002
3003 if (!CPU_MWAIT_HAS_CX)
3004 strlcpy(name, "NONE", namelen);
3005 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
3006 strlcpy(name, "AUTO", namelen);
3007 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
3008 strlcpy(name, "AUTODEEP", namelen);
3009 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
3010 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
3011 strlcpy(name, "INVALID", namelen);
3012 else
3013 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub);
3014
3015 return old_cx_idx;
3016 }
3017
3018 static int
3019 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto)
3020 {
3021 int cx_idx, sub, hint;
3022 char *ptr, *start;
3023
3024 if (allow_auto && strcmp(name, "AUTO") == 0) {
3025 hint = CPU_MWAIT_HINT_AUTO;
3026 cx_idx = CPU_MWAIT_C2;
3027 goto done;
3028 }
3029 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
3030 hint = CPU_MWAIT_HINT_AUTODEEP;
3031 cx_idx = CPU_MWAIT_C3;
3032 goto done;
3033 }
3034
3035 if (strlen(name) < 4 || toupper(name[0]) != 'C')
3036 return -1;
3037 start = &name[1];
3038 ptr = NULL;
3039
3040 cx_idx = strtol(start, &ptr, 10);
3041 if (ptr == start || *ptr != '/')
3042 return -1;
3043 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
3044 return -1;
3045
3046 start = ptr + 1;
3047 ptr = NULL;
3048
3049 sub = strtol(start, &ptr, 10);
3050 if (*ptr != '\0')
3051 return -1;
3052 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
3053 return -1;
3054
3055 hint = MWAIT_EAX_HINT(cx_idx, sub);
3056 done:
3057 *hint0 = hint;
3058 return cx_idx;
3059 }
3060
3061 static int
3062 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx)
3063 {
3064 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
3065 return EOPNOTSUPP;
3066 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
3067 int error;
3068
3069 error = cputimer_intr_powersave_addreq();
3070 if (error)
3071 return error;
3072 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
3073 cputimer_intr_powersave_remreq();
3074 }
3075 return 0;
3076 }
3077
3078 static int
3079 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
3080 boolean_t allow_auto)
3081 {
3082 int error, cx_idx, old_cx_idx, hint;
3083 char name[CPU_MWAIT_CX_NAMELEN];
3084
3085 hint = *hint0;
3086 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name),
3087 allow_auto);
3088
3089 error = sysctl_handle_string(oidp, name, sizeof(name), req);
3090 if (error != 0 || req->newptr == NULL)
3091 return error;
3092
3093 if (!CPU_MWAIT_HAS_CX)
3094 return EOPNOTSUPP;
3095
3096 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto);
3097 if (cx_idx < 0)
3098 return EINVAL;
3099
3100 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
3101 if (error)
3102 return error;
3103
3104 *hint0 = hint;
3105 return 0;
3106 }
3107
3108 static int
3109 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name)
3110 {
3111 int error, cx_idx, old_cx_idx, hint;
3112 char name[CPU_MWAIT_CX_NAMELEN];
3113
3114 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension"));
3115
3116 hint = stat->hint;
3117 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
3118
3119 strlcpy(name, cx_name, sizeof(name));
3120 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
3121 if (cx_idx < 0)
3122 return EINVAL;
3123
3124 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
3125 if (error)
3126 return error;
3127
3128 stat->hint = hint;
3129 return 0;
3130 }
3131
3132 static int
3133 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
3134 {
3135 int hint = cpu_mwait_halt_global;
3136 int error, cx_idx, cpu;
3137 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN];
3138
3139 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
3140
3141 error = sysctl_handle_string(oidp, name, sizeof(name), req);
3142 if (error != 0 || req->newptr == NULL)
3143 return error;
3144
3145 if (!CPU_MWAIT_HAS_CX)
3146 return EOPNOTSUPP;
3147
3148 /* Save name for later per-cpu CX configuration */
3149 strlcpy(cx_name, name, sizeof(cx_name));
3150
3151 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
3152 if (cx_idx < 0)
3153 return EINVAL;
3154
3155 /* Change per-cpu CX configuration */
3156 for (cpu = 0; cpu < ncpus; ++cpu) {
3157 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name);
3158 if (error)
3159 return error;
3160 }
3161
3162 cpu_mwait_halt_global = hint;
3163 return 0;
3164 }
3165
3166 static int
3167 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
3168 {
3169 struct cpu_idle_stat *stat = arg1;
3170 int error;
3171
3172 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3173 &stat->hint, TRUE);
3174 return error;
3175 }
3176
3177 static int
3178 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
3179 {
3180 int error;
3181
3182 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3183 &cpu_mwait_spin, FALSE);
3184 return error;
3185 }
3186
3187 /*
3188 * This manual debugging code is called unconditionally from Xtimer
3189 * (the per-cpu timer interrupt) whether the current thread is in a
3190 * critical section or not) and can be useful in tracking down lockups.
3191 *
3192 * NOTE: MANUAL DEBUG CODE
3193 */
3194 #if 0
3195 static int saveticks[SMP_MAXCPU];
3196 static int savecounts[SMP_MAXCPU];
3197 #endif
3198
3199 void
3200 pcpu_timer_always(struct intrframe *frame)
3201 {
3202 #if 0
3203 globaldata_t gd = mycpu;
3204 int cpu = gd->gd_cpuid;
3205 char buf[64];
3206 short *gptr;
3207 int i;
3208
3209 if (cpu <= 20) {
3210 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
3211 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
3212 ++gptr;
3213
3214 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
3215 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
3216 gd->gd_infomsg);
3217 for (i = 0; buf[i]; ++i) {
3218 gptr[i] = 0x0700 | (unsigned char)buf[i];
3219 }
3220 }
3221 #if 0
3222 if (saveticks[gd->gd_cpuid] != ticks) {
3223 saveticks[gd->gd_cpuid] = ticks;
3224 savecounts[gd->gd_cpuid] = 0;
3225 }
3226 ++savecounts[gd->gd_cpuid];
3227 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
3228 panic("cpud %d panicing on ticks failure",
3229 gd->gd_cpuid);
3230 }
3231 for (i = 0; i < ncpus; ++i) {
3232 int delta;
3233 if (saveticks[i] && panicstr == NULL) {
3234 delta = saveticks[i] - ticks;
3235 if (delta < -10 || delta > 10) {
3236 panic("cpu %d panicing on cpu %d watchdog",
3237 gd->gd_cpuid, i);
3238 }
3239 }
3240 }
3241 #endif
3242 #endif
3243 }
DragonFly BSD