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sdhci - Handle ADMA error interrupt, similar to ACMD12 error interrupt.
[dragonfly.git] / sys / dev / disk / sdhci / sdhci.c
blob0d92f8600aac25f37803b0f63fc2a5f1542d7d3d
1 /*-
2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/callout.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/module.h>
36 #include <sys/spinlock.h>
37 #include <sys/resource.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41
42 #include <bus/mmc/bridge.h>
43 #include <bus/mmc/mmcreg.h>
44 #include <bus/mmc/mmcbrvar.h>
45
46 #include "mmcbr_if.h"
47 #include "sdhci.h"
48 #include "sdhci_if.h"
49
50 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
51
52 int sdhci_debug = 0;
53 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
54 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
55
56 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
57 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
58 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
59 #define RD_MULTI_4(slot, off, ptr, count) \
60 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
61 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
62 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
63 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
64 #define WR_MULTI_4(slot, off, ptr, count) \
65 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
66
67 static int slot_printf(struct sdhci_slot *, const char *, ...)
68 __printflike(2, 3);
69
70 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
71 static void sdhci_start(struct sdhci_slot *slot);
72 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
73
74 static void sdhci_card_task(void *, int);
75
76 static int sdhci_dma_alloc(struct sdhci_slot *slot);
77 static void sdhci_dmamem_free(bus_dmamem_t *mem);
78 static void sdhci_dma_free(struct sdhci_slot *slot);
79 static void sdhci_adma2_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
80 int error);
81
82 /* helper routines */
83 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE)
84 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE)
85 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE)
86 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock);
87 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0);
88 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0);
89
90 #define SDHCI_DEFAULT_MAX_FREQ 50
91
92 #define SDHCI_200_MAX_DIVIDER 256
93 #define SDHCI_300_MAX_DIVIDER 2046
94
95 /*
96 * Broadcom BCM577xx Controller Constants
97 */
98 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */
99 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */
100
101 #define BCM577XX_HOST_CONTROL 0x198
102 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
103 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
104 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
105 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
106
107 static int
108 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
109 {
110 __va_list ap;
111 int retval;
112
113 retval = kprintf("%s-slot%d: ",
114 device_get_nameunit(slot->bus), slot->num);
115
116 __va_start(ap, fmt);
117 retval += kvprintf(fmt, ap);
118 __va_end(ap);
119 return (retval);
120 }
121
122 static void
123 sdhci_dumpregs(struct sdhci_slot *slot)
124 {
125 slot_printf(slot,
126 "============== REGISTER DUMP ==============\n");
127
128 slot_printf(slot, "SDMA addr: 0x%08x | Version: 0x%08x\n",
129 RD4(slot, SDHCI_SDMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
130 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
131 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
132 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
133 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
134 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
135 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
136 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
137 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
138 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
139 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
140 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
141 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
142 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
143 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
144 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n",
145 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
146 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
147 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
148 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
149 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
150 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n",
151 RD4(slot, SDHCI_ADMA_ADDRESS_LOW), RD2(slot, SDHCI_SLOT_INT_STATUS));
152
153 slot_printf(slot,
154 "===========================================\n");
155 }
156
157 static void
158 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
159 {
160 int timeout;
161
162 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
163 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
164 return;
165 }
166
167 /* Some controllers need this kick or reset won't work. */
168 if ((mask & SDHCI_RESET_ALL) == 0 &&
169 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
170 uint32_t clock;
171
172 /* This is to force an update */
173 clock = slot->clock;
174 slot->clock = 0;
175 sdhci_set_clock(slot, clock);
176 }
177
178 if (mask & SDHCI_RESET_ALL) {
179 slot->clock = 0;
180 slot->power = 0;
181 }
182
183 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
184
185 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
186 /*
187 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
188 * specification. The reset bit has internal propagation delay,
189 * so a fast read after write returns 0 even if reset process is
190 * in progress. The workaround is to poll for 1 before polling
191 * for 0. In the worst case, if we miss seeing it asserted the
192 * time we spent waiting is enough to ensure the reset finishes.
193 */
194 timeout = 10000;
195 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
196 if (timeout <= 0)
197 break;
198 timeout--;
199 DELAY(1);
200 }
201 }
202
203 /* Wait max 100 ms */
204 timeout = 10000;
205 /* Controller clears the bits when it's done */
206 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
207 if (timeout <= 0) {
208 slot_printf(slot, "Reset 0x%x never completed.\n",
209 mask);
210 sdhci_dumpregs(slot);
211 return;
212 }
213 timeout--;
214 DELAY(10);
215 }
216 }
217
218 static void
219 sdhci_init(struct sdhci_slot *slot)
220 {
221
222 sdhci_reset(slot, SDHCI_RESET_ALL);
223
224 /* Enable interrupts. */
225 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
226 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
227 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
228 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
229 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
230 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
231 SDHCI_INT_ACMD12ERR | SDHCI_INT_ADMAERR;
232 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
233 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
234 }
235
236 static void
237 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
238 {
239 uint32_t clk_base;
240 uint32_t clk_sel;
241 uint32_t res;
242 uint16_t clk;
243 uint16_t div;
244 int timeout;
245
246 if (clock == slot->clock)
247 return;
248 slot->clock = clock;
249
250 /* Turn off the clock. */
251 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
252 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
253 /* If no clock requested - left it so. */
254 if (clock == 0)
255 return;
256
257 /* Determine the clock base frequency */
258 clk_base = slot->max_clk;
259 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
260 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK;
261
262 /* Select clock source appropriate for the requested frequency. */
263 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
264 clk_base = BCM577XX_ALT_CLOCK_BASE;
265 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT);
266 } else {
267 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT);
268 }
269
270 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
271 }
272
273 /* Recalculate timeout clock frequency based on the new sd clock. */
274 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
275 slot->timeout_clk = slot->clock / 1000;
276
277 if (slot->version < SDHCI_SPEC_300) {
278 /* Looking for highest freq <= clock. */
279 res = clk_base;
280 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
281 if (res <= clock)
282 break;
283 res >>= 1;
284 }
285 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
286 div >>= 1;
287 }
288 else {
289 /* Version 3.0 divisors are multiples of two up to 1023*2 */
290 if (clock >= clk_base)
291 div = 0;
292 else {
293 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
294 if ((clk_base / div) <= clock)
295 break;
296 }
297 }
298 div >>= 1;
299 }
300
301 if (bootverbose || sdhci_debug)
302 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
303 div, clock, clk_base);
304
305 /* Now we have got divider, set it. */
306 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
307 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
308 << SDHCI_DIVIDER_HI_SHIFT;
309
310 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
311 /* Enable clock. */
312 clk |= SDHCI_CLOCK_INT_EN;
313 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
314 /* Wait up to 10 ms until it stabilize. */
315 timeout = 10;
316 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
317 & SDHCI_CLOCK_INT_STABLE)) {
318 if (timeout == 0) {
319 slot_printf(slot,
320 "Internal clock never stabilised.\n");
321 sdhci_dumpregs(slot);
322 return;
323 }
324 timeout--;
325 DELAY(1000);
326 }
327 /* Pass clock signal to the bus. */
328 clk |= SDHCI_CLOCK_CARD_EN;
329 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
330 }
331
332 static void
333 sdhci_set_power(struct sdhci_slot *slot, u_char power)
334 {
335 uint8_t pwr;
336
337 if (slot->power == power)
338 return;
339
340 slot->power = power;
341
342 /* Turn off the power. */
343 pwr = 0;
344 WR1(slot, SDHCI_POWER_CONTROL, pwr);
345 /* If power down requested - left it so. */
346 if (power == 0)
347 return;
348 /* Set voltage. */
349 switch (1 << power) {
350 case MMC_OCR_LOW_VOLTAGE:
351 pwr |= SDHCI_POWER_180;
352 break;
353 case MMC_OCR_290_300:
354 case MMC_OCR_300_310:
355 pwr |= SDHCI_POWER_300;
356 break;
357 case MMC_OCR_320_330:
358 case MMC_OCR_330_340:
359 pwr |= SDHCI_POWER_330;
360 break;
361 }
362 WR1(slot, SDHCI_POWER_CONTROL, pwr);
363 /* Turn on the power. */
364 pwr |= SDHCI_POWER_ON;
365 WR1(slot, SDHCI_POWER_CONTROL, pwr);
366 }
367
368 static void
369 sdhci_read_block_pio(struct sdhci_slot *slot)
370 {
371 uint32_t data;
372 char *buffer;
373 size_t left;
374
375 buffer = slot->curcmd->data->data;
376 buffer += slot->offset;
377 /* Transfer one block at a time. */
378 left = min(512, slot->curcmd->data->len - slot->offset);
379 slot->offset += left;
380
381 /* If we are too fast, broken controllers return zeroes. */
382 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
383 DELAY(10);
384 /* Handle unaligned and aligned buffer cases. */
385 if ((intptr_t)buffer & 3) {
386 while (left > 3) {
387 data = RD4(slot, SDHCI_BUFFER);
388 buffer[0] = data;
389 buffer[1] = (data >> 8);
390 buffer[2] = (data >> 16);
391 buffer[3] = (data >> 24);
392 buffer += 4;
393 left -= 4;
394 }
395 } else {
396 RD_MULTI_4(slot, SDHCI_BUFFER,
397 (uint32_t *)buffer, left >> 2);
398 left &= 3;
399 }
400 /* Handle uneven size case. */
401 if (left > 0) {
402 data = RD4(slot, SDHCI_BUFFER);
403 while (left > 0) {
404 *(buffer++) = data;
405 data >>= 8;
406 left--;
407 }
408 }
409 }
410
411 static void
412 sdhci_write_block_pio(struct sdhci_slot *slot)
413 {
414 uint32_t data = 0;
415 char *buffer;
416 size_t left;
417
418 buffer = slot->curcmd->data->data;
419 buffer += slot->offset;
420 /* Transfer one block at a time. */
421 left = min(512, slot->curcmd->data->len - slot->offset);
422 slot->offset += left;
423
424 /* Handle unaligned and aligned buffer cases. */
425 if ((intptr_t)buffer & 3) {
426 while (left > 3) {
427 data = buffer[0] +
428 (buffer[1] << 8) +
429 (buffer[2] << 16) +
430 (buffer[3] << 24);
431 left -= 4;
432 buffer += 4;
433 WR4(slot, SDHCI_BUFFER, data);
434 }
435 } else {
436 WR_MULTI_4(slot, SDHCI_BUFFER,
437 (uint32_t *)buffer, left >> 2);
438 left &= 3;
439 }
440 /* Handle uneven size case. */
441 if (left > 0) {
442 while (left > 0) {
443 data <<= 8;
444 data += *(buffer++);
445 left--;
446 }
447 WR4(slot, SDHCI_BUFFER, data);
448 }
449 }
450
451 static void
452 sdhci_transfer_pio(struct sdhci_slot *slot)
453 {
454
455 /* Read as many blocks as possible. */
456 if (slot->curcmd->data->flags & MMC_DATA_READ) {
457 while (RD4(slot, SDHCI_PRESENT_STATE) &
458 SDHCI_DATA_AVAILABLE) {
459 sdhci_read_block_pio(slot);
460 if (slot->offset >= slot->curcmd->data->len)
461 break;
462 }
463 } else {
464 while (RD4(slot, SDHCI_PRESENT_STATE) &
465 SDHCI_SPACE_AVAILABLE) {
466 sdhci_write_block_pio(slot);
467 if (slot->offset >= slot->curcmd->data->len)
468 break;
469 }
470 }
471 }
472
473 static void
474 sdhci_card_delay(void *arg)
475 {
476 struct sdhci_slot *slot = arg;
477
478 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task);
479 }
480
481 static void
482 sdhci_card_task(void *arg, int pending)
483 {
484 struct sdhci_slot *slot = arg;
485
486 SDHCI_LOCK(slot);
487 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
488 if (slot->dev == NULL) {
489 /* If card is present - attach mmc bus. */
490 slot->dev = device_add_child(slot->bus, "mmc", -1);
491 device_set_ivars(slot->dev, slot);
492 SDHCI_UNLOCK(slot);
493 device_probe_and_attach(slot->dev);
494 } else
495 SDHCI_UNLOCK(slot);
496 } else {
497 if (slot->dev != NULL) {
498 /* If no card present - detach mmc bus. */
499 device_t d = slot->dev;
500 slot->dev = NULL;
501 SDHCI_UNLOCK(slot);
502 device_delete_child(slot->bus, d);
503 } else
504 SDHCI_UNLOCK(slot);
505 }
506 }
507
508 static int
509 sdhci_dma_alloc(struct sdhci_slot *slot)
510 {
511 int err;
512
513 /* Allocate DMA memory for SDMA. */
514 err = bus_dmamem_coherent(bus_get_dma_tag(slot->bus),
515 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
516 BUS_SPACE_MAXADDR, DMA_BLOCK_SIZE, BUS_DMA_NOWAIT,
517 &slot->sdma_mem);
518 if (err != 0) {
519 device_printf(slot->bus, "Can't alloc DMA memory for SDMA\n");
520 goto done;
521 }
522
523 /* Allocate DMA memory for 32bit ADMA2 descriptors. */
524 err = bus_dmamem_coherent(bus_get_dma_tag(slot->bus),
525 4, 0, BUS_SPACE_MAXADDR_32BIT,
526 BUS_SPACE_MAXADDR, SDHCI_ADMA2_DESCBUF_SIZE, BUS_DMA_NOWAIT,
527 &slot->adma2_descs);
528 if (err != 0) {
529 device_printf(slot->bus,
530 "Can't alloc DMA memory for ADMA2 descriptors\n");
531 goto error1;
532 }
533
534 /* Allocate DMA tag for 32bit ADMA2 data buffer */
535 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus),
536 4, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
537 MAXPHYS, SDHCI_ADMA2_DESC_COUNT,
538 MIN(MAXPHYS, SDHCI_ADMA2_MAX_SEGSIZE),
539 BUS_DMA_ALLOCNOW | BUS_DMA_ALLOCALL,
540 &slot->adma2_tag);
541 if (err != 0) {
542 device_printf(slot->bus, "Can't create DMA tag for ADMA2\n");
543 goto error2;
544 }
545
546 /* Allocate DMA map for ADMA2 data buffer */
547 err = bus_dmamap_create(slot->adma2_tag, BUS_DMA_NOWAIT,
548 &slot->adma2_map);
549 if (err != 0) {
550 device_printf(slot->bus, "Can't create DMA map for ADMA2\n");
551 goto error3;
552 }
553
554 return (0);
555
556 error3:
557 bus_dma_tag_destroy(slot->adma2_tag);
558 error2:
559 sdhci_dmamem_free(&slot->adma2_descs);
560 error1:
561 sdhci_dmamem_free(&slot->sdma_mem);
562 done:
563 return (err);
564 }
565
566 static void
567 sdhci_dmamem_free(bus_dmamem_t *dma)
568 {
569 bus_dmamap_unload(dma->dmem_tag, dma->dmem_map);
570 bus_dmamem_free(dma->dmem_tag, dma->dmem_addr, dma->dmem_map);
571 bus_dma_tag_destroy(dma->dmem_tag);
572 }
573
574 static void
575 sdhci_dma_free(struct sdhci_slot *slot)
576 {
577 bus_dmamap_destroy(slot->adma2_tag, slot->adma2_map);
578 bus_dma_tag_destroy(slot->adma2_tag);
579 sdhci_dmamem_free(&slot->sdma_mem);
580 sdhci_dmamem_free(&slot->adma2_descs);
581 }
582
583 static void
584 sdhci_adma2_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
585 {
586 struct sdhci_slot *slot = arg;
587 bus_dmamem_t *descmem = &slot->adma2_descs;
588 struct sdhci_adma2_desc32 *descs = (void *)descmem->dmem_addr;
589 int i;
590
591 if (error != 0) {
592 /* This signals, that loading was unsuccessful */
593 memset(&descs[0], 0, sizeof(*descs));
594 return;
595 }
596
597 for (i = 0; i < nsegs; i++) {
598 descs[i].address = segs[i].ds_addr;
599 /*
600 * The 65536 segment length case is broken in some sdhc host
601 * controllers, so we actually use a maximum segment length
602 * of 32768 for the DMA mapping and ds_len should be at most
603 * 32768 here.
604 */
605 if (segs[i].ds_len == 65536)
606 descs[i].length = 0;
607 else
608 descs[i].length = segs[i].ds_len;
609 descs[i].attribute =
610 SDHCI_ADMA2_ATTR_VALID | SDHCI_ADMA2_ATTR_OP_TRAN;
611 }
612 descs[nsegs-1].attribute |= SDHCI_ADMA2_ATTR_END;
613 /* If there is room left, explicitly add an invalid descriptor. */
614 if (nsegs < SDHCI_ADMA2_DESC_COUNT)
615 memset(&descs[nsegs], 0, sizeof(*descs));
616 }
617
618 int
619 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
620 {
621 uint32_t caps, freq;
622 int err;
623
624 SDHCI_LOCK_INIT(slot);
625 slot->num = num;
626 slot->bus = dev;
627
628 err = sdhci_dma_alloc(slot);
629 if (err != 0) {
630 SDHCI_LOCK_DESTROY(slot);
631 return (err);
632 }
633
634 /* Initialize slot. */
635 sdhci_init(slot);
636 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
637 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
638 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
639 caps = slot->caps;
640 else
641 caps = RD4(slot, SDHCI_CAPABILITIES);
642 /* Calculate base clock frequency. */
643 if (slot->version >= SDHCI_SPEC_300)
644 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
645 SDHCI_CLOCK_BASE_SHIFT;
646 else
647 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
648 SDHCI_CLOCK_BASE_SHIFT;
649 if (freq != 0)
650 slot->max_clk = freq * 1000000;
651 /*
652 * If the frequency wasn't in the capabilities and the hardware driver
653 * hasn't already set max_clk we're probably not going to work right
654 * with an assumption, so complain about it.
655 */
656 if (slot->max_clk == 0) {
657 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
658 device_printf(dev, "Hardware doesn't specify base clock "
659 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
660 }
661 /* Calculate timeout clock frequency. */
662 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
663 slot->timeout_clk = slot->max_clk / 1000;
664 } else {
665 slot->timeout_clk =
666 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
667 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
668 slot->timeout_clk *= 1000;
669 }
670 /*
671 * If the frequency wasn't in the capabilities and the hardware driver
672 * hasn't already set timeout_clk we'll probably work okay using the
673 * max timeout, but still mention it.
674 */
675 if (slot->timeout_clk == 0) {
676 device_printf(dev, "Hardware doesn't specify timeout clock "
677 "frequency, setting BROKEN_TIMEOUT quirk.\n");
678 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
679 }
680
681 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
682 slot->host.f_max = slot->max_clk;
683 slot->host.host_ocr = 0;
684 if (caps & SDHCI_CAN_VDD_330)
685 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
686 if (caps & SDHCI_CAN_VDD_300)
687 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
688 if (caps & SDHCI_CAN_VDD_180)
689 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
690 if (slot->host.host_ocr == 0) {
691 device_printf(dev, "Hardware doesn't report any "
692 "support voltages.\n");
693 }
694 slot->host.caps = MMC_CAP_4_BIT_DATA;
695 if (caps & SDHCI_CAN_DO_8BITBUS)
696 slot->host.caps |= MMC_CAP_8_BIT_DATA;
697 if (caps & SDHCI_CAN_DO_HISPD)
698 slot->host.caps |= MMC_CAP_HSPEED;
699 /* Decide if we have usable DMA. */
700 if (caps & SDHCI_CAN_DO_DMA)
701 slot->opt |= SDHCI_HAVE_SDMA;
702 if (caps & SDHCI_CAN_DO_ADMA2)
703 slot->opt |= SDHCI_HAVE_ADMA2;
704
705 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) {
706 slot->opt &= ~SDHCI_HAVE_SDMA;
707 slot->opt &= ~SDHCI_HAVE_ADMA2;
708 }
709 if (slot->quirks & SDHCI_QUIRK_FORCE_SDMA)
710 slot->opt |= SDHCI_HAVE_SDMA;
711
712 /*
713 * Use platform-provided transfer backend
714 * with PIO as a fallback mechanism
715 */
716 if (slot->opt & SDHCI_PLATFORM_TRANSFER) {
717 slot->opt &= ~SDHCI_HAVE_SDMA;
718 slot->opt &= ~SDHCI_HAVE_ADMA2;
719 }
720
721 if (bootverbose || sdhci_debug) {
722 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n",
723 slot->max_clk / 1000000,
724 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
725 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
726 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" :
727 "1bit"),
728 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
729 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
730 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
731 (slot->opt & SDHCI_HAVE_ADMA2) ? "ADMA2" :
732 (slot->opt & SDHCI_HAVE_SDMA) ? "SDMA" : "PIO");
733 sdhci_dumpregs(slot);
734 }
735
736 slot->timeout = 10;
737 slot->failures = 0;
738 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
739 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
740 "timeout", CTLFLAG_RW, &slot->timeout, 0,
741 "Maximum timeout for SDHCI transfers (in secs)");
742 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
743 callout_init_mp(&slot->card_callout);
744 callout_init_lk(&slot->timeout_callout, &slot->lock);
745 return (0);
746 }
747
748 void
749 sdhci_start_slot(struct sdhci_slot *slot)
750 {
751 sdhci_card_task(slot, 0);
752 }
753
754 int
755 sdhci_cleanup_slot(struct sdhci_slot *slot)
756 {
757 device_t d;
758
759 callout_drain(&slot->timeout_callout);
760 callout_drain(&slot->card_callout);
761 taskqueue_drain(taskqueue_swi_mp, &slot->card_task);
762
763 SDHCI_LOCK(slot);
764 d = slot->dev;
765 slot->dev = NULL;
766 SDHCI_UNLOCK(slot);
767 if (d != NULL)
768 device_delete_child(slot->bus, d);
769
770 SDHCI_LOCK(slot);
771 sdhci_reset(slot, SDHCI_RESET_ALL);
772 SDHCI_UNLOCK(slot);
773
774 sdhci_dma_free(slot);
775
776 SDHCI_LOCK_DESTROY(slot);
777
778 return (0);
779 }
780
781 int
782 sdhci_generic_suspend(struct sdhci_slot *slot)
783 {
784 sdhci_reset(slot, SDHCI_RESET_ALL);
785
786 return (0);
787 }
788
789 int
790 sdhci_generic_resume(struct sdhci_slot *slot)
791 {
792 sdhci_init(slot);
793
794 return (0);
795 }
796
797 uint32_t
798 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
799 {
800 if (slot->version >= SDHCI_SPEC_300)
801 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
802 else
803 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
804 }
805
806 boolean_t
807 sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot)
808 {
809
810 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
811 }
812
813 int
814 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
815 {
816 struct sdhci_slot *slot = device_get_ivars(reqdev);
817 struct mmc_ios *ios = &slot->host.ios;
818
819 SDHCI_LOCK(slot);
820 /* Do full reset on bus power down to clear from any state. */
821 if (ios->power_mode == power_off) {
822 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
823 sdhci_init(slot);
824 }
825 /* Configure the bus. */
826 sdhci_set_clock(slot, ios->clock);
827 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
828 if (ios->bus_width == bus_width_8) {
829 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
830 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
831 } else if (ios->bus_width == bus_width_4) {
832 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
833 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
834 } else if (ios->bus_width == bus_width_1) {
835 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
836 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
837 } else {
838 panic("Invalid bus width: %d", ios->bus_width);
839 }
840 if (ios->timing == bus_timing_hs &&
841 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
842 slot->hostctrl |= SDHCI_CTRL_HISPD;
843 else
844 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
845 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
846 /* Some controllers like reset after bus changes. */
847 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
848 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
849
850 SDHCI_UNLOCK(slot);
851 return (0);
852 }
853
854 static void
855 sdhci_req_done(struct sdhci_slot *slot)
856 {
857 struct mmc_request *req;
858
859 if (slot->req != NULL && slot->curcmd != NULL) {
860 callout_stop(&slot->timeout_callout);
861 if (slot->curcmd->error != MMC_ERR_TIMEOUT)
862 slot->failures = 0;
863 req = slot->req;
864 slot->req = NULL;
865 slot->curcmd = NULL;
866 req->done(req);
867 }
868 }
869
870 static void
871 sdhci_timeout(void *arg)
872 {
873 struct sdhci_slot *slot = arg;
874
875 if (slot->curcmd != NULL) {
876 slot_printf(slot, " Controller timeout\n");
877 sdhci_dumpregs(slot);
878 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
879 slot->curcmd->error = MMC_ERR_TIMEOUT;
880 sdhci_req_done(slot);
881 } else {
882 slot_printf(slot, " Spurious timeout - no active command\n");
883 }
884 }
885
886 static void
887 sdhci_set_transfer_mode(struct sdhci_slot *slot,
888 struct mmc_data *data)
889 {
890 uint16_t mode;
891
892 if (data == NULL)
893 return;
894
895 mode = SDHCI_TRNS_BLK_CNT_EN;
896 if (data->len > 512)
897 mode |= SDHCI_TRNS_MULTI;
898 if (data->flags & MMC_DATA_READ)
899 mode |= SDHCI_TRNS_READ;
900 if (slot->req->stop)
901 mode |= SDHCI_TRNS_ACMD12;
902 if (slot->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA2))
903 mode |= SDHCI_TRNS_DMA;
904
905 WR2(slot, SDHCI_TRANSFER_MODE, mode);
906 }
907
908 static void
909 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
910 {
911 int flags, timeout;
912 uint32_t mask;
913
914 slot->curcmd = cmd;
915 slot->cmd_done = 0;
916
917 cmd->error = MMC_ERR_NONE;
918
919 /* This flags combination is not supported by controller. */
920 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
921 slot_printf(slot, "Unsupported response type!\n");
922 cmd->error = MMC_ERR_FAILED;
923 sdhci_req_done(slot);
924 return;
925 }
926
927 /* Do not issue command if there is no card, clock or power.
928 * Controller will not detect timeout without clock active. */
929 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
930 slot->power == 0 ||
931 slot->clock == 0) {
932 cmd->error = MMC_ERR_FAILED;
933 sdhci_req_done(slot);
934 return;
935 }
936 /* Always wait for free CMD bus. */
937 mask = SDHCI_CMD_INHIBIT;
938 /* Wait for free DAT if we have data or busy signal. */
939 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
940 mask |= SDHCI_DAT_INHIBIT;
941 /* We shouldn't wait for DAT for stop commands. */
942 if (cmd == slot->req->stop)
943 mask &= ~SDHCI_DAT_INHIBIT;
944 /*
945 * Wait for bus no more then 250 ms. Typically there will be no wait
946 * here at all, but when writing a crash dump we may be bypassing the
947 * host platform's interrupt handler, and in some cases that handler
948 * may be working around hardware quirks such as not respecting r1b
949 * busy indications. In those cases, this wait-loop serves the purpose
950 * of waiting for the prior command and data transfers to be done, and
951 * SD cards are allowed to take up to 250ms for write and erase ops.
952 * (It's usually more like 20-30ms in the real world.)
953 */
954 timeout = 250;
955 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
956 if (timeout == 0) {
957 slot_printf(slot, "Controller never released "
958 "inhibit bit(s).\n");
959 sdhci_dumpregs(slot);
960 cmd->error = MMC_ERR_FAILED;
961 sdhci_req_done(slot);
962 return;
963 }
964 timeout--;
965 DELAY(1000);
966 }
967
968 /* Prepare command flags. */
969 if (!(cmd->flags & MMC_RSP_PRESENT))
970 flags = SDHCI_CMD_RESP_NONE;
971 else if (cmd->flags & MMC_RSP_136)
972 flags = SDHCI_CMD_RESP_LONG;
973 else if (cmd->flags & MMC_RSP_BUSY)
974 flags = SDHCI_CMD_RESP_SHORT_BUSY;
975 else
976 flags = SDHCI_CMD_RESP_SHORT;
977 if (cmd->flags & MMC_RSP_CRC)
978 flags |= SDHCI_CMD_CRC;
979 if (cmd->flags & MMC_RSP_OPCODE)
980 flags |= SDHCI_CMD_INDEX;
981 if (cmd->data)
982 flags |= SDHCI_CMD_DATA;
983 if (cmd->opcode == MMC_STOP_TRANSMISSION)
984 flags |= SDHCI_CMD_TYPE_ABORT;
985 /* Prepare data. */
986 sdhci_start_data(slot, cmd->data);
987 /*
988 * Interrupt aggregation: To reduce total number of interrupts
989 * group response interrupt with data interrupt when possible.
990 * If there going to be data interrupt, mask response one.
991 */
992 if (slot->data_done == 0) {
993 WR4(slot, SDHCI_SIGNAL_ENABLE,
994 slot->intmask &= ~SDHCI_INT_RESPONSE);
995 }
996 /* Set command argument. */
997 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
998 /* Set data transfer mode. */
999 sdhci_set_transfer_mode(slot, cmd->data);
1000 /* Start command. */
1001 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1002
1003 /*
1004 * Start timeout callout. Timeout is dropped to 2 seconds with
1005 * repeated controller timeouts.
1006 */
1007 if (slot->failures)
1008 timeout = slot->timeout / 5;
1009 else
1010 timeout = slot->timeout;
1011 if (timeout < 2)
1012 timeout = 2;
1013 callout_reset(&slot->timeout_callout, timeout * hz,
1014 sdhci_timeout, slot);
1015 }
1016
1017 static void
1018 sdhci_finish_command(struct sdhci_slot *slot)
1019 {
1020 int i;
1021
1022 slot->cmd_done = 1;
1023 /* Interrupt aggregation: Restore command interrupt.
1024 * Main restore point for the case when command interrupt
1025 * happened first. */
1026 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
1027 /* In case of error - reset host and return. */
1028 if (slot->curcmd->error) {
1029 sdhci_reset(slot, SDHCI_RESET_CMD);
1030 sdhci_reset(slot, SDHCI_RESET_DATA);
1031 sdhci_start(slot);
1032 return;
1033 }
1034 /* If command has response - fetch it. */
1035 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1036 if (slot->curcmd->flags & MMC_RSP_136) {
1037 /* CRC is stripped so we need one byte shift. */
1038 uint8_t extra = 0;
1039 for (i = 0; i < 4; i++) {
1040 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
1041 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) {
1042 slot->curcmd->resp[3 - i] = val;
1043 } else {
1044 slot->curcmd->resp[3 - i] =
1045 (val << 8) | extra;
1046 extra = val >> 24;
1047 }
1048 }
1049 } else {
1050 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1051 }
1052 }
1053 /* If data ready - finish. */
1054 if (slot->data_done)
1055 sdhci_start(slot);
1056 }
1057
1058 static void
1059 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1060 {
1061 uint32_t target_timeout, current_timeout;
1062 uint8_t div;
1063
1064 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1065 slot->data_done = 1;
1066 return;
1067 }
1068
1069 slot->data_done = 0;
1070
1071 /* Calculate and set data timeout.*/
1072 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1073 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1074 div = 0xe;
1075 } else {
1076 target_timeout = 1000000;
1077 div = 0;
1078 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1079 while (current_timeout < target_timeout && div < 0xE) {
1080 ++div;
1081 current_timeout <<= 1;
1082 }
1083 /* Compensate for an off-by-one error in the CaFe chip.*/
1084 if (div < 0xE &&
1085 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1086 ++div;
1087 }
1088 }
1089 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1090
1091 if (data == NULL)
1092 return;
1093
1094 /* Use DMA if possible. Prefer ADMA2 over SDMA. */
1095 if ((slot->opt & SDHCI_HAVE_ADMA2)) {
1096 slot->flags |= SDHCI_USE_ADMA2;
1097 slot->flags &= ~SDHCI_USE_SDMA;
1098 } else if ((slot->opt & SDHCI_HAVE_SDMA)) {
1099 slot->flags |= SDHCI_USE_SDMA;
1100 slot->flags &= ~SDHCI_USE_ADMA2;
1101 }
1102 /* If data is small, broken DMA may return zeroes instead of data. */
1103 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1104 (data->len <= 512)) {
1105 slot->flags &= ~SDHCI_USE_SDMA;
1106 slot->flags &= ~SDHCI_USE_ADMA2;
1107 }
1108 /* Some controllers require even block sizes. */
1109 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1110 ((data->len) & 0x3)) {
1111 slot->flags &= ~SDHCI_USE_SDMA;
1112 slot->flags &= ~SDHCI_USE_ADMA2;
1113 }
1114 /* Load DMA buffer. */
1115 if (slot->flags & SDHCI_USE_ADMA2) {
1116 bus_dmamem_t *descmem = &slot->adma2_descs;
1117 struct sdhci_adma2_desc32 *descs = (void *)descmem->dmem_addr;
1118 int err;
1119
1120 /* It shouldn't really be possible for this to fail */
1121 err = bus_dmamap_load(slot->adma2_tag, slot->adma2_map,
1122 data->data, data->len, sdhci_adma2_getaddr, slot,
1123 dumping ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1124 if (err != 0) {
1125 device_printf(slot->bus,
1126 "Dma load for ADMA2 fail: %d\n", err);
1127 } else if (descs[0].address == 0) {
1128 device_printf(slot->bus,
1129 "Dma load for ADMA2 fail, segment constraints\n");
1130 }
1131 if (err != 0 || descs[0].address == 0) {
1132 /* fallback to PIO for this request */
1133 slot->flags &= ~SDHCI_USE_ADMA2;
1134 goto pio_fallback;
1135 }
1136 /* sync dma descriptors */
1137 bus_dmamap_sync(descmem->dmem_tag, descmem->dmem_map,
1138 BUS_DMASYNC_PREWRITE);
1139 /* sync data buffers */
1140 if (data->flags & MMC_DATA_READ) {
1141 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1142 BUS_DMASYNC_PREREAD);
1143 } else {
1144 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1145 BUS_DMASYNC_PREWRITE);
1146 }
1147 WR4(slot, SDHCI_ADMA_ADDRESS_LOW, descmem->dmem_busaddr);
1148 if ((slot->hostctrl & SDHCI_CTRL_DMA_MASK) !=
1149 SDHCI_CTRL_ADMA2) {
1150 slot->hostctrl &= ~SDHCI_CTRL_DMA_MASK;
1151 slot->hostctrl |= SDHCI_CTRL_ADMA2;
1152 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1153 }
1154 /* We don't expect any DMA_END interrupts with ADMA2 */
1155 WR4(slot, SDHCI_SIGNAL_ENABLE,
1156 slot->intmask &= ~SDHCI_INT_DMA_END);
1157 } else if (slot->flags & SDHCI_USE_SDMA) {
1158 bus_dmamem_t *sdma = &slot->sdma_mem;
1159
1160 if (data->flags & MMC_DATA_READ) {
1161 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1162 BUS_DMASYNC_PREREAD);
1163 } else {
1164 memcpy(sdma->dmem_addr, data->data,
1165 (data->len < DMA_BLOCK_SIZE) ?
1166 data->len : DMA_BLOCK_SIZE);
1167 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1168 BUS_DMASYNC_PREWRITE);
1169 }
1170 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
1171 if ((slot->hostctrl & SDHCI_CTRL_DMA_MASK) !=
1172 SDHCI_CTRL_SDMA) {
1173 slot->hostctrl &= ~SDHCI_CTRL_DMA_MASK;
1174 slot->hostctrl |= SDHCI_CTRL_SDMA;
1175 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1176 }
1177 /* Interrupt aggregation: Mask border interrupt
1178 * for the last page and unmask else. */
1179 if (data->len == DMA_BLOCK_SIZE)
1180 slot->intmask &= ~SDHCI_INT_DMA_END;
1181 else
1182 slot->intmask |= SDHCI_INT_DMA_END;
1183 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1184 }
1185 pio_fallback:
1186 /* Current data offset for both PIO and SDMA. */
1187 slot->offset = 0;
1188 /* Set block size and for SDMA request IRQ on 4K border. */
1189 WR2(slot, SDHCI_BLOCK_SIZE,
1190 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
1191 /* Set block count. */
1192 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1193 }
1194
1195 void
1196 sdhci_finish_data(struct sdhci_slot *slot)
1197 {
1198 struct mmc_data *data = slot->curcmd->data;
1199
1200 /* Interrupt aggregation: Restore command interrupt.
1201 * Auxiliary restore point for the case when data interrupt
1202 * happened first. */
1203 if (!slot->cmd_done) {
1204 WR4(slot, SDHCI_SIGNAL_ENABLE,
1205 slot->intmask |= SDHCI_INT_RESPONSE);
1206 }
1207 /* Unload rest of data from DMA buffer. */
1208 if (!slot->data_done && (slot->flags & SDHCI_USE_ADMA2)) {
1209 bus_dmamem_t *descmem = &slot->adma2_descs;
1210
1211 bus_dmamap_sync(descmem->dmem_tag, descmem->dmem_map,
1212 BUS_DMASYNC_POSTWRITE);
1213 if (data->flags & MMC_DATA_READ) {
1214 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1215 BUS_DMASYNC_POSTREAD);
1216 } else {
1217 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1218 BUS_DMASYNC_POSTWRITE);
1219 }
1220 bus_dmamap_unload(slot->adma2_tag, slot->adma2_map);
1221 } else if (!slot->data_done && (slot->flags & SDHCI_USE_SDMA)) {
1222 bus_dmamem_t *sdma = &slot->sdma_mem;
1223
1224 if (data->flags & MMC_DATA_READ) {
1225 size_t left = data->len - slot->offset;
1226 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1227 BUS_DMASYNC_POSTREAD);
1228 memcpy((u_char*)data->data + slot->offset,
1229 sdma->dmem_addr,
1230 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1231 } else {
1232 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1233 BUS_DMASYNC_POSTWRITE);
1234 }
1235 }
1236 slot->data_done = 1;
1237 /* If there was an error - reset the host. */
1238 if (slot->curcmd->error) {
1239 sdhci_reset(slot, SDHCI_RESET_CMD);
1240 sdhci_reset(slot, SDHCI_RESET_DATA);
1241 sdhci_start(slot);
1242 return;
1243 }
1244 /* If we already have command response - finish. */
1245 if (slot->cmd_done)
1246 sdhci_start(slot);
1247 }
1248
1249 static void
1250 sdhci_start(struct sdhci_slot *slot)
1251 {
1252 struct mmc_request *req;
1253
1254 req = slot->req;
1255 if (req == NULL)
1256 return;
1257
1258 if (!(slot->flags & CMD_STARTED)) {
1259 slot->flags |= CMD_STARTED;
1260 sdhci_start_command(slot, req->cmd);
1261 return;
1262 }
1263 /* We don't need this until using Auto-CMD12 feature
1264 if (!(slot->flags & STOP_STARTED) && req->stop) {
1265 slot->flags |= STOP_STARTED;
1266 sdhci_start_command(slot, req->stop);
1267 return;
1268 }
1269 */
1270 if (sdhci_debug > 1)
1271 slot_printf(slot, "result: %d\n", req->cmd->error);
1272 if (!req->cmd->error &&
1273 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1274 sdhci_reset(slot, SDHCI_RESET_CMD);
1275 sdhci_reset(slot, SDHCI_RESET_DATA);
1276 }
1277
1278 sdhci_req_done(slot);
1279 }
1280
1281 int
1282 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1283 {
1284 struct sdhci_slot *slot = device_get_ivars(reqdev);
1285
1286 SDHCI_LOCK(slot);
1287 if (slot->req != NULL) {
1288 SDHCI_UNLOCK(slot);
1289 return (EBUSY);
1290 }
1291 if (sdhci_debug > 1) {
1292 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1293 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1294 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1295 (req->cmd->data)?req->cmd->data->flags:0);
1296 }
1297 slot->req = req;
1298 slot->flags = 0;
1299 sdhci_start(slot);
1300 SDHCI_UNLOCK(slot);
1301 if (dumping) {
1302 while (slot->req != NULL) {
1303 sdhci_generic_intr(slot);
1304 DELAY(10);
1305 }
1306 }
1307 return (0);
1308 }
1309
1310 int
1311 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1312 {
1313 struct sdhci_slot *slot = device_get_ivars(reqdev);
1314 uint32_t val;
1315
1316 SDHCI_LOCK(slot);
1317 val = RD4(slot, SDHCI_PRESENT_STATE);
1318 SDHCI_UNLOCK(slot);
1319 return (!(val & SDHCI_WRITE_PROTECT));
1320 }
1321
1322 int
1323 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1324 {
1325 struct sdhci_slot *slot = device_get_ivars(reqdev);
1326 int err = 0;
1327
1328 SDHCI_LOCK(slot);
1329 while (slot->bus_busy)
1330 lksleep(slot, &slot->lock, 0, "sdhciah", 0);
1331 slot->bus_busy++;
1332 /* Activate led. */
1333 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1334 SDHCI_UNLOCK(slot);
1335 return (err);
1336 }
1337
1338 int
1339 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1340 {
1341 struct sdhci_slot *slot = device_get_ivars(reqdev);
1342
1343 SDHCI_LOCK(slot);
1344 /* Deactivate led. */
1345 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1346 slot->bus_busy--;
1347 SDHCI_UNLOCK(slot);
1348 wakeup(slot);
1349 return (0);
1350 }
1351
1352 static void
1353 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1354 {
1355
1356 if (!slot->curcmd) {
1357 slot_printf(slot, "Got command interrupt 0x%08x, but "
1358 "there is no active command.\n", intmask);
1359 sdhci_dumpregs(slot);
1360 return;
1361 }
1362 if (intmask & SDHCI_INT_TIMEOUT)
1363 slot->curcmd->error = MMC_ERR_TIMEOUT;
1364 else if (intmask & SDHCI_INT_CRC)
1365 slot->curcmd->error = MMC_ERR_BADCRC;
1366 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1367 slot->curcmd->error = MMC_ERR_FIFO;
1368
1369 sdhci_finish_command(slot);
1370 }
1371
1372 static void
1373 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1374 {
1375
1376 if (!slot->curcmd) {
1377 slot_printf(slot, "Got data interrupt 0x%08x, but "
1378 "there is no active command.\n", intmask);
1379 sdhci_dumpregs(slot);
1380 return;
1381 }
1382 if (slot->curcmd->data == NULL &&
1383 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1384 slot_printf(slot, "Got data interrupt 0x%08x, but "
1385 "there is no active data operation.\n",
1386 intmask);
1387 sdhci_dumpregs(slot);
1388 return;
1389 }
1390 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1391 slot->curcmd->error = MMC_ERR_TIMEOUT;
1392 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1393 slot->curcmd->error = MMC_ERR_BADCRC;
1394 if (slot->curcmd->data == NULL &&
1395 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1396 SDHCI_INT_DMA_END))) {
1397 slot_printf(slot, "Got data interrupt 0x%08x, but "
1398 "there is busy-only command.\n", intmask);
1399 sdhci_dumpregs(slot);
1400 slot->curcmd->error = MMC_ERR_INVALID;
1401 }
1402 if (slot->curcmd->error) {
1403 /* No need to continue after any error. */
1404 goto done;
1405 }
1406
1407 /* Handle PIO interrupt. */
1408 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1409 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1410 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1411 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1412 slot->flags |= PLATFORM_DATA_STARTED;
1413 } else
1414 sdhci_transfer_pio(slot);
1415 }
1416 /* Handle DMA border. */
1417 if (intmask & SDHCI_INT_DMA_END) {
1418 struct mmc_data *data = slot->curcmd->data;
1419 bus_dmamem_t *sdma = &slot->sdma_mem;
1420 size_t left;
1421
1422 /* Unload DMA buffer... */
1423 left = data->len - slot->offset;
1424 if (data->flags & MMC_DATA_READ) {
1425 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1426 BUS_DMASYNC_POSTREAD);
1427 memcpy((u_char*)data->data + slot->offset,
1428 sdma->dmem_addr,
1429 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1430 } else {
1431 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1432 BUS_DMASYNC_POSTWRITE);
1433 }
1434 /* ... and reload it again. */
1435 slot->offset += DMA_BLOCK_SIZE;
1436 left = data->len - slot->offset;
1437 if (data->flags & MMC_DATA_READ) {
1438 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1439 BUS_DMASYNC_PREREAD);
1440 } else {
1441 memcpy(sdma->dmem_addr,
1442 (u_char*)data->data + slot->offset,
1443 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1444 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1445 BUS_DMASYNC_PREWRITE);
1446 }
1447 /* Interrupt aggregation: Mask border interrupt
1448 * for the last page. */
1449 if (left == DMA_BLOCK_SIZE) {
1450 slot->intmask &= ~SDHCI_INT_DMA_END;
1451 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1452 }
1453 /* Restart DMA. */
1454 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
1455 }
1456 /* We have got all data. */
1457 if (intmask & SDHCI_INT_DATA_END) {
1458 if (slot->flags & PLATFORM_DATA_STARTED) {
1459 slot->flags &= ~PLATFORM_DATA_STARTED;
1460 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1461 } else {
1462 sdhci_finish_data(slot);
1463 }
1464 }
1465 done:
1466 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1467 if (slot->flags & PLATFORM_DATA_STARTED) {
1468 slot->flags &= ~PLATFORM_DATA_STARTED;
1469 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1470 } else {
1471 sdhci_finish_data(slot);
1472 }
1473 return;
1474 }
1475 }
1476
1477 static void
1478 sdhci_acmd_irq(struct sdhci_slot *slot)
1479 {
1480 uint16_t err;
1481
1482 err = RD4(slot, SDHCI_ACMD12_ERR);
1483 if (!slot->curcmd) {
1484 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1485 "there is no active command.\n", err);
1486 sdhci_dumpregs(slot);
1487 return;
1488 }
1489 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1490 sdhci_reset(slot, SDHCI_RESET_CMD);
1491 }
1492
1493 static void
1494 sdhci_adma_irq(struct sdhci_slot *slot)
1495 {
1496 bus_dmamem_t *descmem = &slot->adma2_descs;
1497 struct sdhci_adma2_desc32 *desc;
1498 bus_addr_t addr = 0;
1499 uint8_t err, adma_state;
1500
1501 err = RD1(slot, SDHCI_ADMA_ERR);
1502 if (slot->curcmd && (slot->flags & SDHCI_USE_ADMA2)) {
1503 slot_printf(slot, "Got ADMA2 error 0x%02x\n", err);
1504 } else {
1505 slot_printf(slot, "Got ADMA2 error 0x%02x, but "
1506 "there is no active command.\n", err);
1507 sdhci_dumpregs(slot);
1508 }
1509
1510 /* Try to print the erronous ADMA2 descriptor */
1511 adma_state = err & SDHCI_ADMA_ERR_STATE_MASK;
1512 if (adma_state == SDHCI_ADMA_ERR_STATE_STOP) {
1513 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);
1514 if (addr > sizeof(*desc))
1515 addr -= sizeof(*desc);
1516 else
1517 addr = 0;
1518 } else if (adma_state == SDHCI_ADMA_ERR_STATE_FDS) {
1519 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);
1520 } else if (adma_state == SDHCI_ADMA_ERR_STATE_TFR) {
1521 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);
1522 if (addr > sizeof(*desc))
1523 addr -= sizeof(*desc);
1524 else
1525 addr = 0;
1526 } else {
1527 slot_printf(slot, "Invalid ADMA2 state 0x%02x\n", adma_state);
1528 }
1529 if (addr >= descmem->dmem_busaddr &&
1530 addr < descmem->dmem_busaddr + SDHCI_ADMA2_DESCBUF_SIZE) {
1531 desc = (void *) ((char *)descmem->dmem_addr +
1532 (addr - descmem->dmem_busaddr));
1533 slot_printf(slot,
1534 "Descriptor: Addr=0x%08x Length=0x%04x Attr=0x%04x\n",
1535 desc->address, desc->length, desc->attribute);
1536 }
1537
1538 if (slot->curcmd && (slot->flags & SDHCI_USE_ADMA2)) {
1539 sdhci_reset(slot, SDHCI_RESET_CMD);
1540 }
1541 }
1542
1543 void
1544 sdhci_generic_intr(struct sdhci_slot *slot)
1545 {
1546 uint32_t intmask;
1547
1548 SDHCI_LOCK(slot);
1549 /* Read slot interrupt status. */
1550 intmask = RD4(slot, SDHCI_INT_STATUS);
1551 if (intmask == 0 || intmask == 0xffffffff) {
1552 SDHCI_UNLOCK(slot);
1553 return;
1554 }
1555 if (sdhci_debug > 2)
1556 slot_printf(slot, "Interrupt %#x\n", intmask);
1557
1558 /* Handle card presence interrupts. */
1559 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1560 WR4(slot, SDHCI_INT_STATUS, intmask &
1561 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1562
1563 if (intmask & SDHCI_INT_CARD_REMOVE) {
1564 if (bootverbose || sdhci_debug)
1565 slot_printf(slot, "Card removed\n");
1566 callout_stop(&slot->card_callout);
1567 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task);
1568 }
1569 if (intmask & SDHCI_INT_CARD_INSERT) {
1570 if (bootverbose || sdhci_debug)
1571 slot_printf(slot, "Card inserted\n");
1572 callout_reset(&slot->card_callout, hz / 2,
1573 sdhci_card_delay, slot);
1574 }
1575 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1576 }
1577 /* Handle command interrupts. */
1578 if (intmask & SDHCI_INT_CMD_MASK) {
1579 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1580 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1581 }
1582 /* Handle data interrupts. */
1583 if (intmask & SDHCI_INT_DATA_MASK) {
1584 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1585 /* Dont call data_irq in case of errored command */
1586 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
1587 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1588 }
1589 /* Handle AutoCMD12 error interrupt. */
1590 if (intmask & SDHCI_INT_ACMD12ERR) {
1591 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1592 sdhci_acmd_irq(slot);
1593 }
1594 /* Handle ADMA2 error interrupt. */
1595 if (intmask & SDHCI_INT_ADMAERR) {
1596 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ADMAERR);
1597 sdhci_adma_irq(slot);
1598 }
1599 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1600 intmask &= ~SDHCI_INT_ACMD12ERR;
1601 intmask &= ~SDHCI_INT_ADMAERR;
1602 intmask &= ~SDHCI_INT_ERROR;
1603 /* Handle bus power interrupt. */
1604 if (intmask & SDHCI_INT_BUS_POWER) {
1605 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1606 slot_printf(slot,
1607 "Card is consuming too much power!\n");
1608 intmask &= ~SDHCI_INT_BUS_POWER;
1609 }
1610 /* The rest is unknown. */
1611 if (intmask) {
1612 WR4(slot, SDHCI_INT_STATUS, intmask);
1613 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1614 intmask);
1615 sdhci_dumpregs(slot);
1616 }
1617
1618 SDHCI_UNLOCK(slot);
1619 }
1620
1621 int
1622 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1623 {
1624 struct sdhci_slot *slot = device_get_ivars(child);
1625
1626 switch (which) {
1627 default:
1628 return (EINVAL);
1629 case MMCBR_IVAR_BUS_MODE:
1630 *(int *)result = slot->host.ios.bus_mode;
1631 break;
1632 case MMCBR_IVAR_BUS_WIDTH:
1633 *(int *)result = slot->host.ios.bus_width;
1634 break;
1635 case MMCBR_IVAR_CHIP_SELECT:
1636 *(int *)result = slot->host.ios.chip_select;
1637 break;
1638 case MMCBR_IVAR_CLOCK:
1639 *(int *)result = slot->host.ios.clock;
1640 break;
1641 case MMCBR_IVAR_F_MIN:
1642 *(int *)result = slot->host.f_min;
1643 break;
1644 case MMCBR_IVAR_F_MAX:
1645 *(int *)result = slot->host.f_max;
1646 break;
1647 case MMCBR_IVAR_HOST_OCR:
1648 *(int *)result = slot->host.host_ocr;
1649 break;
1650 case MMCBR_IVAR_MODE:
1651 *(int *)result = slot->host.mode;
1652 break;
1653 case MMCBR_IVAR_OCR:
1654 *(int *)result = slot->host.ocr;
1655 break;
1656 case MMCBR_IVAR_POWER_MODE:
1657 *(int *)result = slot->host.ios.power_mode;
1658 break;
1659 case MMCBR_IVAR_VDD:
1660 *(int *)result = slot->host.ios.vdd;
1661 break;
1662 case MMCBR_IVAR_CAPS:
1663 *(int *)result = slot->host.caps;
1664 break;
1665 case MMCBR_IVAR_TIMING:
1666 *(int *)result = slot->host.ios.timing;
1667 break;
1668 case MMCBR_IVAR_MAX_DATA:
1669 *(int *)result = 65535;
1670 break;
1671 }
1672 return (0);
1673 }
1674
1675 int
1676 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1677 {
1678 struct sdhci_slot *slot = device_get_ivars(child);
1679
1680 switch (which) {
1681 default:
1682 return (EINVAL);
1683 case MMCBR_IVAR_BUS_MODE:
1684 slot->host.ios.bus_mode = value;
1685 break;
1686 case MMCBR_IVAR_BUS_WIDTH:
1687 slot->host.ios.bus_width = value;
1688 break;
1689 case MMCBR_IVAR_CHIP_SELECT:
1690 slot->host.ios.chip_select = value;
1691 break;
1692 case MMCBR_IVAR_CLOCK:
1693 if (value > 0) {
1694 uint32_t max_clock;
1695 uint32_t clock;
1696 int i;
1697
1698 max_clock = slot->max_clk;
1699 clock = max_clock;
1700
1701 if (slot->version < SDHCI_SPEC_300) {
1702 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1703 i <<= 1) {
1704 if (clock <= value)
1705 break;
1706 clock >>= 1;
1707 }
1708 }
1709 else {
1710 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1711 i += 2) {
1712 if (clock <= value)
1713 break;
1714 clock = max_clock / (i + 2);
1715 }
1716 }
1717
1718 slot->host.ios.clock = clock;
1719 } else
1720 slot->host.ios.clock = 0;
1721 break;
1722 case MMCBR_IVAR_MODE:
1723 slot->host.mode = value;
1724 break;
1725 case MMCBR_IVAR_OCR:
1726 slot->host.ocr = value;
1727 break;
1728 case MMCBR_IVAR_POWER_MODE:
1729 slot->host.ios.power_mode = value;
1730 break;
1731 case MMCBR_IVAR_VDD:
1732 slot->host.ios.vdd = value;
1733 break;
1734 case MMCBR_IVAR_TIMING:
1735 slot->host.ios.timing = value;
1736 break;
1737 case MMCBR_IVAR_CAPS:
1738 case MMCBR_IVAR_HOST_OCR:
1739 case MMCBR_IVAR_F_MIN:
1740 case MMCBR_IVAR_F_MAX:
1741 case MMCBR_IVAR_MAX_DATA:
1742 return (EINVAL);
1743 }
1744 return (0);
1745 }
1746
1747 MODULE_VERSION(sdhci, 1);
DragonFly BSD