sys/dev/netif/nfe/if_nfereg.h

   1 /*      $OpenBSD: if_nfereg.h,v 1.19 2006/05/28 00:20:21 brad Exp $     */
   2 /*      $DragonFly: src/sys/dev/netif/nfe/if_nfereg.h,v 1.13 2008/07/12 11:44:17 sephe Exp $    */
   3
   4 /*
   5  * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
   6  *
   7  * Permission to use, copy, modify, and distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define NFE_PCI_BA              0x10
  21
  22 #define NFE_RX_RING_DEF_COUNT   256
  23 #define NFE_TX_RING_DEF_COUNT   256
  24
  25 #define NFE_JUMBO_FRAMELEN      9018
  26 #define NFE_JUMBO_MTU           (NFE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
  27
  28 #define NFE_JBYTES              (NFE_JUMBO_FRAMELEN + ETHER_ALIGN)
  29 #define NFE_JPOOL_COUNT(sc)     (((sc)->sc_rx_ring_count * 3) / 2)
  30 #define NFE_JPOOL_SIZE(sc)      (NFE_JPOOL_COUNT((sc)) * NFE_JBYTES)
  31
  32 #if (BUS_SPACE_MAXADDR > BUS_SPACE_MAXADDR_32BIT)
  33 #define NFE_BUS_SPACE_MAXADDR   0x7fffffffffULL /* 39 bit */
  34 #else
  35 #define NFE_BUS_SPACE_MAXADDR   BUS_SPACE_MAXADDR
  36 #endif
  37
  38 #define NFE_MAX_SCATTER         32
  39 #define NFE_NSEG_SPARE_JUMBO    5
  40 #define NFE_NSEG_SPARE          1
  41 #define NFE_NSEG_RSVD           1
  42
  43 #define NFE_IRQ_STATUS          0x000
  44 #define NFE_IRQ_MASK            0x004
  45 #define NFE_SETUP_R6            0x008
  46 #define NFE_IMTIMER             0x00c
  47 #define NFE_MAC_RESET           0x034
  48 #define NFE_MISC1               0x080
  49 #define NFE_TX_CTL              0x084
  50 #define NFE_TX_STATUS           0x088
  51 #define NFE_RXFILTER            0x08c
  52 #define NFE_RXBUFSZ             0x090
  53 #define NFE_RX_CTL              0x094
  54 #define NFE_RX_STATUS           0x098
  55 #define NFE_RNDSEED             0x09c
  56 #define NFE_SETUP_R1            0x0a0
  57 #define NFE_SETUP_R2            0x0a4
  58 #define NFE_MACADDR_HI          0x0a8
  59 #define NFE_MACADDR_LO          0x0ac
  60 #define NFE_MULTIADDR_HI        0x0b0
  61 #define NFE_MULTIADDR_LO        0x0b4
  62 #define NFE_MULTIMASK_HI        0x0b8
  63 #define NFE_MULTIMASK_LO        0x0bc
  64 #define NFE_PHY_IFACE           0x0c0
  65 #define NFE_TX_RING_ADDR_LO     0x100
  66 #define NFE_RX_RING_ADDR_LO     0x104
  67 #define NFE_RING_SIZE           0x108
  68 #define NFE_TX_POLL             0x10c
  69 #define NFE_LINKSPEED           0x110
  70 #define NFE_SETUP_R5            0x130
  71 #define NFE_SETUP_R3            0x13C
  72 #define NFE_SETUP_R7            0x140
  73 #define NFE_RXTX_CTL            0x144
  74 #define NFE_TX_RING_ADDR_HI     0x148
  75 #define NFE_RX_RING_ADDR_HI     0x14c
  76 #define NFE_PHY_STATUS          0x180
  77 #define NFE_SETUP_R4            0x184
  78 #define NFE_STATUS              0x188
  79 #define NFE_PHY_SPEED           0x18c
  80 #define NFE_PHY_CTL             0x190
  81 #define NFE_PHY_DATA            0x194
  82 #define NFE_WOL_CTL             0x200
  83 #define NFE_PATTERN_CRC         0x204
  84 #define NFE_PATTERN_MASK        0x208
  85 #define NFE_PWR_CAP             0x268
  86 #define NFE_PWR_STATE           0x26c
  87 #define NFE_VTAG_CTL            0x300
  88 #define NFE_PWR_STATE2          0x600
  89
  90 #define NFE_PHY_ERROR           0x00001
  91 #define NFE_PHY_WRITE           0x00400
  92 #define NFE_PHY_BUSY            0x08000
  93 #define NFE_PHYADD_SHIFT        5
  94
  95 #define NFE_STATUS_MAGIC        0x140000
  96
  97 #define NFE_RESET_ASSERT        0xf3
  98
  99 #define NFE_TX_STATUS_BUSY      0x1
 100 #define NFE_RX_STATUS_BUSY      0x1
 101
 102 #define NFE_R1_MAGIC            0x16070f
 103 #define NFE_R2_MAGIC            0x16
 104 #define NFE_R4_MAGIC            0x08
 105 #define NFE_R6_MAGIC            0x03
 106 #define NFE_WOL_ENABLE          0x1111
 107 #define NFE_RX_START            0x01
 108 #define NFE_TX_START            0x01
 109
 110 #define NFE_IRQ_RXERR           0x0001
 111 #define NFE_IRQ_RX              0x0002
 112 #define NFE_IRQ_RX_NOBUF        0x0004
 113 #define NFE_IRQ_TXERR           0x0008
 114 #define NFE_IRQ_TX_DONE         0x0010
 115 #define NFE_IRQ_TIMER           0x0020
 116 #define NFE_IRQ_LINK            0x0040
 117 #define NFE_IRQ_TXERR2          0x0080
 118 #define NFE_IRQ_TX1             0x0100
 119
 120 #define NFE_IRQ_NOIMTIMER                                               \
 121         (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX |                \
 122          NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE |             \
 123          NFE_IRQ_LINK)
 124 #define NFE_IRQ_IMTIMER         (NFE_IRQ_TIMER | NFE_IRQ_LINK)
 125
 126 #define NFE_RXTX_KICKTX         0x0001
 127 #define NFE_RXTX_BIT1           0x0002
 128 #define NFE_RXTX_BIT2           0x0004
 129 #define NFE_RXTX_RESET          0x0010
 130 #define NFE_RXTX_VTAG_STRIP     0x0040
 131 #define NFE_RXTX_VTAG_INSERT    0x0080
 132 #define NFE_RXTX_RXCSUM         0x0400
 133 #define NFE_RXTX_DESC_V2        0x002100
 134 #define NFE_RXTX_DESC_V3        0xc02200
 135 #define NFE_RXFILTER_MAGIC      0x007f0008
 136 #define NFE_U2M                 (1 << 5)
 137 #define NFE_PROMISC             (1 << 7)
 138
 139 #define NFE_IMTIME(t)           ((((t) * 100) / 1024) & 0xffff)
 140 /* default interrupt moderation timer of 128us */
 141 #define NFE_IMTIME_DEFAULT      NFE_IMTIME(128)
 142
 143 #define NFE_VTAG_ENABLE         (1 << 13)
 144
 145 #define NFE_PWR_VALID           (1 << 8)
 146 #define NFE_PWR_WAKEUP          (1 << 15)
 147
 148 #define NFE_PWRUP_MASK          0x0f11
 149 #define NFE_PWRUP_REV_A3        0x1
 150
 151 #define NFE_MEDIA_SET           0x10000
 152 #define NFE_MEDIA_1000T         0x00032
 153 #define NFE_MEDIA_100TX         0x00064
 154 #define NFE_MEDIA_10T           0x003e8
 155
 156 #define NFE_PHY_100TX           (1 << 0)
 157 #define NFE_PHY_1000T           (1 << 1)
 158 #define NFE_PHY_HDX             (1 << 8)
 159
 160 #define NFE_MISC1_MAGIC         0x003b0f3c
 161 #define NFE_MISC1_HDX           (1 << 1)
 162
 163 #define NFE_SEED_MASK           0x0003ff00
 164 #define NFE_SEED_10T            0x00007f00
 165 #define NFE_SEED_100TX          0x00002d00
 166 #define NFE_SEED_1000T          0x00007400
 167
 168 /* Rx/Tx descriptor */
 169 struct nfe_desc32 {
 170         uint32_t        physaddr;
 171         uint16_t        length;
 172         uint16_t        flags;
 173 #define NFE_RX_FIXME_V1         0x6004
 174 #define NFE_RX_VALID_V1         (1 << 0)
 175 #define NFE_TX_ERROR_V1         0x7808
 176 #define NFE_TX_LASTFRAG_V1      (1 << 0)
 177 } __packed;
 178
 179 #define NFE_V1_TXERR    "\020"  \
 180         "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
 181         "\08FORCEDINT\03RETRY\00LASTPACKET"
 182
 183 /* V2 Rx/Tx descriptor */
 184 struct nfe_desc64 {
 185         uint32_t        physaddr[2];
 186         uint32_t        vtag;
 187 #define NFE_RX_VTAG             (1 << 16)
 188 #define NFE_TX_VTAG             (1 << 18)
 189         uint16_t        length;
 190         uint16_t        flags;
 191 #define NFE_RX_FIXME_V2         0x4300
 192 #define NFE_RX_VALID_V2         (1 << 13)
 193 #define NFE_RX_IP_CSUMOK_V2     0x1000
 194 #define NFE_RX_UDP_CSUMOK_V2    0x1400
 195 #define NFE_RX_TCP_CSUMOK_V2    0x1800
 196 #define NFE_TX_ERROR_V2         0x5c04
 197 #define NFE_TX_LASTFRAG_V2      (1 << 13)
 198 } __packed;
 199
 200 #define NFE_V2_TXERR    "\020"  \
 201         "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
 202
 203 /* flags common to V1/V2 descriptors */
 204 #define NFE_RX_CSUMOK           0x1c00
 205 #define NFE_RX_ERROR            (1 << 14)
 206 #define NFE_RX_READY            (1 << 15)
 207 #define NFE_TX_TCP_CSUM         (1 << 10)
 208 #define NFE_TX_IP_CSUM          (1 << 11)
 209 #define NFE_TX_VALID            (1 << 15)
 210
 211 #define NFE_READ(sc, reg) \
 212         bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))
 213
 214 #define NFE_WRITE(sc, reg, val) \
 215         bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))