?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
More style, comments, includes and unused params fixes for sdhci and mmc.
[dragonfly.git] / sys / dev / disk / sdhci / sdhci.c
blobe029401f44edc0c93a519b10c0e77642dd560a4d
1 /*-
2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/callout.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/module.h>
36 #include <sys/spinlock.h>
37 #include <sys/resource.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41
42 #include <bus/mmc/bridge.h>
43 #include <bus/mmc/mmcreg.h>
44 #include <bus/mmc/mmcbrvar.h>
45
46 #include "mmcbr_if.h"
47 #include "sdhci.h"
48 #include "sdhci_if.h"
49
50 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
51
52 int sdhci_debug = 0;
53 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
54 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
55
56 static int sdhci_sdma_disable = 0;
57 TUNABLE_INT("hw.sdhci.sdma_disable", &sdhci_sdma_disable);
58
59 static int sdhci_adma2_disable = 0;
60 TUNABLE_INT("hw.sdhci.adma2_disable", &sdhci_adma2_disable);
61
62 static int sdhci_adma2_test = 0;
63 TUNABLE_INT("hw.sdhci.adma2_test", &sdhci_adma2_test);
64
65 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
66 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
67 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
68 #define RD_MULTI_4(slot, off, ptr, count) \
69 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
70 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
71 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
72 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
73 #define WR_MULTI_4(slot, off, ptr, count) \
74 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
75
76 static int slot_printf(struct sdhci_slot *, const char *, ...)
77 __printflike(2, 3);
78
79 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
80 static void sdhci_start(struct sdhci_slot *slot);
81 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
82
83 static void sdhci_card_task(void *, int);
84
85 static int sdhci_dma_alloc(struct sdhci_slot *slot);
86 static void sdhci_dmamem_free(bus_dmamem_t *mem);
87 static void sdhci_dma_free(struct sdhci_slot *slot);
88 static void sdhci_adma2_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
89 int error);
90
91 /* helper routines */
92 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE)
93 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE)
94 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE)
95 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock);
96 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0);
97 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0);
98
99 #define SDHCI_DEFAULT_MAX_FREQ 50
100
101 #define SDHCI_200_MAX_DIVIDER 256
102 #define SDHCI_300_MAX_DIVIDER 2046
103
104 /*
105 * Broadcom BCM577xx Controller Constants
106 */
107 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */
108 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */
109
110 #define BCM577XX_HOST_CONTROL 0x198
111 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
112 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
113 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
114 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
115
116 static int
117 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
118 {
119 __va_list ap;
120 int retval;
121
122 retval = kprintf("%s-slot%d: ",
123 device_get_nameunit(slot->bus), slot->num);
124
125 __va_start(ap, fmt);
126 retval += kvprintf(fmt, ap);
127 __va_end(ap);
128 return (retval);
129 }
130
131 static void
132 sdhci_dumpregs(struct sdhci_slot *slot)
133 {
134 slot_printf(slot,
135 "============== REGISTER DUMP ==============\n");
136
137 slot_printf(slot, "SDMA addr: 0x%08x | Version: 0x%08x\n",
138 RD4(slot, SDHCI_SDMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
139 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
140 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
141 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
142 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
143 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
144 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
145 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
146 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
147 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
148 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
149 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
150 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
151 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
152 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
153 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n",
154 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
155 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
156 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
157 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
158 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
159 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n",
160 RD4(slot, SDHCI_ADMA_ADDRESS_LOW), RD2(slot, SDHCI_SLOT_INT_STATUS));
161
162 slot_printf(slot,
163 "===========================================\n");
164 }
165
166 static void
167 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
168 {
169 int timeout;
170 uint32_t clock;
171
172 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
173 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
174 return;
175 }
176
177 /* Some controllers need this kick or reset won't work. */
178 if ((mask & SDHCI_RESET_ALL) == 0 &&
179 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
180 /* This is to force an update */
181 clock = slot->clock;
182 slot->clock = 0;
183 sdhci_set_clock(slot, clock);
184 }
185
186 if (mask & SDHCI_RESET_ALL) {
187 slot->clock = 0;
188 slot->power = 0;
189 }
190
191 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
192
193 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
194 /*
195 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
196 * specification. The reset bit has internal propagation delay,
197 * so a fast read after write returns 0 even if reset process is
198 * in progress. The workaround is to poll for 1 before polling
199 * for 0. In the worst case, if we miss seeing it asserted the
200 * time we spent waiting is enough to ensure the reset finishes.
201 */
202 timeout = 10000;
203 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
204 if (timeout <= 0)
205 break;
206 timeout--;
207 DELAY(1);
208 }
209 }
210
211 /* Wait max 100 ms */
212 timeout = 10000;
213 /* Controller clears the bits when it's done */
214 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
215 if (timeout <= 0) {
216 slot_printf(slot, "Reset 0x%x never completed.\n",
217 mask);
218 sdhci_dumpregs(slot);
219 return;
220 }
221 timeout--;
222 DELAY(10);
223 }
224 }
225
226 static void
227 sdhci_init(struct sdhci_slot *slot)
228 {
229
230 sdhci_reset(slot, SDHCI_RESET_ALL);
231
232 /* Enable interrupts. */
233 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
236 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
237 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
238 SDHCI_INT_ACMD12ERR | SDHCI_INT_ADMAERR;
239 if (!(slot->opt & SDHCI_SLOT_EMBEDDED))
240 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
241 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
242 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
243 }
244
245 static void
246 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
247 {
248 uint32_t clk_base;
249 uint32_t clk_sel;
250 uint32_t res;
251 uint16_t clk;
252 uint16_t div;
253 int timeout;
254
255 if (clock == slot->clock)
256 return;
257 slot->clock = clock;
258
259 /* Turn off the clock. */
260 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
261 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
262 /* If no clock requested - leave it so. */
263 if (clock == 0)
264 return;
265
266 /* Determine the clock base frequency */
267 clk_base = slot->max_clk;
268 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
269 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK;
270
271 /* Select clock source appropriate for the requested frequency. */
272 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
273 clk_base = BCM577XX_ALT_CLOCK_BASE;
274 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT);
275 } else {
276 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT);
277 }
278
279 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
280 }
281
282 /* Recalculate timeout clock frequency based on the new sd clock. */
283 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
284 slot->timeout_clk = slot->clock / 1000;
285
286 if (slot->version < SDHCI_SPEC_300) {
287 /* Looking for highest freq <= clock. */
288 res = clk_base;
289 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
290 if (res <= clock)
291 break;
292 res >>= 1;
293 }
294 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
295 div >>= 1;
296 } else {
297 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
298 if (clock >= clk_base)
299 div = 0;
300 else {
301 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
302 if ((clk_base / div) <= clock)
303 break;
304 }
305 }
306 div >>= 1;
307 }
308
309 if (bootverbose || sdhci_debug)
310 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
311 div, clock, clk_base);
312
313 /* Now we have got divider, set it. */
314 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
315 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
316 << SDHCI_DIVIDER_HI_SHIFT;
317
318 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
319 /* Enable clock. */
320 clk |= SDHCI_CLOCK_INT_EN;
321 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
322 /* Wait up to 10 ms until it stabilize. */
323 timeout = 10;
324 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
325 & SDHCI_CLOCK_INT_STABLE)) {
326 if (timeout == 0) {
327 slot_printf(slot,
328 "Internal clock never stabilised.\n");
329 sdhci_dumpregs(slot);
330 return;
331 }
332 timeout--;
333 DELAY(1000);
334 }
335 /* Pass clock signal to the bus. */
336 clk |= SDHCI_CLOCK_CARD_EN;
337 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
338 }
339
340 static void
341 sdhci_set_power(struct sdhci_slot *slot, u_char power)
342 {
343 uint8_t pwr;
344
345 if (slot->power == power)
346 return;
347
348 slot->power = power;
349
350 /* Turn off the power. */
351 pwr = 0;
352 WR1(slot, SDHCI_POWER_CONTROL, pwr);
353 /* If power down requested - leave it so. */
354 if (power == 0)
355 return;
356 /* Set voltage. */
357 switch (1 << power) {
358 case MMC_OCR_LOW_VOLTAGE:
359 pwr |= SDHCI_POWER_180;
360 break;
361 case MMC_OCR_290_300:
362 case MMC_OCR_300_310:
363 pwr |= SDHCI_POWER_300;
364 break;
365 case MMC_OCR_320_330:
366 case MMC_OCR_330_340:
367 pwr |= SDHCI_POWER_330;
368 break;
369 }
370 WR1(slot, SDHCI_POWER_CONTROL, pwr);
371 /* Turn on the power. */
372 pwr |= SDHCI_POWER_ON;
373 WR1(slot, SDHCI_POWER_CONTROL, pwr);
374 }
375
376 static void
377 sdhci_read_block_pio(struct sdhci_slot *slot)
378 {
379 uint32_t data;
380 char *buffer;
381 size_t left;
382
383 buffer = slot->curcmd->data->data;
384 buffer += slot->offset;
385 /* Transfer one block at a time. */
386 left = min(512, slot->curcmd->data->len - slot->offset);
387 slot->offset += left;
388
389 /* If we are too fast, broken controllers return zeroes. */
390 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
391 DELAY(10);
392 /* Handle unaligned and aligned buffer cases. */
393 if ((intptr_t)buffer & 3) {
394 while (left > 3) {
395 data = RD4(slot, SDHCI_BUFFER);
396 buffer[0] = data;
397 buffer[1] = (data >> 8);
398 buffer[2] = (data >> 16);
399 buffer[3] = (data >> 24);
400 buffer += 4;
401 left -= 4;
402 }
403 } else {
404 RD_MULTI_4(slot, SDHCI_BUFFER,
405 (uint32_t *)buffer, left >> 2);
406 left &= 3;
407 }
408 /* Handle uneven size case. */
409 if (left > 0) {
410 data = RD4(slot, SDHCI_BUFFER);
411 while (left > 0) {
412 *(buffer++) = data;
413 data >>= 8;
414 left--;
415 }
416 }
417 }
418
419 static void
420 sdhci_write_block_pio(struct sdhci_slot *slot)
421 {
422 uint32_t data = 0;
423 char *buffer;
424 size_t left;
425
426 buffer = slot->curcmd->data->data;
427 buffer += slot->offset;
428 /* Transfer one block at a time. */
429 left = min(512, slot->curcmd->data->len - slot->offset);
430 slot->offset += left;
431
432 /* Handle unaligned and aligned buffer cases. */
433 if ((intptr_t)buffer & 3) {
434 while (left > 3) {
435 data = buffer[0] +
436 (buffer[1] << 8) +
437 (buffer[2] << 16) +
438 (buffer[3] << 24);
439 left -= 4;
440 buffer += 4;
441 WR4(slot, SDHCI_BUFFER, data);
442 }
443 } else {
444 WR_MULTI_4(slot, SDHCI_BUFFER,
445 (uint32_t *)buffer, left >> 2);
446 left &= 3;
447 }
448 /* Handle uneven size case. */
449 if (left > 0) {
450 while (left > 0) {
451 data <<= 8;
452 data += *(buffer++);
453 left--;
454 }
455 WR4(slot, SDHCI_BUFFER, data);
456 }
457 }
458
459 static void
460 sdhci_transfer_pio(struct sdhci_slot *slot)
461 {
462
463 /* Read as many blocks as possible. */
464 if (slot->curcmd->data->flags & MMC_DATA_READ) {
465 while (RD4(slot, SDHCI_PRESENT_STATE) &
466 SDHCI_DATA_AVAILABLE) {
467 sdhci_read_block_pio(slot);
468 if (slot->offset >= slot->curcmd->data->len)
469 break;
470 }
471 } else {
472 while (RD4(slot, SDHCI_PRESENT_STATE) &
473 SDHCI_SPACE_AVAILABLE) {
474 sdhci_write_block_pio(slot);
475 if (slot->offset >= slot->curcmd->data->len)
476 break;
477 }
478 }
479 }
480
481 static void
482 sdhci_card_delay(void *arg)
483 {
484 struct sdhci_slot *slot = arg;
485
486 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task);
487 }
488
489 static void
490 sdhci_card_task(void *arg, int pending)
491 {
492 struct sdhci_slot *slot = arg;
493
494 SDHCI_LOCK(slot);
495 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
496 if (slot->dev == NULL) {
497 /* If card is present - attach mmc bus. */
498 slot->dev = device_add_child(slot->bus, "mmc", -1);
499 device_set_ivars(slot->dev, slot);
500 SDHCI_UNLOCK(slot);
501 device_probe_and_attach(slot->dev);
502 } else
503 SDHCI_UNLOCK(slot);
504 } else {
505 if (slot->dev != NULL) {
506 /* If no card present - detach mmc bus. */
507 device_t d = slot->dev;
508 slot->dev = NULL;
509 SDHCI_UNLOCK(slot);
510 device_delete_child(slot->bus, d);
511 } else
512 SDHCI_UNLOCK(slot);
513 }
514 }
515
516 static int
517 sdhci_dma_alloc(struct sdhci_slot *slot)
518 {
519 int err;
520
521 /* Allocate DMA memory for SDMA. */
522 err = bus_dmamem_coherent(bus_get_dma_tag(slot->bus),
523 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
524 BUS_SPACE_MAXADDR, DMA_BLOCK_SIZE, BUS_DMA_NOWAIT,
525 &slot->sdma_mem);
526 if (err != 0) {
527 device_printf(slot->bus, "Can't alloc DMA memory for SDMA\n");
528 goto done;
529 }
530
531 /* Allocate DMA memory for 32bit ADMA2 descriptors. */
532 err = bus_dmamem_coherent(bus_get_dma_tag(slot->bus),
533 4, 0, BUS_SPACE_MAXADDR_32BIT,
534 BUS_SPACE_MAXADDR, SDHCI_ADMA2_DESCBUF_SIZE, BUS_DMA_NOWAIT,
535 &slot->adma2_descs);
536 if (err != 0) {
537 device_printf(slot->bus,
538 "Can't alloc DMA memory for ADMA2 descriptors\n");
539 goto error1;
540 }
541
542 /* Allocate DMA tag for 32bit ADMA2 data buffer */
543 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus),
544 4, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
545 MAXPHYS, SDHCI_ADMA2_DESC_COUNT,
546 MIN(MAXPHYS, SDHCI_ADMA2_MAX_SEGSIZE),
547 BUS_DMA_ALLOCNOW | BUS_DMA_ALLOCALL,
548 &slot->adma2_tag);
549 if (err != 0) {
550 device_printf(slot->bus, "Can't create DMA tag for ADMA2\n");
551 goto error2;
552 }
553
554 /* Allocate DMA map for ADMA2 data buffer */
555 err = bus_dmamap_create(slot->adma2_tag, BUS_DMA_NOWAIT,
556 &slot->adma2_map);
557 if (err != 0) {
558 device_printf(slot->bus, "Can't create DMA map for ADMA2\n");
559 goto error3;
560 }
561
562 return (0);
563
564 error3:
565 bus_dma_tag_destroy(slot->adma2_tag);
566 error2:
567 sdhci_dmamem_free(&slot->adma2_descs);
568 error1:
569 sdhci_dmamem_free(&slot->sdma_mem);
570 done:
571 return (err);
572 }
573
574 static void
575 sdhci_dmamem_free(bus_dmamem_t *dma)
576 {
577 bus_dmamap_unload(dma->dmem_tag, dma->dmem_map);
578 bus_dmamem_free(dma->dmem_tag, dma->dmem_addr, dma->dmem_map);
579 bus_dma_tag_destroy(dma->dmem_tag);
580 }
581
582 static void
583 sdhci_dma_free(struct sdhci_slot *slot)
584 {
585 bus_dmamap_destroy(slot->adma2_tag, slot->adma2_map);
586 bus_dma_tag_destroy(slot->adma2_tag);
587 sdhci_dmamem_free(&slot->sdma_mem);
588 sdhci_dmamem_free(&slot->adma2_descs);
589 }
590
591 static void
592 sdhci_adma2_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
593 {
594 struct sdhci_slot *slot = arg;
595 bus_dmamem_t *descmem = &slot->adma2_descs;
596 struct sdhci_adma2_desc32 *descs = (void *)descmem->dmem_addr;
597 int i;
598
599 if (error != 0) {
600 /* This signals, that loading was unsuccessful */
601 memset(&descs[0], 0, sizeof(*descs));
602 return;
603 }
604
605 for (i = 0; i < nsegs; i++) {
606 descs[i].address = segs[i].ds_addr;
607 /*
608 * The 65536 segment length case is broken in some sdhc host
609 * controllers, so we actually use a maximum segment length
610 * of 32768 for the DMA mapping and ds_len should be at most
611 * 32768 here.
612 */
613 if (segs[i].ds_len == 65536)
614 descs[i].length = 0;
615 else
616 descs[i].length = segs[i].ds_len;
617 descs[i].attribute =
618 SDHCI_ADMA2_ATTR_VALID | SDHCI_ADMA2_ATTR_OP_TRAN;
619 }
620 descs[nsegs-1].attribute |= SDHCI_ADMA2_ATTR_END;
621 /* If there is room left, explicitly add an invalid descriptor. */
622 if (nsegs < SDHCI_ADMA2_DESC_COUNT)
623 memset(&descs[nsegs], 0, sizeof(*descs));
624 }
625
626 int
627 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
628 {
629 uint32_t caps, freq;
630 int err;
631
632 SDHCI_LOCK_INIT(slot);
633 slot->num = num;
634 slot->bus = dev;
635
636 err = sdhci_dma_alloc(slot);
637 if (err != 0) {
638 SDHCI_LOCK_DESTROY(slot);
639 return (err);
640 }
641
642 /* Initialize slot. */
643 sdhci_init(slot);
644 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
645 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
646 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
647 caps = slot->caps;
648 else
649 caps = RD4(slot, SDHCI_CAPABILITIES);
650 if (slot->version >= SDHCI_SPEC_300) {
651 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
652 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
653 device_printf(dev,
654 "Driver doesn't support shared bus slots\n");
655 sdhci_dma_free(slot);
656 SDHCI_LOCK_DESTROY(slot);
657 return (1);
658 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
659 SDHCI_SLOTTYPE_EMBEDDED) {
660 slot->opt |= SDHCI_SLOT_EMBEDDED;
661 }
662 }
663 /* Calculate base clock frequency. */
664 if (slot->version >= SDHCI_SPEC_300)
665 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
666 SDHCI_CLOCK_BASE_SHIFT;
667 else
668 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
669 SDHCI_CLOCK_BASE_SHIFT;
670 if (freq != 0)
671 slot->max_clk = freq * 1000000;
672 /*
673 * If the frequency wasn't in the capabilities and the hardware driver
674 * hasn't already set max_clk we're probably not going to work right
675 * with an assumption, so complain about it.
676 */
677 if (slot->max_clk == 0) {
678 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
679 device_printf(dev, "Hardware doesn't specify base clock "
680 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
681 }
682 /* Calculate timeout clock frequency. */
683 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
684 slot->timeout_clk = slot->max_clk / 1000;
685 } else {
686 slot->timeout_clk =
687 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
688 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
689 slot->timeout_clk *= 1000;
690 }
691 /*
692 * If the frequency wasn't in the capabilities and the hardware driver
693 * hasn't already set timeout_clk we'll probably work okay using the
694 * max timeout, but still mention it.
695 */
696 if (slot->timeout_clk == 0) {
697 device_printf(dev, "Hardware doesn't specify timeout clock "
698 "frequency, setting BROKEN_TIMEOUT quirk.\n");
699 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
700 }
701
702 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
703 slot->host.f_max = slot->max_clk;
704 slot->host.host_ocr = 0;
705 if (caps & SDHCI_CAN_VDD_330)
706 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
707 if (caps & SDHCI_CAN_VDD_300)
708 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
709 if (caps & SDHCI_CAN_VDD_180)
710 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
711 if (slot->host.host_ocr == 0) {
712 device_printf(dev, "Hardware doesn't report any "
713 "support voltages.\n");
714 }
715 slot->host.caps = MMC_CAP_4_BIT_DATA;
716 if (caps & SDHCI_CAN_DO_8BITBUS)
717 slot->host.caps |= MMC_CAP_8_BIT_DATA;
718 if (caps & SDHCI_CAN_DO_HISPD)
719 slot->host.caps |= MMC_CAP_HSPEED;
720 /* Decide if we have usable DMA. */
721 if (caps & SDHCI_CAN_DO_DMA)
722 slot->opt |= SDHCI_HAVE_SDMA;
723 if (caps & SDHCI_CAN_DO_ADMA2)
724 slot->opt |= SDHCI_HAVE_ADMA2;
725
726 /* Use ADMA2 only on whitelisted models, or when explicitly enabled. */
727 if (sdhci_adma2_test == 0 &&
728 (slot->quirks & SDHCI_QUIRK_WHITELIST_ADMA2) == 0) {
729 slot->opt &= ~SDHCI_HAVE_ADMA2;
730 }
731
732 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) {
733 slot->opt &= ~SDHCI_HAVE_SDMA;
734 slot->opt &= ~SDHCI_HAVE_ADMA2;
735 }
736 if (slot->quirks & SDHCI_QUIRK_FORCE_SDMA)
737 slot->opt |= SDHCI_HAVE_SDMA;
738
739 if (sdhci_sdma_disable)
740 slot->opt &= ~SDHCI_HAVE_SDMA;
741 if (sdhci_adma2_disable)
742 slot->opt &= ~SDHCI_HAVE_ADMA2;
743
744 /*
745 * Use platform-provided transfer backend
746 * with PIO as a fallback mechanism
747 */
748 if (slot->opt & SDHCI_PLATFORM_TRANSFER) {
749 slot->opt &= ~SDHCI_HAVE_SDMA;
750 slot->opt &= ~SDHCI_HAVE_ADMA2;
751 }
752
753 if (bootverbose || sdhci_debug) {
754 slot_printf(slot, "%uMHz%s %s%s%s%s %s%s\n",
755 slot->max_clk / 1000000,
756 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
757 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
758 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" :
759 "1bit"),
760 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
761 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
762 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
763 (slot->opt & SDHCI_HAVE_ADMA2) ? "ADMA2" :
764 (slot->opt & SDHCI_HAVE_SDMA) ? "SDMA" : "PIO",
765 (slot->version < SDHCI_SPEC_300) ? "" :
766 (slot->opt & SDHCI_SLOT_EMBEDDED) ? " (embedded)" :
767 " (removable)");
768 sdhci_dumpregs(slot);
769 }
770
771 slot->timeout = 10;
772 slot->failures = 0;
773 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
774 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
775 "timeout", CTLFLAG_RW, &slot->timeout, 0,
776 "Maximum timeout for SDHCI transfers (in secs)");
777 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
778 callout_init_mp(&slot->card_callout);
779 callout_init_lk(&slot->timeout_callout, &slot->lock);
780 return (0);
781 }
782
783 void
784 sdhci_start_slot(struct sdhci_slot *slot)
785 {
786 sdhci_card_task(slot, 0);
787 }
788
789 int
790 sdhci_cleanup_slot(struct sdhci_slot *slot)
791 {
792 device_t d;
793
794 callout_drain(&slot->timeout_callout);
795 callout_drain(&slot->card_callout);
796 taskqueue_drain(taskqueue_swi_mp, &slot->card_task);
797
798 SDHCI_LOCK(slot);
799 d = slot->dev;
800 slot->dev = NULL;
801 SDHCI_UNLOCK(slot);
802 if (d != NULL)
803 device_delete_child(slot->bus, d);
804
805 SDHCI_LOCK(slot);
806 sdhci_reset(slot, SDHCI_RESET_ALL);
807 SDHCI_UNLOCK(slot);
808
809 sdhci_dma_free(slot);
810
811 SDHCI_LOCK_DESTROY(slot);
812
813 return (0);
814 }
815
816 int
817 sdhci_generic_suspend(struct sdhci_slot *slot)
818 {
819 sdhci_reset(slot, SDHCI_RESET_ALL);
820
821 return (0);
822 }
823
824 int
825 sdhci_generic_resume(struct sdhci_slot *slot)
826 {
827 sdhci_init(slot);
828
829 return (0);
830 }
831
832 uint32_t
833 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
834 {
835 if (slot->version >= SDHCI_SPEC_300)
836 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
837 else
838 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
839 }
840
841 boolean_t
842 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
843 {
844 if (slot->opt & SDHCI_SLOT_EMBEDDED)
845 return 1;
846
847 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
848 }
849
850 int
851 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
852 {
853 struct sdhci_slot *slot = device_get_ivars(reqdev);
854 struct mmc_ios *ios = &slot->host.ios;
855
856 SDHCI_LOCK(slot);
857 /* Do full reset on bus power down to clear from any state. */
858 if (ios->power_mode == power_off) {
859 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
860 sdhci_init(slot);
861 }
862 /* Configure the bus. */
863 sdhci_set_clock(slot, ios->clock);
864 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
865 if (ios->bus_width == bus_width_8) {
866 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
867 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
868 } else if (ios->bus_width == bus_width_4) {
869 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
870 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
871 } else if (ios->bus_width == bus_width_1) {
872 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
873 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
874 } else {
875 panic("Invalid bus width: %d", ios->bus_width);
876 }
877 if (ios->timing == bus_timing_hs &&
878 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
879 slot->hostctrl |= SDHCI_CTRL_HISPD;
880 else
881 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
882 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
883 /* Some controllers like reset after bus changes. */
884 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
885 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
886
887 SDHCI_UNLOCK(slot);
888 return (0);
889 }
890
891 static void
892 sdhci_req_done(struct sdhci_slot *slot)
893 {
894 struct mmc_request *req;
895
896 if (slot->req != NULL && slot->curcmd != NULL) {
897 callout_stop(&slot->timeout_callout);
898 if (slot->curcmd->error != MMC_ERR_TIMEOUT)
899 slot->failures = 0;
900 req = slot->req;
901 slot->req = NULL;
902 slot->curcmd = NULL;
903 req->done(req);
904 }
905 }
906
907 static void
908 sdhci_timeout(void *arg)
909 {
910 struct sdhci_slot *slot = arg;
911
912 if (slot->curcmd != NULL) {
913 slot_printf(slot, " Controller timeout\n");
914 sdhci_dumpregs(slot);
915 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
916 slot->curcmd->error = MMC_ERR_TIMEOUT;
917 sdhci_req_done(slot);
918 } else {
919 slot_printf(slot, " Spurious timeout - no active command\n");
920 }
921 }
922
923 static void
924 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
925 {
926 uint16_t mode;
927
928 if (data == NULL)
929 return;
930
931 mode = SDHCI_TRNS_BLK_CNT_EN;
932 if (data->len > 512)
933 mode |= SDHCI_TRNS_MULTI;
934 if (data->flags & MMC_DATA_READ)
935 mode |= SDHCI_TRNS_READ;
936 if (slot->req->stop)
937 mode |= SDHCI_TRNS_ACMD12;
938 if (slot->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA2))
939 mode |= SDHCI_TRNS_DMA;
940
941 WR2(slot, SDHCI_TRANSFER_MODE, mode);
942 }
943
944 static void
945 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
946 {
947 int flags, timeout;
948 uint32_t mask;
949
950 slot->curcmd = cmd;
951 slot->cmd_done = 0;
952
953 cmd->error = MMC_ERR_NONE;
954
955 /* This flags combination is not supported by controller. */
956 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
957 slot_printf(slot, "Unsupported response type!\n");
958 cmd->error = MMC_ERR_FAILED;
959 sdhci_req_done(slot);
960 return;
961 }
962
963 /*
964 * Do not issue command if there is no card, clock or power.
965 * Controller will not detect timeout without clock active.
966 */
967 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
968 slot->power == 0 ||
969 slot->clock == 0) {
970 cmd->error = MMC_ERR_FAILED;
971 sdhci_req_done(slot);
972 return;
973 }
974 /* Always wait for free CMD bus. */
975 mask = SDHCI_CMD_INHIBIT;
976 /* Wait for free DAT if we have data or busy signal. */
977 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
978 mask |= SDHCI_DAT_INHIBIT;
979 /* We shouldn't wait for DAT for stop commands. */
980 if (cmd == slot->req->stop)
981 mask &= ~SDHCI_DAT_INHIBIT;
982 /*
983 * Wait for bus no more then 250 ms. Typically there will be no wait
984 * here at all, but when writing a crash dump we may be bypassing the
985 * host platform's interrupt handler, and in some cases that handler
986 * may be working around hardware quirks such as not respecting r1b
987 * busy indications. In those cases, this wait-loop serves the purpose
988 * of waiting for the prior command and data transfers to be done, and
989 * SD cards are allowed to take up to 250ms for write and erase ops.
990 * (It's usually more like 20-30ms in the real world.)
991 */
992 timeout = 250;
993 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
994 if (timeout == 0) {
995 slot_printf(slot, "Controller never released "
996 "inhibit bit(s).\n");
997 sdhci_dumpregs(slot);
998 cmd->error = MMC_ERR_FAILED;
999 sdhci_req_done(slot);
1000 return;
1001 }
1002 timeout--;
1003 DELAY(1000);
1004 }
1005
1006 /* Prepare command flags. */
1007 if (!(cmd->flags & MMC_RSP_PRESENT))
1008 flags = SDHCI_CMD_RESP_NONE;
1009 else if (cmd->flags & MMC_RSP_136)
1010 flags = SDHCI_CMD_RESP_LONG;
1011 else if (cmd->flags & MMC_RSP_BUSY)
1012 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1013 else
1014 flags = SDHCI_CMD_RESP_SHORT;
1015 if (cmd->flags & MMC_RSP_CRC)
1016 flags |= SDHCI_CMD_CRC;
1017 if (cmd->flags & MMC_RSP_OPCODE)
1018 flags |= SDHCI_CMD_INDEX;
1019 if (cmd->data)
1020 flags |= SDHCI_CMD_DATA;
1021 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1022 flags |= SDHCI_CMD_TYPE_ABORT;
1023 /* Prepare data. */
1024 sdhci_start_data(slot, cmd->data);
1025 /*
1026 * Interrupt aggregation: To reduce total number of interrupts
1027 * group response interrupt with data interrupt when possible.
1028 * If there going to be data interrupt, mask response one.
1029 */
1030 if (slot->data_done == 0) {
1031 WR4(slot, SDHCI_SIGNAL_ENABLE,
1032 slot->intmask &= ~SDHCI_INT_RESPONSE);
1033 }
1034 /* Set command argument. */
1035 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1036 /* Set data transfer mode. */
1037 sdhci_set_transfer_mode(slot, cmd->data);
1038 /* Start command. */
1039 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1040
1041 /*
1042 * Start timeout callout. Timeout is dropped to 2 seconds with
1043 * repeated controller timeouts.
1044 */
1045 if (slot->failures)
1046 timeout = slot->timeout / 5;
1047 else
1048 timeout = slot->timeout;
1049 if (timeout < 2)
1050 timeout = 2;
1051 callout_reset(&slot->timeout_callout, timeout * hz,
1052 sdhci_timeout, slot);
1053 }
1054
1055 static void
1056 sdhci_finish_command(struct sdhci_slot *slot)
1057 {
1058 int i;
1059
1060 slot->cmd_done = 1;
1061 /* Interrupt aggregation: Restore command interrupt.
1062 * Main restore point for the case when command interrupt
1063 * happened first. */
1064 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
1065 /* In case of error - reset host and return. */
1066 if (slot->curcmd->error) {
1067 sdhci_reset(slot, SDHCI_RESET_CMD);
1068 sdhci_reset(slot, SDHCI_RESET_DATA);
1069 sdhci_start(slot);
1070 return;
1071 }
1072 /* If command has response - fetch it. */
1073 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1074 if (slot->curcmd->flags & MMC_RSP_136) {
1075 /* CRC is stripped so we need one byte shift. */
1076 uint8_t extra = 0;
1077 for (i = 0; i < 4; i++) {
1078 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
1079 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) {
1080 slot->curcmd->resp[3 - i] = val;
1081 } else {
1082 slot->curcmd->resp[3 - i] =
1083 (val << 8) | extra;
1084 extra = val >> 24;
1085 }
1086 }
1087 } else {
1088 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1089 }
1090 }
1091 /* If data ready - finish. */
1092 if (slot->data_done)
1093 sdhci_start(slot);
1094 }
1095
1096 static void
1097 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1098 {
1099 uint32_t target_timeout, current_timeout;
1100 uint8_t div;
1101
1102 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1103 slot->data_done = 1;
1104 return;
1105 }
1106
1107 slot->data_done = 0;
1108
1109 /* Calculate and set data timeout.*/
1110 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1111 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1112 div = 0xe;
1113 } else {
1114 target_timeout = 1000000;
1115 div = 0;
1116 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1117 while (current_timeout < target_timeout && div < 0xE) {
1118 ++div;
1119 current_timeout <<= 1;
1120 }
1121 /* Compensate for an off-by-one error in the CaFe chip.*/
1122 if (div < 0xE &&
1123 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1124 ++div;
1125 }
1126 }
1127 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1128
1129 if (data == NULL)
1130 return;
1131
1132 /* Use DMA if possible. Prefer ADMA2 over SDMA. */
1133 if ((slot->opt & SDHCI_HAVE_ADMA2)) {
1134 slot->flags |= SDHCI_USE_ADMA2;
1135 slot->flags &= ~SDHCI_USE_SDMA;
1136 } else if ((slot->opt & SDHCI_HAVE_SDMA)) {
1137 slot->flags |= SDHCI_USE_SDMA;
1138 slot->flags &= ~SDHCI_USE_ADMA2;
1139 }
1140 /* If data is small, broken DMA may return zeroes instead of data. */
1141 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1142 (data->len <= 512)) {
1143 slot->flags &= ~SDHCI_USE_SDMA;
1144 slot->flags &= ~SDHCI_USE_ADMA2;
1145 }
1146 /* Some controllers require even block sizes. */
1147 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1148 ((data->len) & 0x3)) {
1149 slot->flags &= ~SDHCI_USE_SDMA;
1150 slot->flags &= ~SDHCI_USE_ADMA2;
1151 }
1152 /* Load DMA buffer. */
1153 if (slot->flags & SDHCI_USE_ADMA2) {
1154 bus_dmamem_t *descmem = &slot->adma2_descs;
1155 struct sdhci_adma2_desc32 *descs = (void *)descmem->dmem_addr;
1156 int err;
1157
1158 /* It shouldn't really be possible for this to fail */
1159 err = bus_dmamap_load(slot->adma2_tag, slot->adma2_map,
1160 data->data, data->len, sdhci_adma2_getaddr, slot,
1161 dumping ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1162 if (err != 0) {
1163 device_printf(slot->bus,
1164 "Dma load for ADMA2 fail: %d\n", err);
1165 } else if (descs[0].address == 0) {
1166 device_printf(slot->bus,
1167 "Dma load for ADMA2 fail, segment constraints\n");
1168 }
1169 if (err != 0 || descs[0].address == 0) {
1170 /* fallback to PIO for this request */
1171 slot->flags &= ~SDHCI_USE_ADMA2;
1172 goto pio_fallback;
1173 }
1174 /* sync dma descriptors */
1175 bus_dmamap_sync(descmem->dmem_tag, descmem->dmem_map,
1176 BUS_DMASYNC_PREWRITE);
1177 /* sync data buffers */
1178 if (data->flags & MMC_DATA_READ) {
1179 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1180 BUS_DMASYNC_PREREAD);
1181 } else {
1182 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1183 BUS_DMASYNC_PREWRITE);
1184 }
1185 WR4(slot, SDHCI_ADMA_ADDRESS_LOW, descmem->dmem_busaddr);
1186 if ((slot->hostctrl & SDHCI_CTRL_DMA_MASK) !=
1187 SDHCI_CTRL_ADMA2) {
1188 slot->hostctrl &= ~SDHCI_CTRL_DMA_MASK;
1189 slot->hostctrl |= SDHCI_CTRL_ADMA2;
1190 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1191 }
1192 /* We don't expect any DMA_END interrupts with ADMA2 */
1193 WR4(slot, SDHCI_SIGNAL_ENABLE,
1194 slot->intmask &= ~SDHCI_INT_DMA_END);
1195 } else if (slot->flags & SDHCI_USE_SDMA) {
1196 bus_dmamem_t *sdma = &slot->sdma_mem;
1197
1198 if (data->flags & MMC_DATA_READ) {
1199 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1200 BUS_DMASYNC_PREREAD);
1201 } else {
1202 memcpy(sdma->dmem_addr, data->data,
1203 (data->len < DMA_BLOCK_SIZE) ?
1204 data->len : DMA_BLOCK_SIZE);
1205 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1206 BUS_DMASYNC_PREWRITE);
1207 }
1208 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
1209 if ((slot->hostctrl & SDHCI_CTRL_DMA_MASK) !=
1210 SDHCI_CTRL_SDMA) {
1211 slot->hostctrl &= ~SDHCI_CTRL_DMA_MASK;
1212 slot->hostctrl |= SDHCI_CTRL_SDMA;
1213 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1214 }
1215 /* Interrupt aggregation: Mask border interrupt
1216 * for the last page and unmask else. */
1217 if (data->len == DMA_BLOCK_SIZE)
1218 slot->intmask &= ~SDHCI_INT_DMA_END;
1219 else
1220 slot->intmask |= SDHCI_INT_DMA_END;
1221 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1222 }
1223 pio_fallback:
1224 /* Current data offset for both PIO and SDMA. */
1225 slot->offset = 0;
1226 /* Set block size and for SDMA request IRQ on 4K border. */
1227 WR2(slot, SDHCI_BLOCK_SIZE,
1228 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
1229 /* Set block count. */
1230 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1231 }
1232
1233 void
1234 sdhci_finish_data(struct sdhci_slot *slot)
1235 {
1236 struct mmc_data *data = slot->curcmd->data;
1237
1238 /* Interrupt aggregation: Restore command interrupt.
1239 * Auxiliary restore point for the case when data interrupt
1240 * happened first. */
1241 if (!slot->cmd_done) {
1242 WR4(slot, SDHCI_SIGNAL_ENABLE,
1243 slot->intmask |= SDHCI_INT_RESPONSE);
1244 }
1245 /* Unload rest of data from DMA buffer. */
1246 if (!slot->data_done && (slot->flags & SDHCI_USE_ADMA2)) {
1247 bus_dmamem_t *descmem = &slot->adma2_descs;
1248
1249 bus_dmamap_sync(descmem->dmem_tag, descmem->dmem_map,
1250 BUS_DMASYNC_POSTWRITE);
1251 if (data->flags & MMC_DATA_READ) {
1252 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1253 BUS_DMASYNC_POSTREAD);
1254 } else {
1255 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map,
1256 BUS_DMASYNC_POSTWRITE);
1257 }
1258 bus_dmamap_unload(slot->adma2_tag, slot->adma2_map);
1259 } else if (!slot->data_done && (slot->flags & SDHCI_USE_SDMA)) {
1260 bus_dmamem_t *sdma = &slot->sdma_mem;
1261
1262 if (data->flags & MMC_DATA_READ) {
1263 size_t left = data->len - slot->offset;
1264 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1265 BUS_DMASYNC_POSTREAD);
1266 memcpy((u_char*)data->data + slot->offset,
1267 sdma->dmem_addr,
1268 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1269 } else {
1270 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1271 BUS_DMASYNC_POSTWRITE);
1272 }
1273 }
1274 slot->data_done = 1;
1275 /* If there was an error - reset the host. */
1276 if (slot->curcmd->error) {
1277 sdhci_reset(slot, SDHCI_RESET_CMD);
1278 sdhci_reset(slot, SDHCI_RESET_DATA);
1279 sdhci_start(slot);
1280 return;
1281 }
1282 /* If we already have command response - finish. */
1283 if (slot->cmd_done)
1284 sdhci_start(slot);
1285 }
1286
1287 static void
1288 sdhci_start(struct sdhci_slot *slot)
1289 {
1290 struct mmc_request *req;
1291
1292 req = slot->req;
1293 if (req == NULL)
1294 return;
1295
1296 if (!(slot->flags & CMD_STARTED)) {
1297 slot->flags |= CMD_STARTED;
1298 sdhci_start_command(slot, req->cmd);
1299 return;
1300 }
1301 /* We don't need this until using Auto-CMD12 feature
1302 if (!(slot->flags & STOP_STARTED) && req->stop) {
1303 slot->flags |= STOP_STARTED;
1304 sdhci_start_command(slot, req->stop);
1305 return;
1306 }
1307 */
1308 if (sdhci_debug > 1)
1309 slot_printf(slot, "result: %d\n", req->cmd->error);
1310 if (!req->cmd->error &&
1311 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1312 sdhci_reset(slot, SDHCI_RESET_CMD);
1313 sdhci_reset(slot, SDHCI_RESET_DATA);
1314 }
1315
1316 sdhci_req_done(slot);
1317 }
1318
1319 int
1320 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
1321 struct mmc_request *req)
1322 {
1323 struct sdhci_slot *slot = device_get_ivars(reqdev);
1324
1325 SDHCI_LOCK(slot);
1326 if (slot->req != NULL) {
1327 SDHCI_UNLOCK(slot);
1328 return (EBUSY);
1329 }
1330 if (sdhci_debug > 1) {
1331 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1332 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1333 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1334 (req->cmd->data)?req->cmd->data->flags:0);
1335 }
1336 slot->req = req;
1337 slot->flags = 0;
1338 sdhci_start(slot);
1339 SDHCI_UNLOCK(slot);
1340 if (dumping) {
1341 while (slot->req != NULL) {
1342 sdhci_generic_intr(slot);
1343 DELAY(10);
1344 }
1345 }
1346 return (0);
1347 }
1348
1349 int
1350 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
1351 {
1352 struct sdhci_slot *slot = device_get_ivars(reqdev);
1353 uint32_t val;
1354
1355 SDHCI_LOCK(slot);
1356 val = RD4(slot, SDHCI_PRESENT_STATE);
1357 SDHCI_UNLOCK(slot);
1358 return (!(val & SDHCI_WRITE_PROTECT));
1359 }
1360
1361 int
1362 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
1363 {
1364 struct sdhci_slot *slot = device_get_ivars(reqdev);
1365 int err = 0;
1366
1367 SDHCI_LOCK(slot);
1368 while (slot->bus_busy)
1369 lksleep(slot, &slot->lock, 0, "sdhciah", 0);
1370 slot->bus_busy++;
1371 /* Activate led. */
1372 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1373 SDHCI_UNLOCK(slot);
1374 return (err);
1375 }
1376
1377 int
1378 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
1379 {
1380 struct sdhci_slot *slot = device_get_ivars(reqdev);
1381
1382 SDHCI_LOCK(slot);
1383 /* Deactivate led. */
1384 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1385 slot->bus_busy--;
1386 SDHCI_UNLOCK(slot);
1387 wakeup(slot);
1388 return (0);
1389 }
1390
1391 static void
1392 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1393 {
1394
1395 if (!slot->curcmd) {
1396 slot_printf(slot, "Got command interrupt 0x%08x, but "
1397 "there is no active command.\n", intmask);
1398 sdhci_dumpregs(slot);
1399 return;
1400 }
1401 if (intmask & SDHCI_INT_TIMEOUT)
1402 slot->curcmd->error = MMC_ERR_TIMEOUT;
1403 else if (intmask & SDHCI_INT_CRC)
1404 slot->curcmd->error = MMC_ERR_BADCRC;
1405 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1406 slot->curcmd->error = MMC_ERR_FIFO;
1407
1408 sdhci_finish_command(slot);
1409 }
1410
1411 static void
1412 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1413 {
1414
1415 if (!slot->curcmd) {
1416 slot_printf(slot, "Got data interrupt 0x%08x, but "
1417 "there is no active command.\n", intmask);
1418 sdhci_dumpregs(slot);
1419 return;
1420 }
1421 if (slot->curcmd->data == NULL &&
1422 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1423 slot_printf(slot, "Got data interrupt 0x%08x, but "
1424 "there is no active data operation.\n",
1425 intmask);
1426 sdhci_dumpregs(slot);
1427 return;
1428 }
1429 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1430 slot->curcmd->error = MMC_ERR_TIMEOUT;
1431 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1432 slot->curcmd->error = MMC_ERR_BADCRC;
1433 if (slot->curcmd->data == NULL &&
1434 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1435 SDHCI_INT_DMA_END))) {
1436 slot_printf(slot, "Got data interrupt 0x%08x, but "
1437 "there is busy-only command.\n", intmask);
1438 sdhci_dumpregs(slot);
1439 slot->curcmd->error = MMC_ERR_INVALID;
1440 }
1441 if (slot->curcmd->error) {
1442 /* No need to continue after any error. */
1443 goto done;
1444 }
1445
1446 /* Handle PIO interrupt. */
1447 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1448 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1449 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1450 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1451 slot->flags |= PLATFORM_DATA_STARTED;
1452 } else
1453 sdhci_transfer_pio(slot);
1454 }
1455 /* Handle DMA border. */
1456 if (intmask & SDHCI_INT_DMA_END) {
1457 struct mmc_data *data = slot->curcmd->data;
1458 bus_dmamem_t *sdma = &slot->sdma_mem;
1459 size_t left;
1460
1461 /* Unload DMA buffer ... */
1462 left = data->len - slot->offset;
1463 if (data->flags & MMC_DATA_READ) {
1464 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1465 BUS_DMASYNC_POSTREAD);
1466 memcpy((u_char*)data->data + slot->offset,
1467 sdma->dmem_addr,
1468 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1469 } else {
1470 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1471 BUS_DMASYNC_POSTWRITE);
1472 }
1473 /* ... and reload it again. */
1474 slot->offset += DMA_BLOCK_SIZE;
1475 left = data->len - slot->offset;
1476 if (data->flags & MMC_DATA_READ) {
1477 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1478 BUS_DMASYNC_PREREAD);
1479 } else {
1480 memcpy(sdma->dmem_addr,
1481 (u_char*)data->data + slot->offset,
1482 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1483 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1484 BUS_DMASYNC_PREWRITE);
1485 }
1486 /* Interrupt aggregation: Mask border interrupt
1487 * for the last page. */
1488 if (left == DMA_BLOCK_SIZE) {
1489 slot->intmask &= ~SDHCI_INT_DMA_END;
1490 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1491 }
1492 /* Restart DMA. */
1493 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
1494 }
1495 /* We have got all data. */
1496 if (intmask & SDHCI_INT_DATA_END) {
1497 if (slot->flags & PLATFORM_DATA_STARTED) {
1498 slot->flags &= ~PLATFORM_DATA_STARTED;
1499 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1500 } else {
1501 sdhci_finish_data(slot);
1502 }
1503 }
1504 done:
1505 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1506 if (slot->flags & PLATFORM_DATA_STARTED) {
1507 slot->flags &= ~PLATFORM_DATA_STARTED;
1508 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1509 } else {
1510 sdhci_finish_data(slot);
1511 }
1512 return;
1513 }
1514 }
1515
1516 static void
1517 sdhci_acmd_irq(struct sdhci_slot *slot)
1518 {
1519 uint16_t err;
1520
1521 err = RD4(slot, SDHCI_ACMD12_ERR);
1522 if (!slot->curcmd) {
1523 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1524 "there is no active command.\n", err);
1525 sdhci_dumpregs(slot);
1526 return;
1527 }
1528 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1529 sdhci_reset(slot, SDHCI_RESET_CMD);
1530 }
1531
1532 static void
1533 sdhci_adma_irq(struct sdhci_slot *slot)
1534 {
1535 bus_dmamem_t *descmem = &slot->adma2_descs;
1536 struct sdhci_adma2_desc32 *desc;
1537 bus_addr_t addr = 0;
1538 uint8_t err, adma_state;
1539
1540 err = RD1(slot, SDHCI_ADMA_ERR);
1541 if (slot->curcmd && (slot->flags & SDHCI_USE_ADMA2)) {
1542 slot_printf(slot, "Got ADMA2 error 0x%02x\n", err);
1543 } else {
1544 slot_printf(slot, "Got ADMA2 error 0x%02x, but "
1545 "there is no active command.\n", err);
1546 sdhci_dumpregs(slot);
1547 }
1548
1549 /* Try to print the erronous ADMA2 descriptor */
1550 adma_state = err & SDHCI_ADMA_ERR_STATE_MASK;
1551 if (adma_state == SDHCI_ADMA_ERR_STATE_STOP) {
1552 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);
1553 if (addr > sizeof(*desc))
1554 addr -= sizeof(*desc);
1555 else
1556 addr = 0;
1557 } else if (adma_state == SDHCI_ADMA_ERR_STATE_FDS) {
1558 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);
1559 } else if (adma_state == SDHCI_ADMA_ERR_STATE_TFR) {
1560 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);
1561 if (addr > sizeof(*desc))
1562 addr -= sizeof(*desc);
1563 else
1564 addr = 0;
1565 } else {
1566 slot_printf(slot, "Invalid ADMA2 state 0x%02x\n", adma_state);
1567 }
1568 if (addr >= descmem->dmem_busaddr &&
1569 addr < descmem->dmem_busaddr + SDHCI_ADMA2_DESCBUF_SIZE) {
1570 desc = (void *) ((char *)descmem->dmem_addr +
1571 (addr - descmem->dmem_busaddr));
1572 slot_printf(slot,
1573 "Descriptor: Addr=0x%08x Length=0x%04x Attr=0x%04x\n",
1574 desc->address, desc->length, desc->attribute);
1575 }
1576
1577 if (slot->curcmd && (slot->flags & SDHCI_USE_ADMA2)) {
1578 sdhci_reset(slot, SDHCI_RESET_CMD);
1579 }
1580 }
1581
1582 void
1583 sdhci_generic_intr(struct sdhci_slot *slot)
1584 {
1585 uint32_t intmask;
1586
1587 SDHCI_LOCK(slot);
1588 /* Read slot interrupt status. */
1589 intmask = RD4(slot, SDHCI_INT_STATUS);
1590 if (intmask == 0 || intmask == 0xffffffff) {
1591 SDHCI_UNLOCK(slot);
1592 return;
1593 }
1594 if (sdhci_debug > 2)
1595 slot_printf(slot, "Interrupt %#x\n", intmask);
1596
1597 /* Handle card presence interrupts. */
1598 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1599 WR4(slot, SDHCI_INT_STATUS, intmask &
1600 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1601
1602 if (intmask & SDHCI_INT_CARD_REMOVE) {
1603 if (bootverbose || sdhci_debug)
1604 slot_printf(slot, "Card removed\n");
1605 callout_stop(&slot->card_callout);
1606 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task);
1607 }
1608 if (intmask & SDHCI_INT_CARD_INSERT) {
1609 if (bootverbose || sdhci_debug)
1610 slot_printf(slot, "Card inserted\n");
1611 callout_reset(&slot->card_callout, hz / 2,
1612 sdhci_card_delay, slot);
1613 }
1614 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1615 }
1616 /* Handle command interrupts. */
1617 if (intmask & SDHCI_INT_CMD_MASK) {
1618 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1619 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1620 }
1621 /* Handle data interrupts. */
1622 if (intmask & SDHCI_INT_DATA_MASK) {
1623 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1624 /* Dont call data_irq in case of errored command */
1625 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
1626 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1627 }
1628 /* Handle AutoCMD12 error interrupt. */
1629 if (intmask & SDHCI_INT_ACMD12ERR) {
1630 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1631 sdhci_acmd_irq(slot);
1632 }
1633 /* Handle ADMA2 error interrupt. */
1634 if (intmask & SDHCI_INT_ADMAERR) {
1635 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ADMAERR);
1636 sdhci_adma_irq(slot);
1637 }
1638 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1639 intmask &= ~SDHCI_INT_ACMD12ERR;
1640 intmask &= ~SDHCI_INT_ADMAERR;
1641 intmask &= ~SDHCI_INT_ERROR;
1642 /* Handle bus power interrupt. */
1643 if (intmask & SDHCI_INT_BUS_POWER) {
1644 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1645 slot_printf(slot,
1646 "Card is consuming too much power!\n");
1647 intmask &= ~SDHCI_INT_BUS_POWER;
1648 }
1649 /* The rest is unknown. */
1650 if (intmask) {
1651 WR4(slot, SDHCI_INT_STATUS, intmask);
1652 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1653 intmask);
1654 sdhci_dumpregs(slot);
1655 }
1656
1657 SDHCI_UNLOCK(slot);
1658 }
1659
1660 int
1661 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1662 {
1663 struct sdhci_slot *slot = device_get_ivars(child);
1664
1665 switch (which) {
1666 default:
1667 return (EINVAL);
1668 case MMCBR_IVAR_BUS_MODE:
1669 *(int *)result = slot->host.ios.bus_mode;
1670 break;
1671 case MMCBR_IVAR_BUS_WIDTH:
1672 *(int *)result = slot->host.ios.bus_width;
1673 break;
1674 case MMCBR_IVAR_CHIP_SELECT:
1675 *(int *)result = slot->host.ios.chip_select;
1676 break;
1677 case MMCBR_IVAR_CLOCK:
1678 *(int *)result = slot->host.ios.clock;
1679 break;
1680 case MMCBR_IVAR_F_MIN:
1681 *(int *)result = slot->host.f_min;
1682 break;
1683 case MMCBR_IVAR_F_MAX:
1684 *(int *)result = slot->host.f_max;
1685 break;
1686 case MMCBR_IVAR_HOST_OCR:
1687 *(int *)result = slot->host.host_ocr;
1688 break;
1689 case MMCBR_IVAR_MODE:
1690 *(int *)result = slot->host.mode;
1691 break;
1692 case MMCBR_IVAR_OCR:
1693 *(int *)result = slot->host.ocr;
1694 break;
1695 case MMCBR_IVAR_POWER_MODE:
1696 *(int *)result = slot->host.ios.power_mode;
1697 break;
1698 case MMCBR_IVAR_VDD:
1699 *(int *)result = slot->host.ios.vdd;
1700 break;
1701 case MMCBR_IVAR_CAPS:
1702 *(int *)result = slot->host.caps;
1703 break;
1704 case MMCBR_IVAR_TIMING:
1705 *(int *)result = slot->host.ios.timing;
1706 break;
1707 case MMCBR_IVAR_MAX_DATA:
1708 *(int *)result = 65535;
1709 break;
1710 }
1711 return (0);
1712 }
1713
1714 int
1715 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1716 {
1717 struct sdhci_slot *slot = device_get_ivars(child);
1718 uint32_t clock, max_clock;
1719 int i;
1720
1721 switch (which) {
1722 default:
1723 return (EINVAL);
1724 case MMCBR_IVAR_BUS_MODE:
1725 slot->host.ios.bus_mode = value;
1726 break;
1727 case MMCBR_IVAR_BUS_WIDTH:
1728 slot->host.ios.bus_width = value;
1729 break;
1730 case MMCBR_IVAR_CHIP_SELECT:
1731 slot->host.ios.chip_select = value;
1732 break;
1733 case MMCBR_IVAR_CLOCK:
1734 if (value > 0) {
1735 max_clock = slot->max_clk;
1736 clock = max_clock;
1737
1738 if (slot->version < SDHCI_SPEC_300) {
1739 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1740 i <<= 1) {
1741 if (clock <= value)
1742 break;
1743 clock >>= 1;
1744 }
1745 } else {
1746 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1747 i += 2) {
1748 if (clock <= value)
1749 break;
1750 clock = max_clock / (i + 2);
1751 }
1752 }
1753
1754 slot->host.ios.clock = clock;
1755 } else
1756 slot->host.ios.clock = 0;
1757 break;
1758 case MMCBR_IVAR_MODE:
1759 slot->host.mode = value;
1760 break;
1761 case MMCBR_IVAR_OCR:
1762 slot->host.ocr = value;
1763 break;
1764 case MMCBR_IVAR_POWER_MODE:
1765 slot->host.ios.power_mode = value;
1766 break;
1767 case MMCBR_IVAR_VDD:
1768 slot->host.ios.vdd = value;
1769 break;
1770 case MMCBR_IVAR_TIMING:
1771 slot->host.ios.timing = value;
1772 break;
1773 case MMCBR_IVAR_CAPS:
1774 case MMCBR_IVAR_HOST_OCR:
1775 case MMCBR_IVAR_F_MIN:
1776 case MMCBR_IVAR_F_MAX:
1777 case MMCBR_IVAR_MAX_DATA:
1778 return (EINVAL);
1779 }
1780 return (0);
1781 }
1782
1783 MODULE_VERSION(sdhci, 1);
DragonFly BSD