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[dragonfly.git] / share / mk / bsd.cpu.gcc50.mk
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1 # Set default CPU compile flags and baseline CPUTYPE for each arch. The
2 # compile flags must support the minimum CPU type for each architecture but
3 # may tune support for more advanced processors.
5 generic_x86_64= x86_64 mmx sse sse2
6 generic_i386= i386
8 .if !defined(CPUTYPE) || empty(CPUTYPE) || ${CPUTYPE} == "native"
10 . if defined(CPUTYPE) && ${CPUTYPE:Mnative}
11 _CPUCFLAGS= -march=native
12 . else
13 _CPUCFLAGS=
14 . endif
16 MACHINE_CPU= ${generic_${MACHINE_ARCH}}
18 .else
20 ###############################################################################
21 # Logic to set up correct gcc optimization flag. This must be included
22 # after /etc/make.conf so it can react to the local value of CPUTYPE
23 # defined therein. Consult:
24 # https://gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/x86-Options.html
25 ###############################################################################
27 # Some GCC cpu-types have aliases, rename them to a single identifier
28 # If the value for cpu-type is not recognized, throw it away and use -native
30 . if ${CPUTYPE} == "k8" \
31 || ${CPUTYPE} == "opteron" \
32 || ${CPUTYPE} == "athlon-fx"
33 CT2= athlon64
34 . elif ${CPUTYPE} == "k8-sse3" \
35 || ${CPUTYPE} == "opteron-sse3"
36 CT2= athlon64-sse3
37 . elif ${CPUTYPE} == "amdfam10"
38 CT2= barcelona
39 . else
40 CT2= ${CPUTYPE}
41 . endif
43 known_x86_64= athlon64 \
44 athlon64-sse3 \
45 barcelona \
46 bdver1 bdver2 bdver3 bdver4 \
47 bonnell \
48 broadwell \
49 btver1 btver2 \
50 core2 \
51 haswell \
52 i386 \
53 ivybridge \
54 knl \
55 nocona \
56 nehalem \
57 sandybridge \
58 silvermont \
59 skylake \
60 skylake-avx512 \
61 westmere \
62 znver1
64 known_i386= i386
66 . if defined(known_${MACHINE_ARCH}) && \
67 !empty(known_${MACHINE_ARCH}:M${CT2}) # CID: Check CPUTYPE
69 # Set up the list of CPU features based on the CPU type. This is an
70 # unordered list to make it easy for client makefiles to test for the
71 # presence of a CPU feature.
73 . if ${MACHINE_ARCH} == "x86_64"
74 C_nocona= ${generic_x86_64} sse3
75 C_core2= ${C_nocona} ssse3
76 C_nehalem= ${C_core2} sse41 sse42 popcnt
77 C_westmere= ${C_nehalem} aes pclmul
78 C_sandybridge= ${C_westmere} avx
79 C_ivybridge= ${C_sandybridge} fsgsbase rdrnd f16c
80 C_haswell= ${C_ivybridge} movbe avx2 fma bmi bmi2
81 C_broadwell= ${C_haswell} rdseed adcx prefetchw
82 C_skylake= ${C_broadwell} xsavec xsaves clflushop
83 C_knl= ${C_broadwell} avx512f avx512pf avx512er avx512cd
84 C_bonnell= ${C_core2} movbe
85 C_silvermont= ${C_westmere} movbe rdrnd
86 C_skylakeavx512=${C_skylake} pku avx512f avx512vl avx512bw avx512dq avx512cd
87 C_athlon64= ${generic_x86_64} 3dnow
88 C_athlon64sse3= ${C_athlon64} sse3
89 C_barcelona= ${C_athlon64sse3} sse4a abm
90 C_bdver1= ${C_core2} sse4a sse41 sse42 abm fma4 avx xop lwp aes \
91 pclmul cx16
92 C_bdver2= ${C_bdver1} bmi f16c fma tbm
93 C_bdver3= ${C_bdver2} fsgsbase
94 C_bdver4= ${C_bdver3} bmi2 avx2 movbe
95 C_znver1= ${C_core2} bmi bmi2 f16c fma fsgsbase avx avx2 adcx rdseed \
96 mwaitx sha clzero aes pclmul cx16 movbe sse4a sse41 sse42 \
97 abm xsavec xsaves clflushop popcnt
98 C_btver1= ${C_barcelona} cx16
99 C_btver2= ${C_btver1} movbe f16c bmi avx pclmul aes sse41 sse42
100 C_i386= ${generic_i386}
102 . endif # end of x86_64 feature list
104 # i386 used for 32-bit BIOS-based boot loaders
106 . if ${MACHINE_ARCH} == "i386"
107 C_i386= ${generic_i386}
108 . endif # end of i386 feature list
110 _CPUCFLAGS= -march=${CT2}
111 MACHINE_CPU= ${C_${CT2:S|-||}}
113 . else # CID: Check CPUTYPE
115 # CPUTYPE was defined and was not empty, but the value does not match known
116 # CPU types of the defined MACHINE_ARCH. Set -march to native and define
117 # generic features based on MACHINE_ARCH
119 _CPUCFLAGS= -march=native
120 MACHINE_CPU= ${generic_${MACHINE_ARCH}}
122 . endif # CID: Check CPUTYPE
124 .endif