2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
39 * $DragonFly: src/sys/platform/pc64/isa/clock.c,v 1.1 2008/08/29 17:07:19 dillon Exp $
43 * Routines to handle clock hardware.
47 * inittodr, settodr and support routines written
48 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
50 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 //#include "use_apm.h"
54 //#include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/eventhandler.h>
60 #include <sys/kernel.h>
65 #include <sys/sysctl.h>
67 #include <sys/systimer.h>
68 #include <sys/globaldata.h>
69 #include <sys/thread2.h>
70 #include <sys/systimer.h>
71 #include <sys/machintr.h>
73 #include <machine/clock.h>
74 #ifdef CLK_CALIBRATION_LOOP
76 #include <machine/cputypes.h>
77 #include <machine/frame.h>
78 #include <machine/ipl.h>
79 #include <machine/limits.h>
80 #include <machine/md_var.h>
81 #include <machine/psl.h>
82 #include <machine/segments.h>
83 #include <machine/smp.h>
84 #include <machine/specialreg.h>
86 #include <machine_base/icu/icu.h>
87 #include <bus/isa/isa.h>
88 #include <bus/isa/rtc.h>
89 #include <machine_base/isa/timerreg.h>
91 #include <machine_base/isa/intr_machdep.h>
94 /* The interrupt triggered by the 8254 (timer) chip */
96 static void setup_8254_mixed_mode (void);
98 static void i8254_restore(void);
99 static void resettodr_on_shutdown(void *arg __unused
);
102 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
103 * can use a simple formula for leap years.
105 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
106 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
109 #define TIMER_FREQ 1193182
112 static uint8_t i8254_walltimer_sel
;
113 static uint16_t i8254_walltimer_cntr
;
115 int adjkerntz
; /* local offset from GMT in seconds */
116 int disable_rtc_set
; /* disable resettodr() if != 0 */
117 int statclock_disable
= 1; /* we don't use the statclock right now */
119 int64_t tsc_frequency
;
121 int wall_cmos_clock
; /* wall CMOS clock assumed if != 0 */
123 enum tstate
{ RELEASED
, ACQUIRED
};
124 enum tstate timer0_state
;
125 enum tstate timer1_state
;
126 enum tstate timer2_state
;
128 static int beeping
= 0;
129 static const u_char daysinmonth
[] = {31,28,31,30,31,30,31,31,30,31,30,31};
130 static u_char rtc_statusa
= RTCSA_DIVIDER
| RTCSA_NOPROF
;
131 static u_char rtc_statusb
= RTCSB_24HR
| RTCSB_PINTR
;
132 static int rtc_loaded
;
134 static int i8254_cputimer_div
;
136 static struct callout sysbeepstop_ch
;
138 static sysclock_t
i8254_cputimer_count(void);
139 static void i8254_cputimer_construct(struct cputimer
*cputimer
, sysclock_t last
);
140 static void i8254_cputimer_destruct(struct cputimer
*cputimer
);
142 static struct cputimer i8254_cputimer
= {
143 SLIST_ENTRY_INITIALIZER
,
147 i8254_cputimer_count
,
148 cputimer_default_fromhz
,
149 cputimer_default_fromus
,
150 i8254_cputimer_construct
,
151 i8254_cputimer_destruct
,
157 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
158 * counting as of this interrupt. We use timer1 in free-running mode (not
159 * generating any interrupts) as our main counter. Each cpu has timeouts
162 * This code is INTR_MPSAFE and may be called without the BGL held.
165 clkintr(void *dummy
, void *frame_arg
)
167 static sysclock_t sysclock_count
; /* NOTE! Must be static */
168 struct globaldata
*gd
= mycpu
;
170 struct globaldata
*gscan
;
175 * SWSTROBE mode is a one-shot, the timer is no longer running
180 * XXX the dispatcher needs work. right now we call systimer_intr()
181 * directly or via IPI for any cpu with systimers queued, which is
182 * usually *ALL* of them. We need to use the LAPIC timer for this.
184 sysclock_count
= sys_cputimer
->count();
186 for (n
= 0; n
< ncpus
; ++n
) {
187 gscan
= globaldata_find(n
);
188 if (TAILQ_FIRST(&gscan
->gd_systimerq
) == NULL
)
191 lwkt_send_ipiq3(gscan
, (ipifunc3_t
)systimer_intr
,
194 systimer_intr(&sysclock_count
, 0, frame_arg
);
198 if (TAILQ_FIRST(&gd
->gd_systimerq
) != NULL
)
199 systimer_intr(&sysclock_count
, 0, frame_arg
);
208 acquire_timer2(int mode
)
210 if (timer2_state
!= RELEASED
)
212 timer2_state
= ACQUIRED
;
215 * This access to the timer registers is as atomic as possible
216 * because it is a single instruction. We could do better if we
219 outb(TIMER_MODE
, TIMER_SEL2
| (mode
& 0x3f));
226 if (timer2_state
!= ACQUIRED
)
228 outb(TIMER_MODE
, TIMER_SEL2
| TIMER_SQWAVE
| TIMER_16BIT
);
229 timer2_state
= RELEASED
;
234 * This routine receives statistical clock interrupts from the RTC.
235 * As explained above, these occur at 128 interrupts per second.
236 * When profiling, we receive interrupts at a rate of 1024 Hz.
238 * This does not actually add as much overhead as it sounds, because
239 * when the statistical clock is active, the hardclock driver no longer
240 * needs to keep (inaccurate) statistics on its own. This decouples
241 * statistics gathering from scheduling interrupts.
243 * The RTC chip requires that we read status register C (RTC_INTR)
244 * to acknowledge an interrupt, before it will generate the next one.
245 * Under high interrupt load, rtcintr() can be indefinitely delayed and
246 * the clock can tick immediately after the read from RTC_INTR. In this
247 * case, the mc146818A interrupt signal will not drop for long enough
248 * to register with the 8259 PIC. If an interrupt is missed, the stat
249 * clock will halt, considerably degrading system performance. This is
250 * why we use 'while' rather than a more straightforward 'if' below.
251 * Stat clock ticks can still be lost, causing minor loss of accuracy
252 * in the statistics, but the stat clock will no longer stop.
255 rtcintr(void *dummy
, void *frame
)
257 while (rtcin(RTC_INTR
) & RTCIR_PERIOD
)
259 /* statclock(frame); no longer used */
266 DB_SHOW_COMMAND(rtc
, rtc
)
268 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
269 rtcin(RTC_YEAR
), rtcin(RTC_MONTH
), rtcin(RTC_DAY
),
270 rtcin(RTC_HRS
), rtcin(RTC_MIN
), rtcin(RTC_SEC
),
271 rtcin(RTC_STATUSA
), rtcin(RTC_STATUSB
), rtcin(RTC_INTR
));
276 * Return the current cpu timer count as a 32 bit integer.
280 i8254_cputimer_count(void)
282 static __uint16_t cputimer_last
;
287 outb(TIMER_MODE
, i8254_walltimer_sel
| TIMER_LATCH
);
288 count
= (__uint8_t
)inb(i8254_walltimer_cntr
); /* get countdown */
289 count
|= ((__uint8_t
)inb(i8254_walltimer_cntr
) << 8);
290 count
= -count
; /* -> countup */
291 if (count
< cputimer_last
) /* rollover */
292 i8254_cputimer
.base
+= 0x00010000;
293 ret
= i8254_cputimer
.base
| count
;
294 cputimer_last
= count
;
300 * This function is called whenever the system timebase changes, allowing
301 * us to calculate what is needed to convert a system timebase tick
302 * into an 8254 tick for the interrupt timer. If we can convert to a
303 * simple shift, multiplication, or division, we do so. Otherwise 64
304 * bit arithmatic is required every time the interrupt timer is reloaded.
307 cputimer_intr_config(struct cputimer
*timer
)
313 * Will a simple divide do the trick?
315 div
= (timer
->freq
+ (i8254_cputimer
.freq
/ 2)) / i8254_cputimer
.freq
;
316 freq
= i8254_cputimer
.freq
* div
;
318 if (freq
>= timer
->freq
- 1 && freq
<= timer
->freq
+ 1)
319 i8254_cputimer_div
= div
;
321 i8254_cputimer_div
= 0;
325 * Reload for the next timeout. It is possible for the reload value
326 * to be 0 or negative, indicating that an immediate timer interrupt
327 * is desired. For now make the minimum 2 ticks.
329 * We may have to convert from the system timebase to the 8254 timebase.
332 cputimer_intr_reload(sysclock_t reload
)
336 if (i8254_cputimer_div
)
337 reload
/= i8254_cputimer_div
;
339 reload
= (int64_t)reload
* i8254_cputimer
.freq
/ sys_cputimer
->freq
;
345 if (timer0_running
) {
346 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_LATCH
); /* count-down timer */
347 count
= (__uint8_t
)inb(TIMER_CNTR0
); /* lsb */
348 count
|= ((__uint8_t
)inb(TIMER_CNTR0
) << 8); /* msb */
349 if (reload
< count
) {
350 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_SWSTROBE
| TIMER_16BIT
);
351 outb(TIMER_CNTR0
, (__uint8_t
)reload
); /* lsb */
352 outb(TIMER_CNTR0
, (__uint8_t
)(reload
>> 8)); /* msb */
357 reload
= 0; /* full count */
358 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_SWSTROBE
| TIMER_16BIT
);
359 outb(TIMER_CNTR0
, (__uint8_t
)reload
); /* lsb */
360 outb(TIMER_CNTR0
, (__uint8_t
)(reload
>> 8)); /* msb */
366 cputimer_intr_enable(void)
371 * DELAY(usec) - Spin for the specified number of microseconds.
372 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
373 * but do a thread switch in the loop
375 * Relies on timer 1 counting down from (cputimer_freq / hz)
376 * Note: timer had better have been programmed before this is first used!
379 DODELAY(int n
, int doswitch
)
381 int delta
, prev_tick
, tick
, ticks_left
;
386 static int state
= 0;
390 for (n1
= 1; n1
<= 10000000; n1
*= 10)
395 kprintf("DELAY(%d)...", n
);
398 * Guard against the timer being uninitialized if we are called
399 * early for console i/o.
401 if (timer0_state
== RELEASED
)
405 * Read the counter first, so that the rest of the setup overhead is
406 * counted. Then calculate the number of hardware timer ticks
407 * required, rounding up to be sure we delay at least the requested
408 * number of microseconds.
410 prev_tick
= sys_cputimer
->count();
411 ticks_left
= ((u_int
)n
* (int64_t)sys_cputimer
->freq
+ 999999) /
417 while (ticks_left
> 0) {
418 tick
= sys_cputimer
->count();
422 delta
= tick
- prev_tick
;
427 if (doswitch
&& ticks_left
> 0)
432 kprintf(" %d calls to getit() at %d usec each\n",
433 getit_calls
, (n
+ 5) / getit_calls
);
444 DRIVERSLEEP(int usec
)
446 globaldata_t gd
= mycpu
;
448 if (gd
->gd_intr_nesting_level
||
449 gd
->gd_spinlock_rd
||
450 gd
->gd_spinlocks_wr
) {
458 sysbeepstop(void *chan
)
460 outb(IO_PPI
, inb(IO_PPI
)&0xFC); /* disable counter2 output to speaker */
466 sysbeep(int pitch
, int period
)
468 if (acquire_timer2(TIMER_SQWAVE
|TIMER_16BIT
))
471 * Nobody else is using timer2, we do not need the clock lock
473 outb(TIMER_CNTR2
, pitch
);
474 outb(TIMER_CNTR2
, (pitch
>>8));
476 /* enable counter2 output to speaker */
477 outb(IO_PPI
, inb(IO_PPI
) | 3);
479 callout_reset(&sysbeepstop_ch
, period
, sysbeepstop
, NULL
);
485 * RTC support routines
496 val
= inb(IO_RTC
+ 1);
503 writertc(u_char reg
, u_char val
)
509 outb(IO_RTC
+ 1, val
);
510 inb(0x84); /* XXX work around wrong order in rtcin() */
517 return(bcd2bin(rtcin(port
)));
521 calibrate_clocks(void)
524 u_int count
, prev_count
, tot_count
;
525 int sec
, start_sec
, timeout
;
528 kprintf("Calibrating clock(s) ... ");
529 if (!(rtcin(RTC_STATUSD
) & RTCSD_PWR
))
533 /* Read the mc146818A seconds counter. */
535 if (!(rtcin(RTC_STATUSA
) & RTCSA_TUP
)) {
536 sec
= rtcin(RTC_SEC
);
543 /* Wait for the mC146818A seconds counter to change. */
546 if (!(rtcin(RTC_STATUSA
) & RTCSA_TUP
)) {
547 sec
= rtcin(RTC_SEC
);
548 if (sec
!= start_sec
)
555 /* Start keeping track of the i8254 counter. */
556 prev_count
= sys_cputimer
->count();
562 old_tsc
= 0; /* shut up gcc */
565 * Wait for the mc146818A seconds counter to change. Read the i8254
566 * counter for each iteration since this is convenient and only
567 * costs a few usec of inaccuracy. The timing of the final reads
568 * of the counters almost matches the timing of the initial reads,
569 * so the main cause of inaccuracy is the varying latency from
570 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
571 * rtcin(RTC_SEC) that returns a changed seconds count. The
572 * maximum inaccuracy from this cause is < 10 usec on 486's.
576 if (!(rtcin(RTC_STATUSA
) & RTCSA_TUP
))
577 sec
= rtcin(RTC_SEC
);
578 count
= sys_cputimer
->count();
579 tot_count
+= (int)(count
- prev_count
);
581 if (sec
!= start_sec
)
588 * Read the cpu cycle counter. The timing considerations are
589 * similar to those for the i8254 clock.
592 tsc_frequency
= rdtsc() - old_tsc
;
596 kprintf("TSC clock: %llu Hz, ", tsc_frequency
);
597 kprintf("i8254 clock: %u Hz\n", tot_count
);
601 kprintf("failed, using default i8254 clock of %u Hz\n",
602 i8254_cputimer
.freq
);
603 return (i8254_cputimer
.freq
);
609 timer0_state
= ACQUIRED
;
614 * Timer0 is our fine-grained variable clock interrupt
616 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_SWSTROBE
| TIMER_16BIT
);
617 outb(TIMER_CNTR0
, 2); /* lsb */
618 outb(TIMER_CNTR0
, 0); /* msb */
622 * Timer1 or timer2 is our free-running clock, but only if another
623 * has not been selected.
625 cputimer_register(&i8254_cputimer
);
626 cputimer_select(&i8254_cputimer
, 0);
630 i8254_cputimer_construct(struct cputimer
*timer
, sysclock_t oldclock
)
635 * Should we use timer 1 or timer 2 ?
638 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which
);
639 if (which
!= 1 && which
!= 2)
644 timer
->name
= "i8254_timer1";
645 timer
->type
= CPUTIMER_8254_SEL1
;
646 i8254_walltimer_sel
= TIMER_SEL1
;
647 i8254_walltimer_cntr
= TIMER_CNTR1
;
648 timer1_state
= ACQUIRED
;
651 timer
->name
= "i8254_timer2";
652 timer
->type
= CPUTIMER_8254_SEL2
;
653 i8254_walltimer_sel
= TIMER_SEL2
;
654 i8254_walltimer_cntr
= TIMER_CNTR2
;
655 timer2_state
= ACQUIRED
;
659 timer
->base
= (oldclock
+ 0xFFFF) & ~0xFFFF;
662 outb(TIMER_MODE
, i8254_walltimer_sel
| TIMER_RATEGEN
| TIMER_16BIT
);
663 outb(i8254_walltimer_cntr
, 0); /* lsb */
664 outb(i8254_walltimer_cntr
, 0); /* msb */
665 outb(IO_PPI
, inb(IO_PPI
) | 1); /* bit 0: enable gate, bit 1: spkr */
670 i8254_cputimer_destruct(struct cputimer
*timer
)
672 switch(timer
->type
) {
673 case CPUTIMER_8254_SEL1
:
674 timer1_state
= RELEASED
;
676 case CPUTIMER_8254_SEL2
:
677 timer2_state
= RELEASED
;
688 /* Restore all of the RTC's "status" (actually, control) registers. */
689 writertc(RTC_STATUSB
, RTCSB_24HR
);
690 writertc(RTC_STATUSA
, rtc_statusa
);
691 writertc(RTC_STATUSB
, rtc_statusb
);
695 * Restore all the timers.
697 * This function is called to resynchronize our core timekeeping after a
698 * long halt, e.g. from apm_default_resume() and friends. It is also
699 * called if after a BIOS call we have detected munging of the 8254.
700 * It is necessary because cputimer_count() counter's delta may have grown
701 * too large for nanouptime() and friends to handle, or (in the case of 8254
702 * munging) might cause the SYSTIMER code to prematurely trigger.
708 i8254_restore(); /* restore timer_freq and hz */
709 rtc_restore(); /* reenable RTC interrupts */
714 * Initialize 8254 timer 0 early so that it can be used in DELAY().
722 * Can we use the TSC?
724 if (cpu_feature
& CPUID_TSC
)
730 * Initial RTC state, don't do anything unexpected
732 writertc(RTC_STATUSA
, rtc_statusa
);
733 writertc(RTC_STATUSB
, RTCSB_24HR
);
736 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
737 * generate an interrupt, which we will ignore for now.
739 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
740 * (so it counts a full 2^16 and repeats). We will use this timer
744 freq
= calibrate_clocks();
745 #ifdef CLK_CALIBRATION_LOOP
748 "Press a key on the console to abort clock calibration\n");
749 while (cncheckc() == -1)
755 * Use the calibrated i8254 frequency if it seems reasonable.
756 * Otherwise use the default, and don't use the calibrated i586
759 delta
= freq
> i8254_cputimer
.freq
?
760 freq
- i8254_cputimer
.freq
: i8254_cputimer
.freq
- freq
;
761 if (delta
< i8254_cputimer
.freq
/ 100) {
762 #ifndef CLK_USE_I8254_CALIBRATION
765 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
766 freq
= i8254_cputimer
.freq
;
768 cputimer_set_frequency(&i8254_cputimer
, freq
);
772 "%d Hz differs from default of %d Hz by more than 1%%\n",
773 freq
, i8254_cputimer
.freq
);
777 #ifndef CLK_USE_TSC_CALIBRATION
778 if (tsc_frequency
!= 0) {
781 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
785 if (tsc_present
&& tsc_frequency
== 0) {
787 * Calibration of the i586 clock relative to the mc146818A
788 * clock failed. Do a less accurate calibration relative
789 * to the i8254 clock.
791 u_int64_t old_tsc
= rdtsc();
794 tsc_frequency
= rdtsc() - old_tsc
;
795 #ifdef CLK_USE_TSC_CALIBRATION
797 kprintf("TSC clock: %llu Hz (Method B)\n",
803 EVENTHANDLER_REGISTER(shutdown_post_sync
, resettodr_on_shutdown
, NULL
, SHUTDOWN_PRI_LAST
);
807 * We can not use the TSC in SMP mode, until we figure out a
808 * cheap (impossible), reliable and precise (yeah right!) way
809 * to synchronize the TSCs of all the CPUs.
810 * Curse Intel for leaving the counter out of the I/O APIC.
815 * We can not use the TSC if we support APM. Precise timekeeping
816 * on an APM'ed machine is at best a fools pursuit, since
817 * any and all of the time spent in various SMM code can't
818 * be reliably accounted for. Reading the RTC is your only
819 * source of reliable time info. The i8254 looses too of course
820 * but we need to have some kind of time...
821 * We don't know at this point whether APM is going to be used
822 * or not, nor when it might be activated. Play it safe.
825 #endif /* NAPM > 0 */
827 #endif /* !defined(SMP) */
831 * Sync the time of day back to the RTC on shutdown, but only if
832 * we have already loaded it and have not crashed.
835 resettodr_on_shutdown(void *arg __unused
)
837 if (rtc_loaded
&& panicstr
== NULL
) {
843 * Initialize the time of day register, based on the time base which is, e.g.
847 inittodr(time_t base
)
849 unsigned long sec
, days
;
861 /* Look if we have a RTC present and the time is valid */
862 if (!(rtcin(RTC_STATUSD
) & RTCSD_PWR
))
865 /* wait for time update to complete */
866 /* If RTCSA_TUP is zero, we have at least 244us before next update */
868 while (rtcin(RTC_STATUSA
) & RTCSA_TUP
) {
874 #ifdef USE_RTC_CENTURY
875 year
= readrtc(RTC_YEAR
) + readrtc(RTC_CENTURY
) * 100;
877 year
= readrtc(RTC_YEAR
) + 1900;
885 month
= readrtc(RTC_MONTH
);
886 for (m
= 1; m
< month
; m
++)
887 days
+= daysinmonth
[m
-1];
888 if ((month
> 2) && LEAPYEAR(year
))
890 days
+= readrtc(RTC_DAY
) - 1;
892 for (y
= 1970; y
< year
; y
++)
893 days
+= DAYSPERYEAR
+ LEAPYEAR(y
);
894 sec
= ((( days
* 24 +
895 readrtc(RTC_HRS
)) * 60 +
896 readrtc(RTC_MIN
)) * 60 +
898 /* sec now contains the number of seconds, since Jan 1 1970,
899 in the local time zone */
901 sec
+= tz
.tz_minuteswest
* 60 + (wall_cmos_clock
? adjkerntz
: 0);
903 y
= time_second
- sec
;
904 if (y
<= -2 || y
>= 2) {
905 /* badly off, adjust it */
915 kprintf("Invalid time in real time clock.\n");
916 kprintf("Check and reset the date immediately!\n");
920 * Write system time back to RTC
937 /* Disable RTC updates and interrupts. */
938 writertc(RTC_STATUSB
, RTCSB_HALT
| RTCSB_24HR
);
940 /* Calculate local time to put in RTC */
942 tm
-= tz
.tz_minuteswest
* 60 + (wall_cmos_clock
? adjkerntz
: 0);
944 writertc(RTC_SEC
, bin2bcd(tm
%60)); tm
/= 60; /* Write back Seconds */
945 writertc(RTC_MIN
, bin2bcd(tm
%60)); tm
/= 60; /* Write back Minutes */
946 writertc(RTC_HRS
, bin2bcd(tm
%24)); tm
/= 24; /* Write back Hours */
948 /* We have now the days since 01-01-1970 in tm */
949 writertc(RTC_WDAY
, (tm
+4)%7); /* Write back Weekday */
950 for (y
= 1970, m
= DAYSPERYEAR
+ LEAPYEAR(y
);
952 y
++, m
= DAYSPERYEAR
+ LEAPYEAR(y
))
955 /* Now we have the years in y and the day-of-the-year in tm */
956 writertc(RTC_YEAR
, bin2bcd(y
%100)); /* Write back Year */
957 #ifdef USE_RTC_CENTURY
958 writertc(RTC_CENTURY
, bin2bcd(y
/100)); /* ... and Century */
964 if (m
== 1 && LEAPYEAR(y
))
971 writertc(RTC_MONTH
, bin2bcd(m
+ 1)); /* Write back Month */
972 writertc(RTC_DAY
, bin2bcd(tm
+ 1)); /* Write back Month Day */
974 /* Reenable RTC updates and interrupts. */
975 writertc(RTC_STATUSB
, rtc_statusb
);
981 * Start both clocks running. DragonFly note: the stat clock is no longer
982 * used. Instead, 8254 based systimers are used for all major clock
983 * interrupts. statclock_disable is set by default.
986 cpu_initclocks(void *arg __unused
)
994 if (statclock_disable
) {
996 * The stat interrupt mask is different without the
997 * statistics clock. Also, don't set the interrupt
998 * flag which would normally cause the RTC to generate
1001 rtc_statusb
= RTCSB_24HR
;
1003 /* Setting stathz to nonzero early helps avoid races. */
1004 stathz
= RTC_NOPROFRATE
;
1005 profhz
= RTC_PROFRATE
;
1008 /* Finish initializing 8253 timer 0. */
1011 apic_8254_intr
= isa_apic_irq(0);
1012 apic_8254_trial
= 0;
1013 if (apic_8254_intr
>= 0 ) {
1014 if (apic_int_type(0, 0) == 3)
1015 apic_8254_trial
= 1;
1017 /* look for ExtInt on pin 0 */
1018 if (apic_int_type(0, 0) == 3) {
1019 apic_8254_intr
= apic_irq(0, 0);
1020 setup_8254_mixed_mode();
1022 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1025 clkdesc
= register_int(apic_8254_intr
, clkintr
, NULL
, "clk",
1027 INTR_EXCL
| INTR_FAST
|
1028 INTR_NOPOLL
| INTR_MPSAFE
|
1030 machintr_intren(apic_8254_intr
);
1034 register_int(0, clkintr
, NULL
, "clk", NULL
,
1035 INTR_EXCL
| INTR_FAST
|
1036 INTR_NOPOLL
| INTR_MPSAFE
|
1038 machintr_intren(ICU_IRQ0
);
1040 #endif /* APIC_IO */
1042 /* Initialize RTC. */
1043 writertc(RTC_STATUSA
, rtc_statusa
);
1044 writertc(RTC_STATUSB
, RTCSB_24HR
);
1046 if (statclock_disable
== 0) {
1047 diag
= rtcin(RTC_DIAG
);
1049 kprintf("RTC BIOS diagnostic error %b\n", diag
, RTCDG_BITS
);
1052 if (isa_apic_irq(8) != 8)
1053 panic("APIC RTC != 8");
1054 #endif /* APIC_IO */
1056 register_int(8, (inthand2_t
*)rtcintr
, NULL
, "rtc", NULL
,
1057 INTR_EXCL
| INTR_FAST
| INTR_NOPOLL
|
1061 writertc(RTC_STATUSB
, rtc_statusb
);
1065 if (apic_8254_trial
) {
1069 lastcnt
= get_interrupt_counter(apic_8254_intr
);
1072 * XXX this assumes the 8254 is the cpu timer. Force an
1073 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
1074 * then see if we got it.
1076 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1077 cputimer_intr_reload(2); /* XXX assumes 8254 */
1078 base
= sys_cputimer
->count();
1079 while (sys_cputimer
->count() - base
< sys_cputimer
->freq
/ 100)
1081 if (get_interrupt_counter(apic_8254_intr
) - lastcnt
== 0) {
1083 * The MP table is broken.
1084 * The 8254 was not connected to the specified pin
1086 * Workaround: Limited variant of mixed mode.
1088 machintr_intrdis(apic_8254_intr
);
1089 unregister_int(clkdesc
);
1090 kprintf("APIC_IO: Broken MP table detected: "
1091 "8254 is not connected to "
1092 "IOAPIC #%d intpin %d\n",
1093 int_to_apicintpin
[apic_8254_intr
].ioapic
,
1094 int_to_apicintpin
[apic_8254_intr
].int_pin
);
1096 * Revoke current ISA IRQ 0 assignment and
1097 * configure a fallback interrupt routing from
1098 * the 8254 Timer via the 8259 PIC to the
1099 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1100 * We reuse the low level interrupt handler number.
1102 if (apic_irq(0, 0) < 0) {
1103 revoke_apic_irq(apic_8254_intr
);
1104 assign_apic_irq(0, 0, apic_8254_intr
);
1106 apic_8254_intr
= apic_irq(0, 0);
1107 setup_8254_mixed_mode();
1108 register_int(apic_8254_intr
, clkintr
, NULL
, "clk",
1110 INTR_EXCL
| INTR_FAST
|
1111 INTR_NOPOLL
| INTR_MPSAFE
|
1113 machintr_intren(apic_8254_intr
);
1117 if (apic_int_type(0, 0) != 3 ||
1118 int_to_apicintpin
[apic_8254_intr
].ioapic
!= 0 ||
1119 int_to_apicintpin
[apic_8254_intr
].int_pin
!= 0) {
1120 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1121 int_to_apicintpin
[apic_8254_intr
].ioapic
,
1122 int_to_apicintpin
[apic_8254_intr
].int_pin
);
1125 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1128 callout_init(&sysbeepstop_ch
);
1130 SYSINIT(clocks8254
, SI_BOOT2_CLOCKREG
, SI_ORDER_FIRST
, cpu_initclocks
, NULL
)
1135 setup_8254_mixed_mode(void)
1138 * Allow 8254 timer to INTerrupt 8259:
1139 * re-initialize master 8259:
1140 * reset; prog 4 bytes, single ICU, edge triggered
1142 outb(IO_ICU1
, 0x13);
1143 outb(IO_ICU1
+ 1, IDT_OFFSET
); /* start vector (unused) */
1144 outb(IO_ICU1
+ 1, 0x00); /* ignore slave */
1145 outb(IO_ICU1
+ 1, 0x03); /* auto EOI, 8086 */
1146 outb(IO_ICU1
+ 1, 0xfe); /* unmask INT0 */
1148 /* program IO APIC for type 3 INT on INT0 */
1149 if (ext_int_setup(0, 0) < 0)
1150 panic("8254 redirect via APIC pin0 impossible!");
1155 setstatclockrate(int newhz
)
1157 if (newhz
== RTC_PROFRATE
)
1158 rtc_statusa
= RTCSA_DIVIDER
| RTCSA_PROF
;
1160 rtc_statusa
= RTCSA_DIVIDER
| RTCSA_NOPROF
;
1161 writertc(RTC_STATUSA
, rtc_statusa
);
1166 tsc_get_timecount(struct timecounter
*tc
)
1172 #ifdef KERN_TIMESTAMP
1173 #define KERN_TIMESTAMP_SIZE 16384
1174 static u_long tsc
[KERN_TIMESTAMP_SIZE
] ;
1175 SYSCTL_OPAQUE(_debug
, OID_AUTO
, timestamp
, CTLFLAG_RD
, tsc
,
1176 sizeof(tsc
), "LU", "Kernel timestamps");
1182 tsc
[i
] = (u_int32_t
)rdtsc();
1185 if (i
>= KERN_TIMESTAMP_SIZE
)
1187 tsc
[i
] = 0; /* mark last entry */
1189 #endif /* KERN_TIMESTAMP */
1196 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS
)
1203 if (sys_cputimer
== &i8254_cputimer
)
1204 count
= sys_cputimer
->count();
1212 ksnprintf(buf
, sizeof(buf
), "%08x %016llx", count
, (long long)tscval
);
1213 return(SYSCTL_OUT(req
, buf
, strlen(buf
) + 1));
1216 SYSCTL_NODE(_hw
, OID_AUTO
, i8254
, CTLFLAG_RW
, 0, "I8254");
1217 SYSCTL_UINT(_hw_i8254
, OID_AUTO
, freq
, CTLFLAG_RD
, &i8254_cputimer
.freq
, 0,
1219 SYSCTL_PROC(_hw_i8254
, OID_AUTO
, timestamp
, CTLTYPE_STRING
|CTLFLAG_RD
,
1220 0, 0, hw_i8254_timestamp
, "A", "");
1222 SYSCTL_INT(_hw
, OID_AUTO
, tsc_present
, CTLFLAG_RD
,
1223 &tsc_present
, 0, "TSC Available");
1224 SYSCTL_QUAD(_hw
, OID_AUTO
, tsc_frequency
, CTLFLAG_RD
,
1225 &tsc_frequency
, 0, "TSC Frequency");