2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.55 2008/08/02 01:14:43 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/eventhandler.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
70 #include <sys/machintr.h>
72 #include <machine/clock.h>
73 #ifdef CLK_CALIBRATION_LOOP
75 #include <machine/cputypes.h>
76 #include <machine/frame.h>
77 #include <machine/ipl.h>
78 #include <machine/limits.h>
79 #include <machine/md_var.h>
80 #include <machine/psl.h>
81 #include <machine/segments.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
85 #include <machine_base/icu/icu.h>
86 #include <bus/isa/isa.h>
87 #include <bus/isa/rtc.h>
88 #include <machine_base/isa/timerreg.h>
90 #include <machine_base/isa/intr_machdep.h>
93 /* The interrupt triggered by the 8254 (timer) chip */
95 static void setup_8254_mixed_mode (void);
97 static void i8254_restore(void);
98 static void resettodr_on_shutdown(void *arg __unused
);
101 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
102 * can use a simple formula for leap years.
104 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
105 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
108 #define TIMER_FREQ 1193182
111 static uint8_t i8254_walltimer_sel
;
112 static uint16_t i8254_walltimer_cntr
;
114 int adjkerntz
; /* local offset from GMT in seconds */
115 int disable_rtc_set
; /* disable resettodr() if != 0 */
116 int statclock_disable
= 1; /* we don't use the statclock right now */
118 int64_t tsc_frequency
;
120 int wall_cmos_clock
; /* wall CMOS clock assumed if != 0 */
122 enum tstate
{ RELEASED
, ACQUIRED
};
123 enum tstate timer0_state
;
124 enum tstate timer1_state
;
125 enum tstate timer2_state
;
127 static int beeping
= 0;
128 static const u_char daysinmonth
[] = {31,28,31,30,31,30,31,31,30,31,30,31};
129 static u_char rtc_statusa
= RTCSA_DIVIDER
| RTCSA_NOPROF
;
130 static u_char rtc_statusb
= RTCSB_24HR
| RTCSB_PINTR
;
131 static int rtc_loaded
;
133 static int i8254_cputimer_div
;
135 static struct callout sysbeepstop_ch
;
137 static sysclock_t
i8254_cputimer_count(void);
138 static void i8254_cputimer_construct(struct cputimer
*cputimer
, sysclock_t last
);
139 static void i8254_cputimer_destruct(struct cputimer
*cputimer
);
141 static struct cputimer i8254_cputimer
= {
142 SLIST_ENTRY_INITIALIZER
,
146 i8254_cputimer_count
,
147 cputimer_default_fromhz
,
148 cputimer_default_fromus
,
149 i8254_cputimer_construct
,
150 i8254_cputimer_destruct
,
156 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
157 * counting as of this interrupt. We use timer1 in free-running mode (not
158 * generating any interrupts) as our main counter. Each cpu has timeouts
161 * This code is INTR_MPSAFE and may be called without the BGL held.
164 clkintr(void *dummy
, void *frame_arg
)
166 static sysclock_t sysclock_count
; /* NOTE! Must be static */
167 struct globaldata
*gd
= mycpu
;
169 struct globaldata
*gscan
;
174 * SWSTROBE mode is a one-shot, the timer is no longer running
179 * XXX the dispatcher needs work. right now we call systimer_intr()
180 * directly or via IPI for any cpu with systimers queued, which is
181 * usually *ALL* of them. We need to use the LAPIC timer for this.
183 sysclock_count
= sys_cputimer
->count();
185 for (n
= 0; n
< ncpus
; ++n
) {
186 gscan
= globaldata_find(n
);
187 if (TAILQ_FIRST(&gscan
->gd_systimerq
) == NULL
)
190 lwkt_send_ipiq3(gscan
, (ipifunc3_t
)systimer_intr
,
193 systimer_intr(&sysclock_count
, 0, frame_arg
);
197 if (TAILQ_FIRST(&gd
->gd_systimerq
) != NULL
)
198 systimer_intr(&sysclock_count
, 0, frame_arg
);
207 acquire_timer2(int mode
)
209 if (timer2_state
!= RELEASED
)
211 timer2_state
= ACQUIRED
;
214 * This access to the timer registers is as atomic as possible
215 * because it is a single instruction. We could do better if we
218 outb(TIMER_MODE
, TIMER_SEL2
| (mode
& 0x3f));
225 if (timer2_state
!= ACQUIRED
)
227 outb(TIMER_MODE
, TIMER_SEL2
| TIMER_SQWAVE
| TIMER_16BIT
);
228 timer2_state
= RELEASED
;
233 * This routine receives statistical clock interrupts from the RTC.
234 * As explained above, these occur at 128 interrupts per second.
235 * When profiling, we receive interrupts at a rate of 1024 Hz.
237 * This does not actually add as much overhead as it sounds, because
238 * when the statistical clock is active, the hardclock driver no longer
239 * needs to keep (inaccurate) statistics on its own. This decouples
240 * statistics gathering from scheduling interrupts.
242 * The RTC chip requires that we read status register C (RTC_INTR)
243 * to acknowledge an interrupt, before it will generate the next one.
244 * Under high interrupt load, rtcintr() can be indefinitely delayed and
245 * the clock can tick immediately after the read from RTC_INTR. In this
246 * case, the mc146818A interrupt signal will not drop for long enough
247 * to register with the 8259 PIC. If an interrupt is missed, the stat
248 * clock will halt, considerably degrading system performance. This is
249 * why we use 'while' rather than a more straightforward 'if' below.
250 * Stat clock ticks can still be lost, causing minor loss of accuracy
251 * in the statistics, but the stat clock will no longer stop.
254 rtcintr(void *dummy
, void *frame
)
256 while (rtcin(RTC_INTR
) & RTCIR_PERIOD
)
258 /* statclock(frame); no longer used */
265 DB_SHOW_COMMAND(rtc
, rtc
)
267 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
268 rtcin(RTC_YEAR
), rtcin(RTC_MONTH
), rtcin(RTC_DAY
),
269 rtcin(RTC_HRS
), rtcin(RTC_MIN
), rtcin(RTC_SEC
),
270 rtcin(RTC_STATUSA
), rtcin(RTC_STATUSB
), rtcin(RTC_INTR
));
275 * Return the current cpu timer count as a 32 bit integer.
279 i8254_cputimer_count(void)
281 static __uint16_t cputimer_last
;
286 outb(TIMER_MODE
, i8254_walltimer_sel
| TIMER_LATCH
);
287 count
= (__uint8_t
)inb(i8254_walltimer_cntr
); /* get countdown */
288 count
|= ((__uint8_t
)inb(i8254_walltimer_cntr
) << 8);
289 count
= -count
; /* -> countup */
290 if (count
< cputimer_last
) /* rollover */
291 i8254_cputimer
.base
+= 0x00010000;
292 ret
= i8254_cputimer
.base
| count
;
293 cputimer_last
= count
;
299 * This function is called whenever the system timebase changes, allowing
300 * us to calculate what is needed to convert a system timebase tick
301 * into an 8254 tick for the interrupt timer. If we can convert to a
302 * simple shift, multiplication, or division, we do so. Otherwise 64
303 * bit arithmatic is required every time the interrupt timer is reloaded.
306 cputimer_intr_config(struct cputimer
*timer
)
312 * Will a simple divide do the trick?
314 div
= (timer
->freq
+ (i8254_cputimer
.freq
/ 2)) / i8254_cputimer
.freq
;
315 freq
= i8254_cputimer
.freq
* div
;
317 if (freq
>= timer
->freq
- 1 && freq
<= timer
->freq
+ 1)
318 i8254_cputimer_div
= div
;
320 i8254_cputimer_div
= 0;
324 * Reload for the next timeout. It is possible for the reload value
325 * to be 0 or negative, indicating that an immediate timer interrupt
326 * is desired. For now make the minimum 2 ticks.
328 * We may have to convert from the system timebase to the 8254 timebase.
331 i8254_intr_reload(sysclock_t reload
)
335 if (i8254_cputimer_div
)
336 reload
/= i8254_cputimer_div
;
338 reload
= (int64_t)reload
* i8254_cputimer
.freq
/ sys_cputimer
->freq
;
344 if (timer0_running
) {
345 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_LATCH
); /* count-down timer */
346 count
= (__uint8_t
)inb(TIMER_CNTR0
); /* lsb */
347 count
|= ((__uint8_t
)inb(TIMER_CNTR0
) << 8); /* msb */
348 if (reload
< count
) {
349 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_SWSTROBE
| TIMER_16BIT
);
350 outb(TIMER_CNTR0
, (__uint8_t
)reload
); /* lsb */
351 outb(TIMER_CNTR0
, (__uint8_t
)(reload
>> 8)); /* msb */
356 reload
= 0; /* full count */
357 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_SWSTROBE
| TIMER_16BIT
);
358 outb(TIMER_CNTR0
, (__uint8_t
)reload
); /* lsb */
359 outb(TIMER_CNTR0
, (__uint8_t
)(reload
>> 8)); /* msb */
365 extern void lapic_timer_intr_reload(sysclock_t
);
369 cputimer_intr_reload(sysclock_t reload
)
371 i8254_intr_reload(reload
);
373 lapic_timer_intr_reload(reload
);
378 cputimer_intr_enable(void)
383 * DELAY(usec) - Spin for the specified number of microseconds.
384 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
385 * but do a thread switch in the loop
387 * Relies on timer 1 counting down from (cputimer_freq / hz)
388 * Note: timer had better have been programmed before this is first used!
391 DODELAY(int n
, int doswitch
)
393 int delta
, prev_tick
, tick
, ticks_left
;
398 static int state
= 0;
402 for (n1
= 1; n1
<= 10000000; n1
*= 10)
407 kprintf("DELAY(%d)...", n
);
410 * Guard against the timer being uninitialized if we are called
411 * early for console i/o.
413 if (timer0_state
== RELEASED
)
417 * Read the counter first, so that the rest of the setup overhead is
418 * counted. Then calculate the number of hardware timer ticks
419 * required, rounding up to be sure we delay at least the requested
420 * number of microseconds.
422 prev_tick
= sys_cputimer
->count();
423 ticks_left
= ((u_int
)n
* (int64_t)sys_cputimer
->freq
+ 999999) /
429 while (ticks_left
> 0) {
430 tick
= sys_cputimer
->count();
434 delta
= tick
- prev_tick
;
439 if (doswitch
&& ticks_left
> 0)
444 kprintf(" %d calls to getit() at %d usec each\n",
445 getit_calls
, (n
+ 5) / getit_calls
);
456 DRIVERSLEEP(int usec
)
458 globaldata_t gd
= mycpu
;
460 if (gd
->gd_intr_nesting_level
||
461 gd
->gd_spinlock_rd
||
462 gd
->gd_spinlocks_wr
) {
470 sysbeepstop(void *chan
)
472 outb(IO_PPI
, inb(IO_PPI
)&0xFC); /* disable counter2 output to speaker */
478 sysbeep(int pitch
, int period
)
480 if (acquire_timer2(TIMER_SQWAVE
|TIMER_16BIT
))
483 * Nobody else is using timer2, we do not need the clock lock
485 outb(TIMER_CNTR2
, pitch
);
486 outb(TIMER_CNTR2
, (pitch
>>8));
488 /* enable counter2 output to speaker */
489 outb(IO_PPI
, inb(IO_PPI
) | 3);
491 callout_reset(&sysbeepstop_ch
, period
, sysbeepstop
, NULL
);
497 * RTC support routines
508 val
= inb(IO_RTC
+ 1);
515 writertc(u_char reg
, u_char val
)
521 outb(IO_RTC
+ 1, val
);
522 inb(0x84); /* XXX work around wrong order in rtcin() */
529 return(bcd2bin(rtcin(port
)));
533 calibrate_clocks(void)
536 u_int count
, prev_count
, tot_count
;
537 int sec
, start_sec
, timeout
;
540 kprintf("Calibrating clock(s) ... ");
541 if (!(rtcin(RTC_STATUSD
) & RTCSD_PWR
))
545 /* Read the mc146818A seconds counter. */
547 if (!(rtcin(RTC_STATUSA
) & RTCSA_TUP
)) {
548 sec
= rtcin(RTC_SEC
);
555 /* Wait for the mC146818A seconds counter to change. */
558 if (!(rtcin(RTC_STATUSA
) & RTCSA_TUP
)) {
559 sec
= rtcin(RTC_SEC
);
560 if (sec
!= start_sec
)
567 /* Start keeping track of the i8254 counter. */
568 prev_count
= sys_cputimer
->count();
574 old_tsc
= 0; /* shut up gcc */
577 * Wait for the mc146818A seconds counter to change. Read the i8254
578 * counter for each iteration since this is convenient and only
579 * costs a few usec of inaccuracy. The timing of the final reads
580 * of the counters almost matches the timing of the initial reads,
581 * so the main cause of inaccuracy is the varying latency from
582 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
583 * rtcin(RTC_SEC) that returns a changed seconds count. The
584 * maximum inaccuracy from this cause is < 10 usec on 486's.
588 if (!(rtcin(RTC_STATUSA
) & RTCSA_TUP
))
589 sec
= rtcin(RTC_SEC
);
590 count
= sys_cputimer
->count();
591 tot_count
+= (int)(count
- prev_count
);
593 if (sec
!= start_sec
)
600 * Read the cpu cycle counter. The timing considerations are
601 * similar to those for the i8254 clock.
604 tsc_frequency
= rdtsc() - old_tsc
;
608 kprintf("TSC clock: %llu Hz, ", tsc_frequency
);
609 kprintf("i8254 clock: %u Hz\n", tot_count
);
613 kprintf("failed, using default i8254 clock of %u Hz\n",
614 i8254_cputimer
.freq
);
615 return (i8254_cputimer
.freq
);
621 timer0_state
= ACQUIRED
;
626 * Timer0 is our fine-grained variable clock interrupt
628 outb(TIMER_MODE
, TIMER_SEL0
| TIMER_SWSTROBE
| TIMER_16BIT
);
629 outb(TIMER_CNTR0
, 2); /* lsb */
630 outb(TIMER_CNTR0
, 0); /* msb */
634 * Timer1 or timer2 is our free-running clock, but only if another
635 * has not been selected.
637 cputimer_register(&i8254_cputimer
);
638 cputimer_select(&i8254_cputimer
, 0);
642 i8254_cputimer_construct(struct cputimer
*timer
, sysclock_t oldclock
)
647 * Should we use timer 1 or timer 2 ?
650 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which
);
651 if (which
!= 1 && which
!= 2)
656 timer
->name
= "i8254_timer1";
657 timer
->type
= CPUTIMER_8254_SEL1
;
658 i8254_walltimer_sel
= TIMER_SEL1
;
659 i8254_walltimer_cntr
= TIMER_CNTR1
;
660 timer1_state
= ACQUIRED
;
663 timer
->name
= "i8254_timer2";
664 timer
->type
= CPUTIMER_8254_SEL2
;
665 i8254_walltimer_sel
= TIMER_SEL2
;
666 i8254_walltimer_cntr
= TIMER_CNTR2
;
667 timer2_state
= ACQUIRED
;
671 timer
->base
= (oldclock
+ 0xFFFF) & ~0xFFFF;
674 outb(TIMER_MODE
, i8254_walltimer_sel
| TIMER_RATEGEN
| TIMER_16BIT
);
675 outb(i8254_walltimer_cntr
, 0); /* lsb */
676 outb(i8254_walltimer_cntr
, 0); /* msb */
677 outb(IO_PPI
, inb(IO_PPI
) | 1); /* bit 0: enable gate, bit 1: spkr */
682 i8254_cputimer_destruct(struct cputimer
*timer
)
684 switch(timer
->type
) {
685 case CPUTIMER_8254_SEL1
:
686 timer1_state
= RELEASED
;
688 case CPUTIMER_8254_SEL2
:
689 timer2_state
= RELEASED
;
700 /* Restore all of the RTC's "status" (actually, control) registers. */
701 writertc(RTC_STATUSB
, RTCSB_24HR
);
702 writertc(RTC_STATUSA
, rtc_statusa
);
703 writertc(RTC_STATUSB
, rtc_statusb
);
707 * Restore all the timers.
709 * This function is called to resynchronize our core timekeeping after a
710 * long halt, e.g. from apm_default_resume() and friends. It is also
711 * called if after a BIOS call we have detected munging of the 8254.
712 * It is necessary because cputimer_count() counter's delta may have grown
713 * too large for nanouptime() and friends to handle, or (in the case of 8254
714 * munging) might cause the SYSTIMER code to prematurely trigger.
720 i8254_restore(); /* restore timer_freq and hz */
721 rtc_restore(); /* reenable RTC interrupts */
726 * Initialize 8254 timer 0 early so that it can be used in DELAY().
734 * Can we use the TSC?
736 if (cpu_feature
& CPUID_TSC
)
742 * Initial RTC state, don't do anything unexpected
744 writertc(RTC_STATUSA
, rtc_statusa
);
745 writertc(RTC_STATUSB
, RTCSB_24HR
);
748 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
749 * generate an interrupt, which we will ignore for now.
751 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
752 * (so it counts a full 2^16 and repeats). We will use this timer
756 freq
= calibrate_clocks();
757 #ifdef CLK_CALIBRATION_LOOP
760 "Press a key on the console to abort clock calibration\n");
761 while (cncheckc() == -1)
767 * Use the calibrated i8254 frequency if it seems reasonable.
768 * Otherwise use the default, and don't use the calibrated i586
771 delta
= freq
> i8254_cputimer
.freq
?
772 freq
- i8254_cputimer
.freq
: i8254_cputimer
.freq
- freq
;
773 if (delta
< i8254_cputimer
.freq
/ 100) {
774 #ifndef CLK_USE_I8254_CALIBRATION
777 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
778 freq
= i8254_cputimer
.freq
;
780 cputimer_set_frequency(&i8254_cputimer
, freq
);
784 "%d Hz differs from default of %d Hz by more than 1%%\n",
785 freq
, i8254_cputimer
.freq
);
789 #ifndef CLK_USE_TSC_CALIBRATION
790 if (tsc_frequency
!= 0) {
793 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
797 if (tsc_present
&& tsc_frequency
== 0) {
799 * Calibration of the i586 clock relative to the mc146818A
800 * clock failed. Do a less accurate calibration relative
801 * to the i8254 clock.
803 u_int64_t old_tsc
= rdtsc();
806 tsc_frequency
= rdtsc() - old_tsc
;
807 #ifdef CLK_USE_TSC_CALIBRATION
809 kprintf("TSC clock: %llu Hz (Method B)\n",
815 EVENTHANDLER_REGISTER(shutdown_post_sync
, resettodr_on_shutdown
, NULL
, SHUTDOWN_PRI_LAST
);
819 * We can not use the TSC in SMP mode, until we figure out a
820 * cheap (impossible), reliable and precise (yeah right!) way
821 * to synchronize the TSCs of all the CPUs.
822 * Curse Intel for leaving the counter out of the I/O APIC.
827 * We can not use the TSC if we support APM. Precise timekeeping
828 * on an APM'ed machine is at best a fools pursuit, since
829 * any and all of the time spent in various SMM code can't
830 * be reliably accounted for. Reading the RTC is your only
831 * source of reliable time info. The i8254 looses too of course
832 * but we need to have some kind of time...
833 * We don't know at this point whether APM is going to be used
834 * or not, nor when it might be activated. Play it safe.
837 #endif /* NAPM > 0 */
839 #endif /* !defined(SMP) */
843 * Sync the time of day back to the RTC on shutdown, but only if
844 * we have already loaded it and have not crashed.
847 resettodr_on_shutdown(void *arg __unused
)
849 if (rtc_loaded
&& panicstr
== NULL
) {
855 * Initialize the time of day register, based on the time base which is, e.g.
859 inittodr(time_t base
)
861 unsigned long sec
, days
;
873 /* Look if we have a RTC present and the time is valid */
874 if (!(rtcin(RTC_STATUSD
) & RTCSD_PWR
))
877 /* wait for time update to complete */
878 /* If RTCSA_TUP is zero, we have at least 244us before next update */
880 while (rtcin(RTC_STATUSA
) & RTCSA_TUP
) {
886 #ifdef USE_RTC_CENTURY
887 year
= readrtc(RTC_YEAR
) + readrtc(RTC_CENTURY
) * 100;
889 year
= readrtc(RTC_YEAR
) + 1900;
897 month
= readrtc(RTC_MONTH
);
898 for (m
= 1; m
< month
; m
++)
899 days
+= daysinmonth
[m
-1];
900 if ((month
> 2) && LEAPYEAR(year
))
902 days
+= readrtc(RTC_DAY
) - 1;
904 for (y
= 1970; y
< year
; y
++)
905 days
+= DAYSPERYEAR
+ LEAPYEAR(y
);
906 sec
= ((( days
* 24 +
907 readrtc(RTC_HRS
)) * 60 +
908 readrtc(RTC_MIN
)) * 60 +
910 /* sec now contains the number of seconds, since Jan 1 1970,
911 in the local time zone */
913 sec
+= tz
.tz_minuteswest
* 60 + (wall_cmos_clock
? adjkerntz
: 0);
915 y
= time_second
- sec
;
916 if (y
<= -2 || y
>= 2) {
917 /* badly off, adjust it */
927 kprintf("Invalid time in real time clock.\n");
928 kprintf("Check and reset the date immediately!\n");
932 * Write system time back to RTC
949 /* Disable RTC updates and interrupts. */
950 writertc(RTC_STATUSB
, RTCSB_HALT
| RTCSB_24HR
);
952 /* Calculate local time to put in RTC */
954 tm
-= tz
.tz_minuteswest
* 60 + (wall_cmos_clock
? adjkerntz
: 0);
956 writertc(RTC_SEC
, bin2bcd(tm
%60)); tm
/= 60; /* Write back Seconds */
957 writertc(RTC_MIN
, bin2bcd(tm
%60)); tm
/= 60; /* Write back Minutes */
958 writertc(RTC_HRS
, bin2bcd(tm
%24)); tm
/= 24; /* Write back Hours */
960 /* We have now the days since 01-01-1970 in tm */
961 writertc(RTC_WDAY
, (tm
+4)%7); /* Write back Weekday */
962 for (y
= 1970, m
= DAYSPERYEAR
+ LEAPYEAR(y
);
964 y
++, m
= DAYSPERYEAR
+ LEAPYEAR(y
))
967 /* Now we have the years in y and the day-of-the-year in tm */
968 writertc(RTC_YEAR
, bin2bcd(y
%100)); /* Write back Year */
969 #ifdef USE_RTC_CENTURY
970 writertc(RTC_CENTURY
, bin2bcd(y
/100)); /* ... and Century */
976 if (m
== 1 && LEAPYEAR(y
))
983 writertc(RTC_MONTH
, bin2bcd(m
+ 1)); /* Write back Month */
984 writertc(RTC_DAY
, bin2bcd(tm
+ 1)); /* Write back Month Day */
986 /* Reenable RTC updates and interrupts. */
987 writertc(RTC_STATUSB
, rtc_statusb
);
993 * Start both clocks running. DragonFly note: the stat clock is no longer
994 * used. Instead, 8254 based systimers are used for all major clock
995 * interrupts. statclock_disable is set by default.
998 cpu_initclocks(void *arg __unused
)
1002 int apic_8254_trial
;
1004 #endif /* APIC_IO */
1006 callout_init(&sysbeepstop_ch
);
1008 if (statclock_disable
) {
1010 * The stat interrupt mask is different without the
1011 * statistics clock. Also, don't set the interrupt
1012 * flag which would normally cause the RTC to generate
1015 rtc_statusb
= RTCSB_24HR
;
1017 /* Setting stathz to nonzero early helps avoid races. */
1018 stathz
= RTC_NOPROFRATE
;
1019 profhz
= RTC_PROFRATE
;
1022 /* Finish initializing 8253 timer 0. */
1025 apic_8254_intr
= isa_apic_irq(0);
1026 apic_8254_trial
= 0;
1027 if (apic_8254_intr
>= 0 ) {
1028 if (apic_int_type(0, 0) == 3)
1029 apic_8254_trial
= 1;
1031 /* look for ExtInt on pin 0 */
1032 if (apic_int_type(0, 0) == 3) {
1033 apic_8254_intr
= apic_irq(0, 0);
1034 setup_8254_mixed_mode();
1036 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1039 clkdesc
= register_int(apic_8254_intr
, clkintr
, NULL
, "clk",
1041 INTR_EXCL
| INTR_FAST
|
1042 INTR_NOPOLL
| INTR_MPSAFE
|
1044 machintr_intren(apic_8254_intr
);
1048 register_int(0, clkintr
, NULL
, "clk", NULL
,
1049 INTR_EXCL
| INTR_FAST
|
1050 INTR_NOPOLL
| INTR_MPSAFE
|
1052 machintr_intren(ICU_IRQ0
);
1054 #endif /* APIC_IO */
1056 /* Initialize RTC. */
1057 writertc(RTC_STATUSA
, rtc_statusa
);
1058 writertc(RTC_STATUSB
, RTCSB_24HR
);
1060 if (statclock_disable
== 0) {
1061 diag
= rtcin(RTC_DIAG
);
1063 kprintf("RTC BIOS diagnostic error %b\n", diag
, RTCDG_BITS
);
1066 if (isa_apic_irq(8) != 8)
1067 panic("APIC RTC != 8");
1068 #endif /* APIC_IO */
1070 register_int(8, (inthand2_t
*)rtcintr
, NULL
, "rtc", NULL
,
1071 INTR_EXCL
| INTR_FAST
| INTR_NOPOLL
|
1075 writertc(RTC_STATUSB
, rtc_statusb
);
1079 if (apic_8254_trial
) {
1084 * Following code assumes the 8254 is the cpu timer,
1085 * so make sure it is.
1087 KKASSERT(sys_cputimer
== &i8254_cputimer
);
1089 lastcnt
= get_interrupt_counter(apic_8254_intr
);
1092 * Force an 8254 Timer0 interrupt and wait 1/100s for
1093 * it to happen, then see if we got it.
1095 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1096 i8254_intr_reload(2);
1097 base
= sys_cputimer
->count();
1098 while (sys_cputimer
->count() - base
< sys_cputimer
->freq
/ 100)
1100 if (get_interrupt_counter(apic_8254_intr
) - lastcnt
== 0) {
1102 * The MP table is broken.
1103 * The 8254 was not connected to the specified pin
1105 * Workaround: Limited variant of mixed mode.
1107 machintr_intrdis(apic_8254_intr
);
1108 unregister_int(clkdesc
);
1109 kprintf("APIC_IO: Broken MP table detected: "
1110 "8254 is not connected to "
1111 "IOAPIC #%d intpin %d\n",
1112 int_to_apicintpin
[apic_8254_intr
].ioapic
,
1113 int_to_apicintpin
[apic_8254_intr
].int_pin
);
1115 * Revoke current ISA IRQ 0 assignment and
1116 * configure a fallback interrupt routing from
1117 * the 8254 Timer via the 8259 PIC to the
1118 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1119 * We reuse the low level interrupt handler number.
1121 if (apic_irq(0, 0) < 0) {
1122 revoke_apic_irq(apic_8254_intr
);
1123 assign_apic_irq(0, 0, apic_8254_intr
);
1125 apic_8254_intr
= apic_irq(0, 0);
1126 setup_8254_mixed_mode();
1127 register_int(apic_8254_intr
, clkintr
, NULL
, "clk",
1129 INTR_EXCL
| INTR_FAST
|
1130 INTR_NOPOLL
| INTR_MPSAFE
|
1132 machintr_intren(apic_8254_intr
);
1136 if (apic_int_type(0, 0) != 3 ||
1137 int_to_apicintpin
[apic_8254_intr
].ioapic
!= 0 ||
1138 int_to_apicintpin
[apic_8254_intr
].int_pin
!= 0) {
1139 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1140 int_to_apicintpin
[apic_8254_intr
].ioapic
,
1141 int_to_apicintpin
[apic_8254_intr
].int_pin
);
1144 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1148 SYSINIT(clocks8254
, SI_BOOT2_CLOCKREG
, SI_ORDER_FIRST
, cpu_initclocks
, NULL
)
1153 setup_8254_mixed_mode(void)
1156 * Allow 8254 timer to INTerrupt 8259:
1157 * re-initialize master 8259:
1158 * reset; prog 4 bytes, single ICU, edge triggered
1160 outb(IO_ICU1
, 0x13);
1161 outb(IO_ICU1
+ 1, IDT_OFFSET
); /* start vector (unused) */
1162 outb(IO_ICU1
+ 1, 0x00); /* ignore slave */
1163 outb(IO_ICU1
+ 1, 0x03); /* auto EOI, 8086 */
1164 outb(IO_ICU1
+ 1, 0xfe); /* unmask INT0 */
1166 /* program IO APIC for type 3 INT on INT0 */
1167 if (ext_int_setup(0, 0) < 0)
1168 panic("8254 redirect via APIC pin0 impossible!");
1173 setstatclockrate(int newhz
)
1175 if (newhz
== RTC_PROFRATE
)
1176 rtc_statusa
= RTCSA_DIVIDER
| RTCSA_PROF
;
1178 rtc_statusa
= RTCSA_DIVIDER
| RTCSA_NOPROF
;
1179 writertc(RTC_STATUSA
, rtc_statusa
);
1184 tsc_get_timecount(struct timecounter
*tc
)
1190 #ifdef KERN_TIMESTAMP
1191 #define KERN_TIMESTAMP_SIZE 16384
1192 static u_long tsc
[KERN_TIMESTAMP_SIZE
] ;
1193 SYSCTL_OPAQUE(_debug
, OID_AUTO
, timestamp
, CTLFLAG_RD
, tsc
,
1194 sizeof(tsc
), "LU", "Kernel timestamps");
1200 tsc
[i
] = (u_int32_t
)rdtsc();
1203 if (i
>= KERN_TIMESTAMP_SIZE
)
1205 tsc
[i
] = 0; /* mark last entry */
1207 #endif /* KERN_TIMESTAMP */
1214 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS
)
1221 if (sys_cputimer
== &i8254_cputimer
)
1222 count
= sys_cputimer
->count();
1230 ksnprintf(buf
, sizeof(buf
), "%08x %016llx", count
, (long long)tscval
);
1231 return(SYSCTL_OUT(req
, buf
, strlen(buf
) + 1));
1234 SYSCTL_NODE(_hw
, OID_AUTO
, i8254
, CTLFLAG_RW
, 0, "I8254");
1235 SYSCTL_UINT(_hw_i8254
, OID_AUTO
, freq
, CTLFLAG_RD
, &i8254_cputimer
.freq
, 0,
1237 SYSCTL_PROC(_hw_i8254
, OID_AUTO
, timestamp
, CTLTYPE_STRING
|CTLFLAG_RD
,
1238 0, 0, hw_i8254_timestamp
, "A", "");
1240 SYSCTL_INT(_hw
, OID_AUTO
, tsc_present
, CTLFLAG_RD
,
1241 &tsc_present
, 0, "TSC Available");
1242 SYSCTL_QUAD(_hw
, OID_AUTO
, tsc_frequency
, CTLFLAG_RD
,
1243 &tsc_frequency
, 0, "TSC Frequency");