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AHCI - Misc fixes
[dragonfly.git] / sys / dev / disk / ahci / ahci.h
bloba289b5faffe52abb2085b8d39629e7d5f8def2b1
1 /*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
17 */
18
19 #if defined(__DragonFly__)
20 #include "ahci_dragonfly.h"
21 #else
22 #error "build for OS unknown"
23 #endif
24 #include "pmreg.h"
25 #include "atascsi.h"
26
27 /* change to AHCI_DEBUG for dmesg spam */
28 #define NO_AHCI_DEBUG
29
30 #ifdef AHCI_DEBUG
31 #define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \
32 while (0)
33 #define AHCI_D_TIMEOUT 0x00
34 #define AHCI_D_VERBOSE 0x01
35 #define AHCI_D_INTR 0x02
36 #define AHCI_D_XFER 0x08
37 int ahcidebug = AHCI_D_VERBOSE;
38 #else
39 #define DPRINTF(m, f...)
40 #endif
41
42 #define AHCI_PCI_ATI_SB600_MAGIC 0x40
43 #define AHCI_PCI_ATI_SB600_LOCKED 0x01
44
45 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */
46 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
47 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
48 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
49 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
50 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
51 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
52 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
53 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
54 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching Supp */
55 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
56 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
57 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
58 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
59 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
60 #define AHCI_REG_CAP_ISS_G2 (0x2<<20) /* Gen 2 (3 Gbps) */
61 #define AHCI_REG_CAP_ISS_G3 (0x3<<20) /* Gen 3 (6 Gbps) */
62 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
63 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
64 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
65 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
66 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
67 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
68 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
69 #define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */
70 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
71 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
72 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
73 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
74 "\010CCCS" "\007EMS" "\006SXS"
75
76 #define AHCI_REG_GHC 0x004 /* Global HBA Control */
77 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
78 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
79 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
80 #define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */
81 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
82
83 #define AHCI_REG_IS 0x008 /* Interrupt Status */
84 #define AHCI_REG_PI 0x00c /* Ports Implemented */
85
86 #define AHCI_REG_VS 0x010 /* AHCI Version */
87 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
88 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
89 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
90 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
91 #define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */
92 #define AHCI_REG_VS_1_4 0x00010400 /* 1.4 */
93 #define AHCI_REG_VS_1_5 0x00010500 /* 1.5 (future...) */
94
95 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
96 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
97
98 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
99 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
100 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
101
102 #define AHCI_REG_CAP2 0x024 /* Host Capabilities Extended */
103 #define AHCI_REG_CAP2_BOH (1<<0) /* BIOS/OS Handoff */
104 #define AHCI_REG_CAP2_NVMP (1<<1) /* NVMHCI Present */
105 #define AHCI_REG_CAP2_APST (1<<2) /* A-Partial to Slumber Trans */
106 #define AHCI_REG_CAP2_SDS (1<<3) /* Supports DevSleep */
107 #define AHCI_REG_CAP2_SADM (1<<4) /* Supports A-DevSleep Mgmt */
108 #define AHCI_REG_CAP2_DESO (1<<5) /* DevSleep only from Slumber */
109 #define AHCI_FMT_CAP2 "\020" "\006DESO" "\005SADM" "\004SDS" \
110 "\003APST" "\002NVMP" "\001BOH"
111
112 #define AHCI_REG_BOHC 0x028 /* BIOS/OS Handoff Control and Status */
113 #define AHCI_REG_BOHC_BOS (1<<0) /* BIOS Owned Semaphore */
114 #define AHCI_REG_BOHC_OOS (1<<1) /* OS Owned Semaphore */
115 #define AHCI_REG_BOHC_SOOE (1<<2) /* SMI on OS Own chg enable */
116 #define AHCI_REG_BOHC_OOC (1<<3) /* OS Ownership Change */
117 #define AHCI_REG_BOHC_BB (1<<4) /* BIOS Busy */
118 #define AHCI_FMT_BOHC "\020" "\005BB" "\004OOC" "\003SOOE" \
119 "\002OOS" "\001BOS"
120
121 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
122 #define AHCI_PORT_SIZE 0x80
123
124 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
125 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
126 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */
127 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
128
129 #define AHCI_PREG_IS 0x10 /* Interrupt Status */
130 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
131 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
132 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
133 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
134 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
135 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
136 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
137 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
138 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
139 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
140 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
141 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
142 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
143 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
144 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
145 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
146 #define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */
147 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
148 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
149 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
150 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
151 "\002PSS" "\001DHRS"
152
153 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */
154 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
155 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
156 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
157 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
158 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
159 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
160 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
161 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
162 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
163 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
164 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
165 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
166 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
167 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
168 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
169 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
170 #define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */
171 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
172 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
173 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
174 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
175 "\002PSE" "\001DHRE"
176
177 /*
178 * NOTE: bits 22, 21, 20, 19, 18, 16, 15, 14, 13, 12:08, 07:05 are always
179 * read-only. Other bits may be read-only when the related feature
180 * is not supported by the HBA.
181 */
182 #define AHCI_PREG_CMD 0x18 /* Command and Status */
183 #define AHCI_PREG_CMD_ST (1<<0) /* Start */
184 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
185 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
186 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
187 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
188 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
189 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
190 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
191 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
192 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
193 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
194 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
195 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
196 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
197 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
198 #define AHCI_PREG_CMD_FBSCP (1<<22) /* FIS-based sw capable port */
199 #define AHCI_PREG_CMD_APSTE (1<<23) /* Auto Partial to Slumber */
200 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
201 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
202 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
203 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
204 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
205 #define AHCI_PREG_CMD_ICC_DEVSLEEP 0x80000000
206 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
207 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
208 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
209 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000
210 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
211 "\031ATAPI" "\030APSTE" "\027FBSCP" \
212 "\026ESP" "\025CPD" "\024MPSP" \
213 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \
214 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \
215 "\003POD" "\002SUD" "\001ST"
216
217 #define AHCI_PREG_TFD 0x20 /* Task File Data*/
218 #define AHCI_PREG_TFD_STS 0xff
219 #define AHCI_PREG_TFD_STS_ERR (1<<0)
220 #define AHCI_PREG_TFD_STS_DRQ (1<<3)
221 #define AHCI_PREG_TFD_STS_BSY (1<<7)
222 #define AHCI_PREG_TFD_ERR 0xff00
223
224 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
225 #define AHCI_PREG_SIG 0x24 /* Signature */
226
227 #define AHCI_PREG_SSTS 0x28 /* SATA Status */
228 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
229 #define AHCI_PREG_SSTS_DET_NONE 0x0
230 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1
231 #define AHCI_PREG_SSTS_DET_DEV 0x3
232 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
233 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
234 #define AHCI_PREG_SSTS_SPD_NONE 0x00
235 #define AHCI_PREG_SSTS_SPD_GEN1 0x10
236 #define AHCI_PREG_SSTS_SPD_GEN2 0x20
237 #define AHCI_PREG_SSTS_SPD_GEN3 0x30
238 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
239 #define AHCI_PREG_SSTS_IPM_NONE 0x000
240 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
241 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
242 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
243 #define AHCI_PREG_SSTS_IPM_DEVSLEEP 0x800
244
245 #define AHCI_PREG_SCTL 0x2c /* SATA Control */
246 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
247 #define AHCI_PREG_SCTL_DET_NONE 0x0
248 #define AHCI_PREG_SCTL_DET_INIT 0x1
249 #define AHCI_PREG_SCTL_DET_DISABLE 0x4
250 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
251 #define AHCI_PREG_SCTL_SPD_ANY 0x00
252 #define AHCI_PREG_SCTL_SPD_GEN1 0x10
253 #define AHCI_PREG_SCTL_SPD_GEN2 0x20
254 #define AHCI_PREG_SCTL_SPD_GEN3 0x30
255 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
256 #define AHCI_PREG_SCTL_IPM_NONE 0x000
257 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
258 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
259 #define AHCI_PREG_SCTL_IPM_NODEVSLP 0x400
260 #define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */
261 #define AHCI_PREG_SCTL_SPM_NONE 0x0000 /* not used by AHCI */
262 #define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000 /* not used by AHCI */
263 #define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000 /* not used by AHCI */
264 #define AHCI_PREG_SCTL_SPM_DISABLED 0x3000 /* not used by AHCI */
265 #define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */
266 #define AHCI_PREG_SCTL_PMP_SHIFT 16
267
268 #define AHCI_PREG_SERR 0x30 /* SATA Error */
269 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
270 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
271 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
272 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
273 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
274 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
275 #define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */
276 #define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */
277 #define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */
278 #define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */
279 #define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */
280 #define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */
281 #define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */
282 #define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */
283 #define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */
284 #define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */
285 #define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */
286
287 #define AHCI_PFMT_SERR "\020" \
288 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \
289 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \
290 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \
291 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \
292 "\002ERR.M" "\001ERR.I"
293
294 #define AHCI_PREG_SACT 0x34 /* SATA Active */
295 #define AHCI_PREG_CI 0x38 /* Command Issue */
296 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
297 #define AHCI_PREG_SNTF 0x3c /* SNotification */
298
299 /*
300 * EN - Enable FIS based switch, can only be changed when ST is clear
301 *
302 * DEC - Device Error Clear, state machine. Set to 1 by software only
303 * for the EN+SDE case, then poll until hardware sets it back to 0.
304 * Writing 0 has no effect.
305 *
306 * SDE - Set by hardware indicating a single device error occurred. If
307 * not set and an error occurred then the error was whole-port.
308 *
309 * DEV - Set by software to the PM target of the next command to issue
310 * via the PREG_CI registers. Software should not issue multiple
311 * commands covering different targets in a single write. This
312 * basically causes writes to PREG_CI to index within the hardware.
313 *
314 * ADO - (read only) Indicate how many concurrent devices commands may
315 * be issued to at once. Degredation may occur if commands are
316 * issued to more devices but the case is allowed.
317 *
318 * DWE - (read only) Only valid on SDE errors. Hardware indicates which
319 * PM target generated the error in this field.
320 *
321 */
322 #define AHCI_PREG_FBS 0x40 /* FIS-Based Switching Control */
323 #define AHCI_PREG_FBS_EN (1<<0) /* FIS-Based switching enable */
324 #define AHCI_PREG_FBS_DEC (1<<1) /* Device Error Clear */
325 #define AHCI_PREG_FBS_SDE (1<<2) /* Single-device Error */
326 #define AHCI_PREG_FBS_DEV 0x00000F00 /* Device to Issue mask */
327 #define AHCI_PREG_FBS_ADO 0x0000F000 /* Active Dev Optimize */
328 #define AHCI_PREG_FBS_DWE 0x000F0000 /* Device With Error */
329 #define AHCI_PREG_FBS_DEV_SHIFT 8
330 #define AHCI_PREG_FBS_ADO_SHIFT 12
331 #define AHCI_PREG_FBS_DWE_SHIFT 16
332
333 #define AHCI_PREG_DEVSLP 0x44 /* Device Sleep */
334 #define AHCI_PREG_DEVSLP_DSP 0x00000002 /* Device Sleep Present */
335 #define AHCI_PREG_DEVSLP_ADSE 0x00000001 /* A-Device Sleep Enable*/
336
337 /*
338 * AHCI mapped structures
339 */
340 struct ahci_cmd_hdr {
341 u_int16_t flags;
342 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
343 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
344 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
345 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
346 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
347 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
348 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
349 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
350 #define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12
351 u_int16_t prdtl; /* sgl len */
352
353 u_int32_t prdbc; /* transferred byte count */
354
355 u_int32_t ctba_lo;
356 u_int32_t ctba_hi;
357
358 u_int32_t reserved[4];
359 } __packed;
360
361 struct ahci_rfis {
362 u_int8_t dsfis[28];
363 u_int8_t reserved1[4];
364 u_int8_t psfis[24];
365 u_int8_t reserved2[8];
366 u_int8_t rfis[24];
367 u_int8_t reserved3[4];
368 u_int8_t sdbfis[4];
369 u_int8_t ufis[64];
370 u_int8_t reserved4[96];
371 } __packed;
372
373 struct ahci_prdt {
374 u_int32_t dba_lo;
375 u_int32_t dba_hi;
376 u_int32_t reserved;
377 u_int32_t flags;
378 #define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */
379 } __packed;
380
381 /*
382 * The base command table structure is 128 bytes. Each prdt is 16 bytes.
383 * We need to accomodate a 2MB maximum I/O transfer size, which is at least
384 * 512 entries, plus one for page slop.
385 *
386 * Making the ahci_cmd_table 16384 bytes (a reasonable power of 2)
387 * thus requires MAX_PRDT to be set to 1016.
388 */
389 #define AHCI_MAX_PRDT 1016
390 #define AHCI_MAX_PMPORTS 16
391
392 #define AHCI_MAXPHYS (2 * 1024 * 1024) /* 2MB */
393 #if AHCI_MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT
394 #error "AHCI_MAX_PRDT is not big enough"
395 #endif
396
397 struct ahci_cmd_table {
398 u_int8_t cfis[64]; /* Command FIS */
399 u_int8_t acmd[16]; /* ATAPI Command */
400 u_int8_t reserved[48];
401
402 struct ahci_prdt prdt[AHCI_MAX_PRDT];
403 } __packed;
404
405 #define AHCI_MAX_PORTS 32
406
407 struct ahci_dmamem {
408 bus_dma_tag_t adm_tag;
409 bus_dmamap_t adm_map;
410 bus_dma_segment_t adm_seg;
411 bus_addr_t adm_busaddr;
412 caddr_t adm_kva;
413 };
414 #define AHCI_DMA_MAP(_adm) ((_adm)->adm_map)
415 #define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr)
416 #define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva)
417
418 struct ahci_softc;
419 struct ahci_port;
420 struct ahci_device;
421
422 struct ahci_ccb {
423 /* ATA xfer associated with this CCB. Must be 1st struct member. */
424 struct ata_xfer ccb_xa;
425 struct callout ccb_timeout;
426
427 int ccb_slot;
428 struct ahci_port *ccb_port;
429
430 bus_dmamap_t ccb_dmamap;
431 struct ahci_cmd_hdr *ccb_cmd_hdr;
432 struct ahci_cmd_table *ccb_cmd_table;
433
434 void (*ccb_done)(struct ahci_ccb *);
435
436 TAILQ_ENTRY(ahci_ccb) ccb_entry;
437 };
438
439 struct ahci_port {
440 struct ahci_softc *ap_sc;
441 bus_space_handle_t ap_ioh;
442
443 int ap_num;
444 int ap_pmcount;
445 int ap_flags;
446 #define AP_F_BUS_REGISTERED 0x0001
447 #define AP_F_CAM_ATTACHED 0x0002
448 #define AP_F_IN_RESET 0x0004
449 #define AP_F_SCAN_RUNNING 0x0008
450 #define AP_F_SCAN_REQUESTED 0x0010
451 #define AP_F_SCAN_COMPLETED 0x0020
452 #define AP_F_IGNORE_IFS 0x0040
453 #define AP_F_IFS_IGNORED 0x0080
454 #define AP_F_UNUSED_0100 0x0100
455 #define AP_F_EXCLUSIVE_ACCESS 0x0200
456 #define AP_F_ERR_CCB_RESERVED 0x0400
457 #define AP_F_HARSH_REINIT 0x0800
458 #define AP_F_FBSS_ENABLED 0x1000
459 #define AP_F_BOOT_SYNCHRONOUS 0x2000
460 int ap_signal; /* os per-port thread sig */
461 thread_t ap_thread; /* os per-port thread */
462 struct lock ap_lock; /* os per-port lock */
463 struct lock ap_sim_lock; /* cam sim lock */
464 struct lock ap_sig_lock; /* signal thread */
465 #define AP_SIGF_INIT 0x0001
466 #define AP_SIGF_TIMEOUT 0x0002
467 #define AP_SIGF_PORTINT 0x0004
468 #define AP_SIGF_THREAD_SYNC 0x0008
469 #define AP_SIGF_STOP 0x8000
470 struct cam_sim *ap_sim;
471
472 struct ahci_rfis *ap_rfis;
473 struct ahci_dmamem *ap_dmamem_rfis;
474
475 struct ahci_dmamem *ap_dmamem_cmd_list;
476 struct ahci_dmamem *ap_dmamem_cmd_table;
477
478 u_int32_t ap_active; /* active CI command bmask */
479 u_int32_t ap_active_cnt; /* active CI command count */
480 u_int32_t ap_sactive; /* active SACT command bmask */
481 u_int32_t ap_expired; /* deferred expired bmask */
482 u_int32_t ap_intmask; /* interrupts we care about */
483 struct ahci_ccb *ap_ccbs;
484 struct ahci_ccb *ap_err_ccb; /* always CCB SLOT 1 */
485 int ap_run_flags; /* used to check excl mode */
486
487 TAILQ_HEAD(, ahci_ccb) ap_ccb_free;
488 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending;
489 struct lock ap_ccb_lock;
490
491 int ap_type; /* ATA_PORT_T_xxx */
492 int ap_probe; /* ATA_PROBE_xxx */
493 struct ata_port *ap_ata[AHCI_MAX_PMPORTS];
494
495 u_int32_t ap_state;
496 #define AP_S_NORMAL 0
497 #define AP_S_FATAL_ERROR 1
498
499 /* For error recovery. */
500 u_int32_t ap_err_saved_sactive;
501 u_int32_t ap_err_saved_active;
502 u_int32_t ap_err_saved_active_cnt;
503
504 u_int8_t *ap_err_scratch;
505
506 int link_pwr_mgmt;
507
508 struct sysctl_ctx_list sysctl_ctx;
509 struct sysctl_oid *sysctl_tree;
510
511 char ap_name[16];
512 };
513
514 #define PORTNAME(_ap) ((_ap)->ap_name)
515 #define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name)
516
517 struct ahci_softc {
518 device_t sc_dev;
519 const struct ahci_device *sc_ad; /* special casing */
520
521 struct resource *sc_irq; /* bus resources */
522 struct resource *sc_regs; /* bus resources */
523 bus_space_tag_t sc_iot; /* split from sc_regs */
524 bus_space_handle_t sc_ioh; /* split from sc_regs */
525
526 int sc_irq_type;
527 int sc_rid_irq; /* saved bus RIDs */
528 int sc_rid_regs;
529 u_int32_t sc_cap; /* capabilities */
530 u_int32_t sc_cap2; /* capabilities */
531 u_int32_t sc_vers; /* AHCI version */
532 int sc_numports;
533 u_int32_t sc_portmask;
534 u_int32_t sc_ipm_disable;
535
536 void *sc_irq_handle; /* installed irq vector */
537
538 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */
539 bus_dma_tag_t sc_tag_cmdh;
540 bus_dma_tag_t sc_tag_cmdt;
541 bus_dma_tag_t sc_tag_data;
542
543 size_t sc_rfis_size;
544 size_t sc_cmdlist_size;
545
546 int sc_flags;
547 #define AHCI_F_NO_NCQ 0x00000001
548 #define AHCI_F_IGN_FR 0x00000002
549 #define AHCI_F_INT_GOOD 0x00000004
550 #define AHCI_F_FORCE_FBSS 0x00000008
551 #define AHCI_F_IGN_CR 0x00000010
552 #define AHCI_F_CYCLE_FR 0x00000020
553 #define AHCI_F_FORCE_SCLO 0x00000040
554
555 u_int sc_ncmds;
556
557 struct ahci_port *sc_ports[AHCI_MAX_PORTS];
558
559 #ifdef AHCI_COALESCE
560 u_int32_t sc_ccc_mask;
561 u_int32_t sc_ccc_ports;
562 u_int32_t sc_ccc_ports_cur;
563 #endif
564 };
565 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname)
566
567 struct ahci_device {
568 pci_vendor_id_t ad_vendor;
569 pci_product_id_t ad_product;
570 int (*ad_attach)(device_t dev);
571 int (*ad_detach)(device_t dev);
572 char *name;
573 };
574
575 /* Wait for all bits in _b to be cleared */
576 #define ahci_pwait_clr(_ap, _r, _b) \
577 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0)
578 #define ahci_pwait_clr_to(_ap, _to, _r, _b) \
579 ahci_pwait_eq((_ap), _to, (_r), (_b), 0)
580
581 /* Wait for all bits in _b to be set */
582 #define ahci_pwait_set(_ap, _r, _b) \
583 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b))
584 #define ahci_pwait_set_to(_ap, _to, _r, _b) \
585 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b))
586
587 #define AHCI_PWAIT_TIMEOUT 1000
588
589 const struct ahci_device *ahci_lookup_device(device_t dev);
590 int ahci_init(struct ahci_softc *);
591 int ahci_port_init(struct ahci_port *ap);
592 int ahci_port_alloc(struct ahci_softc *, u_int);
593 void ahci_port_state_machine(struct ahci_port *ap, int initial);
594 void ahci_port_free(struct ahci_softc *, u_int);
595 int ahci_port_reset(struct ahci_port *, struct ata_port *at, int);
596 void ahci_port_link_pwr_mgmt(struct ahci_port *, int link_pwr_mgmt);
597 int ahci_port_link_pwr_state(struct ahci_port *);
598
599 u_int32_t ahci_read(struct ahci_softc *, bus_size_t);
600 void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t);
601 int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t);
602 u_int32_t ahci_pread(struct ahci_port *, bus_size_t);
603 void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t);
604 int ahci_pwait_eq(struct ahci_port *, int, bus_size_t,
605 u_int32_t, u_int32_t);
606 void ahci_intr(void *);
607 void ahci_port_intr(struct ahci_port *ap, int blockable);
608
609 int ahci_comreset(struct ahci_port *ap, int *pmdetectp);
610 int ahci_port_start(struct ahci_port *ap);
611 int ahci_port_stop(struct ahci_port *ap, int stop_fis_rx);
612 int ahci_port_clo(struct ahci_port *ap);
613 void ahci_flush_tfd(struct ahci_port *ap);
614 int ahci_set_feature(struct ahci_port *ap, struct ata_port *atx,
615 int feature, int enable);
616
617 int ahci_cam_attach(struct ahci_port *ap);
618 void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found);
619 void ahci_cam_detach(struct ahci_port *ap);
620 int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at);
621
622 struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at);
623 void ahci_ata_put_xfer(struct ata_xfer *xa);
624 int ahci_ata_cmd(struct ata_xfer *xa);
625
626 int ahci_pm_port_probe(struct ahci_port *ap, int);
627 int ahci_pm_port_init(struct ahci_port *ap, struct ata_port *at);
628 int ahci_pm_identify(struct ahci_port *ap);
629 int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard);
630 int ahci_pm_softreset(struct ahci_port *ap, int target);
631 int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap);
632 int ahci_pm_read(struct ahci_port *ap, int target,
633 int which, u_int32_t *res);
634 int ahci_pm_write(struct ahci_port *ap, int target,
635 int which, u_int32_t data);
636 void ahci_pm_check_good(struct ahci_port *ap, int target);
637 void ahci_ata_cmd_timeout(struct ahci_ccb *ccb);
638 void ahci_quick_timeout(struct ahci_ccb *ccb);
639 struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap);
640 void ahci_put_ccb(struct ahci_ccb *ccb);
641 struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *);
642 void ahci_put_err_ccb(struct ahci_ccb *);
643 int ahci_poll(struct ahci_ccb *ccb, int timeout,
644 void (*timeout_fn)(struct ahci_ccb *));
645
646 int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at);
647 void ahci_port_thread_core(struct ahci_port *ap, int mask);
648
649 void ahci_os_sleep(int ms);
650 void ahci_os_hardsleep(int us);
651 int ahci_os_softsleep(void);
652 void ahci_os_start_port(struct ahci_port *ap);
653 void ahci_os_stop_port(struct ahci_port *ap);
654 void ahci_os_signal_port_thread(struct ahci_port *ap, int mask);
655 void ahci_os_lock_port(struct ahci_port *ap);
656 int ahci_os_lock_port_nb(struct ahci_port *ap);
657 void ahci_os_unlock_port(struct ahci_port *ap);
658
659 extern u_int32_t AhciForceGen;
660 extern u_int32_t AhciNoFeatures;
661 extern int ahci_synchronous_boot;
662
663 enum {AHCI_LINK_PWR_MGMT_NONE, AHCI_LINK_PWR_MGMT_MEDIUM,
664 AHCI_LINK_PWR_MGMT_AGGR};
DragonFly BSD