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* Fix support for followings:
[dragonfly.git] / sys / dev / sound / pci / hda / hdac.c
blob8c593c7874b9b7aad43025d3a560c0f9e3061391
1 /*-
2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.7 2007/11/27 23:37:16 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.13 2007/11/30 08:06:00 hasso Exp $
29 */
30
31 /*
32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
33 * that this driver still in its early stage, and possible of rewrite are
34 * pretty much guaranteed. There are supposedly several distinct parent/child
35 * busses to make this "perfect", but as for now and for the sake of
36 * simplicity, everything is gobble up within single source.
37 *
38 * List of subsys:
39 * 1) HDA Controller support
40 * 2) HDA Codecs support, which may include
41 * - HDA
42 * - Modem
43 * - HDMI
44 * 3) Widget parser - the real magic of why this driver works on so
45 * many hardwares with minimal vendor specific quirk. The original
46 * parser was written using Ruby and can be found at
47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
48 * ruby parser take the verbose dmesg dump as its input. Refer to
49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
50 * interesting documents, especially UAA (Universal Audio Architecture).
51 * 4) Possible vendor specific support.
52 * (snd_hda_intel, snd_hda_ati, etc..)
53 *
54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
55 * Compaq V3000 with Conexant HDA.
56 *
57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
58 * * *
59 * * This driver is a collaborative effort made by: *
60 * * *
61 * * Stephane E. Potvin <sepotvin@videotron.ca> *
62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
63 * * Wesley Morgan <morganw@chemikals.org> *
64 * * Daniel Eischen <deischen@FreeBSD.org> *
65 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
66 * * Ariff Abdullah <ariff@FreeBSD.org> *
67 * * *
68 * * ....and various people from freebsd-multimedia@FreeBSD.org *
69 * * *
70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
71 */
72
73 #include <dev/sound/pcm/sound.h>
74 #include <bus/pci/pcireg.h>
75 #include <bus/pci/pcivar.h>
76
77 #include <sys/ctype.h>
78 #include <sys/taskqueue.h>
79
80 #include <dev/sound/pci/hda/hdac_private.h>
81 #include <dev/sound/pci/hda/hdac_reg.h>
82 #include <dev/sound/pci/hda/hda_reg.h>
83 #include <dev/sound/pci/hda/hdac.h>
84
85 #include "mixer_if.h"
86
87 #define HDA_DRV_TEST_REV "20071122_0049"
88 #define HDA_WIDGET_PARSER_REV 1
89
90 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.13 2007/11/30 08:06:00 hasso Exp $");
91
92 #define HDA_BOOTVERBOSE(stmt) do { \
93 if (bootverbose != 0) { \
94 stmt \
95 } \
96 } while(0)
97
98 #if 1
99 #undef HDAC_INTR_EXTRA
100 #define HDAC_INTR_EXTRA 1
101 #endif
102
103 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
104 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
105 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
106 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */
107
108 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
109 #include <machine/specialreg.h>
110 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \
111 vm_offset_t va = (vm_offset_t)(v); \
112 vm_size_t sz = (vm_size_t)(s); \
113 if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) && \
114 va != 0 && sz != 0) \
115 (void)pmap_change_attr(va, sz, (attr)); \
116 } while(0)
117 #else
118 #define HDAC_DMA_ATTR(...)
119 #endif
120
121 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
122 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
123 (fl) == 0xffffffff || \
124 (((fl) & 0xffff0000) == 0xffff0000 && \
125 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
126 (((fl) & 0x0000ffff) == 0x0000ffff && \
127 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
128 #define HDA_MATCH_ALL 0xffffffff
129 #define HDAC_INVALID 0xffffffff
130
131 /* Default controller / jack sense poll: 250ms */
132 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
133
134 /*
135 * Make room for possible 4096 playback/record channels, in 100 years to come.
136 */
137 #define HDAC_TRIGGER_NONE 0x00000000
138 #define HDAC_TRIGGER_PLAY 0x00000fff
139 #define HDAC_TRIGGER_REC 0x00fff000
140 #define HDAC_TRIGGER_UNSOL 0x80000000
141
142 #define HDA_MODEL_CONSTRUCT(vendor, model) \
143 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
144
145 /* Controller models */
146
147 /* Intel */
148 #define INTEL_VENDORID 0x8086
149 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
150 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
151 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
152 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
153 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
154 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
155
156 /* Nvidia */
157 #define NVIDIA_VENDORID 0x10de
158 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
159 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
160 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
161 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
162 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
163 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
164 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)
165 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)
166 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
167
168 /* ATI */
169 #define ATI_VENDORID 0x1002
170 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
171 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
172 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
173
174 /* VIA */
175 #define VIA_VENDORID 0x1106
176 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
177 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
178
179 /* SiS */
180 #define SIS_VENDORID 0x1039
181 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
182 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
183
184 /* OEM/subvendors */
185
186 /* Intel */
187 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
188
189 /* HP/Compaq */
190 #define HP_VENDORID 0x103c
191 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
192 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
193 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
194 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
195 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
196 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
197 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
198 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802)
199 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
200 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
201 #define HP_NX6325_SUBVENDORX 0x103c30b0
202
203 /* Dell */
204 #define DELL_VENDORID 0x1028
205 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
206 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
207 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
208 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
209 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
210
211 /* Clevo */
212 #define CLEVO_VENDORID 0x1558
213 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
214 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
215
216 /* Acer */
217 #define ACER_VENDORID 0x1025
218 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
219 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127)
220 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
221 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
222
223 /* Asus */
224 #define ASUS_VENDORID 0x1043
225 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
226 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
227 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
228 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
229 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
230 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
231 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
232 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
233 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
234 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
235 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
236 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
237 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
238 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
239 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
240
241 /* IBM / Lenovo */
242 #define IBM_VENDORID 0x1014
243 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
244 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
245
246 /* Lenovo */
247 #define LENOVO_VENDORID 0x17aa
248 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
249 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
250 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
251
252 /* Samsung */
253 #define SAMSUNG_VENDORID 0x144d
254 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
255 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
256
257 /* Medion ? */
258 #define MEDION_VENDORID 0x161f
259 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
260 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
261
262 /* Apple Computer Inc. */
263 #define APPLE_VENDORID 0x106b
264 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)
265
266 /*
267 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
268 * instead of their own, which is beyond my comprehension
269 * (see HDA_CODEC_STAC9221 below).
270 */
271 #define APPLE_INTEL_MAC 0x76808384
272
273 /* LG Electronics */
274 #define LG_VENDORID 0x1854
275 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
276 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
277
278 /* Fujitsu Siemens */
279 #define FS_VENDORID 0x1734
280 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
281 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd)
282 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
283
284 /* Fujitsu Limited */
285 #define FL_VENDORID 0x10cf
286 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326)
287 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff)
288
289 /* Toshiba */
290 #define TOSHIBA_VENDORID 0x1179
291 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
292 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)
293 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
294
295 /* Micro-Star International (MSI) */
296 #define MSI_VENDORID 0x1462
297 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
298 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a)
299 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
300
301 /* Giga-Byte Technology */
302 #define GB_VENDORID 0x1458
303 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022)
304 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff)
305
306 /* Uniwill ? */
307 #define UNIWILL_VENDORID 0x1584
308 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
309 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
310
311
312 /* Misc constants.. */
313 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
314 #define HDA_AMP_MUTE_NONE (0)
315 #define HDA_AMP_MUTE_LEFT (1 << 0)
316 #define HDA_AMP_MUTE_RIGHT (1 << 1)
317 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
318
319 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
320 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
321
322 #define HDA_DAC_PATH (1 << 0)
323 #define HDA_ADC_PATH (1 << 1)
324 #define HDA_ADC_RECSEL (1 << 2)
325
326 #define HDA_DAC_LOCKED (1 << 3)
327 #define HDA_ADC_LOCKED (1 << 4)
328
329 #define HDA_CTL_OUT (1 << 0)
330 #define HDA_CTL_IN (1 << 1)
331 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
332
333 #define HDA_GPIO_MAX 8
334 /* 0 - 7 = GPIO , 8 = Flush */
335 #define HDA_QUIRK_GPIO0 (1 << 0)
336 #define HDA_QUIRK_GPIO1 (1 << 1)
337 #define HDA_QUIRK_GPIO2 (1 << 2)
338 #define HDA_QUIRK_GPIO3 (1 << 3)
339 #define HDA_QUIRK_GPIO4 (1 << 4)
340 #define HDA_QUIRK_GPIO5 (1 << 5)
341 #define HDA_QUIRK_GPIO6 (1 << 6)
342 #define HDA_QUIRK_GPIO7 (1 << 7)
343 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
344
345 /* 9 - 25 = anything else */
346 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
347 #define HDA_QUIRK_FIXEDRATE (1 << 10)
348 #define HDA_QUIRK_FORCESTEREO (1 << 11)
349 #define HDA_QUIRK_EAPDINV (1 << 12)
350 #define HDA_QUIRK_DMAPOS (1 << 13)
351
352 /* 26 - 31 = vrefs */
353 #define HDA_QUIRK_IVREF50 (1 << 26)
354 #define HDA_QUIRK_IVREF80 (1 << 27)
355 #define HDA_QUIRK_IVREF100 (1 << 28)
356 #define HDA_QUIRK_OVREF50 (1 << 29)
357 #define HDA_QUIRK_OVREF80 (1 << 30)
358 #define HDA_QUIRK_OVREF100 (1 << 31)
359
360 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
361 HDA_QUIRK_IVREF100)
362 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
363 HDA_QUIRK_OVREF100)
364 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
365
366 #define SOUND_MASK_SKIP (1 << 30)
367 #define SOUND_MASK_DISABLE (1 << 31)
368
369 static const struct {
370 char *key;
371 uint32_t value;
372 } hdac_quirks_tab[] = {
373 { "gpio0", HDA_QUIRK_GPIO0 },
374 { "gpio1", HDA_QUIRK_GPIO1 },
375 { "gpio2", HDA_QUIRK_GPIO2 },
376 { "gpio3", HDA_QUIRK_GPIO3 },
377 { "gpio4", HDA_QUIRK_GPIO4 },
378 { "gpio5", HDA_QUIRK_GPIO5 },
379 { "gpio6", HDA_QUIRK_GPIO6 },
380 { "gpio7", HDA_QUIRK_GPIO7 },
381 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
382 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
383 { "fixedrate", HDA_QUIRK_FIXEDRATE },
384 { "forcestereo", HDA_QUIRK_FORCESTEREO },
385 { "eapdinv", HDA_QUIRK_EAPDINV },
386 { "dmapos", HDA_QUIRK_DMAPOS },
387 { "ivref50", HDA_QUIRK_IVREF50 },
388 { "ivref80", HDA_QUIRK_IVREF80 },
389 { "ivref100", HDA_QUIRK_IVREF100 },
390 { "ovref50", HDA_QUIRK_OVREF50 },
391 { "ovref80", HDA_QUIRK_OVREF80 },
392 { "ovref100", HDA_QUIRK_OVREF100 },
393 { "ivref", HDA_QUIRK_IVREF },
394 { "ovref", HDA_QUIRK_OVREF },
395 { "vref", HDA_QUIRK_VREF },
396 };
397 #define HDAC_QUIRKS_TAB_LEN \
398 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
399
400 #define HDA_BDL_MIN 2
401 #define HDA_BDL_MAX 256
402 #define HDA_BDL_DEFAULT HDA_BDL_MIN
403
404 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
405 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
406
407 #define HDA_BUFSZ_MIN 4096
408 #define HDA_BUFSZ_MAX 65536
409 #define HDA_BUFSZ_DEFAULT 16384
410
411 #define HDA_PARSE_MAXDEPTH 10
412
413 #define HDAC_UNSOLTAG_EVENT_HP 0x00
414 #define HDAC_UNSOLTAG_EVENT_TEST 0x01
415
416 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
417
418 enum {
419 HDA_PARSE_MIXER,
420 HDA_PARSE_DIRECT
421 };
422
423 /* Default */
424 static uint32_t hdac_fmt[] = {
425 AFMT_STEREO | AFMT_S16_LE,
426 0
427 };
428
429 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
430
431 static const struct {
432 uint32_t model;
433 char *desc;
434 } hdac_devices[] = {
435 { HDA_INTEL_82801F, "Intel 82801F" },
436 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
437 { HDA_INTEL_82801G, "Intel 82801G" },
438 { HDA_INTEL_82801H, "Intel 82801H" },
439 { HDA_INTEL_82801I, "Intel 82801I" },
440 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
441 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
442 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" },
443 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" },
444 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" },
445 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" },
446 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" },
447 { HDA_ATI_SB450, "ATI SB450" },
448 { HDA_ATI_SB600, "ATI SB600" },
449 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
450 { HDA_SIS_966, "SiS 966" },
451 /* Unknown */
452 { HDA_INTEL_ALL, "Intel (Unknown)" },
453 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
454 { HDA_ATI_ALL, "ATI (Unknown)" },
455 { HDA_VIA_ALL, "VIA (Unknown)" },
456 { HDA_SIS_ALL, "SiS (Unknown)" },
457 };
458 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
459
460 static const struct {
461 uint16_t vendor;
462 uint8_t reg;
463 uint8_t mask;
464 uint8_t enable;
465 } hdac_pcie_snoop[] = {
466 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
467 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
468 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
469 };
470 #define HDAC_PCIESNOOP_LEN \
471 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
472
473 static const struct {
474 uint32_t rate;
475 int valid;
476 uint16_t base;
477 uint16_t mul;
478 uint16_t div;
479 } hda_rate_tab[] = {
480 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
481 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
482 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
483 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
484 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
485 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
486 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
487 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
488 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
489 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
490 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
491 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
492 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
493 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
494 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
495 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
496 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
497 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
498 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
499 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
500 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
501 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
502 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
503 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
504 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
505 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
506 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
507 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
508 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
509 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
510 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
511 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
512 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
513 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
514 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
515 };
516 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
517
518 /* All codecs you can eat... */
519 #define HDA_CODEC_CONSTRUCT(vendor, id) \
520 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
521
522 /* Realtek */
523 #define REALTEK_VENDORID 0x10ec
524 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
525 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
526 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
527 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
528 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
529 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
530 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
531 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
532 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
533 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
534 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
535 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
536
537 /* Analog Devices */
538 #define ANALOGDEVICES_VENDORID 0x11d4
539 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
540 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
541 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
542 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
543 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
544 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
545
546 /* CMedia */
547 #define CMEDIA_VENDORID 0x434d
548 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
549 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
550
551 /* Sigmatel */
552 #define SIGMATEL_VENDORID 0x8384
553 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
554 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
555 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
556 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
557 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
558 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
559 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
560
561 /*
562 * Conexant
563 *
564 * Ok, the truth is, I don't have any idea at all whether
565 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
566 * place that tell me it is "Venice" is from its Windows driver INF.
567 *
568 * Venice - CX?????
569 * Waikiki - CX20551-22
570 */
571 #define CONEXANT_VENDORID 0x14f1
572 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
573 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
574 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
575
576 /* VIA */
577 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
578 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
579 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
580 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
581 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
582 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
583 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
584 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
585 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
586 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
587 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
588 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
589 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
590
591
592 /* Codecs */
593 static const struct {
594 uint32_t id;
595 char *name;
596 } hdac_codecs[] = {
597 { HDA_CODEC_ALC260, "Realtek ALC260" },
598 { HDA_CODEC_ALC262, "Realtek ALC262" },
599 { HDA_CODEC_ALC268, "Realtek ALC268" },
600 { HDA_CODEC_ALC660, "Realtek ALC660" },
601 { HDA_CODEC_ALC861, "Realtek ALC861" },
602 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
603 { HDA_CODEC_ALC880, "Realtek ALC880" },
604 { HDA_CODEC_ALC882, "Realtek ALC882" },
605 { HDA_CODEC_ALC883, "Realtek ALC883" },
606 { HDA_CODEC_ALC885, "Realtek ALC885" },
607 { HDA_CODEC_ALC888, "Realtek ALC888" },
608 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
609 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
610 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
611 { HDA_CODEC_AD1988, "Analog Devices AD1988" },
612 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
613 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
614 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
615 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
616 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
617 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
618 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" },
619 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
620 { HDA_CODEC_CXVENICE, "Conexant Venice" },
621 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
622 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
623 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
624 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
625 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
626 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
627 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
628 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
629 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
630 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
631 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
632 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
633 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
634 /* Unknown codec */
635 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
636 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
637 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
638 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
639 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
640 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
641 };
642 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
643
644 enum {
645 HDAC_HP_SWITCH_CTL,
646 HDAC_HP_SWITCH_CTRL,
647 HDAC_HP_SWITCH_DEBUG
648 };
649
650 static const struct {
651 uint32_t model;
652 uint32_t id;
653 int type;
654 int inverted;
655 int polling;
656 int execsense;
657 nid_t hpnid;
658 nid_t spkrnid[8];
659 nid_t eapdnid;
660 } hdac_hp_switch[] = {
661 /* Specific OEM models */
662 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
663 0, 0, -1, 17, { 16, -1 }, 16 },
664 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
665 0, 0, -1, 21, { 16, 17, -1 }, -1 } */
666 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
667 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */
668 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
669 0, 0, -1, 6, { 5, -1 }, 5 },
670 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
671 0, 0, -1, 6, { 5, -1 }, 5 },
672 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
673 0, 0, -1, 6, { 5, -1 }, 5 },
674 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL,
675 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */
676 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
677 0, 0, -1, 6, { 5, -1 }, -1 },
678 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL,
679 0, 0, -1, 27, { 20, -1 }, -1 },
680 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
681 0, 0, -1, 13, { 14, -1 }, -1 },
682 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
683 0, 0, -1, 13, { 14, -1 }, -1 },
684 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
685 0, 0, -1, 6, { 5, 7, -1 }, -1 },
686 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL,
687 0, 0, -1, 21, { 20, 22, -1 }, -1 },
688 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
689 0, 0, -1, 10, { 13, -1 }, -1 },
690 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
691 1, 0, -1, 26, { 27, -1 }, -1 },
692 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
693 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */
694 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
695 0, 0, -1, 27, { 20, -1 }, -1 },
696 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
697 0, 0, -1, 20, { 21, -1 }, -1 },
698 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
699 0, 0, -1, 20, { 21, -1 }, -1 },
700 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL,
701 0, 0, -1, 20, { 21, -1 }, -1 },
702 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
703 0, 0, -1, 20, { 21, -1 }, -1 },
704 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
705 0, 0, -1, 20, { 27, -1 }, -1 },
706 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
707 0, 0, -1, 20, { 27, -1 }, -1 },
708 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
709 0, 0, -1, 20, { 21, -1 }, -1 },
710 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
711 0, 0, -1, 20, { 16, -1 }, -1 },
712 /*
713 * All models that at least come from the same vendor with
714 * simmilar codec.
715 */
716 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
717 0, 0, -1, 17, { 16, -1 }, 16 },
718 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
719 0, 0, -1, 6, { 5, -1 }, 5 },
720 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
721 0, 0, -1, 6, { 5, -1 }, -1 },
722 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
723 0, 0, -1, 13, { 14, -1 }, -1 },
724 #if 0
725 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
726 1, 0, -1, 26, { 27, -1 }, -1 },
727 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
728 0, 0, -1, 20, { 21, -1 }, -1 },
729 #endif
730 };
731 #define HDAC_HP_SWITCH_LEN \
732 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
733
734 static const struct {
735 uint32_t model;
736 uint32_t id;
737 nid_t eapdnid;
738 int hp_switch;
739 } hdac_eapd_switch[] = {
740 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
741 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
742 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
743 };
744 #define HDAC_EAPD_SWITCH_LEN \
745 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
746
747 /****************************************************************************
748 * Function prototypes
749 ****************************************************************************/
750 static void hdac_intr_handler(void *);
751 static int hdac_reset(struct hdac_softc *);
752 static int hdac_get_capabilities(struct hdac_softc *);
753 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
754 static int hdac_dma_alloc(struct hdac_softc *,
755 struct hdac_dma *, bus_size_t);
756 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
757 static int hdac_mem_alloc(struct hdac_softc *);
758 static void hdac_mem_free(struct hdac_softc *);
759 static int hdac_irq_alloc(struct hdac_softc *);
760 static void hdac_irq_free(struct hdac_softc *);
761 static void hdac_corb_init(struct hdac_softc *);
762 static void hdac_rirb_init(struct hdac_softc *);
763 static void hdac_corb_start(struct hdac_softc *);
764 static void hdac_rirb_start(struct hdac_softc *);
765 static void hdac_scan_codecs(struct hdac_softc *, int);
766 static int hdac_probe_codec(struct hdac_codec *);
767 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
768 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
769
770 static void hdac_attach2(void *);
771
772 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
773 uint32_t, int);
774 static void hdac_command_send_internal(struct hdac_softc *,
775 struct hdac_command_list *, int);
776
777 static int hdac_probe(device_t);
778 static int hdac_attach(device_t);
779 static int hdac_detach(device_t);
780 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
781 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
782 uint32_t, int, int);
783 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
784 nid_t, int, int);
785 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
786 nid_t, nid_t, int, int, int, int, int, int);
787 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
788 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
789
790 static int hdac_rirb_flush(struct hdac_softc *sc);
791 static int hdac_unsolq_flush(struct hdac_softc *sc);
792
793 #define hdac_command(a1, a2, a3) \
794 hdac_command_sendone_internal(a1, a2, a3)
795
796 #define hdac_codec_id(d) \
797 ((uint32_t)((d == NULL) ? 0x00000000 : \
798 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
799 ((uint32_t)(d)->device_id & 0x0000ffff))))
800
801 static char *
802 hdac_codec_name(struct hdac_devinfo *devinfo)
803 {
804 uint32_t id;
805 int i;
806
807 id = hdac_codec_id(devinfo);
808
809 for (i = 0; i < HDAC_CODECS_LEN; i++) {
810 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
811 return (hdac_codecs[i].name);
812 }
813
814 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
815 }
816
817 static char *
818 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
819 {
820 static char *ossname[] = SOUND_DEVICE_NAMES;
821 static char *unknown = "???";
822 int i;
823
824 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
825 if (devmask & (1 << i))
826 return (ossname[i]);
827 }
828 return (unknown);
829 }
830
831 static void
832 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
833 {
834 static char *ossname[] = SOUND_DEVICE_NAMES;
835 int i, first = 1;
836
837 bzero(buf, len);
838 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
839 if (mask & (1 << i)) {
840 if (first == 0)
841 strlcat(buf, ", ", len);
842 strlcat(buf, ossname[i], len);
843 first = 0;
844 }
845 }
846 }
847
848 static struct hdac_audio_ctl *
849 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
850 {
851 if (devinfo == NULL ||
852 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
853 index == NULL || devinfo->function.audio.ctl == NULL ||
854 devinfo->function.audio.ctlcnt < 1 ||
855 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
856 return (NULL);
857 return (&devinfo->function.audio.ctl[(*index)++]);
858 }
859
860 static struct hdac_audio_ctl *
861 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
862 int index, int cnt)
863 {
864 struct hdac_audio_ctl *ctl, *retctl = NULL;
865 int i, at, atindex, found = 0;
866
867 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
868 return (NULL);
869
870 at = cnt;
871 if (at == 0)
872 at = 1;
873 else if (at < 0)
874 at = -1;
875 atindex = index;
876 if (atindex < 0)
877 atindex = -1;
878
879 i = 0;
880 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
881 if (ctl->enable == 0 || ctl->widget == NULL)
882 continue;
883 if (!(ctl->widget->nid == nid && (atindex == -1 ||
884 ctl->index == atindex)))
885 continue;
886 found++;
887 if (found == cnt)
888 return (ctl);
889 retctl = ctl;
890 }
891
892 return ((at == -1) ? retctl : NULL);
893 }
894
895 static void
896 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
897 {
898 struct hdac_softc *sc;
899 struct hdac_widget *w;
900 struct hdac_audio_ctl *ctl;
901 uint32_t val, id, res;
902 int i = 0, j, timeout, forcemute;
903 nid_t cad;
904
905 if (devinfo == NULL || devinfo->codec == NULL ||
906 devinfo->codec->sc == NULL)
907 return;
908
909 sc = devinfo->codec->sc;
910 cad = devinfo->codec->cad;
911 id = hdac_codec_id(devinfo);
912 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
913 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
914 sc->pci_subvendor) &&
915 hdac_hp_switch[i].id == id)
916 break;
917 }
918
919 if (i >= HDAC_HP_SWITCH_LEN)
920 return;
921
922 forcemute = 0;
923 if (hdac_hp_switch[i].eapdnid != -1) {
924 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
925 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
926 forcemute = (w->param.eapdbtl &
927 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
928 }
929
930 if (hdac_hp_switch[i].execsense != -1)
931 hdac_command(sc,
932 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
933 hdac_hp_switch[i].execsense), cad);
934
935 timeout = 10000;
936 do {
937 res = hdac_command(sc,
938 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid),
939 cad);
940 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff)
941 break;
942 DELAY(10);
943 } while (--timeout != 0);
944
945 HDA_BOOTVERBOSE(
946 device_printf(sc->dev,
947 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n",
948 hdac_hp_switch[i].hpnid, timeout, res);
949 );
950
951 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
952 res ^= hdac_hp_switch[i].inverted;
953
954 switch (hdac_hp_switch[i].type) {
955 case HDAC_HP_SWITCH_CTL:
956 ctl = hdac_audio_ctl_amp_get(devinfo,
957 hdac_hp_switch[i].hpnid, 0, 1);
958 if (ctl != NULL) {
959 val = (res != 0 && forcemute == 0) ?
960 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
961 if (val != ctl->muted) {
962 ctl->muted = val;
963 hdac_audio_ctl_amp_set(ctl,
964 HDA_AMP_MUTE_DEFAULT, ctl->left,
965 ctl->right);
966 }
967 }
968 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
969 ctl = hdac_audio_ctl_amp_get(devinfo,
970 hdac_hp_switch[i].spkrnid[j], 0, 1);
971 if (ctl == NULL)
972 continue;
973 val = (res != 0 || forcemute == 1) ?
974 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
975 if (val == ctl->muted)
976 continue;
977 ctl->muted = val;
978 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
979 ctl->left, ctl->right);
980 }
981 break;
982 case HDAC_HP_SWITCH_CTRL:
983 if (res != 0) {
984 /* HP in */
985 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
986 if (w != NULL && w->type ==
987 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
988 if (forcemute == 0)
989 val = w->wclass.pin.ctrl |
990 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
991 else
992 val = w->wclass.pin.ctrl &
993 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
994 if (val != w->wclass.pin.ctrl) {
995 w->wclass.pin.ctrl = val;
996 hdac_command(sc,
997 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
998 w->nid, w->wclass.pin.ctrl), cad);
999 }
1000 }
1001 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1002 w = hdac_widget_get(devinfo,
1003 hdac_hp_switch[i].spkrnid[j]);
1004 if (w == NULL || w->type !=
1005 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1006 continue;
1007 val = w->wclass.pin.ctrl &
1008 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1009 if (val == w->wclass.pin.ctrl)
1010 continue;
1011 w->wclass.pin.ctrl = val;
1012 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1013 cad, w->nid, w->wclass.pin.ctrl), cad);
1014 }
1015 } else {
1016 /* HP out */
1017 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
1018 if (w != NULL && w->type ==
1019 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1020 val = w->wclass.pin.ctrl &
1021 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1022 if (val != w->wclass.pin.ctrl) {
1023 w->wclass.pin.ctrl = val;
1024 hdac_command(sc,
1025 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1026 w->nid, w->wclass.pin.ctrl), cad);
1027 }
1028 }
1029 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1030 w = hdac_widget_get(devinfo,
1031 hdac_hp_switch[i].spkrnid[j]);
1032 if (w == NULL || w->type !=
1033 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1034 continue;
1035 if (forcemute == 0)
1036 val = w->wclass.pin.ctrl |
1037 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1038 else
1039 val = w->wclass.pin.ctrl &
1040 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1041 if (val == w->wclass.pin.ctrl)
1042 continue;
1043 w->wclass.pin.ctrl = val;
1044 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1045 cad, w->nid, w->wclass.pin.ctrl), cad);
1046 }
1047 }
1048 break;
1049 case HDAC_HP_SWITCH_DEBUG:
1050 if (hdac_hp_switch[i].execsense != -1)
1051 hdac_command(sc,
1052 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
1053 hdac_hp_switch[i].execsense), cad);
1054 res = hdac_command(sc,
1055 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
1056 device_printf(sc->dev,
1057 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1058 hdac_hp_switch[i].hpnid, res);
1059 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1060 w = hdac_widget_get(devinfo,
1061 hdac_hp_switch[i].spkrnid[j]);
1062 if (w == NULL || w->type !=
1063 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1064 continue;
1065 if (hdac_hp_switch[i].execsense != -1)
1066 hdac_command(sc,
1067 HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1068 hdac_hp_switch[i].execsense), cad);
1069 res = hdac_command(sc,
1070 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1071 device_printf(sc->dev,
1072 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1073 j + 1, w->nid, res);
1074 }
1075 break;
1076 default:
1077 break;
1078 }
1079 }
1080
1081 static void
1082 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1083 {
1084 struct hdac_softc *sc;
1085 struct hdac_devinfo *devinfo = NULL;
1086 device_t *devlist = NULL;
1087 int devcount, i;
1088
1089 if (codec == NULL || codec->sc == NULL)
1090 return;
1091
1092 sc = codec->sc;
1093
1094 HDA_BOOTVERBOSE(
1095 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1096 );
1097
1098 device_get_children(sc->dev, &devlist, &devcount);
1099 for (i = 0; devlist != NULL && i < devcount; i++) {
1100 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1101 if (devinfo != NULL && devinfo->node_type ==
1102 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1103 devinfo->codec != NULL &&
1104 devinfo->codec->cad == codec->cad) {
1105 break;
1106 } else
1107 devinfo = NULL;
1108 }
1109 if (devlist != NULL)
1110 kfree(devlist, M_TEMP);
1111
1112 if (devinfo == NULL)
1113 return;
1114
1115 switch (tag) {
1116 case HDAC_UNSOLTAG_EVENT_HP:
1117 hdac_hp_switch_handler(devinfo);
1118 break;
1119 case HDAC_UNSOLTAG_EVENT_TEST:
1120 device_printf(sc->dev, "Unsol Test!\n");
1121 break;
1122 default:
1123 break;
1124 }
1125 }
1126
1127 static int
1128 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1129 {
1130 /* XXX to be removed */
1131 #ifdef HDAC_INTR_EXTRA
1132 uint32_t res;
1133 #endif
1134
1135 if (!(ch->flags & HDAC_CHN_RUNNING))
1136 return (0);
1137
1138 /* XXX to be removed */
1139 #ifdef HDAC_INTR_EXTRA
1140 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1141 #endif
1142
1143 /* XXX to be removed */
1144 #ifdef HDAC_INTR_EXTRA
1145 HDA_BOOTVERBOSE(
1146 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1147 device_printf(sc->dev,
1148 "PCMDIR_%s intr triggered beyond stream boundary:"
1149 "%08x\n",
1150 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1151 );
1152 #endif
1153
1154 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1155 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1156
1157 /* XXX to be removed */
1158 #ifdef HDAC_INTR_EXTRA
1159 if (res & HDAC_SDSTS_BCIS) {
1160 #endif
1161 return (1);
1162 /* XXX to be removed */
1163 #ifdef HDAC_INTR_EXTRA
1164 }
1165 #endif
1166
1167 return (0);
1168 }
1169
1170 /****************************************************************************
1171 * void hdac_intr_handler(void *)
1172 *
1173 * Interrupt handler. Processes interrupts received from the hdac.
1174 ****************************************************************************/
1175 static void
1176 hdac_intr_handler(void *context)
1177 {
1178 struct hdac_softc *sc;
1179 uint32_t intsts;
1180 uint8_t rirbsts;
1181 struct hdac_rirb *rirb_base;
1182 uint32_t trigger;
1183
1184 sc = (struct hdac_softc *)context;
1185
1186 hdac_lock(sc);
1187 if (sc->polling != 0) {
1188 hdac_unlock(sc);
1189 return;
1190 }
1191
1192 /* Do we have anything to do? */
1193 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1194 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1195 hdac_unlock(sc);
1196 return;
1197 }
1198
1199 trigger = 0;
1200
1201 /* Was this a controller interrupt? */
1202 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1203 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1204 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1205 /* Get as many responses that we can */
1206 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1207 HDAC_WRITE_1(&sc->mem,
1208 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1209 if (hdac_rirb_flush(sc) != 0)
1210 trigger |= HDAC_TRIGGER_UNSOL;
1211 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1212 }
1213 /* XXX to be removed */
1214 /* Clear interrupt and exit */
1215 #ifdef HDAC_INTR_EXTRA
1216 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1217 #endif
1218 }
1219
1220 if (intsts & HDAC_INTSTS_SIS_MASK) {
1221 if ((intsts & (1 << sc->num_iss)) &&
1222 hdac_stream_intr(sc, &sc->play) != 0)
1223 trigger |= HDAC_TRIGGER_PLAY;
1224 if ((intsts & (1 << 0)) &&
1225 hdac_stream_intr(sc, &sc->rec) != 0)
1226 trigger |= HDAC_TRIGGER_REC;
1227 /* XXX to be removed */
1228 #ifdef HDAC_INTR_EXTRA
1229 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1230 HDAC_INTSTS_SIS_MASK);
1231 #endif
1232 }
1233
1234 hdac_unlock(sc);
1235
1236 if (trigger & HDAC_TRIGGER_PLAY)
1237 chn_intr(sc->play.c);
1238 if (trigger & HDAC_TRIGGER_REC)
1239 chn_intr(sc->rec.c);
1240 if (trigger & HDAC_TRIGGER_UNSOL)
1241 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task);
1242 }
1243
1244 /****************************************************************************
1245 * int hdac_reset(hdac_softc *)
1246 *
1247 * Reset the hdac to a quiescent and known state.
1248 ****************************************************************************/
1249 static int
1250 hdac_reset(struct hdac_softc *sc)
1251 {
1252 uint32_t gctl;
1253 int count, i;
1254
1255 /*
1256 * Stop all Streams DMA engine
1257 */
1258 for (i = 0; i < sc->num_iss; i++)
1259 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1260 for (i = 0; i < sc->num_oss; i++)
1261 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1262 for (i = 0; i < sc->num_bss; i++)
1263 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1264
1265 /*
1266 * Stop Control DMA engines.
1267 */
1268 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1269 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1270
1271 /*
1272 * Reset DMA position buffer.
1273 */
1274 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1275 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1276
1277 /*
1278 * Reset the controller. The reset must remain asserted for
1279 * a minimum of 100us.
1280 */
1281 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1282 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1283 count = 10000;
1284 do {
1285 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1286 if (!(gctl & HDAC_GCTL_CRST))
1287 break;
1288 DELAY(10);
1289 } while (--count);
1290 if (gctl & HDAC_GCTL_CRST) {
1291 device_printf(sc->dev, "Unable to put hdac in reset\n");
1292 return (ENXIO);
1293 }
1294 DELAY(100);
1295 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1296 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1297 count = 10000;
1298 do {
1299 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1300 if (gctl & HDAC_GCTL_CRST)
1301 break;
1302 DELAY(10);
1303 } while (--count);
1304 if (!(gctl & HDAC_GCTL_CRST)) {
1305 device_printf(sc->dev, "Device stuck in reset\n");
1306 return (ENXIO);
1307 }
1308
1309 /*
1310 * Wait for codecs to finish their own reset sequence. The delay here
1311 * should be of 250us but for some reasons, on it's not enough on my
1312 * computer. Let's use twice as much as necessary to make sure that
1313 * it's reset properly.
1314 */
1315 DELAY(1000);
1316
1317 return (0);
1318 }
1319
1320
1321 /****************************************************************************
1322 * int hdac_get_capabilities(struct hdac_softc *);
1323 *
1324 * Retreive the general capabilities of the hdac;
1325 * Number of Input Streams
1326 * Number of Output Streams
1327 * Number of bidirectional Streams
1328 * 64bit ready
1329 * CORB and RIRB sizes
1330 ****************************************************************************/
1331 static int
1332 hdac_get_capabilities(struct hdac_softc *sc)
1333 {
1334 uint16_t gcap;
1335 uint8_t corbsize, rirbsize;
1336
1337 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1338 sc->num_iss = HDAC_GCAP_ISS(gcap);
1339 sc->num_oss = HDAC_GCAP_OSS(gcap);
1340 sc->num_bss = HDAC_GCAP_BSS(gcap);
1341
1342 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1343
1344 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1345 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1346 HDAC_CORBSIZE_CORBSZCAP_256)
1347 sc->corb_size = 256;
1348 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1349 HDAC_CORBSIZE_CORBSZCAP_16)
1350 sc->corb_size = 16;
1351 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1352 HDAC_CORBSIZE_CORBSZCAP_2)
1353 sc->corb_size = 2;
1354 else {
1355 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1356 __func__, corbsize);
1357 return (ENXIO);
1358 }
1359
1360 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1361 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1362 HDAC_RIRBSIZE_RIRBSZCAP_256)
1363 sc->rirb_size = 256;
1364 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1365 HDAC_RIRBSIZE_RIRBSZCAP_16)
1366 sc->rirb_size = 16;
1367 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1368 HDAC_RIRBSIZE_RIRBSZCAP_2)
1369 sc->rirb_size = 2;
1370 else {
1371 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1372 __func__, rirbsize);
1373 return (ENXIO);
1374 }
1375
1376 return (0);
1377 }
1378
1379
1380 /****************************************************************************
1381 * void hdac_dma_cb
1382 *
1383 * This function is called by bus_dmamap_load when the mapping has been
1384 * established. We just record the physical address of the mapping into
1385 * the struct hdac_dma passed in.
1386 ****************************************************************************/
1387 static void
1388 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1389 {
1390 struct hdac_dma *dma;
1391
1392 if (error == 0) {
1393 dma = (struct hdac_dma *)callback_arg;
1394 dma->dma_paddr = segs[0].ds_addr;
1395 }
1396 }
1397
1398
1399 /****************************************************************************
1400 * int hdac_dma_alloc
1401 *
1402 * This function allocate and setup a dma region (struct hdac_dma).
1403 * It must be freed by a corresponding hdac_dma_free.
1404 ****************************************************************************/
1405 static int
1406 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1407 {
1408 bus_size_t roundsz;
1409 int result;
1410 int lowaddr;
1411
1412 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1413 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1414 BUS_SPACE_MAXADDR_32BIT;
1415 bzero(dma, sizeof(*dma));
1416
1417 /*
1418 * Create a DMA tag
1419 */
1420 result = bus_dma_tag_create(NULL, /* parent */
1421 HDAC_DMA_ALIGNMENT, /* alignment */
1422 0, /* boundary */
1423 lowaddr, /* lowaddr */
1424 BUS_SPACE_MAXADDR, /* highaddr */
1425 NULL, /* filtfunc */
1426 NULL, /* fistfuncarg */
1427 roundsz, /* maxsize */
1428 1, /* nsegments */
1429 roundsz, /* maxsegsz */
1430 0, /* flags */
1431 &dma->dma_tag); /* dmat */
1432 if (result != 0) {
1433 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1434 __func__, result);
1435 goto hdac_dma_alloc_fail;
1436 }
1437
1438 /*
1439 * Allocate DMA memory
1440 */
1441 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1442 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1443 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1444 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1445 &dma->dma_map);
1446 #else
1447 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1448 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1449 #endif
1450 if (result != 0) {
1451 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1452 __func__, result);
1453 goto hdac_dma_alloc_fail;
1454 }
1455
1456 dma->dma_size = roundsz;
1457
1458 /*
1459 * Map the memory
1460 */
1461 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1462 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1463 if (result != 0 || dma->dma_paddr == 0) {
1464 if (result == 0)
1465 result = ENOMEM;
1466 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1467 __func__, result);
1468 goto hdac_dma_alloc_fail;
1469 }
1470
1471 HDA_BOOTVERBOSE(
1472 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1473 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1474 );
1475
1476 return (0);
1477
1478 hdac_dma_alloc_fail:
1479 hdac_dma_free(sc, dma);
1480
1481 return (result);
1482 }
1483
1484
1485 /****************************************************************************
1486 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1487 *
1488 * Free a struct dhac_dma that has been previously allocated via the
1489 * hdac_dma_alloc function.
1490 ****************************************************************************/
1491 static void
1492 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1493 {
1494 if (dma->dma_map != NULL) {
1495 #if 0
1496 /* Flush caches */
1497 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1498 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1499 #endif
1500 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1501 }
1502 if (dma->dma_vaddr != NULL) {
1503 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1504 dma->dma_vaddr = NULL;
1505 }
1506 dma->dma_map = NULL;
1507 if (dma->dma_tag != NULL) {
1508 bus_dma_tag_destroy(dma->dma_tag);
1509 dma->dma_tag = NULL;
1510 }
1511 dma->dma_size = 0;
1512 }
1513
1514 /****************************************************************************
1515 * int hdac_mem_alloc(struct hdac_softc *)
1516 *
1517 * Allocate all the bus resources necessary to speak with the physical
1518 * controller.
1519 ****************************************************************************/
1520 static int
1521 hdac_mem_alloc(struct hdac_softc *sc)
1522 {
1523 struct hdac_mem *mem;
1524
1525 mem = &sc->mem;
1526 mem->mem_rid = PCIR_BAR(0);
1527 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1528 &mem->mem_rid, RF_ACTIVE);
1529 if (mem->mem_res == NULL) {
1530 device_printf(sc->dev,
1531 "%s: Unable to allocate memory resource\n", __func__);
1532 return (ENOMEM);
1533 }
1534 mem->mem_tag = rman_get_bustag(mem->mem_res);
1535 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1536
1537 return (0);
1538 }
1539
1540 /****************************************************************************
1541 * void hdac_mem_free(struct hdac_softc *)
1542 *
1543 * Free up resources previously allocated by hdac_mem_alloc.
1544 ****************************************************************************/
1545 static void
1546 hdac_mem_free(struct hdac_softc *sc)
1547 {
1548 struct hdac_mem *mem;
1549
1550 mem = &sc->mem;
1551 if (mem->mem_res != NULL)
1552 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1553 mem->mem_res);
1554 mem->mem_res = NULL;
1555 }
1556
1557 /****************************************************************************
1558 * int hdac_irq_alloc(struct hdac_softc *)
1559 *
1560 * Allocate and setup the resources necessary for interrupt handling.
1561 ****************************************************************************/
1562 static int
1563 hdac_irq_alloc(struct hdac_softc *sc)
1564 {
1565 struct hdac_irq *irq;
1566 int result;
1567
1568 irq = &sc->irq;
1569 irq->irq_rid = 0x0;
1570
1571 #if 0 /* TODO: No MSI support in DragonFly yet. */
1572 if ((sc->flags & HDAC_F_MSI) &&
1573 (result = pci_msi_count(sc->dev)) == 1 &&
1574 pci_alloc_msi(sc->dev, &result) == 0)
1575 irq->irq_rid = 0x1;
1576 else
1577 #endif
1578 sc->flags &= ~HDAC_F_MSI;
1579
1580 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1581 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1582 if (irq->irq_res == NULL) {
1583 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1584 __func__);
1585 goto hdac_irq_alloc_fail;
1586 }
1587 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1588 hdac_intr_handler, sc, &irq->irq_handle);
1589 if (result != 0) {
1590 device_printf(sc->dev,
1591 "%s: Unable to setup interrupt handler (%x)\n",
1592 __func__, result);
1593 goto hdac_irq_alloc_fail;
1594 }
1595
1596 return (0);
1597
1598 hdac_irq_alloc_fail:
1599 hdac_irq_free(sc);
1600
1601 return (ENXIO);
1602 }
1603
1604 /****************************************************************************
1605 * void hdac_irq_free(struct hdac_softc *)
1606 *
1607 * Free up resources previously allocated by hdac_irq_alloc.
1608 ****************************************************************************/
1609 static void
1610 hdac_irq_free(struct hdac_softc *sc)
1611 {
1612 struct hdac_irq *irq;
1613
1614 irq = &sc->irq;
1615 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1616 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1617 if (irq->irq_res != NULL)
1618 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1619 irq->irq_res);
1620 #if 0 /* TODO: No MSI support in DragonFly yet. */
1621 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1)
1622 pci_release_msi(sc->dev);
1623 #endif
1624 irq->irq_handle = NULL;
1625 irq->irq_res = NULL;
1626 irq->irq_rid = 0x0;
1627 }
1628
1629 /****************************************************************************
1630 * void hdac_corb_init(struct hdac_softc *)
1631 *
1632 * Initialize the corb registers for operations but do not start it up yet.
1633 * The CORB engine must not be running when this function is called.
1634 ****************************************************************************/
1635 static void
1636 hdac_corb_init(struct hdac_softc *sc)
1637 {
1638 uint8_t corbsize;
1639 uint64_t corbpaddr;
1640
1641 /* Setup the CORB size. */
1642 switch (sc->corb_size) {
1643 case 256:
1644 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1645 break;
1646 case 16:
1647 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1648 break;
1649 case 2:
1650 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1651 break;
1652 default:
1653 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1654 }
1655 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1656
1657 /* Setup the CORB Address in the hdac */
1658 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1659 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1660 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1661
1662 /* Set the WP and RP */
1663 sc->corb_wp = 0;
1664 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1665 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1666 /*
1667 * The HDA specification indicates that the CORBRPRST bit will always
1668 * read as zero. Unfortunately, it seems that at least the 82801G
1669 * doesn't reset the bit to zero, which stalls the corb engine.
1670 * manually reset the bit to zero before continuing.
1671 */
1672 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1673
1674 /* Enable CORB error reporting */
1675 #if 0
1676 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1677 #endif
1678 }
1679
1680 /****************************************************************************
1681 * void hdac_rirb_init(struct hdac_softc *)
1682 *
1683 * Initialize the rirb registers for operations but do not start it up yet.
1684 * The RIRB engine must not be running when this function is called.
1685 ****************************************************************************/
1686 static void
1687 hdac_rirb_init(struct hdac_softc *sc)
1688 {
1689 uint8_t rirbsize;
1690 uint64_t rirbpaddr;
1691
1692 /* Setup the RIRB size. */
1693 switch (sc->rirb_size) {
1694 case 256:
1695 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1696 break;
1697 case 16:
1698 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1699 break;
1700 case 2:
1701 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1702 break;
1703 default:
1704 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1705 }
1706 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1707
1708 /* Setup the RIRB Address in the hdac */
1709 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1710 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1711 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1712
1713 /* Setup the WP and RP */
1714 sc->rirb_rp = 0;
1715 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1716
1717 if (sc->polling == 0) {
1718 /* Setup the interrupt threshold */
1719 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1720
1721 /* Enable Overrun and response received reporting */
1722 #if 0
1723 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1724 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1725 #else
1726 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1727 #endif
1728 }
1729
1730 #if 0
1731 /*
1732 * Make sure that the Host CPU cache doesn't contain any dirty
1733 * cache lines that falls in the rirb. If I understood correctly, it
1734 * should be sufficient to do this only once as the rirb is purely
1735 * read-only from now on.
1736 */
1737 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1738 BUS_DMASYNC_PREREAD);
1739 #endif
1740 }
1741
1742 /****************************************************************************
1743 * void hdac_corb_start(hdac_softc *)
1744 *
1745 * Startup the corb DMA engine
1746 ****************************************************************************/
1747 static void
1748 hdac_corb_start(struct hdac_softc *sc)
1749 {
1750 uint32_t corbctl;
1751
1752 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1753 corbctl |= HDAC_CORBCTL_CORBRUN;
1754 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1755 }
1756
1757 /****************************************************************************
1758 * void hdac_rirb_start(hdac_softc *)
1759 *
1760 * Startup the rirb DMA engine
1761 ****************************************************************************/
1762 static void
1763 hdac_rirb_start(struct hdac_softc *sc)
1764 {
1765 uint32_t rirbctl;
1766
1767 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1768 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1769 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1770 }
1771
1772
1773 /****************************************************************************
1774 * void hdac_scan_codecs(struct hdac_softc *, int)
1775 *
1776 * Scan the bus for available codecs, starting with num.
1777 ****************************************************************************/
1778 static void
1779 hdac_scan_codecs(struct hdac_softc *sc, int num)
1780 {
1781 struct hdac_codec *codec;
1782 int i;
1783 uint16_t statests;
1784
1785 if (num < 0)
1786 num = 0;
1787 if (num >= HDAC_CODEC_MAX)
1788 num = HDAC_CODEC_MAX - 1;
1789
1790 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1791 for (i = num; i < HDAC_CODEC_MAX; i++) {
1792 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1793 /* We have found a codec. */
1794 codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1795 M_HDAC, M_ZERO | M_NOWAIT);
1796 if (codec == NULL) {
1797 device_printf(sc->dev,
1798 "Unable to allocate memory for codec\n");
1799 continue;
1800 }
1801 codec->commands = NULL;
1802 codec->responses_received = 0;
1803 codec->verbs_sent = 0;
1804 codec->sc = sc;
1805 codec->cad = i;
1806 sc->codecs[i] = codec;
1807 if (hdac_probe_codec(codec) != 0)
1808 break;
1809 }
1810 }
1811 /* All codecs have been probed, now try to attach drivers to them */
1812 /* bus_generic_attach(sc->dev); */
1813 }
1814
1815 /****************************************************************************
1816 * void hdac_probe_codec(struct hdac_softc *, int)
1817 *
1818 * Probe a the given codec_id for available function groups.
1819 ****************************************************************************/
1820 static int
1821 hdac_probe_codec(struct hdac_codec *codec)
1822 {
1823 struct hdac_softc *sc = codec->sc;
1824 struct hdac_devinfo *devinfo;
1825 uint32_t vendorid, revisionid, subnode;
1826 int startnode;
1827 int endnode;
1828 int i;
1829 nid_t cad = codec->cad;
1830
1831 HDA_BOOTVERBOSE(
1832 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1833 );
1834 vendorid = hdac_command(sc,
1835 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1836 cad);
1837 revisionid = hdac_command(sc,
1838 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1839 cad);
1840 subnode = hdac_command(sc,
1841 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1842 cad);
1843 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1844 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1845
1846 HDA_BOOTVERBOSE(
1847 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1848 startnode, endnode);
1849 );
1850 for (i = startnode; i < endnode; i++) {
1851 devinfo = hdac_probe_function(codec, i);
1852 if (devinfo != NULL) {
1853 /* XXX Ignore other FG. */
1854 devinfo->vendor_id =
1855 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1856 devinfo->device_id =
1857 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1858 devinfo->revision_id =
1859 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1860 devinfo->stepping_id =
1861 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1862 HDA_BOOTVERBOSE(
1863 device_printf(sc->dev,
1864 "HDA_DEBUG: \tFound AFG nid=%d "
1865 "[startnode=%d endnode=%d]\n",
1866 devinfo->nid, startnode, endnode);
1867 );
1868 return (1);
1869 }
1870 }
1871
1872 HDA_BOOTVERBOSE(
1873 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1874 );
1875 return (0);
1876 }
1877
1878 static struct hdac_devinfo *
1879 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1880 {
1881 struct hdac_softc *sc = codec->sc;
1882 struct hdac_devinfo *devinfo;
1883 uint32_t fctgrptype;
1884 nid_t cad = codec->cad;
1885
1886 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1887 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1888
1889 /* XXX For now, ignore other FG. */
1890 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1891 return (NULL);
1892
1893 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1894 M_NOWAIT | M_ZERO);
1895 if (devinfo == NULL) {
1896 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1897 __func__);
1898 return (NULL);
1899 }
1900
1901 devinfo->nid = nid;
1902 devinfo->node_type = fctgrptype;
1903 devinfo->codec = codec;
1904
1905 hdac_add_child(sc, devinfo);
1906
1907 return (devinfo);
1908 }
1909
1910 static void
1911 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1912 {
1913 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1914 device_set_ivars(devinfo->dev, (void *)devinfo);
1915 /* XXX - Print more information when booting verbose??? */
1916 }
1917
1918 static void
1919 hdac_widget_connection_parse(struct hdac_widget *w)
1920 {
1921 struct hdac_softc *sc = w->devinfo->codec->sc;
1922 uint32_t res;
1923 int i, j, max, ents, entnum;
1924 nid_t cad = w->devinfo->codec->cad;
1925 nid_t nid = w->nid;
1926 nid_t cnid, addcnid, prevcnid;
1927
1928 w->nconns = 0;
1929
1930 res = hdac_command(sc,
1931 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1932
1933 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1934
1935 if (ents < 1)
1936 return;
1937
1938 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1939 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1940 prevcnid = 0;
1941
1942 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
1943 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
1944 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
1945 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1946 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1947
1948 for (i = 0; i < ents; i += entnum) {
1949 res = hdac_command(sc,
1950 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1951 for (j = 0; j < entnum; j++) {
1952 cnid = CONN_CNID(res, entnum, j);
1953 if (cnid == 0) {
1954 if (w->nconns < ents)
1955 device_printf(sc->dev,
1956 "%s: nid=%d WARNING: zero cnid "
1957 "entnum=%d j=%d index=%d "
1958 "entries=%d found=%d res=0x%08x\n",
1959 __func__, nid, entnum, j, i,
1960 ents, w->nconns, res);
1961 else
1962 goto getconns_out;
1963 }
1964 if (cnid < w->devinfo->startnode ||
1965 cnid >= w->devinfo->endnode) {
1966 HDA_BOOTVERBOSE(
1967 device_printf(sc->dev,
1968 "%s: GHOST: nid=%d j=%d "
1969 "entnum=%d index=%d res=0x%08x\n",
1970 __func__, nid, j, entnum, i, res);
1971 );
1972 }
1973 if (CONN_RANGE(res, entnum, j) == 0)
1974 addcnid = cnid;
1975 else if (prevcnid == 0 || prevcnid >= cnid) {
1976 device_printf(sc->dev,
1977 "%s: WARNING: Invalid child range "
1978 "nid=%d index=%d j=%d entnum=%d "
1979 "prevcnid=%d cnid=%d res=0x%08x\n",
1980 __func__, nid, i, j, entnum, prevcnid,
1981 cnid, res);
1982 addcnid = cnid;
1983 } else
1984 addcnid = prevcnid + 1;
1985 while (addcnid <= cnid) {
1986 if (w->nconns > max) {
1987 device_printf(sc->dev,
1988 "%s: nid=%d: Adding %d: "
1989 "Max connection reached! max=%d\n",
1990 __func__, nid, addcnid, max + 1);
1991 goto getconns_out;
1992 }
1993 w->conns[w->nconns++] = addcnid++;
1994 }
1995 prevcnid = cnid;
1996 }
1997 }
1998
1999 getconns_out:
2000 HDA_BOOTVERBOSE(
2001 device_printf(sc->dev,
2002 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
2003 __func__, nid, ents, w->nconns);
2004 );
2005 return;
2006 }
2007
2008 static uint32_t
2009 hdac_widget_pin_getconfig(struct hdac_widget *w)
2010 {
2011 struct hdac_softc *sc;
2012 uint32_t config, orig, id;
2013 nid_t cad, nid;
2014
2015 sc = w->devinfo->codec->sc;
2016 cad = w->devinfo->codec->cad;
2017 nid = w->nid;
2018 id = hdac_codec_id(w->devinfo);
2019
2020 config = hdac_command(sc,
2021 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
2022 cad);
2023 orig = config;
2024
2025 /*
2026 * XXX REWRITE!!!! Don't argue!
2027 */
2028 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
2029 switch (nid) {
2030 case 26:
2031 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2032 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2033 break;
2034 case 27:
2035 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2036 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
2037 break;
2038 default:
2039 break;
2040 }
2041 } else if (id == HDA_CODEC_ALC880 &&
2042 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
2043 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2044 /*
2045 * Super broken BIOS
2046 */
2047 switch (nid) {
2048 case 20:
2049 break;
2050 case 21:
2051 break;
2052 case 22:
2053 break;
2054 case 23:
2055 break;
2056 case 24: /* MIC1 */
2057 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2058 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2059 break;
2060 case 25: /* XXX MIC2 */
2061 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2062 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2063 break;
2064 case 26: /* LINE1 */
2065 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2066 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2067 break;
2068 case 27: /* XXX LINE2 */
2069 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2070 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2071 break;
2072 case 28: /* CD */
2073 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2074 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2075 break;
2076 case 30:
2077 break;
2078 case 31:
2079 break;
2080 default:
2081 break;
2082 }
2083 } else if (id == HDA_CODEC_ALC883 &&
2084 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR ||
2085 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) {
2086 switch (nid) {
2087 case 25:
2088 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2089 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2090 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2091 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2092 break;
2093 case 28:
2094 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2095 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2096 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2097 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2098 break;
2099 default:
2100 break;
2101 }
2102 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2103 HP_V3000_SUBVENDOR) {
2104 switch (nid) {
2105 case 18:
2106 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2107 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2108 break;
2109 case 20:
2110 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2111 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2112 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2113 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2114 break;
2115 case 21:
2116 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2117 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2118 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2119 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2120 break;
2121 default:
2122 break;
2123 }
2124 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2125 HP_DV5000_SUBVENDOR) {
2126 switch (nid) {
2127 case 20:
2128 case 21:
2129 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2130 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2131 break;
2132 default:
2133 break;
2134 }
2135 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2136 ASUS_W6F_SUBVENDOR) {
2137 switch (nid) {
2138 case 11:
2139 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2140 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2141 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2142 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2143 break;
2144 case 15:
2145 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2146 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2147 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2148 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2149 break;
2150 default:
2151 break;
2152 }
2153 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2154 UNIWILL_9075_SUBVENDOR) {
2155 switch (nid) {
2156 case 15:
2157 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2158 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2159 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2160 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2161 break;
2162 default:
2163 break;
2164 }
2165 } else if (id == HDA_CODEC_AD1986A &&
2166 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2167 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) {
2168 switch (nid) {
2169 case 28: /* LINE */
2170 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2171 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2172 break;
2173 case 29: /* MIC */
2174 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2175 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2176 break;
2177 default:
2178 break;
2179 }
2180 }
2181
2182 HDA_BOOTVERBOSE(
2183 if (config != orig)
2184 device_printf(sc->dev,
2185 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2186 nid, orig, config);
2187 );
2188
2189 return (config);
2190 }
2191
2192 static uint32_t
2193 hdac_widget_pin_getcaps(struct hdac_widget *w)
2194 {
2195 struct hdac_softc *sc;
2196 uint32_t caps, orig, id;
2197 nid_t cad, nid;
2198
2199 sc = w->devinfo->codec->sc;
2200 cad = w->devinfo->codec->cad;
2201 nid = w->nid;
2202 id = hdac_codec_id(w->devinfo);
2203
2204 caps = hdac_command(sc,
2205 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2206 orig = caps;
2207
2208 HDA_BOOTVERBOSE(
2209 if (caps != orig)
2210 device_printf(sc->dev,
2211 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2212 nid, orig, caps);
2213 );
2214
2215 return (caps);
2216 }
2217
2218 static void
2219 hdac_widget_pin_parse(struct hdac_widget *w)
2220 {
2221 struct hdac_softc *sc = w->devinfo->codec->sc;
2222 uint32_t config, pincap;
2223 char *devstr, *connstr;
2224 nid_t cad = w->devinfo->codec->cad;
2225 nid_t nid = w->nid;
2226
2227 config = hdac_widget_pin_getconfig(w);
2228 w->wclass.pin.config = config;
2229
2230 pincap = hdac_widget_pin_getcaps(w);
2231 w->wclass.pin.cap = pincap;
2232
2233 w->wclass.pin.ctrl = hdac_command(sc,
2234 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2235 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2236 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2237 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2238 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2239
2240 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2241 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2242 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2243 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2244 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2245 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2246 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2247 w->param.eapdbtl = hdac_command(sc,
2248 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2249 w->param.eapdbtl &= 0x7;
2250 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2251 } else
2252 w->param.eapdbtl = HDAC_INVALID;
2253
2254 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2255 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2256 devstr = "line out";
2257 break;
2258 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2259 devstr = "speaker";
2260 break;
2261 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2262 devstr = "headphones out";
2263 break;
2264 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2265 devstr = "CD";
2266 break;
2267 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2268 devstr = "SPDIF out";
2269 break;
2270 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2271 devstr = "digital (other) out";
2272 break;
2273 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2274 devstr = "modem, line side";
2275 break;
2276 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2277 devstr = "modem, handset side";
2278 break;
2279 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2280 devstr = "line in";
2281 break;
2282 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2283 devstr = "AUX";
2284 break;
2285 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2286 devstr = "Mic in";
2287 break;
2288 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2289 devstr = "telephony";
2290 break;
2291 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2292 devstr = "SPDIF in";
2293 break;
2294 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2295 devstr = "digital (other) in";
2296 break;
2297 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2298 devstr = "other";
2299 break;
2300 default:
2301 devstr = "unknown";
2302 break;
2303 }
2304
2305 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2306 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2307 connstr = "jack";
2308 break;
2309 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2310 connstr = "none";
2311 break;
2312 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2313 connstr = "fixed";
2314 break;
2315 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2316 connstr = "jack / fixed";
2317 break;
2318 default:
2319 connstr = "unknown";
2320 break;
2321 }
2322
2323 strlcat(w->name, ": ", sizeof(w->name));
2324 strlcat(w->name, devstr, sizeof(w->name));
2325 strlcat(w->name, " (", sizeof(w->name));
2326 strlcat(w->name, connstr, sizeof(w->name));
2327 strlcat(w->name, ")", sizeof(w->name));
2328 }
2329
2330 static void
2331 hdac_widget_parse(struct hdac_widget *w)
2332 {
2333 struct hdac_softc *sc = w->devinfo->codec->sc;
2334 uint32_t wcap, cap;
2335 char *typestr;
2336 nid_t cad = w->devinfo->codec->cad;
2337 nid_t nid = w->nid;
2338
2339 wcap = hdac_command(sc,
2340 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2341 cad);
2342 w->param.widget_cap = wcap;
2343 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2344
2345 switch (w->type) {
2346 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2347 typestr = "audio output";
2348 break;
2349 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2350 typestr = "audio input";
2351 break;
2352 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2353 typestr = "audio mixer";
2354 break;
2355 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2356 typestr = "audio selector";
2357 break;
2358 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2359 typestr = "pin";
2360 break;
2361 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2362 typestr = "power widget";
2363 break;
2364 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2365 typestr = "volume widget";
2366 break;
2367 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2368 typestr = "beep widget";
2369 break;
2370 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2371 typestr = "vendor widget";
2372 break;
2373 default:
2374 typestr = "unknown type";
2375 break;
2376 }
2377
2378 strlcpy(w->name, typestr, sizeof(w->name));
2379
2380 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2381 hdac_command(sc,
2382 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2383 cad);
2384 DELAY(1000);
2385 }
2386
2387 hdac_widget_connection_parse(w);
2388
2389 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2390 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2391 w->param.outamp_cap =
2392 hdac_command(sc,
2393 HDA_CMD_GET_PARAMETER(cad, nid,
2394 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2395 else
2396 w->param.outamp_cap =
2397 w->devinfo->function.audio.outamp_cap;
2398 } else
2399 w->param.outamp_cap = 0;
2400
2401 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2402 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2403 w->param.inamp_cap =
2404 hdac_command(sc,
2405 HDA_CMD_GET_PARAMETER(cad, nid,
2406 HDA_PARAM_INPUT_AMP_CAP), cad);
2407 else
2408 w->param.inamp_cap =
2409 w->devinfo->function.audio.inamp_cap;
2410 } else
2411 w->param.inamp_cap = 0;
2412
2413 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2414 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2415 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2416 cap = hdac_command(sc,
2417 HDA_CMD_GET_PARAMETER(cad, nid,
2418 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2419 w->param.supp_stream_formats = (cap != 0) ? cap :
2420 w->devinfo->function.audio.supp_stream_formats;
2421 cap = hdac_command(sc,
2422 HDA_CMD_GET_PARAMETER(cad, nid,
2423 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2424 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2425 w->devinfo->function.audio.supp_pcm_size_rate;
2426 } else {
2427 w->param.supp_stream_formats =
2428 w->devinfo->function.audio.supp_stream_formats;
2429 w->param.supp_pcm_size_rate =
2430 w->devinfo->function.audio.supp_pcm_size_rate;
2431 }
2432 } else {
2433 w->param.supp_stream_formats = 0;
2434 w->param.supp_pcm_size_rate = 0;
2435 }
2436
2437 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2438 hdac_widget_pin_parse(w);
2439 }
2440
2441 static struct hdac_widget *
2442 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2443 {
2444 if (devinfo == NULL || devinfo->widget == NULL ||
2445 nid < devinfo->startnode || nid >= devinfo->endnode)
2446 return (NULL);
2447 return (&devinfo->widget[nid - devinfo->startnode]);
2448 }
2449
2450 static __inline int
2451 hda_poll_channel(struct hdac_chan *ch)
2452 {
2453 uint32_t sz, delta;
2454 volatile uint32_t ptr;
2455
2456 if (!(ch->flags & HDAC_CHN_RUNNING))
2457 return (0);
2458
2459 sz = ch->blksz * ch->blkcnt;
2460 if (ch->dmapos != NULL)
2461 ptr = *(ch->dmapos);
2462 else
2463 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2464 ch->off + HDAC_SDLPIB);
2465 ch->ptr = ptr;
2466 ptr %= sz;
2467 ptr &= ~(ch->blksz - 1);
2468 delta = (sz + ptr - ch->prevptr) % sz;
2469
2470 if (delta < ch->blksz)
2471 return (0);
2472
2473 ch->prevptr = ptr;
2474
2475 return (1);
2476 }
2477
2478 #define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \
2479 HDAC_CHN_RUNNING)
2480
2481 static void
2482 hda_poll_callback(void *arg)
2483 {
2484 struct hdac_softc *sc = arg;
2485 uint32_t trigger;
2486
2487 if (sc == NULL)
2488 return;
2489
2490 hdac_lock(sc);
2491 if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2492 hdac_unlock(sc);
2493 return;
2494 }
2495
2496 trigger = 0;
2497 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0;
2498 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0;
2499
2500 /* XXX */
2501 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2502 hda_poll_callback, sc);
2503
2504 hdac_unlock(sc);
2505
2506 if (trigger & HDAC_TRIGGER_PLAY)
2507 chn_intr(sc->play.c);
2508 if (trigger & HDAC_TRIGGER_REC)
2509 chn_intr(sc->rec.c);
2510 }
2511
2512 static int
2513 hdac_rirb_flush(struct hdac_softc *sc)
2514 {
2515 struct hdac_rirb *rirb_base, *rirb;
2516 struct hdac_codec *codec;
2517 struct hdac_command_list *commands;
2518 nid_t cad;
2519 uint32_t resp;
2520 uint8_t rirbwp;
2521 int ret;
2522
2523 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2524 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2525 #if 0
2526 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2527 BUS_DMASYNC_POSTREAD);
2528 #endif
2529 ret = 0;
2530
2531 while (sc->rirb_rp != rirbwp) {
2532 sc->rirb_rp++;
2533 sc->rirb_rp %= sc->rirb_size;
2534 rirb = &rirb_base[sc->rirb_rp];
2535 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2536 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2537 sc->codecs[cad] == NULL)
2538 continue;
2539 resp = rirb->response;
2540 codec = sc->codecs[cad];
2541 commands = codec->commands;
2542 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2543 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2544 ((resp >> 26) & 0xffff);
2545 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2546 } else if (commands != NULL && commands->num_commands > 0 &&
2547 codec->responses_received < commands->num_commands)
2548 commands->responses[codec->responses_received++] =
2549 resp;
2550 ret++;
2551 }
2552
2553 return (ret);
2554 }
2555
2556 static int
2557 hdac_unsolq_flush(struct hdac_softc *sc)
2558 {
2559 nid_t cad;
2560 uint32_t tag;
2561 int ret = 0;
2562
2563 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2564 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2565 while (sc->unsolq_rp != sc->unsolq_wp) {
2566 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2567 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2568 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2569 hdac_unsolicited_handler(sc->codecs[cad], tag);
2570 ret++;
2571 }
2572 sc->unsolq_st = HDAC_UNSOLQ_READY;
2573 }
2574
2575 return (ret);
2576 }
2577
2578 static void
2579 hdac_poll_callback(void *arg)
2580 {
2581 struct hdac_softc *sc = arg;
2582 if (sc == NULL)
2583 return;
2584
2585 hdac_lock(sc);
2586 if (sc->polling == 0 || sc->poll_ival == 0) {
2587 hdac_unlock(sc);
2588 return;
2589 }
2590 if (hdac_rirb_flush(sc) != 0)
2591 hdac_unsolq_flush(sc);
2592 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2593 hdac_unlock(sc);
2594 }
2595
2596 static void
2597 hdac_stream_stop(struct hdac_chan *ch)
2598 {
2599 struct hdac_softc *sc = ch->devinfo->codec->sc;
2600 uint32_t ctl;
2601
2602 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2603 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2604 HDAC_SDCTL_RUN);
2605 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2606
2607 ch->flags &= ~HDAC_CHN_RUNNING;
2608
2609 if (sc->polling != 0) {
2610 int pollticks;
2611
2612 if (hda_chan_active(sc) == 0) {
2613 callout_stop(&sc->poll_hda);
2614 sc->poll_ticks = 1;
2615 } else {
2616 if (sc->play.flags & HDAC_CHN_RUNNING)
2617 ch = &sc->play;
2618 else
2619 ch = &sc->rec;
2620 pollticks = ((uint64_t)hz * ch->blksz) /
2621 ((uint64_t)sndbuf_getbps(ch->b) *
2622 sndbuf_getspd(ch->b));
2623 pollticks >>= 2;
2624 if (pollticks > hz)
2625 pollticks = hz;
2626 if (pollticks < 1) {
2627 HDA_BOOTVERBOSE(
2628 device_printf(sc->dev,
2629 "%s: pollticks=%d < 1 !\n",
2630 __func__, pollticks);
2631 );
2632 pollticks = 1;
2633 }
2634 if (pollticks > sc->poll_ticks) {
2635 HDA_BOOTVERBOSE(
2636 device_printf(sc->dev,
2637 "%s: pollticks %d -> %d\n",
2638 __func__, sc->poll_ticks,
2639 pollticks);
2640 );
2641 sc->poll_ticks = pollticks;
2642 callout_reset(&sc->poll_hda, 1,
2643 hda_poll_callback, sc);
2644 }
2645 }
2646 } else {
2647 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2648 ctl &= ~(1 << (ch->off >> 5));
2649 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2650 }
2651 }
2652
2653 static void
2654 hdac_stream_start(struct hdac_chan *ch)
2655 {
2656 struct hdac_softc *sc = ch->devinfo->codec->sc;
2657 uint32_t ctl;
2658
2659 if (sc->polling != 0) {
2660 int pollticks;
2661
2662 pollticks = ((uint64_t)hz * ch->blksz) /
2663 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2664 pollticks >>= 2;
2665 if (pollticks > hz)
2666 pollticks = hz;
2667 if (pollticks < 1) {
2668 HDA_BOOTVERBOSE(
2669 device_printf(sc->dev,
2670 "%s: pollticks=%d < 1 !\n",
2671 __func__, pollticks);
2672 );
2673 pollticks = 1;
2674 }
2675 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2676 HDA_BOOTVERBOSE(
2677 if (hda_chan_active(sc) == 0) {
2678 device_printf(sc->dev,
2679 "%s: pollticks=%d\n",
2680 __func__, pollticks);
2681 } else {
2682 device_printf(sc->dev,
2683 "%s: pollticks %d -> %d\n",
2684 __func__, sc->poll_ticks,
2685 pollticks);
2686 }
2687 );
2688 sc->poll_ticks = pollticks;
2689 callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2690 sc);
2691 }
2692 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2693 ctl |= HDAC_SDCTL_RUN;
2694 } else {
2695 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2696 ctl |= 1 << (ch->off >> 5);
2697 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2698 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2699 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2700 HDAC_SDCTL_RUN;
2701 }
2702 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2703
2704 ch->flags |= HDAC_CHN_RUNNING;
2705 }
2706
2707 static void
2708 hdac_stream_reset(struct hdac_chan *ch)
2709 {
2710 struct hdac_softc *sc = ch->devinfo->codec->sc;
2711 int timeout = 1000;
2712 int to = timeout;
2713 uint32_t ctl;
2714
2715 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2716 ctl |= HDAC_SDCTL_SRST;
2717 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2718 do {
2719 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2720 if (ctl & HDAC_SDCTL_SRST)
2721 break;
2722 DELAY(10);
2723 } while (--to);
2724 if (!(ctl & HDAC_SDCTL_SRST)) {
2725 device_printf(sc->dev, "timeout in reset\n");
2726 }
2727 ctl &= ~HDAC_SDCTL_SRST;
2728 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2729 to = timeout;
2730 do {
2731 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2732 if (!(ctl & HDAC_SDCTL_SRST))
2733 break;
2734 DELAY(10);
2735 } while (--to);
2736 if (ctl & HDAC_SDCTL_SRST)
2737 device_printf(sc->dev, "can't reset!\n");
2738 }
2739
2740 static void
2741 hdac_stream_setid(struct hdac_chan *ch)
2742 {
2743 struct hdac_softc *sc = ch->devinfo->codec->sc;
2744 uint32_t ctl;
2745
2746 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2747 ctl &= ~HDAC_SDCTL2_STRM_MASK;
2748 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2749 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2750 }
2751
2752 static void
2753 hdac_bdl_setup(struct hdac_chan *ch)
2754 {
2755 struct hdac_softc *sc = ch->devinfo->codec->sc;
2756 struct hdac_bdle *bdle;
2757 uint64_t addr;
2758 uint32_t blksz, blkcnt;
2759 int i;
2760
2761 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2762 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2763
2764 if (sc->polling != 0) {
2765 blksz = ch->blksz * ch->blkcnt;
2766 blkcnt = 1;
2767 } else {
2768 blksz = ch->blksz;
2769 blkcnt = ch->blkcnt;
2770 }
2771
2772 for (i = 0; i < blkcnt; i++, bdle++) {
2773 bdle->addrl = (uint32_t)addr;
2774 bdle->addrh = (uint32_t)(addr >> 32);
2775 bdle->len = blksz;
2776 bdle->ioc = 1 ^ sc->polling;
2777 addr += blksz;
2778 }
2779
2780 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2781 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2782 addr = ch->bdl_dma.dma_paddr;
2783 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2784 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2785 if (ch->dmapos != NULL &&
2786 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2787 addr = sc->pos_dma.dma_paddr;
2788 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2789 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2790 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2791 }
2792 }
2793
2794 static int
2795 hdac_bdl_alloc(struct hdac_chan *ch)
2796 {
2797 struct hdac_softc *sc = ch->devinfo->codec->sc;
2798 int rc;
2799
2800 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2801 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2802 if (rc) {
2803 device_printf(sc->dev, "can't alloc bdl\n");
2804 return (rc);
2805 }
2806
2807 return (0);
2808 }
2809
2810 static void
2811 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2812 int index, int lmute, int rmute,
2813 int left, int right, int dir)
2814 {
2815 uint16_t v = 0;
2816
2817 if (sc == NULL)
2818 return;
2819
2820 if (left != right || lmute != rmute) {
2821 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2822 (lmute << 7) | left;
2823 hdac_command(sc,
2824 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2825 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2826 (rmute << 7) | right;
2827 } else
2828 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2829 (lmute << 7) | left;
2830
2831 hdac_command(sc,
2832 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2833 }
2834
2835 static void
2836 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2837 int left, int right)
2838 {
2839 struct hdac_softc *sc;
2840 nid_t nid, cad;
2841 int lmute, rmute;
2842
2843 if (ctl == NULL || ctl->widget == NULL ||
2844 ctl->widget->devinfo == NULL ||
2845 ctl->widget->devinfo->codec == NULL ||
2846 ctl->widget->devinfo->codec->sc == NULL)
2847 return;
2848
2849 sc = ctl->widget->devinfo->codec->sc;
2850 cad = ctl->widget->devinfo->codec->cad;
2851 nid = ctl->widget->nid;
2852
2853 if (mute == HDA_AMP_MUTE_DEFAULT) {
2854 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2855 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2856 } else {
2857 lmute = HDA_AMP_LEFT_MUTED(mute);
2858 rmute = HDA_AMP_RIGHT_MUTED(mute);
2859 }
2860
2861 if (ctl->dir & HDA_CTL_OUT)
2862 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2863 lmute, rmute, left, right, 0);
2864 if (ctl->dir & HDA_CTL_IN)
2865 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2866 lmute, rmute, left, right, 1);
2867 ctl->left = left;
2868 ctl->right = right;
2869 }
2870
2871 static void
2872 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2873 {
2874 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2875 return;
2876 hdac_command(w->devinfo->codec->sc,
2877 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2878 w->nid, index), w->devinfo->codec->cad);
2879 w->selconn = index;
2880 }
2881
2882
2883 /****************************************************************************
2884 * uint32_t hdac_command_sendone_internal
2885 *
2886 * Wrapper function that sends only one command to a given codec
2887 ****************************************************************************/
2888 static uint32_t
2889 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2890 {
2891 struct hdac_command_list cl;
2892 uint32_t response = HDAC_INVALID;
2893
2894 if (!hdac_lockowned(sc))
2895 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2896 cl.num_commands = 1;
2897 cl.verbs = &verb;
2898 cl.responses = &response;
2899
2900 hdac_command_send_internal(sc, &cl, cad);
2901
2902 return (response);
2903 }
2904
2905 /****************************************************************************
2906 * hdac_command_send_internal
2907 *
2908 * Send a command list to the codec via the corb. We queue as much verbs as
2909 * we can and msleep on the codec. When the interrupt get the responses
2910 * back from the rirb, it will wake us up so we can queue the remaining verbs
2911 * if any.
2912 ****************************************************************************/
2913 static void
2914 hdac_command_send_internal(struct hdac_softc *sc,
2915 struct hdac_command_list *commands, nid_t cad)
2916 {
2917 struct hdac_codec *codec;
2918 int corbrp;
2919 uint32_t *corb;
2920 int timeout;
2921 int retry = 10;
2922 struct hdac_rirb *rirb_base;
2923
2924 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2925 commands->num_commands < 1)
2926 return;
2927
2928 codec = sc->codecs[cad];
2929 codec->commands = commands;
2930 codec->responses_received = 0;
2931 codec->verbs_sent = 0;
2932 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2933 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2934
2935 do {
2936 if (codec->verbs_sent != commands->num_commands) {
2937 /* Queue as many verbs as possible */
2938 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2939 #if 0
2940 bus_dmamap_sync(sc->corb_dma.dma_tag,
2941 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2942 #endif
2943 while (codec->verbs_sent != commands->num_commands &&
2944 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2945 sc->corb_wp++;
2946 sc->corb_wp %= sc->corb_size;
2947 corb[sc->corb_wp] =
2948 commands->verbs[codec->verbs_sent++];
2949 }
2950
2951 /* Send the verbs to the codecs */
2952 #if 0
2953 bus_dmamap_sync(sc->corb_dma.dma_tag,
2954 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2955 #endif
2956 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2957 }
2958
2959 timeout = 1000;
2960 while (hdac_rirb_flush(sc) == 0 && --timeout)
2961 DELAY(10);
2962 } while ((codec->verbs_sent != commands->num_commands ||
2963 codec->responses_received != commands->num_commands) && --retry);
2964
2965 if (retry == 0)
2966 device_printf(sc->dev,
2967 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2968 __func__, commands->num_commands, codec->verbs_sent,
2969 codec->responses_received);
2970
2971 codec->commands = NULL;
2972 codec->responses_received = 0;
2973 codec->verbs_sent = 0;
2974
2975 hdac_unsolq_flush(sc);
2976 }
2977
2978
2979 /****************************************************************************
2980 * Device Methods
2981 ****************************************************************************/
2982
2983 /****************************************************************************
2984 * int hdac_probe(device_t)
2985 *
2986 * Probe for the presence of an hdac. If none is found, check for a generic
2987 * match using the subclass of the device.
2988 ****************************************************************************/
2989 static int
2990 hdac_probe(device_t dev)
2991 {
2992 int i, result;
2993 uint32_t model;
2994 uint16_t class, subclass;
2995 char desc[64];
2996
2997 model = (uint32_t)pci_get_device(dev) << 16;
2998 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2999 class = pci_get_class(dev);
3000 subclass = pci_get_subclass(dev);
3001
3002 bzero(desc, sizeof(desc));
3003 result = ENXIO;
3004 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
3005 if (hdac_devices[i].model == model) {
3006 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3007 result = BUS_PROBE_DEFAULT;
3008 break;
3009 }
3010 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
3011 class == PCIC_MULTIMEDIA &&
3012 subclass == PCIS_MULTIMEDIA_HDA) {
3013 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3014 result = BUS_PROBE_GENERIC;
3015 break;
3016 }
3017 }
3018 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
3019 subclass == PCIS_MULTIMEDIA_HDA) {
3020 strlcpy(desc, "Generic", sizeof(desc));
3021 result = BUS_PROBE_GENERIC;
3022 }
3023 if (result != ENXIO) {
3024 strlcat(desc, " High Definition Audio Controller",
3025 sizeof(desc));
3026 device_set_desc_copy(dev, desc);
3027 }
3028
3029 return (result);
3030 }
3031
3032 static void *
3033 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
3034 struct pcm_channel *c, int dir)
3035 {
3036 struct hdac_devinfo *devinfo = data;
3037 struct hdac_softc *sc = devinfo->codec->sc;
3038 struct hdac_chan *ch;
3039
3040 hdac_lock(sc);
3041 if (dir == PCMDIR_PLAY) {
3042 ch = &sc->play;
3043 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
3044 devinfo->function.audio.playcnt++;
3045 } else {
3046 ch = &sc->rec;
3047 ch->off = devinfo->function.audio.reccnt << 5;
3048 devinfo->function.audio.reccnt++;
3049 }
3050 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3051 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3052 ch->pcmrates[0] = 48000;
3053 ch->pcmrates[1] = 0;
3054 }
3055 if (sc->pos_dma.dma_vaddr != NULL)
3056 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3057 (sc->streamcnt * 8));
3058 else
3059 ch->dmapos = NULL;
3060 ch->sid = ++sc->streamcnt;
3061 ch->dir = dir;
3062 ch->b = b;
3063 ch->c = c;
3064 ch->devinfo = devinfo;
3065 ch->blksz = sc->chan_size / sc->chan_blkcnt;
3066 ch->blkcnt = sc->chan_blkcnt;
3067 hdac_unlock(sc);
3068
3069 if (hdac_bdl_alloc(ch) != 0) {
3070 ch->blkcnt = 0;
3071 return (NULL);
3072 }
3073
3074 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
3075 return (NULL);
3076
3077 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
3078 PAT_UNCACHEABLE);
3079
3080 return (ch);
3081 }
3082
3083 static int
3084 hdac_channel_free(kobj_t obj, void *data)
3085 {
3086 struct hdac_softc *sc;
3087 struct hdac_chan *ch;
3088
3089 ch = (struct hdac_chan *)data;
3090 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
3091 ch->devinfo->codec->sc : NULL;
3092 if (ch != NULL && sc != NULL) {
3093 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3094 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3095 }
3096
3097 return (1);
3098 }
3099
3100 static int
3101 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3102 {
3103 struct hdac_chan *ch = data;
3104 int i;
3105
3106 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3107 if (format == ch->caps.fmtlist[i]) {
3108 ch->fmt = format;
3109 return (0);
3110 }
3111 }
3112
3113 return (EINVAL);
3114 }
3115
3116 static int
3117 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3118 {
3119 struct hdac_chan *ch = data;
3120 uint32_t spd = 0, threshold;
3121 int i;
3122
3123 for (i = 0; ch->pcmrates[i] != 0; i++) {
3124 spd = ch->pcmrates[i];
3125 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3126 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3127 if (speed < threshold)
3128 break;
3129 }
3130
3131 if (spd == 0) /* impossible */
3132 ch->spd = 48000;
3133 else
3134 ch->spd = spd;
3135
3136 return (ch->spd);
3137 }
3138
3139 static void
3140 hdac_stream_setup(struct hdac_chan *ch)
3141 {
3142 struct hdac_softc *sc = ch->devinfo->codec->sc;
3143 struct hdac_widget *w;
3144 int i, chn, totalchn;
3145 nid_t cad = ch->devinfo->codec->cad;
3146 uint16_t fmt;
3147
3148 fmt = 0;
3149 if (ch->fmt & AFMT_S16_LE)
3150 fmt |= ch->bit16 << 4;
3151 else if (ch->fmt & AFMT_S32_LE)
3152 fmt |= ch->bit32 << 4;
3153 else
3154 fmt |= 1 << 4;
3155
3156 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3157 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3158 fmt |= hda_rate_tab[i].base;
3159 fmt |= hda_rate_tab[i].mul;
3160 fmt |= hda_rate_tab[i].div;
3161 break;
3162 }
3163 }
3164
3165 if (ch->fmt & AFMT_STEREO) {
3166 fmt |= 1;
3167 totalchn = 2;
3168 } else
3169 totalchn = 1;
3170
3171 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3172
3173 chn = 0;
3174 for (i = 0; ch->io[i] != -1; i++) {
3175 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3176 if (w == NULL)
3177 continue;
3178 HDA_BOOTVERBOSE(
3179 device_printf(sc->dev,
3180 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3181 "fmt=0x%08x\n",
3182 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3183 ch->io[i], fmt);
3184 );
3185 hdac_command(sc,
3186 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3187 hdac_command(sc,
3188 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3189 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), cad);
3190 chn +=
3191 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ?
3192 2 : 1;
3193 }
3194 }
3195
3196 static int
3197 hdac_channel_setfragments(kobj_t obj, void *data,
3198 uint32_t blksz, uint32_t blkcnt)
3199 {
3200 struct hdac_chan *ch = data;
3201 struct hdac_softc *sc = ch->devinfo->codec->sc;
3202
3203 blksz &= HDA_BLK_ALIGN;
3204
3205 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3206 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3207 if (blksz < HDA_BLK_MIN)
3208 blksz = HDA_BLK_MIN;
3209 if (blkcnt > HDA_BDL_MAX)
3210 blkcnt = HDA_BDL_MAX;
3211 if (blkcnt < HDA_BDL_MIN)
3212 blkcnt = HDA_BDL_MIN;
3213
3214 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3215 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3216 blkcnt >>= 1;
3217 else if ((blksz >> 1) >= HDA_BLK_MIN)
3218 blksz >>= 1;
3219 else
3220 break;
3221 }
3222
3223 if ((sndbuf_getblksz(ch->b) != blksz ||
3224 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3225 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3226 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3227 __func__, blksz, blkcnt);
3228
3229 ch->blksz = sndbuf_getblksz(ch->b);
3230 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3231
3232 return (1);
3233 }
3234
3235 static int
3236 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3237 {
3238 struct hdac_chan *ch = data;
3239 struct hdac_softc *sc = ch->devinfo->codec->sc;
3240
3241 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3242
3243 return (ch->blksz);
3244 }
3245
3246 static void
3247 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3248 {
3249 struct hdac_devinfo *devinfo = ch->devinfo;
3250 nid_t cad = devinfo->codec->cad;
3251 int i;
3252
3253 hdac_stream_stop(ch);
3254
3255 for (i = 0; ch->io[i] != -1; i++) {
3256 hdac_command(sc,
3257 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3258 0), cad);
3259 }
3260 }
3261
3262 static void
3263 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3264 {
3265 ch->ptr = 0;
3266 ch->prevptr = 0;
3267 hdac_stream_stop(ch);
3268 hdac_stream_reset(ch);
3269 hdac_bdl_setup(ch);
3270 hdac_stream_setid(ch);
3271 hdac_stream_setup(ch);
3272 hdac_stream_start(ch);
3273 }
3274
3275 static int
3276 hdac_channel_trigger(kobj_t obj, void *data, int go)
3277 {
3278 struct hdac_chan *ch = data;
3279 struct hdac_softc *sc = ch->devinfo->codec->sc;
3280
3281 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3282 return (0);
3283
3284 hdac_lock(sc);
3285 switch (go) {
3286 case PCMTRIG_START:
3287 hdac_channel_start(sc, ch);
3288 break;
3289 case PCMTRIG_STOP:
3290 case PCMTRIG_ABORT:
3291 hdac_channel_stop(sc, ch);
3292 break;
3293 default:
3294 break;
3295 }
3296 hdac_unlock(sc);
3297
3298 return (0);
3299 }
3300
3301 static int
3302 hdac_channel_getptr(kobj_t obj, void *data)
3303 {
3304 struct hdac_chan *ch = data;
3305 struct hdac_softc *sc = ch->devinfo->codec->sc;
3306 uint32_t ptr;
3307
3308 hdac_lock(sc);
3309 if (sc->polling != 0)
3310 ptr = ch->ptr;
3311 else if (ch->dmapos != NULL)
3312 ptr = *(ch->dmapos);
3313 else
3314 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3315 hdac_unlock(sc);
3316
3317 /*
3318 * Round to available space and force 128 bytes aligment.
3319 */
3320 ptr %= ch->blksz * ch->blkcnt;
3321 ptr &= HDA_BLK_ALIGN;
3322
3323 return (ptr);
3324 }
3325
3326 static struct pcmchan_caps *
3327 hdac_channel_getcaps(kobj_t obj, void *data)
3328 {
3329 return (&((struct hdac_chan *)data)->caps);
3330 }
3331
3332 static kobj_method_t hdac_channel_methods[] = {
3333 KOBJMETHOD(channel_init, hdac_channel_init),
3334 KOBJMETHOD(channel_free, hdac_channel_free),
3335 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3336 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3337 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3338 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3339 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3340 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3341 { 0, 0 }
3342 };
3343 CHANNEL_DECLARE(hdac_channel);
3344
3345 static void
3346 hdac_jack_poll_callback(void *arg)
3347 {
3348 struct hdac_devinfo *devinfo = arg;
3349 struct hdac_softc *sc;
3350
3351 if (devinfo == NULL || devinfo->codec == NULL ||
3352 devinfo->codec->sc == NULL)
3353 return;
3354 sc = devinfo->codec->sc;
3355 hdac_lock(sc);
3356 if (sc->poll_ival == 0) {
3357 hdac_unlock(sc);
3358 return;
3359 }
3360 hdac_hp_switch_handler(devinfo);
3361 callout_reset(&sc->poll_jack, sc->poll_ival,
3362 hdac_jack_poll_callback, devinfo);
3363 hdac_unlock(sc);
3364 }
3365
3366 static int
3367 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3368 {
3369 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3370 struct hdac_softc *sc = devinfo->codec->sc;
3371 struct hdac_widget *w, *cw;
3372 struct hdac_audio_ctl *ctl;
3373 uint32_t mask, recmask, id;
3374 int i, j, softpcmvol;
3375 nid_t cad;
3376
3377 hdac_lock(sc);
3378
3379 mask = 0;
3380 recmask = 0;
3381
3382 id = hdac_codec_id(devinfo);
3383 cad = devinfo->codec->cad;
3384 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3385 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3386 sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3387 continue;
3388 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3389 if (w == NULL || w->enable == 0 || w->type !=
3390 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3391 continue;
3392 if (hdac_hp_switch[i].polling != 0)
3393 callout_reset(&sc->poll_jack, 1,
3394 hdac_jack_poll_callback, devinfo);
3395 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3396 hdac_command(sc,
3397 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3398 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3399 HDAC_UNSOLTAG_EVENT_HP), cad);
3400 else
3401 continue;
3402 hdac_hp_switch_handler(devinfo);
3403 HDA_BOOTVERBOSE(
3404 device_printf(sc->dev,
3405 "HDA_DEBUG: Enabling headphone/speaker "
3406 "audio routing switching:\n");
3407 device_printf(sc->dev,
3408 "HDA_DEBUG: \tindex=%d nid=%d "
3409 "pci_subvendor=0x%08x "
3410 "codec=0x%08x [%s]\n",
3411 i, w->nid, sc->pci_subvendor, id,
3412 (hdac_hp_switch[i].polling != 0) ? "POLL" :
3413 "UNSOL");
3414 );
3415 break;
3416 }
3417 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3418 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3419 sc->pci_subvendor) &&
3420 hdac_eapd_switch[i].id == id))
3421 continue;
3422 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3423 if (w == NULL || w->enable == 0)
3424 break;
3425 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3426 w->param.eapdbtl == HDAC_INVALID)
3427 break;
3428 mask |= SOUND_MASK_OGAIN;
3429 break;
3430 }
3431
3432 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3433 w = hdac_widget_get(devinfo, i);
3434 if (w == NULL || w->enable == 0)
3435 continue;
3436 mask |= w->ctlflags;
3437 if (!(w->pflags & HDA_ADC_RECSEL))
3438 continue;
3439 for (j = 0; j < w->nconns; j++) {
3440 cw = hdac_widget_get(devinfo, w->conns[j]);
3441 if (cw == NULL || cw->enable == 0)
3442 continue;
3443 recmask |= cw->ctlflags;
3444 }
3445 }
3446
3447 if (!(mask & SOUND_MASK_PCM)) {
3448 softpcmvol = 1;
3449 mask |= SOUND_MASK_PCM;
3450 } else
3451 softpcmvol = (devinfo->function.audio.quirks &
3452 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3453
3454 i = 0;
3455 ctl = NULL;
3456 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3457 if (ctl->widget == NULL || ctl->enable == 0)
3458 continue;
3459 if (!(ctl->ossmask & SOUND_MASK_PCM))
3460 continue;
3461 if (ctl->step > 0)
3462 break;
3463 }
3464
3465 if (softpcmvol == 1 || ctl == NULL) {
3466 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3467 HDA_BOOTVERBOSE(
3468 device_printf(sc->dev,
3469 "HDA_DEBUG: %s Soft PCM volume\n",
3470 (softpcmvol == 1) ?
3471 "Forcing" : "Enabling");
3472 );
3473 i = 0;
3474 /*
3475 * XXX Temporary quirk for STAC9220, until the parser
3476 * become smarter.
3477 */
3478 if (id == HDA_CODEC_STAC9220) {
3479 mask |= SOUND_MASK_VOLUME;
3480 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3481 NULL) {
3482 if (ctl->widget == NULL || ctl->enable == 0)
3483 continue;
3484 if (ctl->widget->nid == 11 && ctl->index == 0) {
3485 ctl->ossmask = SOUND_MASK_VOLUME;
3486 ctl->ossval = 100 | (100 << 8);
3487 } else
3488 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3489 }
3490 } else if (id == HDA_CODEC_STAC9221) {
3491 mask |= SOUND_MASK_VOLUME;
3492 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3493 NULL) {
3494 if (ctl->widget == NULL)
3495 continue;
3496 if (ctl->widget->type ==
3497 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3498 ctl->index == 0 && (ctl->widget->nid == 2 ||
3499 ctl->widget->enable != 0)) {
3500 ctl->enable = 1;
3501 ctl->ossmask = SOUND_MASK_VOLUME;
3502 ctl->ossval = 100 | (100 << 8);
3503 } else if (ctl->enable == 0)
3504 continue;
3505 else
3506 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3507 }
3508 } else {
3509 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3510 SOUND_MASK_PCM);
3511 if (!(mask & SOUND_MASK_VOLUME))
3512 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3513 SOUND_MIXER_NONE);
3514 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3515 NULL) {
3516 if (ctl->widget == NULL || ctl->enable == 0)
3517 continue;
3518 if (!HDA_FLAG_MATCH(ctl->ossmask,
3519 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3520 continue;
3521 if (!(ctl->mute == 1 && ctl->step == 0))
3522 ctl->enable = 0;
3523 }
3524 }
3525 }
3526
3527 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3528 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3529 SOUND_MASK_OGAIN);
3530 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3531 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3532
3533 mix_setrecdevs(m, recmask);
3534 mix_setdevs(m, mask);
3535
3536 hdac_unlock(sc);
3537
3538 return (0);
3539 }
3540
3541 static int
3542 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3543 unsigned left, unsigned right)
3544 {
3545 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3546 struct hdac_softc *sc = devinfo->codec->sc;
3547 struct hdac_widget *w;
3548 struct hdac_audio_ctl *ctl;
3549 uint32_t id, mute;
3550 int lvol, rvol, mlvol, mrvol;
3551 int i = 0;
3552
3553 hdac_lock(sc);
3554 if (dev == SOUND_MIXER_OGAIN) {
3555 uint32_t orig;
3556 /*if (left != right || !(left == 0 || left == 1)) {
3557 hdac_unlock(sc);
3558 return (-1);
3559 }*/
3560 id = hdac_codec_id(devinfo);
3561 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3562 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3563 sc->pci_subvendor) &&
3564 hdac_eapd_switch[i].id == id)
3565 break;
3566 }
3567 if (i >= HDAC_EAPD_SWITCH_LEN) {
3568 hdac_unlock(sc);
3569 return (-1);
3570 }
3571 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3572 if (w == NULL ||
3573 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3574 w->param.eapdbtl == HDAC_INVALID) {
3575 hdac_unlock(sc);
3576 return (-1);
3577 }
3578 orig = w->param.eapdbtl;
3579 if (left == 0)
3580 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3581 else
3582 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3583 if (orig != w->param.eapdbtl) {
3584 uint32_t val;
3585
3586 if (hdac_eapd_switch[i].hp_switch != 0)
3587 hdac_hp_switch_handler(devinfo);
3588 val = w->param.eapdbtl;
3589 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3590 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3591 hdac_command(sc,
3592 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3593 w->nid, val), devinfo->codec->cad);
3594 }
3595 hdac_unlock(sc);
3596 return (left | (left << 8));
3597 }
3598 if (dev == SOUND_MIXER_VOLUME)
3599 devinfo->function.audio.mvol = left | (right << 8);
3600
3601 mlvol = devinfo->function.audio.mvol & 0x7f;
3602 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3603 lvol = 0;
3604 rvol = 0;
3605
3606 i = 0;
3607 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3608 if (ctl->widget == NULL || ctl->enable == 0 ||
3609 !(ctl->ossmask & (1 << dev)))
3610 continue;
3611 switch (dev) {
3612 case SOUND_MIXER_VOLUME:
3613 lvol = ((ctl->ossval & 0x7f) * left) / 100;
3614 lvol = (lvol * ctl->step) / 100;
3615 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3616 rvol = (rvol * ctl->step) / 100;
3617 break;
3618 default:
3619 if (ctl->ossmask & SOUND_MASK_VOLUME) {
3620 lvol = (left * mlvol) / 100;
3621 lvol = (lvol * ctl->step) / 100;
3622 rvol = (right * mrvol) / 100;
3623 rvol = (rvol * ctl->step) / 100;
3624 } else {
3625 lvol = (left * ctl->step) / 100;
3626 rvol = (right * ctl->step) / 100;
3627 }
3628 ctl->ossval = left | (right << 8);
3629 break;
3630 }
3631 mute = 0;
3632 if (ctl->step < 1) {
3633 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3634 (ctl->muted & HDA_AMP_MUTE_LEFT);
3635 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3636 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3637 } else {
3638 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3639 (ctl->muted & HDA_AMP_MUTE_LEFT);
3640 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3641 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3642 }
3643 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3644 }
3645 hdac_unlock(sc);
3646
3647 return (left | (right << 8));
3648 }
3649
3650 static int
3651 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3652 {
3653 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3654 struct hdac_widget *w, *cw;
3655 struct hdac_softc *sc = devinfo->codec->sc;
3656 uint32_t ret = src, target;
3657 int i, j;
3658
3659 target = 0;
3660 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3661 if (src & (1 << i)) {
3662 target = 1 << i;
3663 break;
3664 }
3665 }
3666
3667 hdac_lock(sc);
3668
3669 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3670 w = hdac_widget_get(devinfo, i);
3671 if (w == NULL || w->enable == 0)
3672 continue;
3673 if (!(w->pflags & HDA_ADC_RECSEL))
3674 continue;
3675 for (j = 0; j < w->nconns; j++) {
3676 cw = hdac_widget_get(devinfo, w->conns[j]);
3677 if (cw == NULL || cw->enable == 0)
3678 continue;
3679 if ((target == SOUND_MASK_VOLUME &&
3680 cw->type !=
3681 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3682 (target != SOUND_MASK_VOLUME &&
3683 cw->type ==
3684 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3685 continue;
3686 if (cw->ctlflags & target) {
3687 if (!(w->pflags & HDA_ADC_LOCKED))
3688 hdac_widget_connection_select(w, j);
3689 ret = target;
3690 j += w->nconns;
3691 }
3692 }
3693 }
3694
3695 hdac_unlock(sc);
3696
3697 return (ret);
3698 }
3699
3700 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3701 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3702 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3703 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3704 { 0, 0 }
3705 };
3706 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3707
3708 static void
3709 hdac_unsolq_task(void *context, int pending)
3710 {
3711 struct hdac_softc *sc;
3712
3713 sc = (struct hdac_softc *)context;
3714
3715 hdac_lock(sc);
3716 hdac_unsolq_flush(sc);
3717 hdac_unlock(sc);
3718 }
3719
3720 /****************************************************************************
3721 * int hdac_attach(device_t)
3722 *
3723 * Attach the device into the kernel. Interrupts usually won't be enabled
3724 * when this function is called. Setup everything that doesn't require
3725 * interrupts and defer probing of codecs until interrupts are enabled.
3726 ****************************************************************************/
3727 static int
3728 hdac_attach(device_t dev)
3729 {
3730 struct hdac_softc *sc;
3731 int result;
3732 int i;
3733 uint16_t vendor;
3734 uint8_t v;
3735
3736 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
3737 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3738 sc->dev = dev;
3739 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3740 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3741 vendor = pci_get_vendor(dev);
3742
3743 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3744 /* Screw nx6325 - subdevice/subvendor swapped */
3745 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3746 }
3747
3748 callout_init(&sc->poll_hda);
3749 callout_init(&sc->poll_hdac);
3750 callout_init(&sc->poll_jack);
3751
3752 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
3753
3754 sc->poll_ticks = 1;
3755 sc->poll_ival = HDAC_POLL_INTERVAL;
3756 if (resource_int_value(device_get_name(dev),
3757 device_get_unit(dev), "polling", &i) == 0 && i != 0)
3758 sc->polling = 1;
3759 else
3760 sc->polling = 0;
3761
3762 sc->chan_size = pcm_getbuffersize(dev,
3763 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3764
3765 if (resource_int_value(device_get_name(dev),
3766 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3767 i &= HDA_BLK_ALIGN;
3768 if (i < HDA_BLK_MIN)
3769 i = HDA_BLK_MIN;
3770 sc->chan_blkcnt = sc->chan_size / i;
3771 i = 0;
3772 while (sc->chan_blkcnt >> i)
3773 i++;
3774 sc->chan_blkcnt = 1 << (i - 1);
3775 if (sc->chan_blkcnt < HDA_BDL_MIN)
3776 sc->chan_blkcnt = HDA_BDL_MIN;
3777 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3778 sc->chan_blkcnt = HDA_BDL_MAX;
3779 } else
3780 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3781
3782 result = bus_dma_tag_create(NULL, /* parent */
3783 HDAC_DMA_ALIGNMENT, /* alignment */
3784 0, /* boundary */
3785 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3786 BUS_SPACE_MAXADDR, /* highaddr */
3787 NULL, /* filtfunc */
3788 NULL, /* fistfuncarg */
3789 sc->chan_size, /* maxsize */
3790 1, /* nsegments */
3791 sc->chan_size, /* maxsegsz */
3792 0, /* flags */
3793 &sc->chan_dmat); /* dmat */
3794 if (result != 0) {
3795 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3796 __func__, result);
3797 snd_mtxfree(sc->lock);
3798 kfree(sc, M_DEVBUF);
3799 return (ENXIO);
3800 }
3801
3802
3803 sc->hdabus = NULL;
3804 for (i = 0; i < HDAC_CODEC_MAX; i++)
3805 sc->codecs[i] = NULL;
3806
3807 pci_enable_busmaster(dev);
3808
3809 if (vendor == INTEL_VENDORID) {
3810 /* TCSEL -> TC0 */
3811 v = pci_read_config(dev, 0x44, 1);
3812 pci_write_config(dev, 0x44, v & 0xf8, 1);
3813 HDA_BOOTVERBOSE(
3814 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3815 pci_read_config(dev, 0x44, 1));
3816 );
3817 }
3818 #if 0 /* TODO: No MSI support yet in DragonFly. */
3819 if (resource_int_value(device_get_name(dev),
3820 device_get_unit(dev), "msi", &i) == 0 && i != 0 &&
3821 pci_msi_count(dev) == 1)
3822 sc->flags |= HDAC_F_MSI;
3823 else
3824 #endif
3825 sc->flags &= ~HDAC_F_MSI;
3826
3827 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3828 sc->flags |= HDAC_F_DMA_NOCACHE;
3829
3830 if (resource_int_value(device_get_name(dev),
3831 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3832 #else
3833 sc->flags &= ~HDAC_F_DMA_NOCACHE;
3834 #endif
3835 /*
3836 * Try to enable PCIe snoop to avoid messing around with
3837 * uncacheable DMA attribute. Since PCIe snoop register
3838 * config is pretty much vendor specific, there are no
3839 * general solutions on how to enable it, forcing us (even
3840 * Microsoft) to enable uncacheable or write combined DMA
3841 * by default.
3842 *
3843 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3844 */
3845 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3846 if (hdac_pcie_snoop[i].vendor != vendor)
3847 continue;
3848 sc->flags &= ~HDAC_F_DMA_NOCACHE;
3849 if (hdac_pcie_snoop[i].reg == 0x00)
3850 break;
3851 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3852 if ((v & hdac_pcie_snoop[i].enable) ==
3853 hdac_pcie_snoop[i].enable)
3854 break;
3855 v &= hdac_pcie_snoop[i].mask;
3856 v |= hdac_pcie_snoop[i].enable;
3857 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3858 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3859 if ((v & hdac_pcie_snoop[i].enable) !=
3860 hdac_pcie_snoop[i].enable) {
3861 HDA_BOOTVERBOSE(
3862 device_printf(dev,
3863 "WARNING: Failed to enable PCIe "
3864 "snoop!\n");
3865 );
3866 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3867 sc->flags |= HDAC_F_DMA_NOCACHE;
3868 #endif
3869 }
3870 break;
3871 }
3872 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3873 }
3874 #endif
3875
3876 HDA_BOOTVERBOSE(
3877 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
3878 (sc->flags & HDAC_F_DMA_NOCACHE) ?
3879 "Uncacheable" : "PCIe snoop", vendor);
3880 );
3881
3882 /* Allocate resources */
3883 result = hdac_mem_alloc(sc);
3884 if (result != 0)
3885 goto hdac_attach_fail;
3886 result = hdac_irq_alloc(sc);
3887 if (result != 0)
3888 goto hdac_attach_fail;
3889
3890 /* Get Capabilities */
3891 result = hdac_get_capabilities(sc);
3892 if (result != 0)
3893 goto hdac_attach_fail;
3894
3895 /* Allocate CORB and RIRB dma memory */
3896 result = hdac_dma_alloc(sc, &sc->corb_dma,
3897 sc->corb_size * sizeof(uint32_t));
3898 if (result != 0)
3899 goto hdac_attach_fail;
3900 result = hdac_dma_alloc(sc, &sc->rirb_dma,
3901 sc->rirb_size * sizeof(struct hdac_rirb));
3902 if (result != 0)
3903 goto hdac_attach_fail;
3904
3905 /* Quiesce everything */
3906 hdac_reset(sc);
3907
3908 /* Initialize the CORB and RIRB */
3909 hdac_corb_init(sc);
3910 hdac_rirb_init(sc);
3911
3912 /* Defer remaining of initialization until interrupts are enabled */
3913 sc->intrhook.ich_func = hdac_attach2;
3914 sc->intrhook.ich_arg = (void *)sc;
3915 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
3916 sc->intrhook.ich_func = NULL;
3917 hdac_attach2((void *)sc);
3918 }
3919
3920 return (0);
3921
3922 hdac_attach_fail:
3923 hdac_irq_free(sc);
3924 hdac_dma_free(sc, &sc->rirb_dma);
3925 hdac_dma_free(sc, &sc->corb_dma);
3926 hdac_mem_free(sc);
3927 snd_mtxfree(sc->lock);
3928 kfree(sc, M_DEVBUF);
3929
3930 return (ENXIO);
3931 }
3932
3933 static void
3934 hdac_audio_parse(struct hdac_devinfo *devinfo)
3935 {
3936 struct hdac_softc *sc = devinfo->codec->sc;
3937 struct hdac_widget *w;
3938 uint32_t res;
3939 int i;
3940 nid_t cad, nid;
3941
3942 cad = devinfo->codec->cad;
3943 nid = devinfo->nid;
3944
3945 hdac_command(sc,
3946 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
3947
3948 DELAY(100);
3949
3950 res = hdac_command(sc,
3951 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
3952
3953 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
3954 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
3955 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
3956
3957 res = hdac_command(sc,
3958 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
3959 devinfo->function.audio.gpio = res;
3960
3961 HDA_BOOTVERBOSE(
3962 device_printf(sc->dev, " Vendor: 0x%08x\n",
3963 devinfo->vendor_id);
3964 device_printf(sc->dev, " Device: 0x%08x\n",
3965 devinfo->device_id);
3966 device_printf(sc->dev, " Revision: 0x%08x\n",
3967 devinfo->revision_id);
3968 device_printf(sc->dev, " Stepping: 0x%08x\n",
3969 devinfo->stepping_id);
3970 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3971 sc->pci_subvendor);
3972 device_printf(sc->dev, " Nodes: start=%d "
3973 "endnode=%d total=%d\n",
3974 devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3975 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size);
3976 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size);
3977 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n",
3978 sc->num_iss, sc->num_oss, sc->num_bss);
3979 device_printf(sc->dev, " GPIO: 0x%08x\n",
3980 devinfo->function.audio.gpio);
3981 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d "
3982 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
3983 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
3984 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
3985 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
3986 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
3987 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
3988 );
3989
3990 res = hdac_command(sc,
3991 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
3992 cad);
3993 devinfo->function.audio.supp_stream_formats = res;
3994
3995 res = hdac_command(sc,
3996 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
3997 cad);
3998 devinfo->function.audio.supp_pcm_size_rate = res;
3999
4000 res = hdac_command(sc,
4001 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
4002 cad);
4003 devinfo->function.audio.outamp_cap = res;
4004
4005 res = hdac_command(sc,
4006 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
4007 cad);
4008 devinfo->function.audio.inamp_cap = res;
4009
4010 if (devinfo->nodecnt > 0)
4011 devinfo->widget = (struct hdac_widget *)kmalloc(
4012 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
4013 M_NOWAIT | M_ZERO);
4014 else
4015 devinfo->widget = NULL;
4016
4017 if (devinfo->widget == NULL) {
4018 device_printf(sc->dev, "unable to allocate widgets!\n");
4019 devinfo->endnode = devinfo->startnode;
4020 devinfo->nodecnt = 0;
4021 return;
4022 }
4023
4024 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4025 w = hdac_widget_get(devinfo, i);
4026 if (w == NULL)
4027 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
4028 else {
4029 w->devinfo = devinfo;
4030 w->nid = i;
4031 w->enable = 1;
4032 w->selconn = -1;
4033 w->pflags = 0;
4034 w->ctlflags = 0;
4035 w->param.eapdbtl = HDAC_INVALID;
4036 hdac_widget_parse(w);
4037 }
4038 }
4039 }
4040
4041 static void
4042 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
4043 {
4044 struct hdac_softc *sc = devinfo->codec->sc;
4045 struct hdac_audio_ctl *ctls;
4046 struct hdac_widget *w, *cw;
4047 int i, j, cnt, max, ocap, icap;
4048 int mute, offset, step, size;
4049
4050 /* XXX This is redundant */
4051 max = 0;
4052 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4053 w = hdac_widget_get(devinfo, i);
4054 if (w == NULL || w->enable == 0)
4055 continue;
4056 if (w->param.outamp_cap != 0)
4057 max++;
4058 if (w->param.inamp_cap != 0) {
4059 switch (w->type) {
4060 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4061 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4062 for (j = 0; j < w->nconns; j++) {
4063 cw = hdac_widget_get(devinfo,
4064 w->conns[j]);
4065 if (cw == NULL || cw->enable == 0)
4066 continue;
4067 max++;
4068 }
4069 break;
4070 default:
4071 max++;
4072 break;
4073 }
4074 }
4075 }
4076
4077 devinfo->function.audio.ctlcnt = max;
4078
4079 if (max < 1)
4080 return;
4081
4082 ctls = (struct hdac_audio_ctl *)kmalloc(
4083 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
4084
4085 if (ctls == NULL) {
4086 /* Blekh! */
4087 device_printf(sc->dev, "unable to allocate ctls!\n");
4088 devinfo->function.audio.ctlcnt = 0;
4089 return;
4090 }
4091
4092 cnt = 0;
4093 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
4094 if (cnt >= max) {
4095 device_printf(sc->dev, "%s: Ctl overflow!\n",
4096 __func__);
4097 break;
4098 }
4099 w = hdac_widget_get(devinfo, i);
4100 if (w == NULL || w->enable == 0)
4101 continue;
4102 ocap = w->param.outamp_cap;
4103 icap = w->param.inamp_cap;
4104 if (ocap != 0) {
4105 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
4106 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
4107 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
4108 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
4109 /*if (offset > step) {
4110 HDA_BOOTVERBOSE(
4111 device_printf(sc->dev,
4112 "HDA_DEBUG: BUGGY outamp: nid=%d "
4113 "[offset=%d > step=%d]\n",
4114 w->nid, offset, step);
4115 );
4116 offset = step;
4117 }*/
4118 ctls[cnt].enable = 1;
4119 ctls[cnt].widget = w;
4120 ctls[cnt].mute = mute;
4121 ctls[cnt].step = step;
4122 ctls[cnt].size = size;
4123 ctls[cnt].offset = offset;
4124 ctls[cnt].left = offset;
4125 ctls[cnt].right = offset;
4126 ctls[cnt++].dir = HDA_CTL_OUT;
4127 }
4128
4129 if (icap != 0) {
4130 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4131 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4132 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4133 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4134 /*if (offset > step) {
4135 HDA_BOOTVERBOSE(
4136 device_printf(sc->dev,
4137 "HDA_DEBUG: BUGGY inamp: nid=%d "
4138 "[offset=%d > step=%d]\n",
4139 w->nid, offset, step);
4140 );
4141 offset = step;
4142 }*/
4143 switch (w->type) {
4144 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4145 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4146 for (j = 0; j < w->nconns; j++) {
4147 if (cnt >= max) {
4148 device_printf(sc->dev,
4149 "%s: Ctl overflow!\n",
4150 __func__);
4151 break;
4152 }
4153 cw = hdac_widget_get(devinfo,
4154 w->conns[j]);
4155 if (cw == NULL || cw->enable == 0)
4156 continue;
4157 ctls[cnt].enable = 1;
4158 ctls[cnt].widget = w;
4159 ctls[cnt].childwidget = cw;
4160 ctls[cnt].index = j;
4161 ctls[cnt].mute = mute;
4162 ctls[cnt].step = step;
4163 ctls[cnt].size = size;
4164 ctls[cnt].offset = offset;
4165 ctls[cnt].left = offset;
4166 ctls[cnt].right = offset;
4167 ctls[cnt++].dir = HDA_CTL_IN;
4168 }
4169 break;
4170 default:
4171 if (cnt >= max) {
4172 device_printf(sc->dev,
4173 "%s: Ctl overflow!\n",
4174 __func__);
4175 break;
4176 }
4177 ctls[cnt].enable = 1;
4178 ctls[cnt].widget = w;
4179 ctls[cnt].mute = mute;
4180 ctls[cnt].step = step;
4181 ctls[cnt].size = size;
4182 ctls[cnt].offset = offset;
4183 ctls[cnt].left = offset;
4184 ctls[cnt].right = offset;
4185 ctls[cnt++].dir = HDA_CTL_IN;
4186 break;
4187 }
4188 }
4189 }
4190
4191 devinfo->function.audio.ctl = ctls;
4192 }
4193
4194 static const struct {
4195 uint32_t model;
4196 uint32_t id;
4197 uint32_t set, unset;
4198 } hdac_quirks[] = {
4199 /*
4200 * XXX Force stereo quirk. Monoural recording / playback
4201 * on few codecs (especially ALC880) seems broken or
4202 * perhaps unsupported.
4203 */
4204 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4205 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4206 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4207 HDA_QUIRK_GPIO0, 0 },
4208 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4209 HDA_QUIRK_GPIO0, 0 },
4210 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4211 HDA_QUIRK_GPIO0, 0 },
4212 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4213 HDA_QUIRK_GPIO0, 0 },
4214 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4215 HDA_QUIRK_GPIO0, 0 },
4216 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4217 HDA_QUIRK_EAPDINV, 0 },
4218 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A,
4219 HDA_QUIRK_EAPDINV, 0 },
4220 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4221 HDA_QUIRK_OVREF, 0 },
4222 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861,
4223 HDA_QUIRK_OVREF, 0 },
4224 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4225 HDA_QUIRK_OVREF, 0 },
4226 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4227 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4228 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4229 HDA_QUIRK_GPIO1, 0 },
4230 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4231 HDA_QUIRK_EAPDINV, 0 },
4232 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4233 HDA_QUIRK_EAPDINV, 0 },
4234 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885,
4235 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0},
4236 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4237 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4238 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4239 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4240 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4241 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4242 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
4243 0, HDA_QUIRK_FORCESTEREO },
4244 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
4245 HDA_QUIRK_SOFTPCMVOL, 0 }
4246 };
4247 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4248
4249 static void
4250 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4251 {
4252 struct hdac_widget *w;
4253 struct hdac_audio_ctl *ctl;
4254 uint32_t id, subvendor;
4255 int i;
4256
4257 id = hdac_codec_id(devinfo);
4258 subvendor = devinfo->codec->sc->pci_subvendor;
4259
4260 /*
4261 * Quirks
4262 */
4263 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4264 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4265 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4266 continue;
4267 if (hdac_quirks[i].set != 0)
4268 devinfo->function.audio.quirks |=
4269 hdac_quirks[i].set;
4270 if (hdac_quirks[i].unset != 0)
4271 devinfo->function.audio.quirks &=
4272 ~(hdac_quirks[i].unset);
4273 }
4274
4275 switch (id) {
4276 case HDA_CODEC_ALC260:
4277 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4278 w = hdac_widget_get(devinfo, i);
4279 if (w == NULL || w->enable == 0)
4280 continue;
4281 if (w->type !=
4282 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4283 continue;
4284 if (w->nid != 5)
4285 w->enable = 0;
4286 }
4287 if (subvendor == HP_XW4300_SUBVENDOR) {
4288 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4289 if (ctl != NULL && ctl->widget != NULL) {
4290 ctl->ossmask = SOUND_MASK_SPEAKER;
4291 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4292 }
4293 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4294 if (ctl != NULL && ctl->widget != NULL) {
4295 ctl->ossmask = SOUND_MASK_SPEAKER;
4296 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4297 }
4298 } else if (subvendor == HP_3010_SUBVENDOR) {
4299 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4300 if (ctl != NULL && ctl->widget != NULL) {
4301 ctl->ossmask = SOUND_MASK_SPEAKER;
4302 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4303 }
4304 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1);
4305 if (ctl != NULL && ctl->widget != NULL) {
4306 ctl->ossmask = SOUND_MASK_SPEAKER;
4307 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4308 }
4309 }
4310 break;
4311 case HDA_CODEC_ALC262:
4312 if (subvendor == HP_DC7700_SUBVENDOR) {
4313 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1);
4314 if (ctl != NULL && ctl->widget != NULL) {
4315 ctl->ossmask = SOUND_MASK_SPEAKER;
4316 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4317 }
4318 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1);
4319 if (ctl != NULL && ctl->widget != NULL) {
4320 ctl->ossmask = SOUND_MASK_SPEAKER;
4321 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4322 }
4323 }
4324 break;
4325 case HDA_CODEC_ALC861:
4326 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1);
4327 if (ctl != NULL)
4328 ctl->muted = HDA_AMP_MUTE_ALL;
4329 break;
4330 case HDA_CODEC_ALC880:
4331 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4332 w = hdac_widget_get(devinfo, i);
4333 if (w == NULL || w->enable == 0)
4334 continue;
4335 if (w->type ==
4336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4337 w->nid != 9 && w->nid != 29) {
4338 w->enable = 0;
4339 } else if (w->type !=
4340 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
4341 w->nid == 29) {
4342 w->type =
4343 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4344 w->param.widget_cap &=
4345 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4346 w->param.widget_cap |=
4347 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4348 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4349 strlcpy(w->name, "beep widget", sizeof(w->name));
4350 }
4351 }
4352 break;
4353 case HDA_CODEC_ALC883:
4354 /*
4355 * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4356 * Clear vref cap for jack connectivity.
4357 */
4358 w = hdac_widget_get(devinfo, 24);
4359 if (w != NULL && w->enable != 0 && w->type ==
4360 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4361 (w->wclass.pin.config &
4362 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4363 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4364 w->wclass.pin.cap &= ~(
4365 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4366 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4367 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4368 w = hdac_widget_get(devinfo, 25);
4369 if (w != NULL && w->enable != 0 && w->type ==
4370 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4371 (w->wclass.pin.config &
4372 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4373 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4374 w->wclass.pin.cap &= ~(
4375 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4376 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4377 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4378 /*
4379 * nid: 26 = Line-in, leave it alone.
4380 */
4381 break;
4382 case HDA_CODEC_AD1981HD:
4383 w = hdac_widget_get(devinfo, 11);
4384 if (w != NULL && w->enable != 0 && w->nconns > 3)
4385 w->selconn = 3;
4386 if (subvendor == IBM_M52_SUBVENDOR) {
4387 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
4388 if (ctl != NULL)
4389 ctl->ossmask = SOUND_MASK_SPEAKER;
4390 }
4391 break;
4392 case HDA_CODEC_AD1986A:
4393 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4394 w = hdac_widget_get(devinfo, i);
4395 if (w == NULL || w->enable == 0)
4396 continue;
4397 if (w->type !=
4398 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4399 continue;
4400 if (w->nid != 3)
4401 w->enable = 0;
4402 }
4403 if (subvendor == ASUS_M2NPVMX_SUBVENDOR ||
4404 subvendor == ASUS_A8NVMCSM_SUBVENDOR) {
4405 /* nid 28 is mic, nid 29 is line-in */
4406 w = hdac_widget_get(devinfo, 15);
4407 if (w != NULL)
4408 w->selconn = 2;
4409 w = hdac_widget_get(devinfo, 16);
4410 if (w != NULL)
4411 w->selconn = 1;
4412 }
4413 break;
4414 case HDA_CODEC_AD1988:
4415 case HDA_CODEC_AD1988B:
4416 /*w = hdac_widget_get(devinfo, 12);
4417 if (w != NULL) {
4418 w->selconn = 1;
4419 w->pflags |= HDA_ADC_LOCKED;
4420 }
4421 w = hdac_widget_get(devinfo, 13);
4422 if (w != NULL) {
4423 w->selconn = 4;
4424 w->pflags |= HDA_ADC_LOCKED;
4425 }
4426 w = hdac_widget_get(devinfo, 14);
4427 if (w != NULL) {
4428 w->selconn = 2;
4429 w->pflags |= HDA_ADC_LOCKED;
4430 }*/
4431 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1);
4432 if (ctl != NULL) {
4433 ctl->ossmask = SOUND_MASK_IGAIN;
4434 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4435 }
4436 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1);
4437 if (ctl != NULL) {
4438 ctl->ossmask = SOUND_MASK_IGAIN;
4439 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4440 }
4441 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1);
4442 if (ctl != NULL) {
4443 ctl->ossmask = SOUND_MASK_IGAIN;
4444 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4445 }
4446 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1);
4447 if (ctl != NULL) {
4448 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4449 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4450 }
4451 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1);
4452 if (ctl != NULL) {
4453 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4454 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4455 }
4456 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1);
4457 if (ctl != NULL) {
4458 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4459 ctl->widget->ctlflags |= SOUND_MASK_LINE;
4460 }
4461 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1);
4462 if (ctl != NULL) {
4463 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME;
4464 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4465 }
4466 break;
4467 case HDA_CODEC_STAC9221:
4468 /*
4469 * Dell XPS M1210 need all DACs for each output jacks
4470 */
4471 if (subvendor == DELL_XPSM1210_SUBVENDOR)
4472 break;
4473 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4474 w = hdac_widget_get(devinfo, i);
4475 if (w == NULL || w->enable == 0)
4476 continue;
4477 if (w->type !=
4478 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4479 continue;
4480 if (w->nid != 2)
4481 w->enable = 0;
4482 }
4483 break;
4484 case HDA_CODEC_STAC9221D:
4485 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4486 w = hdac_widget_get(devinfo, i);
4487 if (w == NULL || w->enable == 0)
4488 continue;
4489 if (w->type ==
4490 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4491 w->nid != 6)
4492 w->enable = 0;
4493
4494 }
4495 break;
4496 case HDA_CODEC_STAC9227:
4497 w = hdac_widget_get(devinfo, 8);
4498 if (w != NULL)
4499 w->enable = 0;
4500 w = hdac_widget_get(devinfo, 9);
4501 if (w != NULL)
4502 w->enable = 0;
4503 break;
4504 case HDA_CODEC_CXWAIKIKI:
4505 if (subvendor == HP_DV5000_SUBVENDOR) {
4506 w = hdac_widget_get(devinfo, 27);
4507 if (w != NULL)
4508 w->enable = 0;
4509 }
4510 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4511 if (ctl != NULL)
4512 ctl->ossmask = SOUND_MASK_SKIP;
4513 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1);
4514 if (ctl != NULL && ctl->childwidget != NULL &&
4515 ctl->childwidget->enable != 0) {
4516 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME;
4517 ctl->childwidget->ctlflags |= SOUND_MASK_PCM;
4518 }
4519 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1);
4520 if (ctl != NULL && ctl->childwidget != NULL &&
4521 ctl->childwidget->enable != 0) {
4522 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4523 ctl->childwidget->ctlflags |= SOUND_MASK_LINE;
4524 }
4525 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1);
4526 if (ctl != NULL && ctl->childwidget != NULL &&
4527 ctl->childwidget->enable != 0) {
4528 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4529 ctl->childwidget->ctlflags |= SOUND_MASK_MIC;
4530 }
4531 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1);
4532 if (ctl != NULL) {
4533 ctl->ossmask = SOUND_MASK_SKIP;
4534 /* XXX mixer \=rec mic broken.. why?!? */
4535 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */
4536 }
4537 break;
4538 default:
4539 break;
4540 }
4541 }
4542
4543 static int
4544 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
4545 {
4546 int *dev = &devinfo->function.audio.ossidx;
4547
4548 while (*dev < SOUND_MIXER_NRDEVICES) {
4549 switch (*dev) {
4550 case SOUND_MIXER_VOLUME:
4551 case SOUND_MIXER_BASS:
4552 case SOUND_MIXER_TREBLE:
4553 case SOUND_MIXER_PCM:
4554 case SOUND_MIXER_SPEAKER:
4555 case SOUND_MIXER_LINE:
4556 case SOUND_MIXER_MIC:
4557 case SOUND_MIXER_CD:
4558 case SOUND_MIXER_RECLEV:
4559 case SOUND_MIXER_IGAIN:
4560 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
4561 (*dev)++;
4562 break;
4563 default:
4564 return (*dev)++;
4565 break;
4566 }
4567 }
4568
4569 return (-1);
4570 }
4571
4572 static int
4573 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4574 {
4575 struct hdac_widget *w;
4576 int i, ret = 0;
4577
4578 if (depth > HDA_PARSE_MAXDEPTH)
4579 return (0);
4580 w = hdac_widget_get(devinfo, nid);
4581 if (w == NULL || w->enable == 0)
4582 return (0);
4583 switch (w->type) {
4584 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4585 w->pflags |= HDA_DAC_PATH;
4586 ret = 1;
4587 break;
4588 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4589 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4590 for (i = 0; i < w->nconns; i++) {
4591 if (hdac_widget_find_dac_path(devinfo,
4592 w->conns[i], depth + 1) != 0) {
4593 if (w->selconn == -1)
4594 w->selconn = i;
4595 ret = 1;
4596 w->pflags |= HDA_DAC_PATH;
4597 }
4598 }
4599 break;
4600 default:
4601 break;
4602 }
4603 return (ret);
4604 }
4605
4606 static int
4607 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4608 {
4609 struct hdac_widget *w;
4610 int i, conndev, ret = 0;
4611
4612 if (depth > HDA_PARSE_MAXDEPTH)
4613 return (0);
4614 w = hdac_widget_get(devinfo, nid);
4615 if (w == NULL || w->enable == 0)
4616 return (0);
4617 switch (w->type) {
4618 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4619 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4620 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4621 for (i = 0; i < w->nconns; i++) {
4622 if (hdac_widget_find_adc_path(devinfo, w->conns[i],
4623 depth + 1) != 0) {
4624 if (w->selconn == -1)
4625 w->selconn = i;
4626 w->pflags |= HDA_ADC_PATH;
4627 ret = 1;
4628 }
4629 }
4630 break;
4631 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4632 conndev = w->wclass.pin.config &
4633 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4634 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4635 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
4636 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
4637 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
4638 w->pflags |= HDA_ADC_PATH;
4639 ret = 1;
4640 }
4641 break;
4642 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4643 if (w->pflags & HDA_DAC_PATH) {
4644 w->pflags |= HDA_ADC_PATH;
4645 ret = 1;
4646 }
4647 break;*/
4648 default:
4649 break;
4650 }
4651 return (ret);
4652 }
4653
4654 static uint32_t
4655 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
4656 nid_t nid, nid_t pnid, int index, int depth)
4657 {
4658 struct hdac_widget *w, *pw;
4659 struct hdac_audio_ctl *ctl;
4660 uint32_t fl = 0;
4661 int i, ossdev, conndev, strategy;
4662
4663 if (depth > HDA_PARSE_MAXDEPTH)
4664 return (0);
4665
4666 w = hdac_widget_get(devinfo, nid);
4667 if (w == NULL || w->enable == 0)
4668 return (0);
4669
4670 pw = hdac_widget_get(devinfo, pnid);
4671 strategy = devinfo->function.audio.parsing_strategy;
4672
4673 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
4674 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
4675 for (i = 0; i < w->nconns; i++) {
4676 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
4677 w->nid, i, depth + 1);
4678 }
4679 w->ctlflags |= fl;
4680 return (fl);
4681 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
4682 (w->pflags & HDA_DAC_PATH)) {
4683 i = 0;
4684 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4685 if (ctl->enable == 0 || ctl->widget == NULL)
4686 continue;
4687 /* XXX This should be compressed! */
4688 if (((ctl->widget->nid == w->nid) ||
4689 (ctl->widget->nid == pnid && ctl->index == index &&
4690 (ctl->dir & HDA_CTL_IN)) ||
4691 (ctl->widget->nid == pnid && pw != NULL &&
4692 pw->type ==
4693 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4694 (pw->nconns < 2 || pw->selconn == index ||
4695 pw->selconn == -1) &&
4696 (ctl->dir & HDA_CTL_OUT)) ||
4697 (strategy == HDA_PARSE_DIRECT &&
4698 ctl->widget->nid == w->nid)) &&
4699 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4700 /*if (pw != NULL && pw->selconn == -1)
4701 pw->selconn = index;
4702 fl |= SOUND_MASK_VOLUME;
4703 fl |= SOUND_MASK_PCM;
4704 ctl->ossmask |= SOUND_MASK_VOLUME;
4705 ctl->ossmask |= SOUND_MASK_PCM;
4706 ctl->ossdev = SOUND_MIXER_PCM;*/
4707 if (!(w->ctlflags & SOUND_MASK_PCM) ||
4708 (pw != NULL &&
4709 !(pw->ctlflags & SOUND_MASK_PCM))) {
4710 fl |= SOUND_MASK_VOLUME;
4711 fl |= SOUND_MASK_PCM;
4712 ctl->ossmask |= SOUND_MASK_VOLUME;
4713 ctl->ossmask |= SOUND_MASK_PCM;
4714 ctl->ossdev = SOUND_MIXER_PCM;
4715 w->ctlflags |= SOUND_MASK_VOLUME;
4716 w->ctlflags |= SOUND_MASK_PCM;
4717 if (pw != NULL) {
4718 if (pw->selconn == -1)
4719 pw->selconn = index;
4720 pw->ctlflags |=
4721 SOUND_MASK_VOLUME;
4722 pw->ctlflags |=
4723 SOUND_MASK_PCM;
4724 }
4725 }
4726 }
4727 }
4728 w->ctlflags |= fl;
4729 return (fl);
4730 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4731 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4732 (w->pflags & HDA_ADC_PATH)) {
4733 conndev = w->wclass.pin.config &
4734 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4735 i = 0;
4736 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4737 if (ctl->enable == 0 || ctl->widget == NULL)
4738 continue;
4739 /* XXX This should be compressed! */
4740 if (((ctl->widget->nid == pnid && ctl->index == index &&
4741 (ctl->dir & HDA_CTL_IN)) ||
4742 (ctl->widget->nid == pnid && pw != NULL &&
4743 pw->type ==
4744 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4745 (pw->nconns < 2 || pw->selconn == index ||
4746 pw->selconn == -1) &&
4747 (ctl->dir & HDA_CTL_OUT)) ||
4748 (strategy == HDA_PARSE_DIRECT &&
4749 ctl->widget->nid == w->nid)) &&
4750 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4751 if (pw != NULL && pw->selconn == -1)
4752 pw->selconn = index;
4753 ossdev = 0;
4754 switch (conndev) {
4755 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
4756 ossdev = SOUND_MIXER_MIC;
4757 break;
4758 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
4759 ossdev = SOUND_MIXER_LINE;
4760 break;
4761 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
4762 ossdev = SOUND_MIXER_CD;
4763 break;
4764 default:
4765 ossdev =
4766 hdac_audio_ctl_ossmixer_getnextdev(
4767 devinfo);
4768 if (ossdev < 0)
4769 ossdev = 0;
4770 break;
4771 }
4772 if (strategy == HDA_PARSE_MIXER) {
4773 fl |= SOUND_MASK_VOLUME;
4774 ctl->ossmask |= SOUND_MASK_VOLUME;
4775 }
4776 fl |= 1 << ossdev;
4777 ctl->ossmask |= 1 << ossdev;
4778 ctl->ossdev = ossdev;
4779 }
4780 }
4781 w->ctlflags |= fl;
4782 return (fl);
4783 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4784 i = 0;
4785 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4786 if (ctl->enable == 0 || ctl->widget == NULL)
4787 continue;
4788 /* XXX This should be compressed! */
4789 if (((ctl->widget->nid == pnid && ctl->index == index &&
4790 (ctl->dir & HDA_CTL_IN)) ||
4791 (ctl->widget->nid == pnid && pw != NULL &&
4792 pw->type ==
4793 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4794 (pw->nconns < 2 || pw->selconn == index ||
4795 pw->selconn == -1) &&
4796 (ctl->dir & HDA_CTL_OUT)) ||
4797 (strategy == HDA_PARSE_DIRECT &&
4798 ctl->widget->nid == w->nid)) &&
4799 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4800 if (pw != NULL && pw->selconn == -1)
4801 pw->selconn = index;
4802 fl |= SOUND_MASK_VOLUME;
4803 fl |= SOUND_MASK_SPEAKER;
4804 ctl->ossmask |= SOUND_MASK_VOLUME;
4805 ctl->ossmask |= SOUND_MASK_SPEAKER;
4806 ctl->ossdev = SOUND_MIXER_SPEAKER;
4807 }
4808 }
4809 w->ctlflags |= fl;
4810 return (fl);
4811 }
4812 return (0);
4813 }
4814
4815 static uint32_t
4816 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4817 {
4818 struct hdac_widget *w, *cw;
4819 struct hdac_audio_ctl *ctl;
4820 uint32_t fl;
4821 int i;
4822
4823 if (depth > HDA_PARSE_MAXDEPTH)
4824 return (0);
4825
4826 w = hdac_widget_get(devinfo, nid);
4827 if (w == NULL || w->enable == 0)
4828 return (0);
4829 /*if (!(w->pflags & HDA_ADC_PATH))
4830 return (0);
4831 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4832 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4833 return (0);*/
4834 i = 0;
4835 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4836 if (ctl->enable == 0 || ctl->widget == NULL)
4837 continue;
4838 if (ctl->widget->nid == nid) {
4839 ctl->ossmask |= SOUND_MASK_RECLEV;
4840 w->ctlflags |= SOUND_MASK_RECLEV;
4841 return (SOUND_MASK_RECLEV);
4842 }
4843 }
4844 for (i = 0; i < w->nconns; i++) {
4845 cw = hdac_widget_get(devinfo, w->conns[i]);
4846 if (cw == NULL || cw->enable == 0)
4847 continue;
4848 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4849 continue;
4850 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
4851 if (fl != 0) {
4852 cw->ctlflags |= fl;
4853 w->ctlflags |= fl;
4854 return (fl);
4855 }
4856 }
4857 return (0);
4858 }
4859
4860 static int
4861 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4862 {
4863 struct hdac_widget *w, *cw;
4864 int i, child = 0;
4865
4866 if (depth > HDA_PARSE_MAXDEPTH)
4867 return (0);
4868
4869 w = hdac_widget_get(devinfo, nid);
4870 if (w == NULL || w->enable == 0)
4871 return (0);
4872 /*if (!(w->pflags & HDA_ADC_PATH))
4873 return (0);
4874 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4875 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4876 return (0);*/
4877 /* XXX weak! */
4878 for (i = 0; i < w->nconns; i++) {
4879 cw = hdac_widget_get(devinfo, w->conns[i]);
4880 if (cw == NULL)
4881 continue;
4882 if (++child > 1) {
4883 w->pflags |= HDA_ADC_RECSEL;
4884 return (1);
4885 }
4886 }
4887 for (i = 0; i < w->nconns; i++) {
4888 if (hdac_audio_ctl_recsel_build(devinfo,
4889 w->conns[i], depth + 1) != 0)
4890 return (1);
4891 }
4892 return (0);
4893 }
4894
4895 static int
4896 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
4897 {
4898 struct hdac_widget *w, *cw;
4899 int i, j, conndev, found_dac = 0;
4900 int strategy;
4901
4902 strategy = devinfo->function.audio.parsing_strategy;
4903
4904 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4905 w = hdac_widget_get(devinfo, i);
4906 if (w == NULL || w->enable == 0)
4907 continue;
4908 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4909 continue;
4910 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
4911 continue;
4912 conndev = w->wclass.pin.config &
4913 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4914 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4915 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4916 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
4917 continue;
4918 for (j = 0; j < w->nconns; j++) {
4919 cw = hdac_widget_get(devinfo, w->conns[j]);
4920 if (cw == NULL || cw->enable == 0)
4921 continue;
4922 if (strategy == HDA_PARSE_MIXER && !(cw->type ==
4923 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4924 cw->type ==
4925 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4926 continue;
4927 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
4928 != 0) {
4929 if (w->selconn == -1)
4930 w->selconn = j;
4931 w->pflags |= HDA_DAC_PATH;
4932 found_dac++;
4933 }
4934 }
4935 }
4936
4937 return (found_dac);
4938 }
4939
4940 static void
4941 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
4942 {
4943 struct hdac_widget *w;
4944 struct hdac_audio_ctl *ctl;
4945 int i, j, dacs, strategy;
4946
4947 /* Construct DAC path */
4948 strategy = HDA_PARSE_MIXER;
4949 devinfo->function.audio.parsing_strategy = strategy;
4950 HDA_BOOTVERBOSE(
4951 device_printf(devinfo->codec->sc->dev,
4952 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
4953 HDA_WIDGET_PARSER_REV);
4954 );
4955 dacs = hdac_audio_build_tree_strategy(devinfo);
4956 if (dacs == 0) {
4957 HDA_BOOTVERBOSE(
4958 device_printf(devinfo->codec->sc->dev,
4959 "HDA_DEBUG: HWiP: 0 DAC path found! "
4960 "Retrying parser "
4961 "using HDA_PARSE_DIRECT strategy.\n");
4962 );
4963 strategy = HDA_PARSE_DIRECT;
4964 devinfo->function.audio.parsing_strategy = strategy;
4965 dacs = hdac_audio_build_tree_strategy(devinfo);
4966 }
4967
4968 HDA_BOOTVERBOSE(
4969 device_printf(devinfo->codec->sc->dev,
4970 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
4971 "strategy.\n",
4972 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
4973 );
4974
4975 /* Construct ADC path */
4976 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4977 w = hdac_widget_get(devinfo, i);
4978 if (w == NULL || w->enable == 0)
4979 continue;
4980 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4981 continue;
4982 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
4983 }
4984
4985 /* Output mixers */
4986 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4987 w = hdac_widget_get(devinfo, i);
4988 if (w == NULL || w->enable == 0)
4989 continue;
4990 if ((strategy == HDA_PARSE_MIXER &&
4991 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4992 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4993 && (w->pflags & HDA_DAC_PATH)) ||
4994 (strategy == HDA_PARSE_DIRECT && (w->pflags &
4995 (HDA_DAC_PATH | HDA_ADC_PATH)))) {
4996 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
4997 w->nid, devinfo->startnode - 1, 0, 0);
4998 } else if (w->type ==
4999 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
5000 j = 0;
5001 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
5002 NULL) {
5003 if (ctl->enable == 0 || ctl->widget == NULL)
5004 continue;
5005 if (ctl->widget->nid != w->nid)
5006 continue;
5007 ctl->ossmask |= SOUND_MASK_VOLUME;
5008 ctl->ossmask |= SOUND_MASK_SPEAKER;
5009 ctl->ossdev = SOUND_MIXER_SPEAKER;
5010 w->ctlflags |= SOUND_MASK_VOLUME;
5011 w->ctlflags |= SOUND_MASK_SPEAKER;
5012 }
5013 }
5014 }
5015
5016 /* Input mixers (rec) */
5017 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5018 w = hdac_widget_get(devinfo, i);
5019 if (w == NULL || w->enable == 0)
5020 continue;
5021 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
5022 w->pflags & HDA_ADC_PATH))
5023 continue;
5024 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
5025 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
5026 }
5027 }
5028
5029 #define HDA_COMMIT_CONN (1 << 0)
5030 #define HDA_COMMIT_CTRL (1 << 1)
5031 #define HDA_COMMIT_EAPD (1 << 2)
5032 #define HDA_COMMIT_GPIO (1 << 3)
5033 #define HDA_COMMIT_MISC (1 << 4)
5034 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
5035 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC)
5036
5037 static void
5038 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
5039 {
5040 struct hdac_softc *sc = devinfo->codec->sc;
5041 struct hdac_widget *w;
5042 nid_t cad;
5043 int i;
5044
5045 if (!(cfl & HDA_COMMIT_ALL))
5046 return;
5047
5048 cad = devinfo->codec->cad;
5049
5050 if ((cfl & HDA_COMMIT_MISC)) {
5051 if (sc->pci_subvendor == APPLE_INTEL_MAC)
5052 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
5053 0x7e7, 0), cad);
5054 }
5055
5056 if (cfl & HDA_COMMIT_GPIO) {
5057 uint32_t gdata, gmask, gdir;
5058 int commitgpio, numgpio;
5059
5060 gdata = 0;
5061 gmask = 0;
5062 gdir = 0;
5063 commitgpio = 0;
5064
5065 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
5066 devinfo->function.audio.gpio);
5067
5068 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
5069 commitgpio = (numgpio > 0) ? 1 : 0;
5070 else {
5071 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
5072 if (!(devinfo->function.audio.quirks &
5073 (1 << i)))
5074 continue;
5075 if (commitgpio == 0) {
5076 commitgpio = 1;
5077 HDA_BOOTVERBOSE(
5078 gdata = hdac_command(sc,
5079 HDA_CMD_GET_GPIO_DATA(cad,
5080 devinfo->nid), cad);
5081 gmask = hdac_command(sc,
5082 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
5083 devinfo->nid), cad);
5084 gdir = hdac_command(sc,
5085 HDA_CMD_GET_GPIO_DIRECTION(cad,
5086 devinfo->nid), cad);
5087 device_printf(sc->dev,
5088 "GPIO init: data=0x%08x "
5089 "mask=0x%08x dir=0x%08x\n",
5090 gdata, gmask, gdir);
5091 gdata = 0;
5092 gmask = 0;
5093 gdir = 0;
5094 );
5095 }
5096 gdata |= 1 << i;
5097 gmask |= 1 << i;
5098 gdir |= 1 << i;
5099 }
5100 }
5101
5102 if (commitgpio != 0) {
5103 HDA_BOOTVERBOSE(
5104 device_printf(sc->dev,
5105 "GPIO commit: data=0x%08x mask=0x%08x "
5106 "dir=0x%08x\n",
5107 gdata, gmask, gdir);
5108 );
5109 hdac_command(sc,
5110 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
5111 gmask), cad);
5112 hdac_command(sc,
5113 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
5114 gdir), cad);
5115 hdac_command(sc,
5116 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
5117 gdata), cad);
5118 }
5119 }
5120
5121 for (i = 0; i < devinfo->nodecnt; i++) {
5122 w = &devinfo->widget[i];
5123 if (w == NULL || w->enable == 0)
5124 continue;
5125 if (cfl & HDA_COMMIT_CONN) {
5126 if (w->selconn == -1)
5127 w->selconn = 0;
5128 if (w->nconns > 0)
5129 hdac_widget_connection_select(w, w->selconn);
5130 }
5131 if ((cfl & HDA_COMMIT_CTRL) &&
5132 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5133 uint32_t pincap;
5134
5135 pincap = w->wclass.pin.cap;
5136
5137 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
5138 (HDA_DAC_PATH | HDA_ADC_PATH))
5139 device_printf(sc->dev, "WARNING: node %d "
5140 "participate both for DAC/ADC!\n", w->nid);
5141 if (w->pflags & HDA_DAC_PATH) {
5142 w->wclass.pin.ctrl &=
5143 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
5144 if ((w->wclass.pin.config &
5145 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
5146 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
5147 w->wclass.pin.ctrl &=
5148 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
5149 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
5150 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5151 w->wclass.pin.ctrl |=
5152 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5153 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5154 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
5155 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5156 w->wclass.pin.ctrl |=
5157 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5158 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5159 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
5160 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5161 w->wclass.pin.ctrl |=
5162 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5163 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5164 } else if (w->pflags & HDA_ADC_PATH) {
5165 w->wclass.pin.ctrl &=
5166 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5167 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
5168 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
5169 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5170 w->wclass.pin.ctrl |=
5171 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5172 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5173 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
5174 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5175 w->wclass.pin.ctrl |=
5176 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5177 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5178 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
5179 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5180 w->wclass.pin.ctrl |=
5181 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5182 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5183 } else
5184 w->wclass.pin.ctrl &= ~(
5185 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
5186 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5187 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
5188 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
5189 hdac_command(sc,
5190 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
5191 w->wclass.pin.ctrl), cad);
5192 }
5193 if ((cfl & HDA_COMMIT_EAPD) &&
5194 w->param.eapdbtl != HDAC_INVALID) {
5195 uint32_t val;
5196
5197 val = w->param.eapdbtl;
5198 if (devinfo->function.audio.quirks &
5199 HDA_QUIRK_EAPDINV)
5200 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
5201 hdac_command(sc,
5202 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
5203 val), cad);
5204
5205 }
5206 DELAY(1000);
5207 }
5208 }
5209
5210 static void
5211 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
5212 {
5213 struct hdac_softc *sc = devinfo->codec->sc;
5214 struct hdac_audio_ctl *ctl;
5215 int i;
5216
5217 devinfo->function.audio.mvol = 100 | (100 << 8);
5218 i = 0;
5219 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5220 if (ctl->enable == 0 || ctl->widget == NULL) {
5221 HDA_BOOTVERBOSE(
5222 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5223 i, (ctl->widget != NULL) ?
5224 ctl->widget->nid : -1);
5225 if (ctl->childwidget != NULL)
5226 kprintf(" childnid=%d",
5227 ctl->childwidget->nid);
5228 if (ctl->widget == NULL)
5229 kprintf(" NULL WIDGET!");
5230 kprintf(" DISABLED\n");
5231 );
5232 continue;
5233 }
5234 HDA_BOOTVERBOSE(
5235 if (ctl->ossmask == 0) {
5236 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5237 i, ctl->widget->nid);
5238 if (ctl->childwidget != NULL)
5239 kprintf(" childnid=%d",
5240 ctl->childwidget->nid);
5241 kprintf(" Bind to NONE\n");
5242 }
5243 );
5244 if (ctl->step > 0) {
5245 ctl->ossval = (ctl->left * 100) / ctl->step;
5246 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
5247 } else
5248 ctl->ossval = 0;
5249 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
5250 ctl->left, ctl->right);
5251 }
5252 }
5253
5254 static int
5255 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
5256 {
5257 struct hdac_chan *ch;
5258 struct hdac_widget *w;
5259 uint32_t cap, fmtcap, pcmcap, path;
5260 int i, type, ret, max;
5261
5262 if (dir == PCMDIR_PLAY) {
5263 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
5264 ch = &devinfo->codec->sc->play;
5265 path = HDA_DAC_PATH;
5266 } else {
5267 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
5268 ch = &devinfo->codec->sc->rec;
5269 path = HDA_ADC_PATH;
5270 }
5271
5272 ch->caps = hdac_caps;
5273 ch->caps.fmtlist = ch->fmtlist;
5274 ch->bit16 = 1;
5275 ch->bit32 = 0;
5276 ch->pcmrates[0] = 48000;
5277 ch->pcmrates[1] = 0;
5278
5279 ret = 0;
5280 fmtcap = devinfo->function.audio.supp_stream_formats;
5281 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
5282 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
5283
5284 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
5285 w = hdac_widget_get(devinfo, i);
5286 if (w == NULL || w->enable == 0 || w->type != type ||
5287 !(w->pflags & path))
5288 continue;
5289 cap = w->param.widget_cap;
5290 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
5291 continue;*/
5292 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
5293 continue;
5294 cap = w->param.supp_stream_formats;
5295 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
5296 }
5297 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
5298 }*/
5299 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5300 continue;
5301 if (ret == 0) {
5302 fmtcap = w->param.supp_stream_formats;
5303 pcmcap = w->param.supp_pcm_size_rate;
5304 } else {
5305 fmtcap &= w->param.supp_stream_formats;
5306 pcmcap &= w->param.supp_pcm_size_rate;
5307 }
5308 ch->io[ret++] = i;
5309 }
5310 ch->io[ret] = -1;
5311
5312 ch->supp_stream_formats = fmtcap;
5313 ch->supp_pcm_size_rate = pcmcap;
5314
5315 /*
5316 * 8bit = 0
5317 * 16bit = 1
5318 * 20bit = 2
5319 * 24bit = 3
5320 * 32bit = 4
5321 */
5322 if (ret > 0) {
5323 cap = pcmcap;
5324 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5325 ch->bit16 = 1;
5326 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5327 ch->bit16 = 0;
5328 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5329 ch->bit32 = 4;
5330 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5331 ch->bit32 = 3;
5332 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5333 ch->bit32 = 2;
5334 i = 0;
5335 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
5336 ch->fmtlist[i++] = AFMT_S16_LE;
5337 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
5338 if (ch->bit32 > 0) {
5339 if (!(devinfo->function.audio.quirks &
5340 HDA_QUIRK_FORCESTEREO))
5341 ch->fmtlist[i++] = AFMT_S32_LE;
5342 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
5343 }
5344 ch->fmtlist[i] = 0;
5345 i = 0;
5346 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5347 ch->pcmrates[i++] = 8000;
5348 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5349 ch->pcmrates[i++] = 11025;
5350 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5351 ch->pcmrates[i++] = 16000;
5352 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5353 ch->pcmrates[i++] = 22050;
5354 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5355 ch->pcmrates[i++] = 32000;
5356 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5357 ch->pcmrates[i++] = 44100;
5358 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
5359 ch->pcmrates[i++] = 48000;
5360 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5361 ch->pcmrates[i++] = 88200;
5362 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5363 ch->pcmrates[i++] = 96000;
5364 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5365 ch->pcmrates[i++] = 176400;
5366 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5367 ch->pcmrates[i++] = 192000;
5368 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
5369 ch->pcmrates[i] = 0;
5370 if (i > 0) {
5371 ch->caps.minspeed = ch->pcmrates[0];
5372 ch->caps.maxspeed = ch->pcmrates[i - 1];
5373 }
5374 }
5375
5376 return (ret);
5377 }
5378
5379 static void
5380 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
5381 {
5382 struct hdac_audio_ctl *ctl;
5383 struct hdac_softc *sc = devinfo->codec->sc;
5384 int i;
5385 uint32_t fl = 0;
5386
5387
5388 if (flag == 0) {
5389 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
5390 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
5391 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
5392 }
5393
5394 i = 0;
5395 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5396 if (ctl->enable == 0 || ctl->widget == NULL ||
5397 ctl->widget->enable == 0 || (ctl->ossmask &
5398 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)))
5399 continue;
5400 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
5401 (flag != 0 && (ctl->ossmask & flag))) {
5402 if (banner != NULL) {
5403 device_printf(sc->dev, "\n");
5404 device_printf(sc->dev, "%s\n", banner);
5405 }
5406 goto hdac_ctl_dump_it_all;
5407 }
5408 }
5409
5410 return;
5411
5412 hdac_ctl_dump_it_all:
5413 i = 0;
5414 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5415 if (ctl->enable == 0 || ctl->widget == NULL ||
5416 ctl->widget->enable == 0)
5417 continue;
5418 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
5419 (flag != 0 && (ctl->ossmask & flag))))
5420 continue;
5421 if (flag == 0) {
5422 device_printf(sc->dev, "\n");
5423 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
5424 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
5425 }
5426 device_printf(sc->dev, " |\n");
5427 device_printf(sc->dev, " +- nid: %2d index: %2d ",
5428 ctl->widget->nid, ctl->index);
5429 if (ctl->childwidget != NULL)
5430 kprintf("(nid: %2d) ", ctl->childwidget->nid);
5431 else
5432 kprintf(" ");
5433 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
5434 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
5435 ctl->ossmask);
5436 }
5437 }
5438
5439 static void
5440 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
5441 {
5442 uint32_t cap;
5443
5444 cap = fcap;
5445 if (cap != 0) {
5446 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap);
5447 device_printf(sc->dev, " Format:");
5448 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
5449 kprintf(" AC3");
5450 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
5451 kprintf(" FLOAT32");
5452 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5453 kprintf(" PCM");
5454 kprintf("\n");
5455 }
5456 cap = pcmcap;
5457 if (cap != 0) {
5458 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap);
5459 device_printf(sc->dev, " PCM size:");
5460 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5461 kprintf(" 8");
5462 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5463 kprintf(" 16");
5464 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5465 kprintf(" 20");
5466 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5467 kprintf(" 24");
5468 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5469 kprintf(" 32");
5470 kprintf("\n");
5471 device_printf(sc->dev, " PCM rate:");
5472 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5473 kprintf(" 8");
5474 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5475 kprintf(" 11");
5476 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5477 kprintf(" 16");
5478 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5479 kprintf(" 22");
5480 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5481 kprintf(" 32");
5482 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5483 kprintf(" 44");
5484 kprintf(" 48");
5485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5486 kprintf(" 88");
5487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5488 kprintf(" 96");
5489 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5490 kprintf(" 176");
5491 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5492 kprintf(" 192");
5493 kprintf("\n");
5494 }
5495 }
5496
5497 static void
5498 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
5499 {
5500 uint32_t pincap, wcap;
5501
5502 pincap = w->wclass.pin.cap;
5503 wcap = w->param.widget_cap;
5504
5505 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
5506 device_printf(sc->dev, " ");
5507 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
5508 kprintf(" ISC");
5509 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
5510 kprintf(" TRQD");
5511 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
5512 kprintf(" PDC");
5513 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
5514 kprintf(" HP");
5515 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
5516 kprintf(" OUT");
5517 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
5518 kprintf(" IN");
5519 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
5520 kprintf(" BAL");
5521 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
5522 kprintf(" VREF[");
5523 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5524 kprintf(" 50");
5525 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5526 kprintf(" 80");
5527 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5528 kprintf(" 100");
5529 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
5530 kprintf(" GROUND");
5531 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
5532 kprintf(" HIZ");
5533 kprintf(" ]");
5534 }
5535 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
5536 kprintf(" EAPD");
5537 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
5538 kprintf(" : UNSOL");
5539 kprintf("\n");
5540 device_printf(sc->dev, " Pin config: 0x%08x\n",
5541 w->wclass.pin.config);
5542 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
5543 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
5544 kprintf(" HP");
5545 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
5546 kprintf(" IN");
5547 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
5548 kprintf(" OUT");
5549 kprintf("\n");
5550 }
5551
5552 static void
5553 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
5554 {
5555 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
5556 device_printf(sc->dev, " "
5557 "mute=%d step=%d size=%d offset=%d\n",
5558 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
5559 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
5560 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
5561 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
5562 }
5563
5564 static void
5565 hdac_dump_nodes(struct hdac_devinfo *devinfo)
5566 {
5567 struct hdac_softc *sc = devinfo->codec->sc;
5568 struct hdac_widget *w, *cw;
5569 int i, j;
5570
5571 device_printf(sc->dev, "\n");
5572 device_printf(sc->dev, "Default Parameter\n");
5573 device_printf(sc->dev, "-----------------\n");
5574 hdac_dump_audio_formats(sc,
5575 devinfo->function.audio.supp_stream_formats,
5576 devinfo->function.audio.supp_pcm_size_rate);
5577 device_printf(sc->dev, " IN amp: 0x%08x\n",
5578 devinfo->function.audio.inamp_cap);
5579 device_printf(sc->dev, " OUT amp: 0x%08x\n",
5580 devinfo->function.audio.outamp_cap);
5581 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5582 w = hdac_widget_get(devinfo, i);
5583 if (w == NULL) {
5584 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
5585 continue;
5586 }
5587 device_printf(sc->dev, "\n");
5588 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid,
5589 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
5590 "DIGITAL" : "ANALOG",
5591 (w->enable == 0) ? " [DISABLED]" : "");
5592 device_printf(sc->dev, " name: %s\n", w->name);
5593 device_printf(sc->dev, " widget_cap: 0x%08x\n",
5594 w->param.widget_cap);
5595 device_printf(sc->dev, " Parse flags: 0x%08x\n",
5596 w->pflags);
5597 device_printf(sc->dev, " Ctl flags: 0x%08x\n",
5598 w->ctlflags);
5599 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
5600 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
5601 hdac_dump_audio_formats(sc,
5602 w->param.supp_stream_formats,
5603 w->param.supp_pcm_size_rate);
5604 } else if (w->type ==
5605 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5606 hdac_dump_pin(sc, w);
5607 if (w->param.eapdbtl != HDAC_INVALID)
5608 device_printf(sc->dev, " EAPD: 0x%08x\n",
5609 w->param.eapdbtl);
5610 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
5611 w->param.outamp_cap != 0)
5612 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
5613 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
5614 w->param.inamp_cap != 0)
5615 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
5616 device_printf(sc->dev, " connections: %d\n", w->nconns);
5617 for (j = 0; j < w->nconns; j++) {
5618 cw = hdac_widget_get(devinfo, w->conns[j]);
5619 device_printf(sc->dev, " |\n");
5620 device_printf(sc->dev, " + <- nid=%d [%s]",
5621 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
5622 if (cw == NULL)
5623 kprintf(" [UNKNOWN]");
5624 else if (cw->enable == 0)
5625 kprintf(" [DISABLED]");
5626 if (w->nconns > 1 && w->selconn == j && w->type !=
5627 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5628 kprintf(" (selected)");
5629 kprintf("\n");
5630 }
5631 }
5632
5633 }
5634
5635 static int
5636 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5637 {
5638 struct hdac_widget *w, *cw;
5639 struct hdac_softc *sc = devinfo->codec->sc;
5640 int i;
5641
5642 if (depth > HDA_PARSE_MAXDEPTH)
5643 return (0);
5644
5645 w = hdac_widget_get(devinfo, nid);
5646 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
5647 return (0);
5648
5649 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5650 device_printf(sc->dev, "\n");
5651 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5652 device_printf(sc->dev, " ^\n");
5653 device_printf(sc->dev, " |\n");
5654 device_printf(sc->dev, " +-----<------+\n");
5655 } else {
5656 device_printf(sc->dev, " ^\n");
5657 device_printf(sc->dev, " |\n");
5658 device_printf(sc->dev, " ");
5659 kprintf(" nid=%d [%s]\n", w->nid, w->name);
5660 }
5661
5662 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
5663 return (1);
5664 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
5665 for (i = 0; i < w->nconns; i++) {
5666 cw = hdac_widget_get(devinfo, w->conns[i]);
5667 if (cw == NULL || cw->enable == 0 || cw->type ==
5668 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5669 continue;
5670 if (hdac_dump_dac_internal(devinfo, cw->nid,
5671 depth + 1) != 0)
5672 return (1);
5673 }
5674 } else if ((w->type ==
5675 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
5676 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5677 w->selconn > -1 && w->selconn < w->nconns) {
5678 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
5679 depth + 1) != 0)
5680 return (1);
5681 }
5682
5683 return (0);
5684 }
5685
5686 static void
5687 hdac_dump_dac(struct hdac_devinfo *devinfo)
5688 {
5689 struct hdac_widget *w;
5690 struct hdac_softc *sc = devinfo->codec->sc;
5691 int i, printed = 0;
5692
5693 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5694 w = hdac_widget_get(devinfo, i);
5695 if (w == NULL || w->enable == 0)
5696 continue;
5697 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
5698 !(w->pflags & HDA_DAC_PATH))
5699 continue;
5700 if (printed == 0) {
5701 printed = 1;
5702 device_printf(sc->dev, "\n");
5703 device_printf(sc->dev, "Playback path:\n");
5704 }
5705 hdac_dump_dac_internal(devinfo, w->nid, 0);
5706 }
5707 }
5708
5709 static void
5710 hdac_dump_adc(struct hdac_devinfo *devinfo)
5711 {
5712 struct hdac_widget *w, *cw;
5713 struct hdac_softc *sc = devinfo->codec->sc;
5714 int i, j;
5715 int printed = 0;
5716 char ossdevs[256];
5717
5718 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5719 w = hdac_widget_get(devinfo, i);
5720 if (w == NULL || w->enable == 0)
5721 continue;
5722 if (!(w->pflags & HDA_ADC_RECSEL))
5723 continue;
5724 if (printed == 0) {
5725 printed = 1;
5726 device_printf(sc->dev, "\n");
5727 device_printf(sc->dev, "Recording sources:\n");
5728 }
5729 device_printf(sc->dev, "\n");
5730 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5731 for (j = 0; j < w->nconns; j++) {
5732 cw = hdac_widget_get(devinfo, w->conns[j]);
5733 if (cw == NULL || cw->enable == 0)
5734 continue;
5735 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
5736 ossdevs, sizeof(ossdevs));
5737 device_printf(sc->dev, " |\n");
5738 device_printf(sc->dev, " + <- nid=%d [%s]",
5739 cw->nid, cw->name);
5740 if (strlen(ossdevs) > 0) {
5741 kprintf(" [recsrc: %s]", ossdevs);
5742 }
5743 kprintf("\n");
5744 }
5745 }
5746 }
5747
5748 static void
5749 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
5750 {
5751 nid_t *nids;
5752
5753 if (pcnt > 0) {
5754 device_printf(sc->dev, "\n");
5755 device_printf(sc->dev, " PCM Playback: %d\n", pcnt);
5756 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5757 sc->play.supp_pcm_size_rate);
5758 device_printf(sc->dev, " DAC:");
5759 for (nids = sc->play.io; *nids != -1; nids++)
5760 kprintf(" %d", *nids);
5761 kprintf("\n");
5762 }
5763
5764 if (rcnt > 0) {
5765 device_printf(sc->dev, "\n");
5766 device_printf(sc->dev, " PCM Record: %d\n", rcnt);
5767 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5768 sc->rec.supp_pcm_size_rate);
5769 device_printf(sc->dev, " ADC:");
5770 for (nids = sc->rec.io; *nids != -1; nids++)
5771 kprintf(" %d", *nids);
5772 kprintf("\n");
5773 }
5774 }
5775
5776 static void
5777 hdac_release_resources(struct hdac_softc *sc)
5778 {
5779 struct hdac_devinfo *devinfo = NULL;
5780 device_t *devlist = NULL;
5781 int i, devcount;
5782
5783 if (sc == NULL)
5784 return;
5785
5786 hdac_lock(sc);
5787 sc->polling = 0;
5788 sc->poll_ival = 0;
5789 callout_stop(&sc->poll_hda);
5790 callout_stop(&sc->poll_hdac);
5791 callout_stop(&sc->poll_jack);
5792 hdac_reset(sc);
5793 hdac_unlock(sc);
5794
5795 hdac_irq_free(sc);
5796
5797 /* give pending interrupts stuck on the lock a chance to clear */
5798 /* bad hack */
5799 tsleep(&sc->irq, 0, "hdaslp", hz / 10);
5800
5801 device_get_children(sc->dev, &devlist, &devcount);
5802 for (i = 0; devlist != NULL && i < devcount; i++) {
5803 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
5804 if (devinfo == NULL)
5805 continue;
5806 if (devinfo->widget != NULL)
5807 kfree(devinfo->widget, M_HDAC);
5808 if (devinfo->node_type ==
5809 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
5810 devinfo->function.audio.ctl != NULL)
5811 kfree(devinfo->function.audio.ctl, M_HDAC);
5812 kfree(devinfo, M_HDAC);
5813 device_delete_child(sc->dev, devlist[i]);
5814 }
5815 if (devlist != NULL)
5816 kfree(devlist, M_TEMP);
5817
5818 for (i = 0; i < HDAC_CODEC_MAX; i++) {
5819 if (sc->codecs[i] != NULL)
5820 kfree(sc->codecs[i], M_HDAC);
5821 sc->codecs[i] = NULL;
5822 }
5823
5824 hdac_dma_free(sc, &sc->pos_dma);
5825 hdac_dma_free(sc, &sc->rirb_dma);
5826 hdac_dma_free(sc, &sc->corb_dma);
5827 if (sc->play.blkcnt > 0)
5828 hdac_dma_free(sc, &sc->play.bdl_dma);
5829 if (sc->rec.blkcnt > 0)
5830 hdac_dma_free(sc, &sc->rec.bdl_dma);
5831 if (sc->chan_dmat != NULL) {
5832 bus_dma_tag_destroy(sc->chan_dmat);
5833 sc->chan_dmat = NULL;
5834 }
5835 hdac_mem_free(sc);
5836 snd_mtxfree(sc->lock);
5837 kfree(sc, M_DEVBUF);
5838 }
5839
5840 /* This function surely going to make its way into upper level someday. */
5841 static void
5842 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
5843 {
5844 char *res = NULL;
5845 int i = 0, j, k, len, inv;
5846
5847 if (on != NULL)
5848 *on = 0;
5849 if (off != NULL)
5850 *off = 0;
5851 if (sc == NULL)
5852 return;
5853 if (resource_string_value(device_get_name(sc->dev),
5854 device_get_unit(sc->dev), "config", &res) != 0)
5855 return;
5856 if (!(res != NULL && strlen(res) > 0))
5857 return;
5858 HDA_BOOTVERBOSE(
5859 device_printf(sc->dev, "HDA_DEBUG: HDA Config:");
5860 );
5861 for (;;) {
5862 while (res[i] != '\0' &&
5863 (res[i] == ',' || isspace(res[i]) != 0))
5864 i++;
5865 if (res[i] == '\0') {
5866 HDA_BOOTVERBOSE(
5867 kprintf("\n");
5868 );
5869 return;
5870 }
5871 j = i;
5872 while (res[j] != '\0' &&
5873 !(res[j] == ',' || isspace(res[j]) != 0))
5874 j++;
5875 len = j - i;
5876 if (len > 2 && strncmp(res + i, "no", 2) == 0)
5877 inv = 2;
5878 else
5879 inv = 0;
5880 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
5881 if (strncmp(res + i + inv,
5882 hdac_quirks_tab[k].key, len - inv) != 0)
5883 continue;
5884 if (len - inv != strlen(hdac_quirks_tab[k].key))
5885 break;
5886 HDA_BOOTVERBOSE(
5887 kprintf(" %s%s", (inv != 0) ? "no" : "",
5888 hdac_quirks_tab[k].key);
5889 );
5890 if (inv == 0 && on != NULL)
5891 *on |= hdac_quirks_tab[k].value;
5892 else if (inv != 0 && off != NULL)
5893 *off |= hdac_quirks_tab[k].value;
5894 break;
5895 }
5896 i = j;
5897 }
5898 }
5899
5900 #ifdef SND_DYNSYSCTL
5901 static int
5902 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
5903 {
5904 struct hdac_softc *sc;
5905 struct hdac_devinfo *devinfo;
5906 device_t dev;
5907 uint32_t ctl;
5908 int err, val;
5909
5910 dev = oidp->oid_arg1;
5911 devinfo = pcm_getdevinfo(dev);
5912 if (devinfo == NULL || devinfo->codec == NULL ||
5913 devinfo->codec->sc == NULL)
5914 return (EINVAL);
5915 sc = devinfo->codec->sc;
5916 hdac_lock(sc);
5917 val = sc->polling;
5918 hdac_unlock(sc);
5919 err = sysctl_handle_int(oidp, &val, 0, req);
5920
5921 if (err != 0 || req->newptr == NULL)
5922 return (err);
5923 if (val < 0 || val > 1)
5924 return (EINVAL);
5925
5926 hdac_lock(sc);
5927 if (val != sc->polling) {
5928 if (hda_chan_active(sc) != 0)
5929 err = EBUSY;
5930 else if (val == 0) {
5931 callout_stop(&sc->poll_hdac);
5932 hdac_unlock(sc);
5933 hdac_lock(sc);
5934 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT,
5935 sc->rirb_size / 2);
5936 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5937 ctl |= HDAC_RIRBCTL_RINTCTL;
5938 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5939 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
5940 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
5941 sc->polling = 0;
5942 DELAY(1000);
5943 } else {
5944 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0);
5945 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0);
5946 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5947 ctl &= ~HDAC_RIRBCTL_RINTCTL;
5948 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5949 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback,
5950 sc);
5951 sc->polling = 1;
5952 DELAY(1000);
5953 }
5954 }
5955 hdac_unlock(sc);
5956
5957 return (err);
5958 }
5959
5960 static int
5961 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
5962 {
5963 struct hdac_softc *sc;
5964 struct hdac_devinfo *devinfo;
5965 device_t dev;
5966 int err, val;
5967
5968 dev = oidp->oid_arg1;
5969 devinfo = pcm_getdevinfo(dev);
5970 if (devinfo == NULL || devinfo->codec == NULL ||
5971 devinfo->codec->sc == NULL)
5972 return (EINVAL);
5973 sc = devinfo->codec->sc;
5974 hdac_lock(sc);
5975 val = ((uint64_t)sc->poll_ival * 1000) / hz;
5976 hdac_unlock(sc);
5977 err = sysctl_handle_int(oidp, &val, 0, req);
5978
5979 if (err != 0 || req->newptr == NULL)
5980 return (err);
5981
5982 if (val < 1)
5983 val = 1;
5984 if (val > 5000)
5985 val = 5000;
5986 val = ((uint64_t)val * hz) / 1000;
5987 if (val < 1)
5988 val = 1;
5989 if (val > (hz * 5))
5990 val = hz * 5;
5991
5992 hdac_lock(sc);
5993 sc->poll_ival = val;
5994 hdac_unlock(sc);
5995
5996 return (err);
5997 }
5998
5999 #ifdef SND_DEBUG
6000 static int
6001 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
6002 {
6003 struct hdac_softc *sc;
6004 struct hdac_devinfo *devinfo;
6005 struct hdac_widget *w;
6006 device_t dev;
6007 uint32_t res, pincap, execres;
6008 int i, err, val;
6009 nid_t cad;
6010
6011 dev = oidp->oid_arg1;
6012 devinfo = pcm_getdevinfo(dev);
6013 if (devinfo == NULL || devinfo->codec == NULL ||
6014 devinfo->codec->sc == NULL)
6015 return (EINVAL);
6016 val = 0;
6017 err = sysctl_handle_int(oidp, &val, 0, req);
6018 if (err != 0 || req->newptr == NULL || val == 0)
6019 return (err);
6020 sc = devinfo->codec->sc;
6021 cad = devinfo->codec->cad;
6022 hdac_lock(sc);
6023 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid);
6024 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6025 w = hdac_widget_get(devinfo, i);
6026 if (w == NULL || w->type !=
6027 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6028 continue;
6029 pincap = w->wclass.pin.cap;
6030 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) ||
6031 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) &&
6032 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) {
6033 timeout = 10000;
6034 hdac_command(sc,
6035 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad);
6036 do {
6037 res = hdac_command(sc,
6038 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
6039 if (res != 0x7fffffff)
6040 break;
6041 DELAY(10);
6042 } while (--timeout != 0);
6043 } else {
6044 timeout = -1;
6045 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad,
6046 w->nid), cad);
6047 }
6048 device_printf(dev,
6049 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n",
6050 w->nid, timeout, res,
6051 (w->enable == 0) ? "DISABLED" : "ENABLED");
6052 }
6053 device_printf(dev,
6054 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
6055 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
6056 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
6057 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
6058 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
6059 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
6060 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
6061 device_printf(dev, " GPI:");
6062 res = hdac_command(sc,
6063 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
6064 kprintf(" data=0x%08x", res);
6065 res = hdac_command(sc,
6066 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
6067 cad);
6068 kprintf(" wake=0x%08x", res);
6069 res = hdac_command(sc,
6070 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
6071 cad);
6072 kprintf(" unsol=0x%08x", res);
6073 res = hdac_command(sc,
6074 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
6075 kprintf(" sticky=0x%08x\n", res);
6076 }
6077 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
6078 device_printf(dev, " GPO:");
6079 res = hdac_command(sc,
6080 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
6081 kprintf(" data=0x%08x\n", res);
6082 }
6083 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
6084 device_printf(dev, "GPI0:");
6085 res = hdac_command(sc,
6086 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
6087 kprintf(" data=0x%08x", res);
6088 res = hdac_command(sc,
6089 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
6090 kprintf(" enable=0x%08x", res);
6091 res = hdac_command(sc,
6092 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
6093 kprintf(" direction=0x%08x\n", res);
6094 res = hdac_command(sc,
6095 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
6096 device_printf(dev, " wake=0x%08x", res);
6097 res = hdac_command(sc,
6098 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
6099 cad);
6100 kprintf(" unsol=0x%08x", res);
6101 res = hdac_command(sc,
6102 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
6103 kprintf(" sticky=0x%08x\n", res);
6104 }
6105 hdac_unlock(sc);
6106 return (0);
6107 }
6108 #endif
6109 #endif
6110
6111 static void
6112 hdac_attach2(void *arg)
6113 {
6114 struct hdac_softc *sc;
6115 struct hdac_widget *w;
6116 struct hdac_audio_ctl *ctl;
6117 uint32_t quirks_on, quirks_off;
6118 int pcnt, rcnt, codec_index;
6119 int i;
6120 char status[SND_STATUSLEN];
6121 device_t *devlist = NULL;
6122 int devcount;
6123 struct hdac_devinfo *devinfo = NULL;
6124
6125 sc = (struct hdac_softc *)arg;
6126
6127 hdac_config_fetch(sc, &quirks_on, &quirks_off);
6128
6129 HDA_BOOTVERBOSE(
6130 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n",
6131 quirks_on, quirks_off);
6132 );
6133
6134 if (resource_int_value(device_get_name(sc->dev),
6135 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) {
6136 switch (sc->pci_subvendor) {
6137 case GB_G33S2H_SUBVENDOR:
6138 codec_index = 2;
6139 break;
6140 default:
6141 codec_index = 0;
6142 break;
6143 }
6144 }
6145
6146 hdac_lock(sc);
6147
6148 /* Remove ourselves from the config hooks */
6149 if (sc->intrhook.ich_func != NULL) {
6150 config_intrhook_disestablish(&sc->intrhook);
6151 sc->intrhook.ich_func = NULL;
6152 }
6153
6154 /* Start the corb and rirb engines */
6155 HDA_BOOTVERBOSE(
6156 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n");
6157 );
6158 hdac_corb_start(sc);
6159 HDA_BOOTVERBOSE(
6160 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n");
6161 );
6162 hdac_rirb_start(sc);
6163
6164 HDA_BOOTVERBOSE(
6165 device_printf(sc->dev,
6166 "HDA_DEBUG: Enabling controller interrupt...\n");
6167 );
6168 if (sc->polling == 0)
6169 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
6170 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
6171 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
6172 HDAC_GCTL_UNSOL);
6173
6174 DELAY(1000);
6175
6176 HDA_BOOTVERBOSE(
6177 device_printf(sc->dev,
6178 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n",
6179 codec_index);
6180 );
6181 hdac_scan_codecs(sc, codec_index);
6182
6183 device_get_children(sc->dev, &devlist, &devcount);
6184 for (i = 0; devlist != NULL && i < devcount; i++) {
6185 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
6186 if (devinfo != NULL && devinfo->node_type ==
6187 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
6188 break;
6189 } else
6190 devinfo = NULL;
6191 }
6192 if (devlist != NULL)
6193 kfree(devlist, M_TEMP);
6194
6195 if (devinfo == NULL) {
6196 hdac_unlock(sc);
6197 device_printf(sc->dev, "Audio Function Group not found!\n");
6198 hdac_release_resources(sc);
6199 return;
6200 }
6201
6202 HDA_BOOTVERBOSE(
6203 device_printf(sc->dev,
6204 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n",
6205 devinfo->nid, devinfo->codec->cad);
6206 );
6207 hdac_audio_parse(devinfo);
6208 HDA_BOOTVERBOSE(
6209 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n");
6210 );
6211 hdac_audio_ctl_parse(devinfo);
6212 HDA_BOOTVERBOSE(
6213 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n");
6214 );
6215 hdac_vendor_patch_parse(devinfo);
6216 if (quirks_on != 0)
6217 devinfo->function.audio.quirks |= quirks_on;
6218 if (quirks_off != 0)
6219 devinfo->function.audio.quirks &= ~quirks_off;
6220
6221 /* XXX Disable all DIGITAL path. */
6222 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6223 w = hdac_widget_get(devinfo, i);
6224 if (w == NULL)
6225 continue;
6226 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
6227 w->enable = 0;
6228 continue;
6229 }
6230 /* XXX Disable useless pin ? */
6231 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6232 (w->wclass.pin.config &
6233 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
6234 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
6235 w->enable = 0;
6236 }
6237 i = 0;
6238 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6239 if (ctl->widget == NULL)
6240 continue;
6241 if (ctl->ossmask & SOUND_MASK_DISABLE)
6242 ctl->enable = 0;
6243 w = ctl->widget;
6244 if (w->enable == 0 ||
6245 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6246 ctl->enable = 0;
6247 w = ctl->childwidget;
6248 if (w == NULL)
6249 continue;
6250 if (w->enable == 0 ||
6251 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6252 ctl->enable = 0;
6253 }
6254
6255 HDA_BOOTVERBOSE(
6256 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n");
6257 );
6258 hdac_audio_build_tree(devinfo);
6259
6260 i = 0;
6261 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6262 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))
6263 ctl->ossmask = 0;
6264 }
6265 HDA_BOOTVERBOSE(
6266 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n");
6267 );
6268 hdac_audio_commit(devinfo, HDA_COMMIT_ALL);
6269 HDA_BOOTVERBOSE(
6270 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n");
6271 );
6272 hdac_audio_ctl_commit(devinfo);
6273
6274 HDA_BOOTVERBOSE(
6275 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n");
6276 );
6277 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY);
6278 HDA_BOOTVERBOSE(
6279 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n");
6280 );
6281 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC);
6282
6283 hdac_unlock(sc);
6284 HDA_BOOTVERBOSE(
6285 device_printf(sc->dev,
6286 "HDA_DEBUG: OSS mixer initialization...\n");
6287 );
6288
6289 /*
6290 * There is no point of return after this. If the driver failed,
6291 * so be it. Let the detach procedure do all the cleanup.
6292 */
6293 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0)
6294 device_printf(sc->dev, "Can't register mixer\n");
6295
6296 if (pcnt > 0)
6297 pcnt = 1;
6298 if (rcnt > 0)
6299 rcnt = 1;
6300
6301 HDA_BOOTVERBOSE(
6302 device_printf(sc->dev,
6303 "HDA_DEBUG: Registering PCM channels...\n");
6304 );
6305 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0)
6306 device_printf(sc->dev, "Can't register PCM\n");
6307
6308 sc->registered++;
6309
6310 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
6311 hdac_dma_alloc(sc, &sc->pos_dma,
6312 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
6313 HDA_BOOTVERBOSE(
6314 device_printf(sc->dev,
6315 "Failed to allocate DMA pos buffer (non-fatal)\n");
6316 );
6317 }
6318
6319 for (i = 0; i < pcnt; i++)
6320 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo);
6321 for (i = 0; i < rcnt; i++)
6322 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo);
6323
6324 #ifdef SND_DYNSYSCTL
6325 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6326 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6327 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6328 sysctl_hdac_polling, "I", "Enable polling mode");
6329 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6330 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6331 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
6332 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
6333 "Controller/Jack Sense polling interval (1-1000 ms)");
6334 #ifdef SND_DEBUG
6335 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6336 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6337 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6338 sysctl_hdac_pindump, "I", "Dump pin states/data");
6339 #endif
6340 #endif
6341
6342 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]",
6343 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res),
6344 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV);
6345 pcm_setstatus(sc->dev, status);
6346 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo));
6347 HDA_BOOTVERBOSE(
6348 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n",
6349 hdac_codec_id(devinfo));
6350 );
6351 device_printf(sc->dev, "<HDA Driver Revision: %s>\n",
6352 HDA_DRV_TEST_REV);
6353
6354 HDA_BOOTVERBOSE(
6355 if (devinfo->function.audio.quirks != 0) {
6356 device_printf(sc->dev, "\n");
6357 device_printf(sc->dev, "HDA config/quirks:");
6358 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
6359 if ((devinfo->function.audio.quirks &
6360 hdac_quirks_tab[i].value) ==
6361 hdac_quirks_tab[i].value)
6362 kprintf(" %s", hdac_quirks_tab[i].key);
6363 }
6364 kprintf("\n");
6365 }
6366 device_printf(sc->dev, "\n");
6367 device_printf(sc->dev, "+-------------------+\n");
6368 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
6369 device_printf(sc->dev, "+-------------------+\n");
6370 hdac_dump_nodes(devinfo);
6371 device_printf(sc->dev, "\n");
6372 device_printf(sc->dev, "+------------------------+\n");
6373 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
6374 device_printf(sc->dev, "+------------------------+\n");
6375 device_printf(sc->dev, "\n");
6376 i = 0;
6377 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6378 device_printf(sc->dev, "%3d: nid=%d", i,
6379 (ctl->widget != NULL) ? ctl->widget->nid : -1);
6380 if (ctl->childwidget != NULL)
6381 kprintf(" cnid=%d", ctl->childwidget->nid);
6382 kprintf(" dir=0x%x index=%d "
6383 "ossmask=0x%08x ossdev=%d%s\n",
6384 ctl->dir, ctl->index,
6385 ctl->ossmask, ctl->ossdev,
6386 (ctl->enable == 0) ? " [DISABLED]" : "");
6387 }
6388 device_printf(sc->dev, "\n");
6389 device_printf(sc->dev, "+-----------------------------------+\n");
6390 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n");
6391 device_printf(sc->dev, "+-----------------------------------+\n");
6392 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME);
6393 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM);
6394 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD);
6395 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC);
6396 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE);
6397 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV);
6398 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER);
6399 hdac_dump_ctls(devinfo, NULL, 0);
6400 hdac_dump_dac(devinfo);
6401 hdac_dump_adc(devinfo);
6402 device_printf(sc->dev, "\n");
6403 device_printf(sc->dev, "+--------------------------------------+\n");
6404 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n");
6405 device_printf(sc->dev, "+--------------------------------------+\n");
6406 hdac_dump_pcmchannels(sc, pcnt, rcnt);
6407 );
6408
6409 if (sc->polling != 0) {
6410 hdac_lock(sc);
6411 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
6412 hdac_unlock(sc);
6413 }
6414 }
6415
6416 /****************************************************************************
6417 * int hdac_detach(device_t)
6418 *
6419 * Detach and free up resources utilized by the hdac device.
6420 ****************************************************************************/
6421 static int
6422 hdac_detach(device_t dev)
6423 {
6424 struct hdac_softc *sc = NULL;
6425 struct hdac_devinfo *devinfo = NULL;
6426 int err;
6427
6428 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev);
6429 if (devinfo != NULL && devinfo->codec != NULL)
6430 sc = devinfo->codec->sc;
6431 if (sc == NULL)
6432 return (0);
6433
6434 if (sc->registered > 0) {
6435 err = pcm_unregister(dev);
6436 if (err != 0)
6437 return (err);
6438 }
6439
6440 hdac_release_resources(sc);
6441
6442 return (0);
6443 }
6444
6445 static device_method_t hdac_methods[] = {
6446 /* device interface */
6447 DEVMETHOD(device_probe, hdac_probe),
6448 DEVMETHOD(device_attach, hdac_attach),
6449 DEVMETHOD(device_detach, hdac_detach),
6450 { 0, 0 }
6451 };
6452
6453 static driver_t hdac_driver = {
6454 "pcm",
6455 hdac_methods,
6456 PCM_SOFTC_SIZE,
6457 };
6458
6459 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0);
6460 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
6461 MODULE_VERSION(snd_hda, 1);
DragonFly BSD