sys/dev/netif/e1000/if_igb.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
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   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
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  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
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  18       this software without specific prior written permission.
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  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _IGB_H_DEFINED_
  36 #define _IGB_H_DEFINED_
  37
  38 /* Tunables */
  39
  40 /*
  41  * IGB_TXD: Maximum number of Transmit Descriptors
  42  *
  43  *   This value is the number of transmit descriptors allocated by the driver.
  44  *   Increasing this value allows the driver to queue more transmits. Each
  45  *   descriptor is 16 bytes.
  46  *   Since TDLEN should be multiple of 128bytes, the number of transmit
  47  *   desscriptors should meet the following condition.
  48  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
  49  */
  50 #define IGB_MIN_TXD             80
  51 #define IGB_DEFAULT_TXD         256
  52 #define IGB_MAX_TXD             4096
  53
  54 /*
  55  * IGB_RXD: Maximum number of Transmit Descriptors
  56  *
  57  *   This value is the number of receive descriptors allocated by the driver.
  58  *   Increasing this value allows the driver to buffer more incoming packets.
  59  *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
  60  *   descriptor. The maximum MTU size is 16110.
  61  *   Since TDLEN should be multiple of 128bytes, the number of transmit
  62  *   desscriptors should meet the following condition.
  63  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
  64  */
  65 #define IGB_MIN_RXD             80
  66 #define IGB_DEFAULT_RXD         256
  67 #define IGB_MAX_RXD             4096
  68
  69 /*
  70  * IGB_TIDV - Transmit Interrupt Delay Value
  71  * Valid Range: 0-65535 (0=off)
  72  * Default Value: 64
  73  *   This value delays the generation of transmit interrupts in units of
  74  *   1.024 microseconds. Transmit interrupt reduction can improve CPU
  75  *   efficiency if properly tuned for specific network traffic. If the
  76  *   system is reporting dropped transmits, this value may be set too high
  77  *   causing the driver to run out of available transmit descriptors.
  78  */
  79 #define IGB_TIDV                         64
  80
  81 /*
  82  * IGB_TADV - Transmit Absolute Interrupt Delay Value
  83  * Valid Range: 0-65535 (0=off)
  84  * Default Value: 64
  85  *   This value, in units of 1.024 microseconds, limits the delay in which a
  86  *   transmit interrupt is generated. Useful only if IGB_TIDV is non-zero,
  87  *   this value ensures that an interrupt is generated after the initial
  88  *   packet is sent on the wire within the set amount of time.  Proper tuning,
  89  *   along with IGB_TIDV, may improve traffic throughput in specific
  90  *   network conditions.
  91  */
  92 #define IGB_TADV                         64
  93
  94 /*
  95  * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer)
  96  * Valid Range: 0-65535 (0=off)
  97  * Default Value: 0
  98  *   This value delays the generation of receive interrupts in units of 1.024
  99  *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
 100  *   properly tuned for specific network traffic. Increasing this value adds
 101  *   extra latency to frame reception and can end up decreasing the throughput
 102  *   of TCP traffic. If the system is reporting dropped receives, this value
 103  *   may be set too high, causing the driver to run out of available receive
 104  *   descriptors.
 105  *
 106  *   CAUTION: When setting IGB_RDTR to a value other than 0, adapters
 107  *            may hang (stop transmitting) under certain network conditions.
 108  *            If this occurs a WATCHDOG message is logged in the system
 109  *            event log. In addition, the controller is automatically reset,
 110  *            restoring the network connection. To eliminate the potential
 111  *            for the hang ensure that IGB_RDTR is set to 0.
 112  */
 113 #define IGB_RDTR                         0
 114
 115 /*
 116  * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
 117  * Valid Range: 0-65535 (0=off)
 118  * Default Value: 64
 119  *   This value, in units of 1.024 microseconds, limits the delay in which a
 120  *   receive interrupt is generated. Useful only if IGB_RDTR is non-zero,
 121  *   this value ensures that an interrupt is generated after the initial
 122  *   packet is received within the set amount of time.  Proper tuning,
 123  *   along with IGB_RDTR, may improve traffic throughput in specific network
 124  *   conditions.
 125  */
 126 #define IGB_RADV                         64
 127
 128 /*
 129  * This parameter controls the duration of transmit watchdog timer.
 130  */
 131 #define IGB_WATCHDOG                   (10 * hz)
 132
 133 /*
 134  * This parameter controls when the driver calls the routine to reclaim
 135  * transmit descriptors.
 136  */
 137 #define IGB_TX_CLEANUP_THRESHOLD        (adapter->num_tx_desc / 8)
 138 #define IGB_TX_OP_THRESHOLD     (adapter->num_tx_desc / 32)
 139
 140 /*
 141  * This parameter controls whether or not autonegotation is enabled.
 142  *              0 - Disable autonegotiation
 143  *              1 - Enable  autonegotiation
 144  */
 145 #define DO_AUTO_NEG                     1
 146
 147 /*
 148  * This parameter control whether or not the driver will wait for
 149  * autonegotiation to complete.
 150  *              1 - Wait for autonegotiation to complete
 151  *              0 - Don't wait for autonegotiation to complete
 152  */
 153 #define WAIT_FOR_AUTO_NEG_DEFAULT       0
 154
 155 /* Tunables -- End */
 156
 157 #define AUTONEG_ADV_DEFAULT     (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
 158                                 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
 159                                 ADVERTISE_1000_FULL)
 160
 161 #define AUTO_ALL_MODES          0
 162
 163 /* PHY master/slave setting */
 164 #define IGB_MASTER_SLAVE                e1000_ms_hw_default
 165
 166 /*
 167  * Micellaneous constants
 168  */
 169 #define IGB_VENDOR_ID                   0x8086
 170
 171 #define IGB_JUMBO_PBA                   0x00000028
 172 #define IGB_DEFAULT_PBA                 0x00000030
 173 #define IGB_SMARTSPEED_DOWNSHIFT        3
 174 #define IGB_SMARTSPEED_MAX              15
 175 #define IGB_MAX_LOOP                    10
 176
 177 #define IGB_RX_PTHRESH                  (hw->mac.type <= e1000_82576 ? 16 : 8)
 178 #define IGB_RX_HTHRESH                  8
 179 #define IGB_RX_WTHRESH                  1
 180
 181 #define IGB_TX_PTHRESH                  8
 182 #define IGB_TX_HTHRESH                  1
 183 #define IGB_TX_WTHRESH                  ((hw->mac.type == e1000_82576 && \
 184                                           adapter->msix_mem) ? 1 : 16)
 185
 186 #define MAX_NUM_MULTICAST_ADDRESSES     128
 187 #define PCI_ANY_ID                      (~0U)
 188 #define ETHER_ALIGN                     2
 189 #define IGB_TX_BUFFER_SIZE              ((uint32_t) 1514)
 190 #define IGB_FC_PAUSE_TIME               0x0680
 191 #define IGB_EEPROM_APME                 0x400;
 192
 193 /*
 194  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
 195  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
 196  * also optimize cache line size effect. H/W supports up to cache line size 128.
 197  */
 198 #define IGB_DBA_ALIGN                   128
 199
 200 #define SPEED_MODE_BIT (1<<21)          /* On PCI-E MACs only */
 201
 202 /* PCI Config defines */
 203 #define IGB_MSIX_BAR            3
 204
 205 /*
 206 ** This is the total number of MSIX vectors you wish
 207 ** to use, it also controls the size of resources.
 208 ** The 82575 has a total of 10, 82576 has 25. Set this
 209 ** to the real amount you need to streamline data storage.
 210 */
 211 #define IGB_MSIX_VEC            6       /* MSIX vectors configured */
 212
 213 /* Defines for printing debug information */
 214 #define DEBUG_INIT  0
 215 #define DEBUG_IOCTL 0
 216 #define DEBUG_HW    0
 217
 218 #define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  kprintf(S "\n")
 219 #define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  kprintf(S "\n", A)
 220 #define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  kprintf(S "\n", A, B)
 221 #define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) kprintf(S "\n")
 222 #define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) kprintf(S "\n", A)
 223 #define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) kprintf(S "\n", A, B)
 224 #define HW_DEBUGOUT(S)              if (DEBUG_HW) kprintf(S "\n")
 225 #define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) kprintf(S "\n", A)
 226 #define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) kprintf(S "\n", A, B)
 227
 228 #define IGB_MAX_SCATTER         64
 229 #define IGB_VFTA_SIZE           128
 230 #define IGB_BR_SIZE             4096    /* ring buf size */
 231 #define IGB_TSO_SIZE            (65535 + sizeof(struct ether_vlan_header))
 232 #define IGB_TSO_SEG_SIZE        4096    /* Max dma segment size */
 233 #define IGB_HDR_BUF             128
 234 #define IGB_PKTTYPE_MASK        0x0000FFF0
 235 #define ETH_ZLEN                60
 236 #define ETH_ADDR_LEN            6
 237
 238 /* Offload bits in mbuf flag */
 239 #if __FreeBSD_version >= 800000
 240 #define CSUM_OFFLOAD            (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
 241 #else
 242 #define CSUM_OFFLOAD            (CSUM_IP|CSUM_TCP|CSUM_UDP)
 243 #endif
 244
 245 /* Define the starting Interrupt rate per Queue */
 246 #define IGB_INTS_PER_SEC        8000
 247 #define IGB_DEFAULT_ITR          1000000000/(IGB_INTS_PER_SEC * 256)
 248
 249
 250 /* Header split codes for get_buf */
 251 #define IGB_CLEAN_HEADER                0x01
 252 #define IGB_CLEAN_PAYLOAD               0x02
 253 #define IGB_CLEAN_BOTH                  (IGB_CLEAN_HEADER | IGB_CLEAN_PAYLOAD)
 254
 255 #define IGB_LINK_ITR            2000
 256
 257 /* Precision Time Sync (IEEE 1588) defines */
 258 #define ETHERTYPE_IEEE1588      0x88F7
 259 #define PICOSECS_PER_TICK       20833
 260 #define TSYNC_PORT              319 /* UDP port for the protocol */
 261
 262 /*
 263  * Bus dma allocation structure used by
 264  * e1000_dma_malloc and e1000_dma_free.
 265  */
 266 struct igb_dma_alloc {
 267         bus_addr_t              dma_paddr;
 268         caddr_t                 dma_vaddr;
 269         bus_dma_tag_t           dma_tag;
 270         bus_dmamap_t            dma_map;
 271         bus_dma_segment_t       dma_seg;
 272         int                     dma_nseg;
 273 };
 274
 275
 276 /*
 277 ** Driver queue struct: this is the interrupt container
 278 **  for the associated tx and rx ring.
 279 */
 280 struct igb_queue {
 281         struct adapter          *adapter;
 282         u32                     msix;           /* This queue's MSIX vector */
 283         u32                     eims;           /* This queue's EIMS bit */
 284         u32                     eitr_setting;
 285         struct resource         *res;
 286         void                    *tag;
 287         struct tx_ring          *txr;
 288         struct rx_ring          *rxr;
 289         struct task             que_task;
 290         struct taskqueue        *tq;
 291         u64                     irqs;
 292 };
 293
 294 /*
 295  * Transmit ring: one per queue
 296  */
 297 struct tx_ring {
 298         struct adapter          *adapter;
 299         u32                     me;
 300         struct spinlock         tx_spin;
 301         char                    spin_name[16];
 302         struct igb_dma_alloc    txdma;
 303         struct e1000_tx_desc    *tx_base;
 304         u32                     next_avail_desc;
 305         u32                     next_to_clean;
 306         volatile u16            tx_avail;
 307         struct igb_tx_buffer    *tx_buffers;
 308 #if __FreeBSD_version >= 800000
 309         struct buf_ring         *br;
 310 #endif
 311         bus_dma_tag_t           txtag;
 312
 313         u32                     bytes;
 314         u32                     packets;
 315
 316         bool                    watchdog_check;
 317         int                     watchdog_time;
 318         u64                     no_desc_avail;
 319         u64                     tx_packets;
 320 };
 321
 322 /*
 323  * Receive ring: one per queue
 324  */
 325 struct rx_ring {
 326         struct adapter          *adapter;
 327         u32                     me;
 328         struct igb_dma_alloc    rxdma;
 329         union e1000_adv_rx_desc *rx_base;
 330 #if NET_LRO
 331         struct lro_ctrl         lro;
 332 #endif
 333         bool                    lro_enabled;
 334         bool                    hdr_split;
 335         bool                    discard;
 336         struct spinlock         rx_spin;
 337         char                    spin_name[16];
 338         u32                     last_cleaned;
 339         u32                     next_to_check;
 340         struct igb_rx_buf       *rx_buffers;
 341         bus_dma_tag_t           rx_htag;        /* dma tag for rx head */
 342         bus_dmamap_t            rx_hspare_map;
 343         bus_dma_tag_t           rx_ptag;        /* dma tag for rx packet */
 344         bus_dmamap_t            rx_pspare_map;
 345         /*
 346          * First/last mbuf pointers, for
 347          * collecting multisegment RX packets.
 348          */
 349         struct mbuf            *fmp;
 350         struct mbuf            *lmp;
 351
 352         u32                     bytes;
 353         u32                     packets;
 354
 355         /* Soft stats */
 356         u64                     rx_split_packets;
 357         u64                     rx_discarded;
 358         u64                     rx_packets;
 359         u64                     rx_bytes;
 360 };
 361
 362 struct adapter {
 363         struct arpcom           arpcom;
 364         struct ifnet    *ifp;
 365         struct e1000_hw hw;
 366
 367         struct e1000_osdep osdep;
 368         device_t dev;
 369
 370         struct resource *pci_mem;
 371         struct resource *msix_mem;
 372         struct resource *res;
 373         void            *tag;
 374         u32             eims_mask;
 375
 376         int             linkvec;
 377         int             link_mask;
 378         struct task     link_task;
 379         int             link_irq;
 380
 381         struct ifmedia  media;
 382         struct callout  timer;
 383         int             msix;   /* total vectors allocated */
 384         int             if_flags;
 385         int             max_frame_size;
 386         int             min_frame_size;
 387         struct spinlock core_spin;
 388         int             igb_insert_vlan_header;
 389         struct task     rxtx_task;
 390         struct taskqueue *tq;   /* adapter task queue */
 391         u16             num_queues;
 392
 393         eventhandler_tag vlan_attach;
 394         eventhandler_tag vlan_detach;
 395         u32             num_vlans;
 396
 397         /* Management and WOL features */
 398         int             wol;
 399         int             has_manage;
 400
 401         /* Info about the board itself */
 402         u8              link_active;
 403         u16             link_speed;
 404         u16             link_duplex;
 405         u32             smartspeed;
 406
 407         /* Interface queues */
 408         struct igb_queue        *queues;
 409
 410         /*
 411          * Transmit rings
 412          */
 413         struct tx_ring          *tx_rings;
 414         u16                     num_tx_desc;
 415
 416         /*
 417          * Receive rings
 418          */
 419         struct rx_ring          *rx_rings;
 420         bool                    rx_hdr_split;
 421         u16                     num_rx_desc;
 422         int                     rx_process_limit;
 423         u32                     rx_mbuf_sz;
 424         u32                     rx_mask;
 425
 426         /* Misc stats maintained by the driver */
 427         unsigned long   dropped_pkts;
 428         unsigned long   mbuf_defrag_failed;
 429         unsigned long   mbuf_header_failed;
 430         unsigned long   mbuf_packet_failed;
 431         unsigned long   no_tx_map_avail;
 432         unsigned long   no_tx_dma_setup;
 433         unsigned long   watchdog_events;
 434         unsigned long   rx_overruns;
 435
 436         boolean_t       in_detach;
 437
 438 #ifdef IGB_IEEE1588
 439         /* IEEE 1588 precision time support */
 440         struct cyclecounter     cycles;
 441         struct nettimer         clock;
 442         struct nettime_compare  compare;
 443         struct hwtstamp_ctrl    hwtstamp;
 444 #endif
 445
 446         /* sysctl tree glue */
 447         struct sysctl_ctx_list  sysctl_ctx;
 448         struct sysctl_oid       *sysctl_tree;
 449
 450         struct e1000_hw_stats stats;
 451 };
 452
 453 /* ******************************************************************************
 454  * vendor_info_array
 455  *
 456  * This array contains the list of Subvendor/Subdevice IDs on which the driver
 457  * should load.
 458  *
 459  * ******************************************************************************/
 460 typedef struct _igb_vendor_info_t {
 461         unsigned int vendor_id;
 462         unsigned int device_id;
 463         unsigned int subvendor_id;
 464         unsigned int subdevice_id;
 465         unsigned int index;
 466 } igb_vendor_info_t;
 467
 468
 469 struct igb_tx_buffer {
 470         int             next_eop;  /* Index of the desc to watch */
 471         struct mbuf    *m_head;
 472         bus_dmamap_t    map;         /* bus_dma map for packet */
 473 };
 474
 475 struct igb_rx_buf {
 476         struct mbuf    *m_head;
 477         struct mbuf    *m_pack;
 478         bus_dmamap_t    head_map;       /* bus_dma map for packet */
 479         bus_dmamap_t    pack_map;       /* bus_dma map for packet */
 480 };
 481
 482 #define IGB_CORE_LOCK_INIT(_sc, _name)  spin_init(&(_sc)->core_spin)
 483 #define IGB_CORE_LOCK_DESTROY(_sc)      spin_uninit(&(_sc)->core_spin)
 484 #define IGB_CORE_LOCK(_sc)              spin_lock_wr(&(_sc)->core_spin)
 485 #define IGB_CORE_UNLOCK(_sc)            spin_unlock_wr(&(_sc)->core_spin)
 486 #define IGB_CORE_LOCK_ASSERT(_sc)
 487
 488 #define IGB_TX_LOCK_DESTROY(_sc)        spin_uninit(&(_sc)->tx_spin)
 489 #define IGB_TX_LOCK(_sc)                spin_lock_wr(&(_sc)->tx_spin)
 490 #define IGB_TX_UNLOCK(_sc)              spin_unlock_wr(&(_sc)->tx_spin)
 491 #define IGB_TX_TRYLOCK(_sc)             spin_trylock_wr(&(_sc)->tx_spin)
 492 #define IGB_TX_LOCK_ASSERT(_sc)
 493
 494 #define IGB_RX_LOCK_DESTROY(_sc)        spin_uninit(&(_sc)->rx_spin)
 495 #define IGB_RX_LOCK(_sc)                spin_lock_wr(&(_sc)->rx_spin)
 496 #define IGB_RX_UNLOCK(_sc)              spin_unlock_wr(&(_sc)->rx_spin)
 497 #define IGB_TX_LOCK_ASSERT(_sc)
 498
 499 #endif /* _IGB_H_DEFINED_ */
 500
 501