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- Merge input/microphone support for ASUS A8N-VMCSM series.
[dragonfly.git] / sys / dev / sound / pci / hda / hdac.c
blob733ced34fd8a8ee4fef4b7632a60c6edfd193028
1 /*-
2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.4 2007/07/04 04:05:22 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.10 2007/11/30 07:41:28 hasso Exp $
29 */
30
31 /*
32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
33 * that this driver still in its early stage, and possible of rewrite are
34 * pretty much guaranteed. There are supposedly several distinct parent/child
35 * busses to make this "perfect", but as for now and for the sake of
36 * simplicity, everything is gobble up within single source.
37 *
38 * List of subsys:
39 * 1) HDA Controller support
40 * 2) HDA Codecs support, which may include
41 * - HDA
42 * - Modem
43 * - HDMI
44 * 3) Widget parser - the real magic of why this driver works on so
45 * many hardwares with minimal vendor specific quirk. The original
46 * parser was written using Ruby and can be found at
47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
48 * ruby parser take the verbose dmesg dump as its input. Refer to
49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
50 * interesting documents, especially UAA (Universal Audio Architecture).
51 * 4) Possible vendor specific support.
52 * (snd_hda_intel, snd_hda_ati, etc..)
53 *
54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
55 * Compaq V3000 with Conexant HDA.
56 *
57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
58 * * *
59 * * This driver is a collaborative effort made by: *
60 * * *
61 * * Stephane E. Potvin <sepotvin@videotron.ca> *
62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
63 * * Wesley Morgan <morganw@chemikals.org> *
64 * * Daniel Eischen <deischen@FreeBSD.org> *
65 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
66 * * Ariff Abdullah <ariff@FreeBSD.org> *
67 * * *
68 * * ....and various people from freebsd-multimedia@FreeBSD.org *
69 * * *
70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
71 */
72
73 #include <dev/sound/pcm/sound.h>
74 #include <bus/pci/pcireg.h>
75 #include <bus/pci/pcivar.h>
76
77 #include <sys/ctype.h>
78 #include <sys/taskqueue.h>
79
80 #include <dev/sound/pci/hda/hdac_private.h>
81 #include <dev/sound/pci/hda/hdac_reg.h>
82 #include <dev/sound/pci/hda/hda_reg.h>
83 #include <dev/sound/pci/hda/hdac.h>
84
85 #include "mixer_if.h"
86
87 #define HDA_DRV_TEST_REV "20070702_0046"
88 #define HDA_WIDGET_PARSER_REV 1
89
90 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.10 2007/11/30 07:41:28 hasso Exp $");
91
92 #define HDA_BOOTVERBOSE(stmt) do { \
93 if (bootverbose != 0) { \
94 stmt \
95 } \
96 } while(0)
97
98 #if 1
99 #undef HDAC_INTR_EXTRA
100 #define HDAC_INTR_EXTRA 1
101 #endif
102
103 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
104 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
105 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
106 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */
107
108 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
109 #include <machine/specialreg.h>
110 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \
111 vm_offset_t va = (vm_offset_t)(v); \
112 vm_size_t sz = (vm_size_t)(s); \
113 if ((sc) != NULL && (sc)->nocache != 0 && va != 0 && sz != 0) \
114 (void)pmap_change_attr(va, sz, (attr)); \
115 } while(0)
116 #else
117 #define HDAC_DMA_ATTR(...)
118 #endif
119
120 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
121 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
122 (fl) == 0xffffffff || \
123 (((fl) & 0xffff0000) == 0xffff0000 && \
124 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
125 (((fl) & 0x0000ffff) == 0x0000ffff && \
126 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
127 #define HDA_MATCH_ALL 0xffffffff
128 #define HDAC_INVALID 0xffffffff
129
130 /* Default controller / jack sense poll: 250ms */
131 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
132
133 /*
134 * Make room for possible 4096 playback/record channels, in 100 years to come.
135 */
136 #define HDAC_TRIGGER_NONE 0x00000000
137 #define HDAC_TRIGGER_PLAY 0x00000fff
138 #define HDAC_TRIGGER_REC 0x00fff000
139 #define HDAC_TRIGGER_UNSOL 0x80000000
140
141 #define HDA_MODEL_CONSTRUCT(vendor, model) \
142 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
143
144 /* Controller models */
145
146 /* Intel */
147 #define INTEL_VENDORID 0x8086
148 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
149 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
150 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
151 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
152 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
153
154 /* Nvidia */
155 #define NVIDIA_VENDORID 0x10de
156 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
157 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
158 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
159 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
160 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
161 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
162 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
163
164 /* ATI */
165 #define ATI_VENDORID 0x1002
166 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
167 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
168 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
169
170 /* VIA */
171 #define VIA_VENDORID 0x1106
172 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
173 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
174
175 /* SiS */
176 #define SIS_VENDORID 0x1039
177 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
178 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
179
180 /* OEM/subvendors */
181
182 /* Intel */
183 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
184
185 /* HP/Compaq */
186 #define HP_VENDORID 0x103c
187 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
188 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
189 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
190 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
191 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
192 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
193 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
194 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
195 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
196 #define HP_NX6325_SUBVENDORX 0x103c30b0
197
198 /* Dell */
199 #define DELL_VENDORID 0x1028
200 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
201 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
202 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
203 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
204 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
205
206 /* Clevo */
207 #define CLEVO_VENDORID 0x1558
208 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
209 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
210
211 /* Acer */
212 #define ACER_VENDORID 0x1025
213 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
214 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
215 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
216
217 /* Asus */
218 #define ASUS_VENDORID 0x1043
219 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
220 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
221 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
222 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
223 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
224 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
225 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
226 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
227 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
228 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
229 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
230 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
231 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
232 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
233 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
234
235 /* IBM / Lenovo */
236 #define IBM_VENDORID 0x1014
237 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
238 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
239
240 /* Lenovo */
241 #define LENOVO_VENDORID 0x17aa
242 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
243 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
244
245 /* Samsung */
246 #define SAMSUNG_VENDORID 0x144d
247 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
248 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
249
250 /* Medion ? */
251 #define MEDION_VENDORID 0x161f
252 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
253 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
254
255 /*
256 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
257 * instead of their own, which is beyond my comprehension
258 * (see HDA_CODEC_STAC9221 below).
259 */
260 #define APPLE_INTEL_MAC 0x76808384
261
262 /* LG Electronics */
263 #define LG_VENDORID 0x1854
264 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
265 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
266
267 /* Fujitsu Siemens */
268 #define FS_VENDORID 0x1734
269 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
270 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
271
272 /* Toshiba */
273 #define TOSHIBA_VENDORID 0x1179
274 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
275 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
276
277 /* Micro-Star International (MSI) */
278 #define MSI_VENDORID 0x1462
279 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
280 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
281
282 /* Uniwill ? */
283 #define UNIWILL_VENDORID 0x1584
284 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
285 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
286
287
288 /* Misc constants.. */
289 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
290 #define HDA_AMP_MUTE_NONE (0)
291 #define HDA_AMP_MUTE_LEFT (1 << 0)
292 #define HDA_AMP_MUTE_RIGHT (1 << 1)
293 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
294
295 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
296 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
297
298 #define HDA_DAC_PATH (1 << 0)
299 #define HDA_ADC_PATH (1 << 1)
300 #define HDA_ADC_RECSEL (1 << 2)
301
302 #define HDA_DAC_LOCKED (1 << 3)
303 #define HDA_ADC_LOCKED (1 << 4)
304
305 #define HDA_CTL_OUT (1 << 0)
306 #define HDA_CTL_IN (1 << 1)
307 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
308
309 #define HDA_GPIO_MAX 8
310 /* 0 - 7 = GPIO , 8 = Flush */
311 #define HDA_QUIRK_GPIO0 (1 << 0)
312 #define HDA_QUIRK_GPIO1 (1 << 1)
313 #define HDA_QUIRK_GPIO2 (1 << 2)
314 #define HDA_QUIRK_GPIO3 (1 << 3)
315 #define HDA_QUIRK_GPIO4 (1 << 4)
316 #define HDA_QUIRK_GPIO5 (1 << 5)
317 #define HDA_QUIRK_GPIO6 (1 << 6)
318 #define HDA_QUIRK_GPIO7 (1 << 7)
319 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
320
321 /* 9 - 25 = anything else */
322 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
323 #define HDA_QUIRK_FIXEDRATE (1 << 10)
324 #define HDA_QUIRK_FORCESTEREO (1 << 11)
325 #define HDA_QUIRK_EAPDINV (1 << 12)
326 #define HDA_QUIRK_DMAPOS (1 << 13)
327
328 /* 26 - 31 = vrefs */
329 #define HDA_QUIRK_IVREF50 (1 << 26)
330 #define HDA_QUIRK_IVREF80 (1 << 27)
331 #define HDA_QUIRK_IVREF100 (1 << 28)
332 #define HDA_QUIRK_OVREF50 (1 << 29)
333 #define HDA_QUIRK_OVREF80 (1 << 30)
334 #define HDA_QUIRK_OVREF100 (1 << 31)
335
336 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
337 HDA_QUIRK_IVREF100)
338 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
339 HDA_QUIRK_OVREF100)
340 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
341
342 #define SOUND_MASK_SKIP (1 << 30)
343 #define SOUND_MASK_DISABLE (1 << 31)
344
345 static const struct {
346 char *key;
347 uint32_t value;
348 } hdac_quirks_tab[] = {
349 { "gpio0", HDA_QUIRK_GPIO0 },
350 { "gpio1", HDA_QUIRK_GPIO1 },
351 { "gpio2", HDA_QUIRK_GPIO2 },
352 { "gpio3", HDA_QUIRK_GPIO3 },
353 { "gpio4", HDA_QUIRK_GPIO4 },
354 { "gpio5", HDA_QUIRK_GPIO5 },
355 { "gpio6", HDA_QUIRK_GPIO6 },
356 { "gpio7", HDA_QUIRK_GPIO7 },
357 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
358 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
359 { "fixedrate", HDA_QUIRK_FIXEDRATE },
360 { "forcestereo", HDA_QUIRK_FORCESTEREO },
361 { "eapdinv", HDA_QUIRK_EAPDINV },
362 { "dmapos", HDA_QUIRK_DMAPOS },
363 { "ivref50", HDA_QUIRK_IVREF50 },
364 { "ivref80", HDA_QUIRK_IVREF80 },
365 { "ivref100", HDA_QUIRK_IVREF100 },
366 { "ovref50", HDA_QUIRK_OVREF50 },
367 { "ovref80", HDA_QUIRK_OVREF80 },
368 { "ovref100", HDA_QUIRK_OVREF100 },
369 { "ivref", HDA_QUIRK_IVREF },
370 { "ovref", HDA_QUIRK_OVREF },
371 { "vref", HDA_QUIRK_VREF },
372 };
373 #define HDAC_QUIRKS_TAB_LEN \
374 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
375
376 #define HDA_BDL_MIN 2
377 #define HDA_BDL_MAX 256
378 #define HDA_BDL_DEFAULT HDA_BDL_MIN
379
380 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
381 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
382
383 #define HDA_BUFSZ_MIN 4096
384 #define HDA_BUFSZ_MAX 65536
385 #define HDA_BUFSZ_DEFAULT 16384
386
387 #define HDA_PARSE_MAXDEPTH 10
388
389 #define HDAC_UNSOLTAG_EVENT_HP 0x00
390 #define HDAC_UNSOLTAG_EVENT_TEST 0x01
391
392 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
393
394 enum {
395 HDA_PARSE_MIXER,
396 HDA_PARSE_DIRECT
397 };
398
399 /* Default */
400 static uint32_t hdac_fmt[] = {
401 AFMT_STEREO | AFMT_S16_LE,
402 0
403 };
404
405 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
406
407 static const struct {
408 uint32_t model;
409 char *desc;
410 } hdac_devices[] = {
411 { HDA_INTEL_82801F, "Intel 82801F" },
412 { HDA_INTEL_82801G, "Intel 82801G" },
413 { HDA_INTEL_82801H, "Intel 82801H" },
414 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
415 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
416 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
417 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" },
418 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" },
419 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" },
420 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" },
421 { HDA_ATI_SB450, "ATI SB450" },
422 { HDA_ATI_SB600, "ATI SB600" },
423 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
424 { HDA_SIS_966, "SiS 966" },
425 /* Unknown */
426 { HDA_INTEL_ALL, "Intel (Unknown)" },
427 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
428 { HDA_ATI_ALL, "ATI (Unknown)" },
429 { HDA_VIA_ALL, "VIA (Unknown)" },
430 { HDA_SIS_ALL, "SiS (Unknown)" },
431 };
432 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
433
434 static const struct {
435 uint16_t vendor;
436 uint8_t reg;
437 uint8_t mask;
438 uint8_t enable;
439 } hdac_pcie_snoop[] = {
440 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
441 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
442 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
443 };
444 #define HDAC_PCIESNOOP_LEN \
445 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
446
447 static const struct {
448 uint32_t rate;
449 int valid;
450 uint16_t base;
451 uint16_t mul;
452 uint16_t div;
453 } hda_rate_tab[] = {
454 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
455 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
456 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
457 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
458 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
459 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
460 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
461 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
462 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
463 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
464 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
465 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
466 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
467 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
468 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
469 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
470 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
471 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
472 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
473 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
474 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
475 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
476 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
477 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
478 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
479 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
480 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
481 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
482 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
483 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
484 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
485 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
486 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
487 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
488 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
489 };
490 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
491
492 /* All codecs you can eat... */
493 #define HDA_CODEC_CONSTRUCT(vendor, id) \
494 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
495
496 /* Realtek */
497 #define REALTEK_VENDORID 0x10ec
498 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
499 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
500 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
501 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
502 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
503 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
504 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
505 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
506 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
507 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
508 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
509
510 /* Analog Devices */
511 #define ANALOGDEVICES_VENDORID 0x11d4
512 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
513 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
514 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
515 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
516 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
517 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
518
519 /* CMedia */
520 #define CMEDIA_VENDORID 0x434d
521 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
522 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
523
524 /* Sigmatel */
525 #define SIGMATEL_VENDORID 0x8384
526 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
527 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
528 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
529 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
530 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
531 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
532 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
533
534 /*
535 * Conexant
536 *
537 * Ok, the truth is, I don't have any idea at all whether
538 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
539 * place that tell me it is "Venice" is from its Windows driver INF.
540 *
541 * Venice - CX?????
542 * Waikiki - CX20551-22
543 */
544 #define CONEXANT_VENDORID 0x14f1
545 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
546 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
547 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
548
549 /* VIA */
550 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
551 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
552 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
553 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
554 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
555 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
556 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
557 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
558 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
559 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
560 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
561 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
562 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
563
564
565 /* Codecs */
566 static const struct {
567 uint32_t id;
568 char *name;
569 } hdac_codecs[] = {
570 { HDA_CODEC_ALC260, "Realtek ALC260" },
571 { HDA_CODEC_ALC262, "Realtek ALC262" },
572 { HDA_CODEC_ALC660, "Realtek ALC660" },
573 { HDA_CODEC_ALC861, "Realtek ALC861" },
574 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
575 { HDA_CODEC_ALC880, "Realtek ALC880" },
576 { HDA_CODEC_ALC882, "Realtek ALC882" },
577 { HDA_CODEC_ALC883, "Realtek ALC883" },
578 { HDA_CODEC_ALC885, "Realtek ALC885" },
579 { HDA_CODEC_ALC888, "Realtek ALC888" },
580 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
581 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
582 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
583 { HDA_CODEC_AD1988, "Analog Devices AD1988" },
584 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
585 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
586 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
587 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
588 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
589 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
590 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" },
591 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
592 { HDA_CODEC_CXVENICE, "Conexant Venice" },
593 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
594 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
595 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
596 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
597 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
598 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
599 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
600 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
601 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
602 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
603 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
604 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
605 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
606 /* Unknown codec */
607 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
608 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
609 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
610 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
611 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
612 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
613 };
614 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
615
616 enum {
617 HDAC_HP_SWITCH_CTL,
618 HDAC_HP_SWITCH_CTRL,
619 HDAC_HP_SWITCH_DEBUG
620 };
621
622 static const struct {
623 uint32_t model;
624 uint32_t id;
625 int type;
626 int inverted;
627 int polling;
628 int execsense;
629 nid_t hpnid;
630 nid_t spkrnid[8];
631 nid_t eapdnid;
632 } hdac_hp_switch[] = {
633 /* Specific OEM models */
634 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
635 0, 0, -1, 17, { 16, -1 }, 16 },
636 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
637 0, 0, -1, 21, { 16, 17, -1 }, -1 } */
638 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
639 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/
640 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
641 0, 0, -1, 6, { 5, -1 }, 5 },
642 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
643 0, 0, -1, 6, { 5, -1 }, 5 },
644 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
645 0, 0, -1, 6, { 5, -1 }, 5 },
646 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
647 0, 0, -1, 6, { 5, -1 }, -1 },
648 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
649 0, 0, -1, 13, { 14, -1 }, -1 },
650 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
651 0, 0, -1, 13, { 14, -1 }, -1 },
652 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
653 0, 0, -1, 6, { 5, 7, -1 }, -1 },
654 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
655 0, 0, -1, 10, { 13, -1 }, -1 },
656 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
657 1, 0, -1, 26, { 27, -1 }, -1 },
658 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
659 0, 0, -1, 27, { 20, -1 }, -1 },
660 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
661 0, 0, -1, 20, { 21, -1 }, -1 },
662 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
663 0, 0, -1, 20, { 21, -1 }, -1 },
664 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
665 0, 0, -1, 20, { 21, -1 }, -1 },
666 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
667 0, 0, -1, 20, { 27, -1 }, -1 },
668 /*
669 * All models that at least come from the same vendor with
670 * simmilar codec.
671 */
672 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
673 0, 0, -1, 17, { 16, -1 }, 16 },
674 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
675 0, 0, -1, 6, { 5, -1 }, 5 },
676 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
677 0, 0, -1, 6, { 5, -1 }, -1 },
678 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
679 0, 0, -1, 13, { 14, -1 }, -1 },
680 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
681 1, 0, -1, 26, { 27, -1 }, -1 },
682 #if 0
683 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
684 0, 0, -1, 20, { 21, -1 }, -1 },
685 #endif
686 };
687 #define HDAC_HP_SWITCH_LEN \
688 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
689
690 static const struct {
691 uint32_t model;
692 uint32_t id;
693 nid_t eapdnid;
694 int hp_switch;
695 } hdac_eapd_switch[] = {
696 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
697 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
698 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
699 };
700 #define HDAC_EAPD_SWITCH_LEN \
701 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
702
703 /****************************************************************************
704 * Function prototypes
705 ****************************************************************************/
706 static void hdac_intr_handler(void *);
707 static int hdac_reset(struct hdac_softc *);
708 static int hdac_get_capabilities(struct hdac_softc *);
709 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
710 static int hdac_dma_alloc(struct hdac_softc *,
711 struct hdac_dma *, bus_size_t);
712 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
713 static int hdac_mem_alloc(struct hdac_softc *);
714 static void hdac_mem_free(struct hdac_softc *);
715 static int hdac_irq_alloc(struct hdac_softc *);
716 static void hdac_irq_free(struct hdac_softc *);
717 static void hdac_corb_init(struct hdac_softc *);
718 static void hdac_rirb_init(struct hdac_softc *);
719 static void hdac_corb_start(struct hdac_softc *);
720 static void hdac_rirb_start(struct hdac_softc *);
721 static void hdac_scan_codecs(struct hdac_softc *);
722 static int hdac_probe_codec(struct hdac_codec *);
723 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
724 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
725
726 static void hdac_attach2(void *);
727
728 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
729 uint32_t, int);
730 static void hdac_command_send_internal(struct hdac_softc *,
731 struct hdac_command_list *, int);
732
733 static int hdac_probe(device_t);
734 static int hdac_attach(device_t);
735 static int hdac_detach(device_t);
736 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
737 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
738 uint32_t, int, int);
739 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
740 nid_t, int, int);
741 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
742 nid_t, nid_t, int, int, int, int, int, int);
743 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
744 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
745
746 static int hdac_rirb_flush(struct hdac_softc *sc);
747 static int hdac_unsolq_flush(struct hdac_softc *sc);
748
749 #define hdac_command(a1, a2, a3) \
750 hdac_command_sendone_internal(a1, a2, a3)
751
752 #define hdac_codec_id(d) \
753 ((uint32_t)((d == NULL) ? 0x00000000 : \
754 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
755 ((uint32_t)(d)->device_id & 0x0000ffff))))
756
757 static char *
758 hdac_codec_name(struct hdac_devinfo *devinfo)
759 {
760 uint32_t id;
761 int i;
762
763 id = hdac_codec_id(devinfo);
764
765 for (i = 0; i < HDAC_CODECS_LEN; i++) {
766 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
767 return (hdac_codecs[i].name);
768 }
769
770 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
771 }
772
773 static char *
774 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
775 {
776 static char *ossname[] = SOUND_DEVICE_NAMES;
777 static char *unknown = "???";
778 int i;
779
780 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
781 if (devmask & (1 << i))
782 return (ossname[i]);
783 }
784 return (unknown);
785 }
786
787 static void
788 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
789 {
790 static char *ossname[] = SOUND_DEVICE_NAMES;
791 int i, first = 1;
792
793 bzero(buf, len);
794 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
795 if (mask & (1 << i)) {
796 if (first == 0)
797 strlcat(buf, ", ", len);
798 strlcat(buf, ossname[i], len);
799 first = 0;
800 }
801 }
802 }
803
804 static struct hdac_audio_ctl *
805 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
806 {
807 if (devinfo == NULL ||
808 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
809 index == NULL || devinfo->function.audio.ctl == NULL ||
810 devinfo->function.audio.ctlcnt < 1 ||
811 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
812 return (NULL);
813 return (&devinfo->function.audio.ctl[(*index)++]);
814 }
815
816 static struct hdac_audio_ctl *
817 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
818 int index, int cnt)
819 {
820 struct hdac_audio_ctl *ctl, *retctl = NULL;
821 int i, at, atindex, found = 0;
822
823 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
824 return (NULL);
825
826 at = cnt;
827 if (at == 0)
828 at = 1;
829 else if (at < 0)
830 at = -1;
831 atindex = index;
832 if (atindex < 0)
833 atindex = -1;
834
835 i = 0;
836 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
837 if (ctl->enable == 0 || ctl->widget == NULL)
838 continue;
839 if (!(ctl->widget->nid == nid && (atindex == -1 ||
840 ctl->index == atindex)))
841 continue;
842 found++;
843 if (found == cnt)
844 return (ctl);
845 retctl = ctl;
846 }
847
848 return ((at == -1) ? retctl : NULL);
849 }
850
851 static void
852 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
853 {
854 struct hdac_softc *sc;
855 struct hdac_widget *w;
856 struct hdac_audio_ctl *ctl;
857 uint32_t val, id, res;
858 int i = 0, j, timeout, forcemute;
859 nid_t cad;
860
861 if (devinfo == NULL || devinfo->codec == NULL ||
862 devinfo->codec->sc == NULL)
863 return;
864
865 sc = devinfo->codec->sc;
866 cad = devinfo->codec->cad;
867 id = hdac_codec_id(devinfo);
868 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
869 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
870 sc->pci_subvendor) &&
871 hdac_hp_switch[i].id == id)
872 break;
873 }
874
875 if (i >= HDAC_HP_SWITCH_LEN)
876 return;
877
878 forcemute = 0;
879 if (hdac_hp_switch[i].eapdnid != -1) {
880 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
881 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
882 forcemute = (w->param.eapdbtl &
883 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
884 }
885
886 if (hdac_hp_switch[i].execsense != -1)
887 hdac_command(sc,
888 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
889 hdac_hp_switch[i].execsense), cad);
890
891 timeout = 10000;
892 do {
893 res = hdac_command(sc,
894 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid),
895 cad);
896 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff)
897 break;
898 DELAY(10);
899 } while (--timeout != 0);
900
901 HDA_BOOTVERBOSE(
902 device_printf(sc->dev,
903 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n",
904 hdac_hp_switch[i].hpnid, timeout, res);
905 );
906
907 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
908 res ^= hdac_hp_switch[i].inverted;
909
910 switch (hdac_hp_switch[i].type) {
911 case HDAC_HP_SWITCH_CTL:
912 ctl = hdac_audio_ctl_amp_get(devinfo,
913 hdac_hp_switch[i].hpnid, 0, 1);
914 if (ctl != NULL) {
915 val = (res != 0 && forcemute == 0) ?
916 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
917 if (val != ctl->muted) {
918 ctl->muted = val;
919 hdac_audio_ctl_amp_set(ctl,
920 HDA_AMP_MUTE_DEFAULT, ctl->left,
921 ctl->right);
922 }
923 }
924 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
925 ctl = hdac_audio_ctl_amp_get(devinfo,
926 hdac_hp_switch[i].spkrnid[j], 0, 1);
927 if (ctl == NULL)
928 continue;
929 val = (res != 0 || forcemute == 1) ?
930 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
931 if (val == ctl->muted)
932 continue;
933 ctl->muted = val;
934 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
935 ctl->left, ctl->right);
936 }
937 break;
938 case HDAC_HP_SWITCH_CTRL:
939 if (res != 0) {
940 /* HP in */
941 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
942 if (w != NULL && w->type ==
943 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
944 if (forcemute == 0)
945 val = w->wclass.pin.ctrl |
946 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
947 else
948 val = w->wclass.pin.ctrl &
949 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
950 if (val != w->wclass.pin.ctrl) {
951 w->wclass.pin.ctrl = val;
952 hdac_command(sc,
953 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
954 w->nid, w->wclass.pin.ctrl), cad);
955 }
956 }
957 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
958 w = hdac_widget_get(devinfo,
959 hdac_hp_switch[i].spkrnid[j]);
960 if (w == NULL || w->type !=
961 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
962 continue;
963 val = w->wclass.pin.ctrl &
964 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
965 if (val == w->wclass.pin.ctrl)
966 continue;
967 w->wclass.pin.ctrl = val;
968 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
969 cad, w->nid, w->wclass.pin.ctrl), cad);
970 }
971 } else {
972 /* HP out */
973 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
974 if (w != NULL && w->type ==
975 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
976 val = w->wclass.pin.ctrl &
977 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
978 if (val != w->wclass.pin.ctrl) {
979 w->wclass.pin.ctrl = val;
980 hdac_command(sc,
981 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
982 w->nid, w->wclass.pin.ctrl), cad);
983 }
984 }
985 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
986 w = hdac_widget_get(devinfo,
987 hdac_hp_switch[i].spkrnid[j]);
988 if (w == NULL || w->type !=
989 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
990 continue;
991 if (forcemute == 0)
992 val = w->wclass.pin.ctrl |
993 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
994 else
995 val = w->wclass.pin.ctrl &
996 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
997 if (val == w->wclass.pin.ctrl)
998 continue;
999 w->wclass.pin.ctrl = val;
1000 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1001 cad, w->nid, w->wclass.pin.ctrl), cad);
1002 }
1003 }
1004 break;
1005 case HDAC_HP_SWITCH_DEBUG:
1006 if (hdac_hp_switch[i].execsense != -1)
1007 hdac_command(sc,
1008 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
1009 hdac_hp_switch[i].execsense), cad);
1010 res = hdac_command(sc,
1011 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
1012 device_printf(sc->dev,
1013 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1014 hdac_hp_switch[i].hpnid, res);
1015 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1016 w = hdac_widget_get(devinfo,
1017 hdac_hp_switch[i].spkrnid[j]);
1018 if (w == NULL || w->type !=
1019 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1020 continue;
1021 if (hdac_hp_switch[i].execsense != -1)
1022 hdac_command(sc,
1023 HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1024 hdac_hp_switch[i].execsense), cad);
1025 res = hdac_command(sc,
1026 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1027 device_printf(sc->dev,
1028 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1029 j + 1, w->nid, res);
1030 }
1031 break;
1032 default:
1033 break;
1034 }
1035 }
1036
1037 static void
1038 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1039 {
1040 struct hdac_softc *sc;
1041 struct hdac_devinfo *devinfo = NULL;
1042 device_t *devlist = NULL;
1043 int devcount, i;
1044
1045 if (codec == NULL || codec->sc == NULL)
1046 return;
1047
1048 sc = codec->sc;
1049
1050 HDA_BOOTVERBOSE(
1051 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1052 );
1053
1054 device_get_children(sc->dev, &devlist, &devcount);
1055 for (i = 0; devlist != NULL && i < devcount; i++) {
1056 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1057 if (devinfo != NULL && devinfo->node_type ==
1058 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1059 devinfo->codec != NULL &&
1060 devinfo->codec->cad == codec->cad) {
1061 break;
1062 } else
1063 devinfo = NULL;
1064 }
1065 if (devlist != NULL)
1066 kfree(devlist, M_TEMP);
1067
1068 if (devinfo == NULL)
1069 return;
1070
1071 switch (tag) {
1072 case HDAC_UNSOLTAG_EVENT_HP:
1073 hdac_hp_switch_handler(devinfo);
1074 break;
1075 case HDAC_UNSOLTAG_EVENT_TEST:
1076 device_printf(sc->dev, "Unsol Test!\n");
1077 break;
1078 default:
1079 break;
1080 }
1081 }
1082
1083 static int
1084 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1085 {
1086 /* XXX to be removed */
1087 #ifdef HDAC_INTR_EXTRA
1088 uint32_t res;
1089 #endif
1090
1091 if (ch->blkcnt == 0)
1092 return (0);
1093
1094 /* XXX to be removed */
1095 #ifdef HDAC_INTR_EXTRA
1096 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1097 #endif
1098
1099 /* XXX to be removed */
1100 #ifdef HDAC_INTR_EXTRA
1101 HDA_BOOTVERBOSE(
1102 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1103 device_printf(sc->dev,
1104 "PCMDIR_%s intr triggered beyond stream boundary:"
1105 "%08x\n",
1106 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1107 );
1108 #endif
1109
1110 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1111 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1112
1113 /* XXX to be removed */
1114 #ifdef HDAC_INTR_EXTRA
1115 if (res & HDAC_SDSTS_BCIS) {
1116 #endif
1117 return (1);
1118 /* XXX to be removed */
1119 #ifdef HDAC_INTR_EXTRA
1120 }
1121 #endif
1122
1123 return (0);
1124 }
1125
1126 /****************************************************************************
1127 * void hdac_intr_handler(void *)
1128 *
1129 * Interrupt handler. Processes interrupts received from the hdac.
1130 ****************************************************************************/
1131 static void
1132 hdac_intr_handler(void *context)
1133 {
1134 struct hdac_softc *sc;
1135 uint32_t intsts;
1136 uint8_t rirbsts;
1137 struct hdac_rirb *rirb_base;
1138 uint32_t trigger;
1139
1140 sc = (struct hdac_softc *)context;
1141
1142 hdac_lock(sc);
1143 if (sc->polling != 0) {
1144 hdac_unlock(sc);
1145 return;
1146 }
1147
1148 /* Do we have anything to do? */
1149 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1150 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1151 hdac_unlock(sc);
1152 return;
1153 }
1154
1155 trigger = 0;
1156
1157 /* Was this a controller interrupt? */
1158 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1159 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1160 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1161 /* Get as many responses that we can */
1162 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1163 HDAC_WRITE_1(&sc->mem,
1164 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1165 if (hdac_rirb_flush(sc) != 0)
1166 trigger |= HDAC_TRIGGER_UNSOL;
1167 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1168 }
1169 /* XXX to be removed */
1170 /* Clear interrupt and exit */
1171 #ifdef HDAC_INTR_EXTRA
1172 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1173 #endif
1174 }
1175
1176 if (intsts & HDAC_INTSTS_SIS_MASK) {
1177 if ((intsts & (1 << sc->num_iss)) &&
1178 hdac_stream_intr(sc, &sc->play) != 0)
1179 trigger |= HDAC_TRIGGER_PLAY;
1180 if ((intsts & (1 << 0)) &&
1181 hdac_stream_intr(sc, &sc->rec) != 0)
1182 trigger |= HDAC_TRIGGER_REC;
1183 /* XXX to be removed */
1184 #ifdef HDAC_INTR_EXTRA
1185 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1186 HDAC_INTSTS_SIS_MASK);
1187 #endif
1188 }
1189
1190 hdac_unlock(sc);
1191
1192 if (trigger & HDAC_TRIGGER_PLAY)
1193 chn_intr(sc->play.c);
1194 if (trigger & HDAC_TRIGGER_REC)
1195 chn_intr(sc->rec.c);
1196 if (trigger & HDAC_TRIGGER_UNSOL)
1197 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task);
1198 }
1199
1200 /****************************************************************************
1201 * int hdac_reset(hdac_softc *)
1202 *
1203 * Reset the hdac to a quiescent and known state.
1204 ****************************************************************************/
1205 static int
1206 hdac_reset(struct hdac_softc *sc)
1207 {
1208 uint32_t gctl;
1209 int count, i;
1210
1211 /*
1212 * Stop all Streams DMA engine
1213 */
1214 for (i = 0; i < sc->num_iss; i++)
1215 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1216 for (i = 0; i < sc->num_oss; i++)
1217 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1218 for (i = 0; i < sc->num_bss; i++)
1219 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1220
1221 /*
1222 * Stop Control DMA engines.
1223 */
1224 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1225 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1226
1227 /*
1228 * Reset DMA position buffer.
1229 */
1230 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1231 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1232
1233 /*
1234 * Reset the controller. The reset must remain asserted for
1235 * a minimum of 100us.
1236 */
1237 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1238 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1239 count = 10000;
1240 do {
1241 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1242 if (!(gctl & HDAC_GCTL_CRST))
1243 break;
1244 DELAY(10);
1245 } while (--count);
1246 if (gctl & HDAC_GCTL_CRST) {
1247 device_printf(sc->dev, "Unable to put hdac in reset\n");
1248 return (ENXIO);
1249 }
1250 DELAY(100);
1251 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1252 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1253 count = 10000;
1254 do {
1255 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1256 if (gctl & HDAC_GCTL_CRST)
1257 break;
1258 DELAY(10);
1259 } while (--count);
1260 if (!(gctl & HDAC_GCTL_CRST)) {
1261 device_printf(sc->dev, "Device stuck in reset\n");
1262 return (ENXIO);
1263 }
1264
1265 /*
1266 * Wait for codecs to finish their own reset sequence. The delay here
1267 * should be of 250us but for some reasons, on it's not enough on my
1268 * computer. Let's use twice as much as necessary to make sure that
1269 * it's reset properly.
1270 */
1271 DELAY(1000);
1272
1273 return (0);
1274 }
1275
1276
1277 /****************************************************************************
1278 * int hdac_get_capabilities(struct hdac_softc *);
1279 *
1280 * Retreive the general capabilities of the hdac;
1281 * Number of Input Streams
1282 * Number of Output Streams
1283 * Number of bidirectional Streams
1284 * 64bit ready
1285 * CORB and RIRB sizes
1286 ****************************************************************************/
1287 static int
1288 hdac_get_capabilities(struct hdac_softc *sc)
1289 {
1290 uint16_t gcap;
1291 uint8_t corbsize, rirbsize;
1292
1293 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1294 sc->num_iss = HDAC_GCAP_ISS(gcap);
1295 sc->num_oss = HDAC_GCAP_OSS(gcap);
1296 sc->num_bss = HDAC_GCAP_BSS(gcap);
1297
1298 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1299
1300 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1301 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1302 HDAC_CORBSIZE_CORBSZCAP_256)
1303 sc->corb_size = 256;
1304 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1305 HDAC_CORBSIZE_CORBSZCAP_16)
1306 sc->corb_size = 16;
1307 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1308 HDAC_CORBSIZE_CORBSZCAP_2)
1309 sc->corb_size = 2;
1310 else {
1311 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1312 __func__, corbsize);
1313 return (ENXIO);
1314 }
1315
1316 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1317 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1318 HDAC_RIRBSIZE_RIRBSZCAP_256)
1319 sc->rirb_size = 256;
1320 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1321 HDAC_RIRBSIZE_RIRBSZCAP_16)
1322 sc->rirb_size = 16;
1323 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1324 HDAC_RIRBSIZE_RIRBSZCAP_2)
1325 sc->rirb_size = 2;
1326 else {
1327 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1328 __func__, rirbsize);
1329 return (ENXIO);
1330 }
1331
1332 return (0);
1333 }
1334
1335
1336 /****************************************************************************
1337 * void hdac_dma_cb
1338 *
1339 * This function is called by bus_dmamap_load when the mapping has been
1340 * established. We just record the physical address of the mapping into
1341 * the struct hdac_dma passed in.
1342 ****************************************************************************/
1343 static void
1344 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1345 {
1346 struct hdac_dma *dma;
1347
1348 if (error == 0) {
1349 dma = (struct hdac_dma *)callback_arg;
1350 dma->dma_paddr = segs[0].ds_addr;
1351 }
1352 }
1353
1354
1355 /****************************************************************************
1356 * int hdac_dma_alloc
1357 *
1358 * This function allocate and setup a dma region (struct hdac_dma).
1359 * It must be freed by a corresponding hdac_dma_free.
1360 ****************************************************************************/
1361 static int
1362 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1363 {
1364 bus_size_t roundsz;
1365 int result;
1366 int lowaddr;
1367
1368 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1369 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1370 BUS_SPACE_MAXADDR_32BIT;
1371 bzero(dma, sizeof(*dma));
1372
1373 /*
1374 * Create a DMA tag
1375 */
1376 result = bus_dma_tag_create(NULL, /* parent */
1377 HDAC_DMA_ALIGNMENT, /* alignment */
1378 0, /* boundary */
1379 lowaddr, /* lowaddr */
1380 BUS_SPACE_MAXADDR, /* highaddr */
1381 NULL, /* filtfunc */
1382 NULL, /* fistfuncarg */
1383 roundsz, /* maxsize */
1384 1, /* nsegments */
1385 roundsz, /* maxsegsz */
1386 0, /* flags */
1387 &dma->dma_tag); /* dmat */
1388 if (result != 0) {
1389 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1390 __func__, result);
1391 goto hdac_dma_alloc_fail;
1392 }
1393
1394 /*
1395 * Allocate DMA memory
1396 */
1397 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1398 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1399 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1400 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map);
1401 #else
1402 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1403 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1404 #endif
1405 if (result != 0) {
1406 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1407 __func__, result);
1408 goto hdac_dma_alloc_fail;
1409 }
1410
1411 dma->dma_size = roundsz;
1412
1413 /*
1414 * Map the memory
1415 */
1416 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1417 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1418 if (result != 0 || dma->dma_paddr == 0) {
1419 if (result == 0)
1420 result = ENOMEM;
1421 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1422 __func__, result);
1423 goto hdac_dma_alloc_fail;
1424 }
1425
1426 HDA_BOOTVERBOSE(
1427 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1428 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1429 );
1430
1431 return (0);
1432
1433 hdac_dma_alloc_fail:
1434 hdac_dma_free(sc, dma);
1435
1436 return (result);
1437 }
1438
1439
1440 /****************************************************************************
1441 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1442 *
1443 * Free a struct dhac_dma that has been previously allocated via the
1444 * hdac_dma_alloc function.
1445 ****************************************************************************/
1446 static void
1447 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1448 {
1449 if (dma->dma_map != NULL) {
1450 #if 0
1451 /* Flush caches */
1452 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1453 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1454 #endif
1455 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1456 }
1457 if (dma->dma_vaddr != NULL) {
1458 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1459 dma->dma_vaddr = NULL;
1460 }
1461 dma->dma_map = NULL;
1462 if (dma->dma_tag != NULL) {
1463 bus_dma_tag_destroy(dma->dma_tag);
1464 dma->dma_tag = NULL;
1465 }
1466 dma->dma_size = 0;
1467 }
1468
1469 /****************************************************************************
1470 * int hdac_mem_alloc(struct hdac_softc *)
1471 *
1472 * Allocate all the bus resources necessary to speak with the physical
1473 * controller.
1474 ****************************************************************************/
1475 static int
1476 hdac_mem_alloc(struct hdac_softc *sc)
1477 {
1478 struct hdac_mem *mem;
1479
1480 mem = &sc->mem;
1481 mem->mem_rid = PCIR_BAR(0);
1482 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1483 &mem->mem_rid, RF_ACTIVE);
1484 if (mem->mem_res == NULL) {
1485 device_printf(sc->dev,
1486 "%s: Unable to allocate memory resource\n", __func__);
1487 return (ENOMEM);
1488 }
1489 mem->mem_tag = rman_get_bustag(mem->mem_res);
1490 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1491
1492 return (0);
1493 }
1494
1495 /****************************************************************************
1496 * void hdac_mem_free(struct hdac_softc *)
1497 *
1498 * Free up resources previously allocated by hdac_mem_alloc.
1499 ****************************************************************************/
1500 static void
1501 hdac_mem_free(struct hdac_softc *sc)
1502 {
1503 struct hdac_mem *mem;
1504
1505 mem = &sc->mem;
1506 if (mem->mem_res != NULL)
1507 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1508 mem->mem_res);
1509 mem->mem_res = NULL;
1510 }
1511
1512 /****************************************************************************
1513 * int hdac_irq_alloc(struct hdac_softc *)
1514 *
1515 * Allocate and setup the resources necessary for interrupt handling.
1516 ****************************************************************************/
1517 static int
1518 hdac_irq_alloc(struct hdac_softc *sc)
1519 {
1520 struct hdac_irq *irq;
1521 int result;
1522
1523 irq = &sc->irq;
1524 irq->irq_rid = 0x0;
1525 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1526 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1527 if (irq->irq_res == NULL) {
1528 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1529 __func__);
1530 goto hdac_irq_alloc_fail;
1531 }
1532 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1533 hdac_intr_handler, sc, &irq->irq_handle);
1534 if (result != 0) {
1535 device_printf(sc->dev,
1536 "%s: Unable to setup interrupt handler (%x)\n",
1537 __func__, result);
1538 goto hdac_irq_alloc_fail;
1539 }
1540
1541 return (0);
1542
1543 hdac_irq_alloc_fail:
1544 hdac_irq_free(sc);
1545
1546 return (ENXIO);
1547 }
1548
1549 /****************************************************************************
1550 * void hdac_irq_free(struct hdac_softc *)
1551 *
1552 * Free up resources previously allocated by hdac_irq_alloc.
1553 ****************************************************************************/
1554 static void
1555 hdac_irq_free(struct hdac_softc *sc)
1556 {
1557 struct hdac_irq *irq;
1558
1559 irq = &sc->irq;
1560 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1561 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1562 if (irq->irq_res != NULL)
1563 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1564 irq->irq_res);
1565 irq->irq_handle = NULL;
1566 irq->irq_res = NULL;
1567 }
1568
1569 /****************************************************************************
1570 * void hdac_corb_init(struct hdac_softc *)
1571 *
1572 * Initialize the corb registers for operations but do not start it up yet.
1573 * The CORB engine must not be running when this function is called.
1574 ****************************************************************************/
1575 static void
1576 hdac_corb_init(struct hdac_softc *sc)
1577 {
1578 uint8_t corbsize;
1579 uint64_t corbpaddr;
1580
1581 /* Setup the CORB size. */
1582 switch (sc->corb_size) {
1583 case 256:
1584 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1585 break;
1586 case 16:
1587 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1588 break;
1589 case 2:
1590 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1591 break;
1592 default:
1593 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1594 }
1595 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1596
1597 /* Setup the CORB Address in the hdac */
1598 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1599 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1600 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1601
1602 /* Set the WP and RP */
1603 sc->corb_wp = 0;
1604 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1605 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1606 /*
1607 * The HDA specification indicates that the CORBRPRST bit will always
1608 * read as zero. Unfortunately, it seems that at least the 82801G
1609 * doesn't reset the bit to zero, which stalls the corb engine.
1610 * manually reset the bit to zero before continuing.
1611 */
1612 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1613
1614 /* Enable CORB error reporting */
1615 #if 0
1616 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1617 #endif
1618 }
1619
1620 /****************************************************************************
1621 * void hdac_rirb_init(struct hdac_softc *)
1622 *
1623 * Initialize the rirb registers for operations but do not start it up yet.
1624 * The RIRB engine must not be running when this function is called.
1625 ****************************************************************************/
1626 static void
1627 hdac_rirb_init(struct hdac_softc *sc)
1628 {
1629 uint8_t rirbsize;
1630 uint64_t rirbpaddr;
1631
1632 /* Setup the RIRB size. */
1633 switch (sc->rirb_size) {
1634 case 256:
1635 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1636 break;
1637 case 16:
1638 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1639 break;
1640 case 2:
1641 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1642 break;
1643 default:
1644 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1645 }
1646 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1647
1648 /* Setup the RIRB Address in the hdac */
1649 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1650 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1651 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1652
1653 /* Setup the WP and RP */
1654 sc->rirb_rp = 0;
1655 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1656
1657 if (sc->polling == 0) {
1658 /* Setup the interrupt threshold */
1659 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1660
1661 /* Enable Overrun and response received reporting */
1662 #if 0
1663 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1664 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1665 #else
1666 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1667 #endif
1668 }
1669
1670 #if 0
1671 /*
1672 * Make sure that the Host CPU cache doesn't contain any dirty
1673 * cache lines that falls in the rirb. If I understood correctly, it
1674 * should be sufficient to do this only once as the rirb is purely
1675 * read-only from now on.
1676 */
1677 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1678 BUS_DMASYNC_PREREAD);
1679 #endif
1680 }
1681
1682 /****************************************************************************
1683 * void hdac_corb_start(hdac_softc *)
1684 *
1685 * Startup the corb DMA engine
1686 ****************************************************************************/
1687 static void
1688 hdac_corb_start(struct hdac_softc *sc)
1689 {
1690 uint32_t corbctl;
1691
1692 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1693 corbctl |= HDAC_CORBCTL_CORBRUN;
1694 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1695 }
1696
1697 /****************************************************************************
1698 * void hdac_rirb_start(hdac_softc *)
1699 *
1700 * Startup the rirb DMA engine
1701 ****************************************************************************/
1702 static void
1703 hdac_rirb_start(struct hdac_softc *sc)
1704 {
1705 uint32_t rirbctl;
1706
1707 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1708 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1709 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1710 }
1711
1712
1713 /****************************************************************************
1714 * void hdac_scan_codecs(struct hdac_softc *)
1715 *
1716 * Scan the bus for available codecs.
1717 ****************************************************************************/
1718 static void
1719 hdac_scan_codecs(struct hdac_softc *sc)
1720 {
1721 struct hdac_codec *codec;
1722 int i;
1723 uint16_t statests;
1724
1725 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1726 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1727 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1728 /* We have found a codec. */
1729 codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1730 M_HDAC, M_ZERO | M_NOWAIT);
1731 if (codec == NULL) {
1732 device_printf(sc->dev,
1733 "Unable to allocate memory for codec\n");
1734 continue;
1735 }
1736 codec->commands = NULL;
1737 codec->responses_received = 0;
1738 codec->verbs_sent = 0;
1739 codec->sc = sc;
1740 codec->cad = i;
1741 sc->codecs[i] = codec;
1742 if (hdac_probe_codec(codec) != 0)
1743 break;
1744 }
1745 }
1746 /* All codecs have been probed, now try to attach drivers to them */
1747 /* bus_generic_attach(sc->dev); */
1748 }
1749
1750 /****************************************************************************
1751 * void hdac_probe_codec(struct hdac_softc *, int)
1752 *
1753 * Probe a the given codec_id for available function groups.
1754 ****************************************************************************/
1755 static int
1756 hdac_probe_codec(struct hdac_codec *codec)
1757 {
1758 struct hdac_softc *sc = codec->sc;
1759 struct hdac_devinfo *devinfo;
1760 uint32_t vendorid, revisionid, subnode;
1761 int startnode;
1762 int endnode;
1763 int i;
1764 nid_t cad = codec->cad;
1765
1766 HDA_BOOTVERBOSE(
1767 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1768 );
1769 vendorid = hdac_command(sc,
1770 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1771 cad);
1772 revisionid = hdac_command(sc,
1773 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1774 cad);
1775 subnode = hdac_command(sc,
1776 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1777 cad);
1778 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1779 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1780
1781 HDA_BOOTVERBOSE(
1782 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1783 startnode, endnode);
1784 );
1785 for (i = startnode; i < endnode; i++) {
1786 devinfo = hdac_probe_function(codec, i);
1787 if (devinfo != NULL) {
1788 /* XXX Ignore other FG. */
1789 devinfo->vendor_id =
1790 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1791 devinfo->device_id =
1792 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1793 devinfo->revision_id =
1794 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1795 devinfo->stepping_id =
1796 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1797 HDA_BOOTVERBOSE(
1798 device_printf(sc->dev,
1799 "HDA_DEBUG: \tFound AFG nid=%d "
1800 "[startnode=%d endnode=%d]\n",
1801 devinfo->nid, startnode, endnode);
1802 );
1803 return (1);
1804 }
1805 }
1806
1807 HDA_BOOTVERBOSE(
1808 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1809 );
1810 return (0);
1811 }
1812
1813 static struct hdac_devinfo *
1814 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1815 {
1816 struct hdac_softc *sc = codec->sc;
1817 struct hdac_devinfo *devinfo;
1818 uint32_t fctgrptype;
1819 nid_t cad = codec->cad;
1820
1821 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1822 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1823
1824 /* XXX For now, ignore other FG. */
1825 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1826 return (NULL);
1827
1828 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1829 M_NOWAIT | M_ZERO);
1830 if (devinfo == NULL) {
1831 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1832 __func__);
1833 return (NULL);
1834 }
1835
1836 devinfo->nid = nid;
1837 devinfo->node_type = fctgrptype;
1838 devinfo->codec = codec;
1839
1840 hdac_add_child(sc, devinfo);
1841
1842 return (devinfo);
1843 }
1844
1845 static void
1846 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1847 {
1848 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1849 device_set_ivars(devinfo->dev, (void *)devinfo);
1850 /* XXX - Print more information when booting verbose??? */
1851 }
1852
1853 static void
1854 hdac_widget_connection_parse(struct hdac_widget *w)
1855 {
1856 struct hdac_softc *sc = w->devinfo->codec->sc;
1857 uint32_t res;
1858 int i, j, max, ents, entnum;
1859 nid_t cad = w->devinfo->codec->cad;
1860 nid_t nid = w->nid;
1861 nid_t cnid, addcnid, prevcnid;
1862
1863 w->nconns = 0;
1864
1865 res = hdac_command(sc,
1866 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1867
1868 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1869
1870 if (ents < 1)
1871 return;
1872
1873 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1874 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1875 prevcnid = 0;
1876
1877 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
1878 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
1879 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
1880 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1881 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1882
1883 for (i = 0; i < ents; i += entnum) {
1884 res = hdac_command(sc,
1885 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1886 for (j = 0; j < entnum; j++) {
1887 cnid = CONN_CNID(res, entnum, j);
1888 if (cnid == 0) {
1889 if (w->nconns < ents)
1890 device_printf(sc->dev,
1891 "%s: nid=%d WARNING: zero cnid "
1892 "entnum=%d j=%d index=%d "
1893 "entries=%d found=%d res=0x%08x\n",
1894 __func__, nid, entnum, j, i,
1895 ents, w->nconns, res);
1896 else
1897 goto getconns_out;
1898 }
1899 if (cnid < w->devinfo->startnode ||
1900 cnid >= w->devinfo->endnode) {
1901 HDA_BOOTVERBOSE(
1902 device_printf(sc->dev,
1903 "%s: GHOST: nid=%d j=%d "
1904 "entnum=%d index=%d res=0x%08x\n",
1905 __func__, nid, j, entnum, i, res);
1906 );
1907 }
1908 if (CONN_RANGE(res, entnum, j) == 0)
1909 addcnid = cnid;
1910 else if (prevcnid == 0 || prevcnid >= cnid) {
1911 device_printf(sc->dev,
1912 "%s: WARNING: Invalid child range "
1913 "nid=%d index=%d j=%d entnum=%d "
1914 "prevcnid=%d cnid=%d res=0x%08x\n",
1915 __func__, nid, i, j, entnum, prevcnid,
1916 cnid, res);
1917 addcnid = cnid;
1918 } else
1919 addcnid = prevcnid + 1;
1920 while (addcnid <= cnid) {
1921 if (w->nconns > max) {
1922 device_printf(sc->dev,
1923 "%s: nid=%d: Adding %d: "
1924 "Max connection reached! max=%d\n",
1925 __func__, nid, addcnid, max + 1);
1926 goto getconns_out;
1927 }
1928 w->conns[w->nconns++] = addcnid++;
1929 }
1930 prevcnid = cnid;
1931 }
1932 }
1933
1934 getconns_out:
1935 HDA_BOOTVERBOSE(
1936 device_printf(sc->dev,
1937 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
1938 __func__, nid, ents, w->nconns);
1939 );
1940 return;
1941 }
1942
1943 static uint32_t
1944 hdac_widget_pin_getconfig(struct hdac_widget *w)
1945 {
1946 struct hdac_softc *sc;
1947 uint32_t config, orig, id;
1948 nid_t cad, nid;
1949
1950 sc = w->devinfo->codec->sc;
1951 cad = w->devinfo->codec->cad;
1952 nid = w->nid;
1953 id = hdac_codec_id(w->devinfo);
1954
1955 config = hdac_command(sc,
1956 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
1957 cad);
1958 orig = config;
1959
1960 /*
1961 * XXX REWRITE!!!! Don't argue!
1962 */
1963 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
1964 switch (nid) {
1965 case 26:
1966 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1967 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1968 break;
1969 case 27:
1970 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1971 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
1972 break;
1973 default:
1974 break;
1975 }
1976 } else if (id == HDA_CODEC_ALC880 &&
1977 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
1978 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
1979 /*
1980 * Super broken BIOS
1981 */
1982 switch (nid) {
1983 case 20:
1984 break;
1985 case 21:
1986 break;
1987 case 22:
1988 break;
1989 case 23:
1990 break;
1991 case 24: /* MIC1 */
1992 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1993 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1994 break;
1995 case 25: /* XXX MIC2 */
1996 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1997 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1998 break;
1999 case 26: /* LINE1 */
2000 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2001 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2002 break;
2003 case 27: /* XXX LINE2 */
2004 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2005 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2006 break;
2007 case 28: /* CD */
2008 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2009 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2010 break;
2011 case 30:
2012 break;
2013 case 31:
2014 break;
2015 default:
2016 break;
2017 }
2018 } else if (id == HDA_CODEC_ALC883 &&
2019 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) {
2020 switch (nid) {
2021 case 25:
2022 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2023 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2024 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2025 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2026 break;
2027 case 28:
2028 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2029 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2030 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2031 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2032 break;
2033 default:
2034 break;
2035 }
2036 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2037 HP_V3000_SUBVENDOR) {
2038 switch (nid) {
2039 case 18:
2040 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2041 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2042 break;
2043 case 20:
2044 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2045 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2046 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2047 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2048 break;
2049 case 21:
2050 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2051 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2052 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2053 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2054 break;
2055 default:
2056 break;
2057 }
2058 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2059 HP_DV5000_SUBVENDOR) {
2060 switch (nid) {
2061 case 20:
2062 case 21:
2063 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2064 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2065 break;
2066 default:
2067 break;
2068 }
2069 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2070 ASUS_W6F_SUBVENDOR) {
2071 switch (nid) {
2072 case 11:
2073 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2074 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2075 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2076 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2077 break;
2078 case 15:
2079 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2080 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2081 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2082 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2083 break;
2084 default:
2085 break;
2086 }
2087 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2088 UNIWILL_9075_SUBVENDOR) {
2089 switch (nid) {
2090 case 15:
2091 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2092 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2093 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2094 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2095 break;
2096 default:
2097 break;
2098 }
2099 } else if (id == HDA_CODEC_AD1986A &&
2100 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2101 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) {
2102 switch (nid) {
2103 case 28: /* LINE */
2104 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2105 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2106 break;
2107 case 29: /* MIC */
2108 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2109 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2110 break;
2111 default:
2112 break;
2113 }
2114 }
2115
2116 HDA_BOOTVERBOSE(
2117 if (config != orig)
2118 device_printf(sc->dev,
2119 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2120 nid, orig, config);
2121 );
2122
2123 return (config);
2124 }
2125
2126 static uint32_t
2127 hdac_widget_pin_getcaps(struct hdac_widget *w)
2128 {
2129 struct hdac_softc *sc;
2130 uint32_t caps, orig, id;
2131 nid_t cad, nid;
2132
2133 sc = w->devinfo->codec->sc;
2134 cad = w->devinfo->codec->cad;
2135 nid = w->nid;
2136 id = hdac_codec_id(w->devinfo);
2137
2138 caps = hdac_command(sc,
2139 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2140 orig = caps;
2141
2142 HDA_BOOTVERBOSE(
2143 if (caps != orig)
2144 device_printf(sc->dev,
2145 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2146 nid, orig, caps);
2147 );
2148
2149 return (caps);
2150 }
2151
2152 static void
2153 hdac_widget_pin_parse(struct hdac_widget *w)
2154 {
2155 struct hdac_softc *sc = w->devinfo->codec->sc;
2156 uint32_t config, pincap;
2157 char *devstr, *connstr;
2158 nid_t cad = w->devinfo->codec->cad;
2159 nid_t nid = w->nid;
2160
2161 config = hdac_widget_pin_getconfig(w);
2162 w->wclass.pin.config = config;
2163
2164 pincap = hdac_widget_pin_getcaps(w);
2165 w->wclass.pin.cap = pincap;
2166
2167 w->wclass.pin.ctrl = hdac_command(sc,
2168 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2169 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2170 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2171 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2172 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2173
2174 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2175 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2176 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2177 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2178 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2179 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2180 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2181 w->param.eapdbtl = hdac_command(sc,
2182 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2183 w->param.eapdbtl &= 0x7;
2184 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2185 } else
2186 w->param.eapdbtl = HDAC_INVALID;
2187
2188 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2189 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2190 devstr = "line out";
2191 break;
2192 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2193 devstr = "speaker";
2194 break;
2195 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2196 devstr = "headphones out";
2197 break;
2198 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2199 devstr = "CD";
2200 break;
2201 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2202 devstr = "SPDIF out";
2203 break;
2204 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2205 devstr = "digital (other) out";
2206 break;
2207 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2208 devstr = "modem, line side";
2209 break;
2210 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2211 devstr = "modem, handset side";
2212 break;
2213 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2214 devstr = "line in";
2215 break;
2216 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2217 devstr = "AUX";
2218 break;
2219 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2220 devstr = "Mic in";
2221 break;
2222 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2223 devstr = "telephony";
2224 break;
2225 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2226 devstr = "SPDIF in";
2227 break;
2228 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2229 devstr = "digital (other) in";
2230 break;
2231 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2232 devstr = "other";
2233 break;
2234 default:
2235 devstr = "unknown";
2236 break;
2237 }
2238
2239 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2240 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2241 connstr = "jack";
2242 break;
2243 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2244 connstr = "none";
2245 break;
2246 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2247 connstr = "fixed";
2248 break;
2249 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2250 connstr = "jack / fixed";
2251 break;
2252 default:
2253 connstr = "unknown";
2254 break;
2255 }
2256
2257 strlcat(w->name, ": ", sizeof(w->name));
2258 strlcat(w->name, devstr, sizeof(w->name));
2259 strlcat(w->name, " (", sizeof(w->name));
2260 strlcat(w->name, connstr, sizeof(w->name));
2261 strlcat(w->name, ")", sizeof(w->name));
2262 }
2263
2264 static void
2265 hdac_widget_parse(struct hdac_widget *w)
2266 {
2267 struct hdac_softc *sc = w->devinfo->codec->sc;
2268 uint32_t wcap, cap;
2269 char *typestr;
2270 nid_t cad = w->devinfo->codec->cad;
2271 nid_t nid = w->nid;
2272
2273 wcap = hdac_command(sc,
2274 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2275 cad);
2276 w->param.widget_cap = wcap;
2277 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2278
2279 switch (w->type) {
2280 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2281 typestr = "audio output";
2282 break;
2283 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2284 typestr = "audio input";
2285 break;
2286 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2287 typestr = "audio mixer";
2288 break;
2289 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2290 typestr = "audio selector";
2291 break;
2292 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2293 typestr = "pin";
2294 break;
2295 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2296 typestr = "power widget";
2297 break;
2298 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2299 typestr = "volume widget";
2300 break;
2301 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2302 typestr = "beep widget";
2303 break;
2304 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2305 typestr = "vendor widget";
2306 break;
2307 default:
2308 typestr = "unknown type";
2309 break;
2310 }
2311
2312 strlcpy(w->name, typestr, sizeof(w->name));
2313
2314 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2315 hdac_command(sc,
2316 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2317 cad);
2318 DELAY(1000);
2319 }
2320
2321 hdac_widget_connection_parse(w);
2322
2323 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2324 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2325 w->param.outamp_cap =
2326 hdac_command(sc,
2327 HDA_CMD_GET_PARAMETER(cad, nid,
2328 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2329 else
2330 w->param.outamp_cap =
2331 w->devinfo->function.audio.outamp_cap;
2332 } else
2333 w->param.outamp_cap = 0;
2334
2335 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2336 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2337 w->param.inamp_cap =
2338 hdac_command(sc,
2339 HDA_CMD_GET_PARAMETER(cad, nid,
2340 HDA_PARAM_INPUT_AMP_CAP), cad);
2341 else
2342 w->param.inamp_cap =
2343 w->devinfo->function.audio.inamp_cap;
2344 } else
2345 w->param.inamp_cap = 0;
2346
2347 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2348 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2349 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2350 cap = hdac_command(sc,
2351 HDA_CMD_GET_PARAMETER(cad, nid,
2352 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2353 w->param.supp_stream_formats = (cap != 0) ? cap :
2354 w->devinfo->function.audio.supp_stream_formats;
2355 cap = hdac_command(sc,
2356 HDA_CMD_GET_PARAMETER(cad, nid,
2357 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2358 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2359 w->devinfo->function.audio.supp_pcm_size_rate;
2360 } else {
2361 w->param.supp_stream_formats =
2362 w->devinfo->function.audio.supp_stream_formats;
2363 w->param.supp_pcm_size_rate =
2364 w->devinfo->function.audio.supp_pcm_size_rate;
2365 }
2366 } else {
2367 w->param.supp_stream_formats = 0;
2368 w->param.supp_pcm_size_rate = 0;
2369 }
2370
2371 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2372 hdac_widget_pin_parse(w);
2373 }
2374
2375 static struct hdac_widget *
2376 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2377 {
2378 if (devinfo == NULL || devinfo->widget == NULL ||
2379 nid < devinfo->startnode || nid >= devinfo->endnode)
2380 return (NULL);
2381 return (&devinfo->widget[nid - devinfo->startnode]);
2382 }
2383
2384 static __inline int
2385 hda_poll_channel(struct hdac_chan *ch)
2386 {
2387 uint32_t sz, delta;
2388 volatile uint32_t ptr;
2389
2390 if (ch->active == 0)
2391 return (0);
2392
2393 sz = ch->blksz * ch->blkcnt;
2394 if (ch->dmapos != NULL)
2395 ptr = *(ch->dmapos);
2396 else
2397 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2398 ch->off + HDAC_SDLPIB);
2399 ch->ptr = ptr;
2400 ptr %= sz;
2401 ptr &= ~(ch->blksz - 1);
2402 delta = (sz + ptr - ch->prevptr) % sz;
2403
2404 if (delta < ch->blksz)
2405 return (0);
2406
2407 ch->prevptr = ptr;
2408
2409 return (1);
2410 }
2411
2412 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active)
2413
2414 static void
2415 hda_poll_callback(void *arg)
2416 {
2417 struct hdac_softc *sc = arg;
2418 uint32_t trigger;
2419
2420 if (sc == NULL)
2421 return;
2422
2423 hdac_lock(sc);
2424 if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2425 hdac_unlock(sc);
2426 return;
2427 }
2428
2429 trigger = 0;
2430 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0;
2431 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0;
2432
2433 /* XXX */
2434 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2435 hda_poll_callback, sc);
2436
2437 hdac_unlock(sc);
2438
2439 if (trigger & HDAC_TRIGGER_PLAY)
2440 chn_intr(sc->play.c);
2441 if (trigger & HDAC_TRIGGER_REC)
2442 chn_intr(sc->rec.c);
2443 }
2444
2445 static int
2446 hdac_rirb_flush(struct hdac_softc *sc)
2447 {
2448 struct hdac_rirb *rirb_base, *rirb;
2449 struct hdac_codec *codec;
2450 struct hdac_command_list *commands;
2451 nid_t cad;
2452 uint32_t resp;
2453 uint8_t rirbwp;
2454 int ret;
2455
2456 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2457 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2458 #if 0
2459 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2460 BUS_DMASYNC_POSTREAD);
2461 #endif
2462 ret = 0;
2463
2464 while (sc->rirb_rp != rirbwp) {
2465 sc->rirb_rp++;
2466 sc->rirb_rp %= sc->rirb_size;
2467 rirb = &rirb_base[sc->rirb_rp];
2468 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2469 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2470 sc->codecs[cad] == NULL)
2471 continue;
2472 resp = rirb->response;
2473 codec = sc->codecs[cad];
2474 commands = codec->commands;
2475 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2476 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2477 ((resp >> 26) & 0xffff);
2478 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2479 } else if (commands != NULL && commands->num_commands > 0 &&
2480 codec->responses_received < commands->num_commands)
2481 commands->responses[codec->responses_received++] =
2482 resp;
2483 ret++;
2484 }
2485
2486 return (ret);
2487 }
2488
2489 static int
2490 hdac_unsolq_flush(struct hdac_softc *sc)
2491 {
2492 nid_t cad;
2493 uint32_t tag;
2494 int ret = 0;
2495
2496 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2497 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2498 while (sc->unsolq_rp != sc->unsolq_wp) {
2499 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2500 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2501 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2502 hdac_unsolicited_handler(sc->codecs[cad], tag);
2503 ret++;
2504 }
2505 sc->unsolq_st = HDAC_UNSOLQ_READY;
2506 }
2507
2508 return (ret);
2509 }
2510
2511 static void
2512 hdac_poll_callback(void *arg)
2513 {
2514 struct hdac_softc *sc = arg;
2515 if (sc == NULL)
2516 return;
2517
2518 hdac_lock(sc);
2519 if (sc->polling == 0 || sc->poll_ival == 0) {
2520 hdac_unlock(sc);
2521 return;
2522 }
2523 if (hdac_rirb_flush(sc) != 0)
2524 hdac_unsolq_flush(sc);
2525 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2526 hdac_unlock(sc);
2527 }
2528
2529 static void
2530 hdac_stream_stop(struct hdac_chan *ch)
2531 {
2532 struct hdac_softc *sc = ch->devinfo->codec->sc;
2533 uint32_t ctl;
2534
2535 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2536 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2537 HDAC_SDCTL_RUN);
2538 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2539
2540 ch->active = 0;
2541
2542 if (sc->polling != 0) {
2543 int pollticks;
2544
2545 if (hda_chan_active(sc) == 0) {
2546 callout_stop(&sc->poll_hda);
2547 sc->poll_ticks = 1;
2548 } else {
2549 if (sc->play.active != 0)
2550 ch = &sc->play;
2551 else
2552 ch = &sc->rec;
2553 pollticks = ((uint64_t)hz * ch->blksz) /
2554 ((uint64_t)sndbuf_getbps(ch->b) *
2555 sndbuf_getspd(ch->b));
2556 pollticks >>= 2;
2557 if (pollticks > hz)
2558 pollticks = hz;
2559 if (pollticks < 1) {
2560 HDA_BOOTVERBOSE(
2561 device_printf(sc->dev,
2562 "%s: pollticks=%d < 1 !\n",
2563 __func__, pollticks);
2564 );
2565 pollticks = 1;
2566 }
2567 if (pollticks > sc->poll_ticks) {
2568 HDA_BOOTVERBOSE(
2569 device_printf(sc->dev,
2570 "%s: pollticks %d -> %d\n",
2571 __func__, sc->poll_ticks,
2572 pollticks);
2573 );
2574 sc->poll_ticks = pollticks;
2575 callout_reset(&sc->poll_hda, 1,
2576 hda_poll_callback, sc);
2577 }
2578 }
2579 } else {
2580 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2581 ctl &= ~(1 << (ch->off >> 5));
2582 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2583 }
2584 }
2585
2586 static void
2587 hdac_stream_start(struct hdac_chan *ch)
2588 {
2589 struct hdac_softc *sc = ch->devinfo->codec->sc;
2590 uint32_t ctl;
2591
2592 if (sc->polling != 0) {
2593 int pollticks;
2594
2595 pollticks = ((uint64_t)hz * ch->blksz) /
2596 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2597 pollticks >>= 2;
2598 if (pollticks > hz)
2599 pollticks = hz;
2600 if (pollticks < 1) {
2601 HDA_BOOTVERBOSE(
2602 device_printf(sc->dev,
2603 "%s: pollticks=%d < 1 !\n",
2604 __func__, pollticks);
2605 );
2606 pollticks = 1;
2607 }
2608 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2609 HDA_BOOTVERBOSE(
2610 if (hda_chan_active(sc) == 0) {
2611 device_printf(sc->dev,
2612 "%s: pollticks=%d\n",
2613 __func__, pollticks);
2614 } else {
2615 device_printf(sc->dev,
2616 "%s: pollticks %d -> %d\n",
2617 __func__, sc->poll_ticks,
2618 pollticks);
2619 }
2620 );
2621 sc->poll_ticks = pollticks;
2622 callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2623 sc);
2624 }
2625 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2626 ctl |= HDAC_SDCTL_RUN;
2627 } else {
2628 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2629 ctl |= 1 << (ch->off >> 5);
2630 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2631 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2632 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2633 HDAC_SDCTL_RUN;
2634 }
2635 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2636
2637 ch->active = 1;
2638 }
2639
2640 static void
2641 hdac_stream_reset(struct hdac_chan *ch)
2642 {
2643 struct hdac_softc *sc = ch->devinfo->codec->sc;
2644 int timeout = 1000;
2645 int to = timeout;
2646 uint32_t ctl;
2647
2648 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2649 ctl |= HDAC_SDCTL_SRST;
2650 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2651 do {
2652 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2653 if (ctl & HDAC_SDCTL_SRST)
2654 break;
2655 DELAY(10);
2656 } while (--to);
2657 if (!(ctl & HDAC_SDCTL_SRST)) {
2658 device_printf(sc->dev, "timeout in reset\n");
2659 }
2660 ctl &= ~HDAC_SDCTL_SRST;
2661 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2662 to = timeout;
2663 do {
2664 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2665 if (!(ctl & HDAC_SDCTL_SRST))
2666 break;
2667 DELAY(10);
2668 } while (--to);
2669 if (ctl & HDAC_SDCTL_SRST)
2670 device_printf(sc->dev, "can't reset!\n");
2671 }
2672
2673 static void
2674 hdac_stream_setid(struct hdac_chan *ch)
2675 {
2676 struct hdac_softc *sc = ch->devinfo->codec->sc;
2677 uint32_t ctl;
2678
2679 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2680 ctl &= ~HDAC_SDCTL2_STRM_MASK;
2681 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2682 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2683 }
2684
2685 static void
2686 hdac_bdl_setup(struct hdac_chan *ch)
2687 {
2688 struct hdac_softc *sc = ch->devinfo->codec->sc;
2689 struct hdac_bdle *bdle;
2690 uint64_t addr;
2691 uint32_t blksz, blkcnt;
2692 int i;
2693
2694 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2695 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2696
2697 if (sc->polling != 0) {
2698 blksz = ch->blksz * ch->blkcnt;
2699 blkcnt = 1;
2700 } else {
2701 blksz = ch->blksz;
2702 blkcnt = ch->blkcnt;
2703 }
2704
2705 for (i = 0; i < blkcnt; i++, bdle++) {
2706 bdle->addrl = (uint32_t)addr;
2707 bdle->addrh = (uint32_t)(addr >> 32);
2708 bdle->len = blksz;
2709 bdle->ioc = 1 ^ sc->polling;
2710 addr += blksz;
2711 }
2712
2713 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2714 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2715 addr = ch->bdl_dma.dma_paddr;
2716 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2717 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2718 if (ch->dmapos != NULL &&
2719 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2720 addr = sc->pos_dma.dma_paddr;
2721 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2722 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2723 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2724 }
2725 }
2726
2727 static int
2728 hdac_bdl_alloc(struct hdac_chan *ch)
2729 {
2730 struct hdac_softc *sc = ch->devinfo->codec->sc;
2731 int rc;
2732
2733 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2734 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2735 if (rc) {
2736 device_printf(sc->dev, "can't alloc bdl\n");
2737 return (rc);
2738 }
2739
2740 return (0);
2741 }
2742
2743 static void
2744 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2745 int index, int lmute, int rmute,
2746 int left, int right, int dir)
2747 {
2748 uint16_t v = 0;
2749
2750 if (sc == NULL)
2751 return;
2752
2753 if (left != right || lmute != rmute) {
2754 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2755 (lmute << 7) | left;
2756 hdac_command(sc,
2757 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2758 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2759 (rmute << 7) | right;
2760 } else
2761 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2762 (lmute << 7) | left;
2763
2764 hdac_command(sc,
2765 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2766 }
2767
2768 static void
2769 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2770 int left, int right)
2771 {
2772 struct hdac_softc *sc;
2773 nid_t nid, cad;
2774 int lmute, rmute;
2775
2776 if (ctl == NULL || ctl->widget == NULL ||
2777 ctl->widget->devinfo == NULL ||
2778 ctl->widget->devinfo->codec == NULL ||
2779 ctl->widget->devinfo->codec->sc == NULL)
2780 return;
2781
2782 sc = ctl->widget->devinfo->codec->sc;
2783 cad = ctl->widget->devinfo->codec->cad;
2784 nid = ctl->widget->nid;
2785
2786 if (mute == HDA_AMP_MUTE_DEFAULT) {
2787 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2788 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2789 } else {
2790 lmute = HDA_AMP_LEFT_MUTED(mute);
2791 rmute = HDA_AMP_RIGHT_MUTED(mute);
2792 }
2793
2794 if (ctl->dir & HDA_CTL_OUT)
2795 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2796 lmute, rmute, left, right, 0);
2797 if (ctl->dir & HDA_CTL_IN)
2798 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2799 lmute, rmute, left, right, 1);
2800 ctl->left = left;
2801 ctl->right = right;
2802 }
2803
2804 static void
2805 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2806 {
2807 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2808 return;
2809 hdac_command(w->devinfo->codec->sc,
2810 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2811 w->nid, index), w->devinfo->codec->cad);
2812 w->selconn = index;
2813 }
2814
2815
2816 /****************************************************************************
2817 * uint32_t hdac_command_sendone_internal
2818 *
2819 * Wrapper function that sends only one command to a given codec
2820 ****************************************************************************/
2821 static uint32_t
2822 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2823 {
2824 struct hdac_command_list cl;
2825 uint32_t response = HDAC_INVALID;
2826
2827 if (!hdac_lockowned(sc))
2828 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2829 cl.num_commands = 1;
2830 cl.verbs = &verb;
2831 cl.responses = &response;
2832
2833 hdac_command_send_internal(sc, &cl, cad);
2834
2835 return (response);
2836 }
2837
2838 /****************************************************************************
2839 * hdac_command_send_internal
2840 *
2841 * Send a command list to the codec via the corb. We queue as much verbs as
2842 * we can and msleep on the codec. When the interrupt get the responses
2843 * back from the rirb, it will wake us up so we can queue the remaining verbs
2844 * if any.
2845 ****************************************************************************/
2846 static void
2847 hdac_command_send_internal(struct hdac_softc *sc,
2848 struct hdac_command_list *commands, nid_t cad)
2849 {
2850 struct hdac_codec *codec;
2851 int corbrp;
2852 uint32_t *corb;
2853 int timeout;
2854 int retry = 10;
2855 struct hdac_rirb *rirb_base;
2856
2857 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2858 commands->num_commands < 1)
2859 return;
2860
2861 codec = sc->codecs[cad];
2862 codec->commands = commands;
2863 codec->responses_received = 0;
2864 codec->verbs_sent = 0;
2865 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2866 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2867
2868 do {
2869 if (codec->verbs_sent != commands->num_commands) {
2870 /* Queue as many verbs as possible */
2871 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2872 #if 0
2873 bus_dmamap_sync(sc->corb_dma.dma_tag,
2874 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2875 #endif
2876 while (codec->verbs_sent != commands->num_commands &&
2877 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2878 sc->corb_wp++;
2879 sc->corb_wp %= sc->corb_size;
2880 corb[sc->corb_wp] =
2881 commands->verbs[codec->verbs_sent++];
2882 }
2883
2884 /* Send the verbs to the codecs */
2885 #if 0
2886 bus_dmamap_sync(sc->corb_dma.dma_tag,
2887 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2888 #endif
2889 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2890 }
2891
2892 timeout = 1000;
2893 while (hdac_rirb_flush(sc) == 0 && --timeout)
2894 DELAY(10);
2895 } while ((codec->verbs_sent != commands->num_commands ||
2896 codec->responses_received != commands->num_commands) && --retry);
2897
2898 if (retry == 0)
2899 device_printf(sc->dev,
2900 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2901 __func__, commands->num_commands, codec->verbs_sent,
2902 codec->responses_received);
2903
2904 codec->commands = NULL;
2905 codec->responses_received = 0;
2906 codec->verbs_sent = 0;
2907
2908 hdac_unsolq_flush(sc);
2909 }
2910
2911
2912 /****************************************************************************
2913 * Device Methods
2914 ****************************************************************************/
2915
2916 /****************************************************************************
2917 * int hdac_probe(device_t)
2918 *
2919 * Probe for the presence of an hdac. If none is found, check for a generic
2920 * match using the subclass of the device.
2921 ****************************************************************************/
2922 static int
2923 hdac_probe(device_t dev)
2924 {
2925 int i, result;
2926 uint32_t model;
2927 uint16_t class, subclass;
2928 char desc[64];
2929
2930 model = (uint32_t)pci_get_device(dev) << 16;
2931 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2932 class = pci_get_class(dev);
2933 subclass = pci_get_subclass(dev);
2934
2935 bzero(desc, sizeof(desc));
2936 result = ENXIO;
2937 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2938 if (hdac_devices[i].model == model) {
2939 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2940 result = BUS_PROBE_DEFAULT;
2941 break;
2942 }
2943 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2944 class == PCIC_MULTIMEDIA &&
2945 subclass == PCIS_MULTIMEDIA_HDA) {
2946 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2947 result = BUS_PROBE_GENERIC;
2948 break;
2949 }
2950 }
2951 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
2952 subclass == PCIS_MULTIMEDIA_HDA) {
2953 strlcpy(desc, "Generic", sizeof(desc));
2954 result = BUS_PROBE_GENERIC;
2955 }
2956 if (result != ENXIO) {
2957 strlcat(desc, " High Definition Audio Controller",
2958 sizeof(desc));
2959 device_set_desc_copy(dev, desc);
2960 }
2961
2962 return (result);
2963 }
2964
2965 static void *
2966 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
2967 struct pcm_channel *c, int dir)
2968 {
2969 struct hdac_devinfo *devinfo = data;
2970 struct hdac_softc *sc = devinfo->codec->sc;
2971 struct hdac_chan *ch;
2972
2973 hdac_lock(sc);
2974 if (dir == PCMDIR_PLAY) {
2975 ch = &sc->play;
2976 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
2977 devinfo->function.audio.playcnt++;
2978 } else {
2979 ch = &sc->rec;
2980 ch->off = devinfo->function.audio.reccnt << 5;
2981 devinfo->function.audio.reccnt++;
2982 }
2983 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
2984 ch->caps.minspeed = ch->caps.maxspeed = 48000;
2985 ch->pcmrates[0] = 48000;
2986 ch->pcmrates[1] = 0;
2987 }
2988 if (sc->pos_dma.dma_vaddr != NULL)
2989 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
2990 (sc->streamcnt * 8));
2991 else
2992 ch->dmapos = NULL;
2993 ch->sid = ++sc->streamcnt;
2994 ch->dir = dir;
2995 ch->b = b;
2996 ch->c = c;
2997 ch->devinfo = devinfo;
2998 ch->blksz = sc->chan_size / sc->chan_blkcnt;
2999 ch->blkcnt = sc->chan_blkcnt;
3000 hdac_unlock(sc);
3001
3002 if (hdac_bdl_alloc(ch) != 0) {
3003 ch->blkcnt = 0;
3004 return (NULL);
3005 }
3006
3007 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
3008 return (NULL);
3009
3010 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
3011 PAT_UNCACHEABLE);
3012
3013 return (ch);
3014 }
3015
3016 static int
3017 hdac_channel_free(kobj_t obj, void *data)
3018 {
3019 struct hdac_softc *sc;
3020 struct hdac_chan *ch;
3021
3022 ch = (struct hdac_chan *)data;
3023 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
3024 ch->devinfo->codec->sc : NULL;
3025 if (ch != NULL && sc != NULL) {
3026 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3027 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3028 }
3029
3030 return (1);
3031 }
3032
3033 static int
3034 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3035 {
3036 struct hdac_chan *ch = data;
3037 int i;
3038
3039 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3040 if (format == ch->caps.fmtlist[i]) {
3041 ch->fmt = format;
3042 return (0);
3043 }
3044 }
3045
3046 return (EINVAL);
3047 }
3048
3049 static int
3050 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3051 {
3052 struct hdac_chan *ch = data;
3053 uint32_t spd = 0, threshold;
3054 int i;
3055
3056 for (i = 0; ch->pcmrates[i] != 0; i++) {
3057 spd = ch->pcmrates[i];
3058 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3059 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3060 if (speed < threshold)
3061 break;
3062 }
3063
3064 if (spd == 0) /* impossible */
3065 ch->spd = 48000;
3066 else
3067 ch->spd = spd;
3068
3069 return (ch->spd);
3070 }
3071
3072 static void
3073 hdac_stream_setup(struct hdac_chan *ch)
3074 {
3075 struct hdac_softc *sc = ch->devinfo->codec->sc;
3076 int i;
3077 nid_t cad = ch->devinfo->codec->cad;
3078 uint16_t fmt;
3079
3080 fmt = 0;
3081 if (ch->fmt & AFMT_S16_LE)
3082 fmt |= ch->bit16 << 4;
3083 else if (ch->fmt & AFMT_S32_LE)
3084 fmt |= ch->bit32 << 4;
3085 else
3086 fmt |= 1 << 4;
3087
3088 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3089 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3090 fmt |= hda_rate_tab[i].base;
3091 fmt |= hda_rate_tab[i].mul;
3092 fmt |= hda_rate_tab[i].div;
3093 break;
3094 }
3095 }
3096
3097 if (ch->fmt & AFMT_STEREO)
3098 fmt |= 1;
3099
3100 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3101
3102 for (i = 0; ch->io[i] != -1; i++) {
3103 HDA_BOOTVERBOSE(
3104 device_printf(sc->dev,
3105 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3106 "fmt=0x%08x\n",
3107 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3108 ch->io[i], fmt);
3109 );
3110 hdac_command(sc,
3111 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3112 hdac_command(sc,
3113 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3114 ch->sid << 4), cad);
3115 }
3116 }
3117
3118 static int
3119 hdac_channel_setfragments(kobj_t obj, void *data,
3120 uint32_t blksz, uint32_t blkcnt)
3121 {
3122 struct hdac_chan *ch = data;
3123 struct hdac_softc *sc = ch->devinfo->codec->sc;
3124
3125 blksz &= HDA_BLK_ALIGN;
3126
3127 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3128 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3129 if (blksz < HDA_BLK_MIN)
3130 blksz = HDA_BLK_MIN;
3131 if (blkcnt > HDA_BDL_MAX)
3132 blkcnt = HDA_BDL_MAX;
3133 if (blkcnt < HDA_BDL_MIN)
3134 blkcnt = HDA_BDL_MIN;
3135
3136 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3137 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3138 blkcnt >>= 1;
3139 else if ((blksz >> 1) >= HDA_BLK_MIN)
3140 blksz >>= 1;
3141 else
3142 break;
3143 }
3144
3145 if ((sndbuf_getblksz(ch->b) != blksz ||
3146 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3147 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3148 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3149 __func__, blksz, blkcnt);
3150
3151 ch->blksz = sndbuf_getblksz(ch->b);
3152 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3153
3154 return (1);
3155 }
3156
3157 static int
3158 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3159 {
3160 struct hdac_chan *ch = data;
3161 struct hdac_softc *sc = ch->devinfo->codec->sc;
3162
3163 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3164
3165 return (ch->blksz);
3166 }
3167
3168 static void
3169 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3170 {
3171 struct hdac_devinfo *devinfo = ch->devinfo;
3172 nid_t cad = devinfo->codec->cad;
3173 int i;
3174
3175 hdac_stream_stop(ch);
3176
3177 for (i = 0; ch->io[i] != -1; i++) {
3178 hdac_command(sc,
3179 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3180 0), cad);
3181 }
3182 }
3183
3184 static void
3185 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3186 {
3187 ch->ptr = 0;
3188 ch->prevptr = 0;
3189 hdac_stream_stop(ch);
3190 hdac_stream_reset(ch);
3191 hdac_bdl_setup(ch);
3192 hdac_stream_setid(ch);
3193 hdac_stream_setup(ch);
3194 hdac_stream_start(ch);
3195 }
3196
3197 static int
3198 hdac_channel_trigger(kobj_t obj, void *data, int go)
3199 {
3200 struct hdac_chan *ch = data;
3201 struct hdac_softc *sc = ch->devinfo->codec->sc;
3202
3203 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3204 return (0);
3205
3206 hdac_lock(sc);
3207 switch (go) {
3208 case PCMTRIG_START:
3209 hdac_channel_start(sc, ch);
3210 break;
3211 case PCMTRIG_STOP:
3212 case PCMTRIG_ABORT:
3213 hdac_channel_stop(sc, ch);
3214 break;
3215 default:
3216 break;
3217 }
3218 hdac_unlock(sc);
3219
3220 return (0);
3221 }
3222
3223 static int
3224 hdac_channel_getptr(kobj_t obj, void *data)
3225 {
3226 struct hdac_chan *ch = data;
3227 struct hdac_softc *sc = ch->devinfo->codec->sc;
3228 uint32_t ptr;
3229
3230 hdac_lock(sc);
3231 if (sc->polling != 0)
3232 ptr = ch->ptr;
3233 else if (ch->dmapos != NULL)
3234 ptr = *(ch->dmapos);
3235 else
3236 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3237 hdac_unlock(sc);
3238
3239 /*
3240 * Round to available space and force 128 bytes aligment.
3241 */
3242 ptr %= ch->blksz * ch->blkcnt;
3243 ptr &= HDA_BLK_ALIGN;
3244
3245 return (ptr);
3246 }
3247
3248 static struct pcmchan_caps *
3249 hdac_channel_getcaps(kobj_t obj, void *data)
3250 {
3251 return (&((struct hdac_chan *)data)->caps);
3252 }
3253
3254 static kobj_method_t hdac_channel_methods[] = {
3255 KOBJMETHOD(channel_init, hdac_channel_init),
3256 KOBJMETHOD(channel_free, hdac_channel_free),
3257 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3258 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3259 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3260 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3261 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3262 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3263 { 0, 0 }
3264 };
3265 CHANNEL_DECLARE(hdac_channel);
3266
3267 static void
3268 hdac_jack_poll_callback(void *arg)
3269 {
3270 struct hdac_devinfo *devinfo = arg;
3271 struct hdac_softc *sc;
3272
3273 if (devinfo == NULL || devinfo->codec == NULL ||
3274 devinfo->codec->sc == NULL)
3275 return;
3276 sc = devinfo->codec->sc;
3277 hdac_lock(sc);
3278 if (sc->poll_ival == 0) {
3279 hdac_unlock(sc);
3280 return;
3281 }
3282 hdac_hp_switch_handler(devinfo);
3283 callout_reset(&sc->poll_jack, sc->poll_ival,
3284 hdac_jack_poll_callback, devinfo);
3285 hdac_unlock(sc);
3286 }
3287
3288 static int
3289 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3290 {
3291 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3292 struct hdac_softc *sc = devinfo->codec->sc;
3293 struct hdac_widget *w, *cw;
3294 struct hdac_audio_ctl *ctl;
3295 uint32_t mask, recmask, id;
3296 int i, j, softpcmvol;
3297 nid_t cad;
3298
3299 hdac_lock(sc);
3300
3301 mask = 0;
3302 recmask = 0;
3303
3304 id = hdac_codec_id(devinfo);
3305 cad = devinfo->codec->cad;
3306 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3307 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3308 sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3309 continue;
3310 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3311 if (w == NULL || w->enable == 0 || w->type !=
3312 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3313 continue;
3314 if (hdac_hp_switch[i].polling != 0)
3315 callout_reset(&sc->poll_jack, 1,
3316 hdac_jack_poll_callback, devinfo);
3317 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3318 hdac_command(sc,
3319 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3320 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3321 HDAC_UNSOLTAG_EVENT_HP), cad);
3322 else
3323 continue;
3324 hdac_hp_switch_handler(devinfo);
3325 HDA_BOOTVERBOSE(
3326 device_printf(sc->dev,
3327 "HDA_DEBUG: Enabling headphone/speaker "
3328 "audio routing switching:\n");
3329 device_printf(sc->dev,
3330 "HDA_DEBUG: \tindex=%d nid=%d "
3331 "pci_subvendor=0x%08x "
3332 "codec=0x%08x [%s]\n",
3333 i, w->nid, sc->pci_subvendor, id,
3334 (hdac_hp_switch[i].polling != 0) ? "POLL" :
3335 "UNSOL");
3336 );
3337 break;
3338 }
3339 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3340 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3341 sc->pci_subvendor) &&
3342 hdac_eapd_switch[i].id == id))
3343 continue;
3344 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3345 if (w == NULL || w->enable == 0)
3346 break;
3347 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3348 w->param.eapdbtl == HDAC_INVALID)
3349 break;
3350 mask |= SOUND_MASK_OGAIN;
3351 break;
3352 }
3353
3354 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3355 w = hdac_widget_get(devinfo, i);
3356 if (w == NULL || w->enable == 0)
3357 continue;
3358 mask |= w->ctlflags;
3359 if (!(w->pflags & HDA_ADC_RECSEL))
3360 continue;
3361 for (j = 0; j < w->nconns; j++) {
3362 cw = hdac_widget_get(devinfo, w->conns[j]);
3363 if (cw == NULL || cw->enable == 0)
3364 continue;
3365 recmask |= cw->ctlflags;
3366 }
3367 }
3368
3369 if (!(mask & SOUND_MASK_PCM)) {
3370 softpcmvol = 1;
3371 mask |= SOUND_MASK_PCM;
3372 } else
3373 softpcmvol = (devinfo->function.audio.quirks &
3374 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3375
3376 i = 0;
3377 ctl = NULL;
3378 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3379 if (ctl->widget == NULL || ctl->enable == 0)
3380 continue;
3381 if (!(ctl->ossmask & SOUND_MASK_PCM))
3382 continue;
3383 if (ctl->step > 0)
3384 break;
3385 }
3386
3387 if (softpcmvol == 1 || ctl == NULL) {
3388 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3389 HDA_BOOTVERBOSE(
3390 device_printf(sc->dev,
3391 "HDA_DEBUG: %s Soft PCM volume\n",
3392 (softpcmvol == 1) ?
3393 "Forcing" : "Enabling");
3394 );
3395 i = 0;
3396 /*
3397 * XXX Temporary quirk for STAC9220, until the parser
3398 * become smarter.
3399 */
3400 if (id == HDA_CODEC_STAC9220) {
3401 mask |= SOUND_MASK_VOLUME;
3402 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3403 NULL) {
3404 if (ctl->widget == NULL || ctl->enable == 0)
3405 continue;
3406 if (ctl->widget->nid == 11 && ctl->index == 0) {
3407 ctl->ossmask = SOUND_MASK_VOLUME;
3408 ctl->ossval = 100 | (100 << 8);
3409 } else
3410 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3411 }
3412 } else if (id == HDA_CODEC_STAC9221) {
3413 mask |= SOUND_MASK_VOLUME;
3414 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3415 NULL) {
3416 if (ctl->widget == NULL)
3417 continue;
3418 if (ctl->widget->type ==
3419 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3420 ctl->index == 0 && (ctl->widget->nid == 2 ||
3421 ctl->widget->enable != 0)) {
3422 ctl->enable = 1;
3423 ctl->ossmask = SOUND_MASK_VOLUME;
3424 ctl->ossval = 100 | (100 << 8);
3425 } else if (ctl->enable == 0)
3426 continue;
3427 else
3428 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3429 }
3430 } else {
3431 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3432 SOUND_MASK_PCM);
3433 if (!(mask & SOUND_MASK_VOLUME))
3434 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3435 SOUND_MIXER_NONE);
3436 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3437 NULL) {
3438 if (ctl->widget == NULL || ctl->enable == 0)
3439 continue;
3440 if (!HDA_FLAG_MATCH(ctl->ossmask,
3441 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3442 continue;
3443 if (!(ctl->mute == 1 && ctl->step == 0))
3444 ctl->enable = 0;
3445 }
3446 }
3447 }
3448
3449 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3450 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3451 SOUND_MASK_OGAIN);
3452 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3453 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3454
3455 mix_setrecdevs(m, recmask);
3456 mix_setdevs(m, mask);
3457
3458 hdac_unlock(sc);
3459
3460 return (0);
3461 }
3462
3463 static int
3464 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3465 unsigned left, unsigned right)
3466 {
3467 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3468 struct hdac_softc *sc = devinfo->codec->sc;
3469 struct hdac_widget *w;
3470 struct hdac_audio_ctl *ctl;
3471 uint32_t id, mute;
3472 int lvol, rvol, mlvol, mrvol;
3473 int i = 0;
3474
3475 hdac_lock(sc);
3476 if (dev == SOUND_MIXER_OGAIN) {
3477 uint32_t orig;
3478 /*if (left != right || !(left == 0 || left == 1)) {
3479 hdac_unlock(sc);
3480 return (-1);
3481 }*/
3482 id = hdac_codec_id(devinfo);
3483 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3484 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3485 sc->pci_subvendor) &&
3486 hdac_eapd_switch[i].id == id)
3487 break;
3488 }
3489 if (i >= HDAC_EAPD_SWITCH_LEN) {
3490 hdac_unlock(sc);
3491 return (-1);
3492 }
3493 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3494 if (w == NULL ||
3495 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3496 w->param.eapdbtl == HDAC_INVALID) {
3497 hdac_unlock(sc);
3498 return (-1);
3499 }
3500 orig = w->param.eapdbtl;
3501 if (left == 0)
3502 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3503 else
3504 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3505 if (orig != w->param.eapdbtl) {
3506 uint32_t val;
3507
3508 if (hdac_eapd_switch[i].hp_switch != 0)
3509 hdac_hp_switch_handler(devinfo);
3510 val = w->param.eapdbtl;
3511 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3512 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3513 hdac_command(sc,
3514 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3515 w->nid, val), devinfo->codec->cad);
3516 }
3517 hdac_unlock(sc);
3518 return (left | (left << 8));
3519 }
3520 if (dev == SOUND_MIXER_VOLUME)
3521 devinfo->function.audio.mvol = left | (right << 8);
3522
3523 mlvol = devinfo->function.audio.mvol & 0x7f;
3524 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3525 lvol = 0;
3526 rvol = 0;
3527
3528 i = 0;
3529 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3530 if (ctl->widget == NULL || ctl->enable == 0 ||
3531 !(ctl->ossmask & (1 << dev)))
3532 continue;
3533 switch (dev) {
3534 case SOUND_MIXER_VOLUME:
3535 lvol = ((ctl->ossval & 0x7f) * left) / 100;
3536 lvol = (lvol * ctl->step) / 100;
3537 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3538 rvol = (rvol * ctl->step) / 100;
3539 break;
3540 default:
3541 if (ctl->ossmask & SOUND_MASK_VOLUME) {
3542 lvol = (left * mlvol) / 100;
3543 lvol = (lvol * ctl->step) / 100;
3544 rvol = (right * mrvol) / 100;
3545 rvol = (rvol * ctl->step) / 100;
3546 } else {
3547 lvol = (left * ctl->step) / 100;
3548 rvol = (right * ctl->step) / 100;
3549 }
3550 ctl->ossval = left | (right << 8);
3551 break;
3552 }
3553 mute = 0;
3554 if (ctl->step < 1) {
3555 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3556 (ctl->muted & HDA_AMP_MUTE_LEFT);
3557 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3558 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3559 } else {
3560 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3561 (ctl->muted & HDA_AMP_MUTE_LEFT);
3562 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3563 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3564 }
3565 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3566 }
3567 hdac_unlock(sc);
3568
3569 return (left | (right << 8));
3570 }
3571
3572 static int
3573 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3574 {
3575 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3576 struct hdac_widget *w, *cw;
3577 struct hdac_softc *sc = devinfo->codec->sc;
3578 uint32_t ret = src, target;
3579 int i, j;
3580
3581 target = 0;
3582 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3583 if (src & (1 << i)) {
3584 target = 1 << i;
3585 break;
3586 }
3587 }
3588
3589 hdac_lock(sc);
3590
3591 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3592 w = hdac_widget_get(devinfo, i);
3593 if (w == NULL || w->enable == 0)
3594 continue;
3595 if (!(w->pflags & HDA_ADC_RECSEL))
3596 continue;
3597 for (j = 0; j < w->nconns; j++) {
3598 cw = hdac_widget_get(devinfo, w->conns[j]);
3599 if (cw == NULL || cw->enable == 0)
3600 continue;
3601 if ((target == SOUND_MASK_VOLUME &&
3602 cw->type !=
3603 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3604 (target != SOUND_MASK_VOLUME &&
3605 cw->type ==
3606 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3607 continue;
3608 if (cw->ctlflags & target) {
3609 if (!(w->pflags & HDA_ADC_LOCKED))
3610 hdac_widget_connection_select(w, j);
3611 ret = target;
3612 j += w->nconns;
3613 }
3614 }
3615 }
3616
3617 hdac_unlock(sc);
3618
3619 return (ret);
3620 }
3621
3622 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3623 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3624 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3625 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3626 { 0, 0 }
3627 };
3628 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3629
3630 static void
3631 hdac_unsolq_task(void *context, int pending)
3632 {
3633 struct hdac_softc *sc;
3634
3635 sc = (struct hdac_softc *)context;
3636
3637 hdac_lock(sc);
3638 hdac_unsolq_flush(sc);
3639 hdac_unlock(sc);
3640 }
3641
3642 /****************************************************************************
3643 * int hdac_attach(device_t)
3644 *
3645 * Attach the device into the kernel. Interrupts usually won't be enabled
3646 * when this function is called. Setup everything that doesn't require
3647 * interrupts and defer probing of codecs until interrupts are enabled.
3648 ****************************************************************************/
3649 static int
3650 hdac_attach(device_t dev)
3651 {
3652 struct hdac_softc *sc;
3653 int result;
3654 int i;
3655 uint16_t vendor;
3656 uint8_t v;
3657
3658 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
3659 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3660 sc->dev = dev;
3661 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3662 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3663 vendor = pci_get_vendor(dev);
3664
3665 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3666 /* Screw nx6325 - subdevice/subvendor swapped */
3667 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3668 }
3669
3670 callout_init(&sc->poll_hda);
3671 callout_init(&sc->poll_hdac);
3672 callout_init(&sc->poll_jack);
3673
3674 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
3675
3676 sc->poll_ticks = 1;
3677 sc->poll_ival = HDAC_POLL_INTERVAL;
3678 if (resource_int_value(device_get_name(dev),
3679 device_get_unit(dev), "polling", &i) == 0 && i != 0)
3680 sc->polling = 1;
3681 else
3682 sc->polling = 0;
3683
3684 sc->chan_size = pcm_getbuffersize(dev,
3685 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3686
3687 if (resource_int_value(device_get_name(dev),
3688 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3689 i &= HDA_BLK_ALIGN;
3690 if (i < HDA_BLK_MIN)
3691 i = HDA_BLK_MIN;
3692 sc->chan_blkcnt = sc->chan_size / i;
3693 i = 0;
3694 while (sc->chan_blkcnt >> i)
3695 i++;
3696 sc->chan_blkcnt = 1 << (i - 1);
3697 if (sc->chan_blkcnt < HDA_BDL_MIN)
3698 sc->chan_blkcnt = HDA_BDL_MIN;
3699 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3700 sc->chan_blkcnt = HDA_BDL_MAX;
3701 } else
3702 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3703
3704 result = bus_dma_tag_create(NULL, /* parent */
3705 HDAC_DMA_ALIGNMENT, /* alignment */
3706 0, /* boundary */
3707 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3708 BUS_SPACE_MAXADDR, /* highaddr */
3709 NULL, /* filtfunc */
3710 NULL, /* fistfuncarg */
3711 sc->chan_size, /* maxsize */
3712 1, /* nsegments */
3713 sc->chan_size, /* maxsegsz */
3714 0, /* flags */
3715 &sc->chan_dmat); /* dmat */
3716 if (result != 0) {
3717 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3718 __func__, result);
3719 snd_mtxfree(sc->lock);
3720 kfree(sc, M_DEVBUF);
3721 return (ENXIO);
3722 }
3723
3724
3725 sc->hdabus = NULL;
3726 for (i = 0; i < HDAC_CODEC_MAX; i++)
3727 sc->codecs[i] = NULL;
3728
3729 pci_enable_busmaster(dev);
3730
3731 if (vendor == INTEL_VENDORID) {
3732 /* TCSEL -> TC0 */
3733 v = pci_read_config(dev, 0x44, 1);
3734 pci_write_config(dev, 0x44, v & 0xf8, 1);
3735 HDA_BOOTVERBOSE(
3736 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3737 pci_read_config(dev, 0x44, 1));
3738 );
3739 }
3740
3741 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3742 sc->nocache = 1;
3743
3744 if (resource_int_value(device_get_name(dev),
3745 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3746 #else
3747 sc->nocache = 0;
3748 #endif
3749 /*
3750 * Try to enable PCIe snoop to avoid messing around with
3751 * uncacheable DMA attribute. Since PCIe snoop register
3752 * config is pretty much vendor specific, there are no
3753 * general solutions on how to enable it, forcing us (even
3754 * Microsoft) to enable uncacheable or write combined DMA
3755 * by default.
3756 *
3757 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3758 */
3759 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3760 if (hdac_pcie_snoop[i].vendor != vendor)
3761 continue;
3762 sc->nocache = 0;
3763 if (hdac_pcie_snoop[i].reg == 0x00)
3764 break;
3765 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3766 if ((v & hdac_pcie_snoop[i].enable) ==
3767 hdac_pcie_snoop[i].enable)
3768 break;
3769 v &= hdac_pcie_snoop[i].mask;
3770 v |= hdac_pcie_snoop[i].enable;
3771 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3772 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3773 if ((v & hdac_pcie_snoop[i].enable) !=
3774 hdac_pcie_snoop[i].enable) {
3775 HDA_BOOTVERBOSE(
3776 device_printf(dev,
3777 "WARNING: Failed to enable PCIe "
3778 "snoop!\n");
3779 );
3780 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3781 sc->nocache = 1;
3782 #endif
3783 }
3784 break;
3785 }
3786 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3787 }
3788 #endif
3789
3790 HDA_BOOTVERBOSE(
3791 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
3792 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor);
3793 );
3794
3795 /* Allocate resources */
3796 result = hdac_mem_alloc(sc);
3797 if (result != 0)
3798 goto hdac_attach_fail;
3799 result = hdac_irq_alloc(sc);
3800 if (result != 0)
3801 goto hdac_attach_fail;
3802
3803 /* Get Capabilities */
3804 result = hdac_get_capabilities(sc);
3805 if (result != 0)
3806 goto hdac_attach_fail;
3807
3808 /* Allocate CORB and RIRB dma memory */
3809 result = hdac_dma_alloc(sc, &sc->corb_dma,
3810 sc->corb_size * sizeof(uint32_t));
3811 if (result != 0)
3812 goto hdac_attach_fail;
3813 result = hdac_dma_alloc(sc, &sc->rirb_dma,
3814 sc->rirb_size * sizeof(struct hdac_rirb));
3815 if (result != 0)
3816 goto hdac_attach_fail;
3817
3818 /* Quiesce everything */
3819 hdac_reset(sc);
3820
3821 /* Initialize the CORB and RIRB */
3822 hdac_corb_init(sc);
3823 hdac_rirb_init(sc);
3824
3825 /* Defer remaining of initialization until interrupts are enabled */
3826 sc->intrhook.ich_func = hdac_attach2;
3827 sc->intrhook.ich_arg = (void *)sc;
3828 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
3829 sc->intrhook.ich_func = NULL;
3830 hdac_attach2((void *)sc);
3831 }
3832
3833 return (0);
3834
3835 hdac_attach_fail:
3836 hdac_irq_free(sc);
3837 hdac_dma_free(sc, &sc->rirb_dma);
3838 hdac_dma_free(sc, &sc->corb_dma);
3839 hdac_mem_free(sc);
3840 snd_mtxfree(sc->lock);
3841 kfree(sc, M_DEVBUF);
3842
3843 return (ENXIO);
3844 }
3845
3846 static void
3847 hdac_audio_parse(struct hdac_devinfo *devinfo)
3848 {
3849 struct hdac_softc *sc = devinfo->codec->sc;
3850 struct hdac_widget *w;
3851 uint32_t res;
3852 int i;
3853 nid_t cad, nid;
3854
3855 cad = devinfo->codec->cad;
3856 nid = devinfo->nid;
3857
3858 hdac_command(sc,
3859 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
3860
3861 DELAY(100);
3862
3863 res = hdac_command(sc,
3864 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
3865
3866 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
3867 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
3868 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
3869
3870 res = hdac_command(sc,
3871 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
3872 devinfo->function.audio.gpio = res;
3873
3874 HDA_BOOTVERBOSE(
3875 device_printf(sc->dev, " Vendor: 0x%08x\n",
3876 devinfo->vendor_id);
3877 device_printf(sc->dev, " Device: 0x%08x\n",
3878 devinfo->device_id);
3879 device_printf(sc->dev, " Revision: 0x%08x\n",
3880 devinfo->revision_id);
3881 device_printf(sc->dev, " Stepping: 0x%08x\n",
3882 devinfo->stepping_id);
3883 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3884 sc->pci_subvendor);
3885 device_printf(sc->dev, " Nodes: start=%d "
3886 "endnode=%d total=%d\n",
3887 devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3888 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size);
3889 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size);
3890 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n",
3891 sc->num_iss, sc->num_oss, sc->num_bss);
3892 device_printf(sc->dev, " GPIO: 0x%08x\n",
3893 devinfo->function.audio.gpio);
3894 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d "
3895 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
3896 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
3897 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
3898 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
3899 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
3900 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
3901 );
3902
3903 res = hdac_command(sc,
3904 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
3905 cad);
3906 devinfo->function.audio.supp_stream_formats = res;
3907
3908 res = hdac_command(sc,
3909 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
3910 cad);
3911 devinfo->function.audio.supp_pcm_size_rate = res;
3912
3913 res = hdac_command(sc,
3914 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
3915 cad);
3916 devinfo->function.audio.outamp_cap = res;
3917
3918 res = hdac_command(sc,
3919 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
3920 cad);
3921 devinfo->function.audio.inamp_cap = res;
3922
3923 if (devinfo->nodecnt > 0)
3924 devinfo->widget = (struct hdac_widget *)kmalloc(
3925 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
3926 M_NOWAIT | M_ZERO);
3927 else
3928 devinfo->widget = NULL;
3929
3930 if (devinfo->widget == NULL) {
3931 device_printf(sc->dev, "unable to allocate widgets!\n");
3932 devinfo->endnode = devinfo->startnode;
3933 devinfo->nodecnt = 0;
3934 return;
3935 }
3936
3937 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3938 w = hdac_widget_get(devinfo, i);
3939 if (w == NULL)
3940 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
3941 else {
3942 w->devinfo = devinfo;
3943 w->nid = i;
3944 w->enable = 1;
3945 w->selconn = -1;
3946 w->pflags = 0;
3947 w->ctlflags = 0;
3948 w->param.eapdbtl = HDAC_INVALID;
3949 hdac_widget_parse(w);
3950 }
3951 }
3952 }
3953
3954 static void
3955 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
3956 {
3957 struct hdac_softc *sc = devinfo->codec->sc;
3958 struct hdac_audio_ctl *ctls;
3959 struct hdac_widget *w, *cw;
3960 int i, j, cnt, max, ocap, icap;
3961 int mute, offset, step, size;
3962
3963 /* XXX This is redundant */
3964 max = 0;
3965 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3966 w = hdac_widget_get(devinfo, i);
3967 if (w == NULL || w->enable == 0)
3968 continue;
3969 if (w->param.outamp_cap != 0)
3970 max++;
3971 if (w->param.inamp_cap != 0) {
3972 switch (w->type) {
3973 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3974 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3975 for (j = 0; j < w->nconns; j++) {
3976 cw = hdac_widget_get(devinfo,
3977 w->conns[j]);
3978 if (cw == NULL || cw->enable == 0)
3979 continue;
3980 max++;
3981 }
3982 break;
3983 default:
3984 max++;
3985 break;
3986 }
3987 }
3988 }
3989
3990 devinfo->function.audio.ctlcnt = max;
3991
3992 if (max < 1)
3993 return;
3994
3995 ctls = (struct hdac_audio_ctl *)kmalloc(
3996 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
3997
3998 if (ctls == NULL) {
3999 /* Blekh! */
4000 device_printf(sc->dev, "unable to allocate ctls!\n");
4001 devinfo->function.audio.ctlcnt = 0;
4002 return;
4003 }
4004
4005 cnt = 0;
4006 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
4007 if (cnt >= max) {
4008 device_printf(sc->dev, "%s: Ctl overflow!\n",
4009 __func__);
4010 break;
4011 }
4012 w = hdac_widget_get(devinfo, i);
4013 if (w == NULL || w->enable == 0)
4014 continue;
4015 ocap = w->param.outamp_cap;
4016 icap = w->param.inamp_cap;
4017 if (ocap != 0) {
4018 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
4019 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
4020 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
4021 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
4022 /*if (offset > step) {
4023 HDA_BOOTVERBOSE(
4024 device_printf(sc->dev,
4025 "HDA_DEBUG: BUGGY outamp: nid=%d "
4026 "[offset=%d > step=%d]\n",
4027 w->nid, offset, step);
4028 );
4029 offset = step;
4030 }*/
4031 ctls[cnt].enable = 1;
4032 ctls[cnt].widget = w;
4033 ctls[cnt].mute = mute;
4034 ctls[cnt].step = step;
4035 ctls[cnt].size = size;
4036 ctls[cnt].offset = offset;
4037 ctls[cnt].left = offset;
4038 ctls[cnt].right = offset;
4039 ctls[cnt++].dir = HDA_CTL_OUT;
4040 }
4041
4042 if (icap != 0) {
4043 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4044 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4045 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4046 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4047 /*if (offset > step) {
4048 HDA_BOOTVERBOSE(
4049 device_printf(sc->dev,
4050 "HDA_DEBUG: BUGGY inamp: nid=%d "
4051 "[offset=%d > step=%d]\n",
4052 w->nid, offset, step);
4053 );
4054 offset = step;
4055 }*/
4056 switch (w->type) {
4057 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4058 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4059 for (j = 0; j < w->nconns; j++) {
4060 if (cnt >= max) {
4061 device_printf(sc->dev,
4062 "%s: Ctl overflow!\n",
4063 __func__);
4064 break;
4065 }
4066 cw = hdac_widget_get(devinfo,
4067 w->conns[j]);
4068 if (cw == NULL || cw->enable == 0)
4069 continue;
4070 ctls[cnt].enable = 1;
4071 ctls[cnt].widget = w;
4072 ctls[cnt].childwidget = cw;
4073 ctls[cnt].index = j;
4074 ctls[cnt].mute = mute;
4075 ctls[cnt].step = step;
4076 ctls[cnt].size = size;
4077 ctls[cnt].offset = offset;
4078 ctls[cnt].left = offset;
4079 ctls[cnt].right = offset;
4080 ctls[cnt++].dir = HDA_CTL_IN;
4081 }
4082 break;
4083 default:
4084 if (cnt >= max) {
4085 device_printf(sc->dev,
4086 "%s: Ctl overflow!\n",
4087 __func__);
4088 break;
4089 }
4090 ctls[cnt].enable = 1;
4091 ctls[cnt].widget = w;
4092 ctls[cnt].mute = mute;
4093 ctls[cnt].step = step;
4094 ctls[cnt].size = size;
4095 ctls[cnt].offset = offset;
4096 ctls[cnt].left = offset;
4097 ctls[cnt].right = offset;
4098 ctls[cnt++].dir = HDA_CTL_IN;
4099 break;
4100 }
4101 }
4102 }
4103
4104 devinfo->function.audio.ctl = ctls;
4105 }
4106
4107 static const struct {
4108 uint32_t model;
4109 uint32_t id;
4110 uint32_t set, unset;
4111 } hdac_quirks[] = {
4112 /*
4113 * XXX Force stereo quirk. Monoural recording / playback
4114 * on few codecs (especially ALC880) seems broken or
4115 * perhaps unsupported.
4116 */
4117 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4118 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4119 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4120 HDA_QUIRK_GPIO0, 0 },
4121 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4122 HDA_QUIRK_GPIO0, 0 },
4123 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4124 HDA_QUIRK_GPIO0, 0 },
4125 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4126 HDA_QUIRK_GPIO0, 0 },
4127 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4128 HDA_QUIRK_GPIO0, 0 },
4129 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4130 HDA_QUIRK_EAPDINV, 0 },
4131 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A,
4132 HDA_QUIRK_EAPDINV, 0 },
4133 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4134 HDA_QUIRK_OVREF, 0 },
4135 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861,
4136 HDA_QUIRK_OVREF, 0 },
4137 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4138 HDA_QUIRK_OVREF, 0 },
4139 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4140 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4141 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4142 HDA_QUIRK_GPIO1, 0 },
4143 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4144 HDA_QUIRK_EAPDINV, 0 },
4145 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4146 HDA_QUIRK_EAPDINV, 0 },
4147 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4148 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4149 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4150 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4151 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4152 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4153 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
4154 0, HDA_QUIRK_FORCESTEREO },
4155 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
4156 HDA_QUIRK_SOFTPCMVOL, 0 }
4157 };
4158 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4159
4160 static void
4161 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4162 {
4163 struct hdac_widget *w;
4164 struct hdac_audio_ctl *ctl;
4165 uint32_t id, subvendor;
4166 int i;
4167
4168 id = hdac_codec_id(devinfo);
4169 subvendor = devinfo->codec->sc->pci_subvendor;
4170
4171 /*
4172 * Quirks
4173 */
4174 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4175 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4176 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4177 continue;
4178 if (hdac_quirks[i].set != 0)
4179 devinfo->function.audio.quirks |=
4180 hdac_quirks[i].set;
4181 if (hdac_quirks[i].unset != 0)
4182 devinfo->function.audio.quirks &=
4183 ~(hdac_quirks[i].unset);
4184 }
4185
4186 switch (id) {
4187 case HDA_CODEC_ALC260:
4188 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4189 w = hdac_widget_get(devinfo, i);
4190 if (w == NULL || w->enable == 0)
4191 continue;
4192 if (w->type !=
4193 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4194 continue;
4195 if (w->nid != 5)
4196 w->enable = 0;
4197 }
4198 if (subvendor == HP_XW4300_SUBVENDOR) {
4199 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4200 if (ctl != NULL && ctl->widget != NULL) {
4201 ctl->ossmask = SOUND_MASK_SPEAKER;
4202 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4203 }
4204 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4205 if (ctl != NULL && ctl->widget != NULL) {
4206 ctl->ossmask = SOUND_MASK_SPEAKER;
4207 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4208 }
4209 } else if (subvendor == HP_3010_SUBVENDOR) {
4210 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4211 if (ctl != NULL && ctl->widget != NULL) {
4212 ctl->ossmask = SOUND_MASK_SPEAKER;
4213 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4214 }
4215 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1);
4216 if (ctl != NULL && ctl->widget != NULL) {
4217 ctl->ossmask = SOUND_MASK_SPEAKER;
4218 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4219 }
4220 }
4221 break;
4222 case HDA_CODEC_ALC861:
4223 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1);
4224 if (ctl != NULL)
4225 ctl->muted = HDA_AMP_MUTE_ALL;
4226 break;
4227 case HDA_CODEC_ALC880:
4228 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4229 w = hdac_widget_get(devinfo, i);
4230 if (w == NULL || w->enable == 0)
4231 continue;
4232 if (w->type ==
4233 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4234 w->nid != 9 && w->nid != 29) {
4235 w->enable = 0;
4236 } else if (w->type !=
4237 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
4238 w->nid == 29) {
4239 w->type =
4240 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4241 w->param.widget_cap &=
4242 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4243 w->param.widget_cap |=
4244 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4245 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4246 strlcpy(w->name, "beep widget", sizeof(w->name));
4247 }
4248 }
4249 break;
4250 case HDA_CODEC_ALC883:
4251 /*
4252 * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4253 * Clear vref cap for jack connectivity.
4254 */
4255 w = hdac_widget_get(devinfo, 24);
4256 if (w != NULL && w->enable != 0 && w->type ==
4257 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4258 (w->wclass.pin.config &
4259 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4260 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4261 w->wclass.pin.cap &= ~(
4262 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4263 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4264 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4265 w = hdac_widget_get(devinfo, 25);
4266 if (w != NULL && w->enable != 0 && w->type ==
4267 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4268 (w->wclass.pin.config &
4269 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4270 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4271 w->wclass.pin.cap &= ~(
4272 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4273 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4274 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4275 /*
4276 * nid: 26 = Line-in, leave it alone.
4277 */
4278 break;
4279 case HDA_CODEC_AD1981HD:
4280 w = hdac_widget_get(devinfo, 11);
4281 if (w != NULL && w->enable != 0 && w->nconns > 3)
4282 w->selconn = 3;
4283 if (subvendor == IBM_M52_SUBVENDOR) {
4284 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
4285 if (ctl != NULL)
4286 ctl->ossmask = SOUND_MASK_SPEAKER;
4287 }
4288 break;
4289 case HDA_CODEC_AD1986A:
4290 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4291 w = hdac_widget_get(devinfo, i);
4292 if (w == NULL || w->enable == 0)
4293 continue;
4294 if (w->type !=
4295 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4296 continue;
4297 if (w->nid != 3)
4298 w->enable = 0;
4299 }
4300 if (subvendor == ASUS_M2NPVMX_SUBVENDOR ||
4301 subvendor == ASUS_A8NVMCSM_SUBVENDOR) {
4302 /* nid 28 is mic, nid 29 is line-in */
4303 w = hdac_widget_get(devinfo, 15);
4304 if (w != NULL)
4305 w->selconn = 2;
4306 w = hdac_widget_get(devinfo, 16);
4307 if (w != NULL)
4308 w->selconn = 1;
4309 }
4310 break;
4311 case HDA_CODEC_AD1988:
4312 case HDA_CODEC_AD1988B:
4313 /*w = hdac_widget_get(devinfo, 12);
4314 if (w != NULL) {
4315 w->selconn = 1;
4316 w->pflags |= HDA_ADC_LOCKED;
4317 }
4318 w = hdac_widget_get(devinfo, 13);
4319 if (w != NULL) {
4320 w->selconn = 4;
4321 w->pflags |= HDA_ADC_LOCKED;
4322 }
4323 w = hdac_widget_get(devinfo, 14);
4324 if (w != NULL) {
4325 w->selconn = 2;
4326 w->pflags |= HDA_ADC_LOCKED;
4327 }*/
4328 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1);
4329 if (ctl != NULL) {
4330 ctl->ossmask = SOUND_MASK_IGAIN;
4331 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4332 }
4333 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1);
4334 if (ctl != NULL) {
4335 ctl->ossmask = SOUND_MASK_IGAIN;
4336 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4337 }
4338 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1);
4339 if (ctl != NULL) {
4340 ctl->ossmask = SOUND_MASK_IGAIN;
4341 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4342 }
4343 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1);
4344 if (ctl != NULL) {
4345 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4346 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4347 }
4348 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1);
4349 if (ctl != NULL) {
4350 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4351 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4352 }
4353 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1);
4354 if (ctl != NULL) {
4355 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4356 ctl->widget->ctlflags |= SOUND_MASK_LINE;
4357 }
4358 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1);
4359 if (ctl != NULL) {
4360 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME;
4361 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4362 }
4363 break;
4364 case HDA_CODEC_STAC9221:
4365 /*
4366 * Dell XPS M1210 need all DACs for each output jacks
4367 */
4368 if (subvendor == DELL_XPSM1210_SUBVENDOR)
4369 break;
4370 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4371 w = hdac_widget_get(devinfo, i);
4372 if (w == NULL || w->enable == 0)
4373 continue;
4374 if (w->type !=
4375 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4376 continue;
4377 if (w->nid != 2)
4378 w->enable = 0;
4379 }
4380 break;
4381 case HDA_CODEC_STAC9221D:
4382 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4383 w = hdac_widget_get(devinfo, i);
4384 if (w == NULL || w->enable == 0)
4385 continue;
4386 if (w->type ==
4387 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4388 w->nid != 6)
4389 w->enable = 0;
4390
4391 }
4392 break;
4393 case HDA_CODEC_STAC9227:
4394 w = hdac_widget_get(devinfo, 8);
4395 if (w != NULL)
4396 w->enable = 0;
4397 w = hdac_widget_get(devinfo, 9);
4398 if (w != NULL)
4399 w->enable = 0;
4400 break;
4401 case HDA_CODEC_CXWAIKIKI:
4402 if (subvendor == HP_DV5000_SUBVENDOR) {
4403 w = hdac_widget_get(devinfo, 27);
4404 if (w != NULL)
4405 w->enable = 0;
4406 }
4407 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4408 if (ctl != NULL)
4409 ctl->ossmask = SOUND_MASK_SKIP;
4410 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1);
4411 if (ctl != NULL && ctl->childwidget != NULL &&
4412 ctl->childwidget->enable != 0) {
4413 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME;
4414 ctl->childwidget->ctlflags |= SOUND_MASK_PCM;
4415 }
4416 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1);
4417 if (ctl != NULL && ctl->childwidget != NULL &&
4418 ctl->childwidget->enable != 0) {
4419 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4420 ctl->childwidget->ctlflags |= SOUND_MASK_LINE;
4421 }
4422 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1);
4423 if (ctl != NULL && ctl->childwidget != NULL &&
4424 ctl->childwidget->enable != 0) {
4425 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4426 ctl->childwidget->ctlflags |= SOUND_MASK_MIC;
4427 }
4428 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1);
4429 if (ctl != NULL) {
4430 ctl->ossmask = SOUND_MASK_SKIP;
4431 /* XXX mixer \=rec mic broken.. why?!? */
4432 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */
4433 }
4434 break;
4435 default:
4436 break;
4437 }
4438 }
4439
4440 static int
4441 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
4442 {
4443 int *dev = &devinfo->function.audio.ossidx;
4444
4445 while (*dev < SOUND_MIXER_NRDEVICES) {
4446 switch (*dev) {
4447 case SOUND_MIXER_VOLUME:
4448 case SOUND_MIXER_BASS:
4449 case SOUND_MIXER_TREBLE:
4450 case SOUND_MIXER_PCM:
4451 case SOUND_MIXER_SPEAKER:
4452 case SOUND_MIXER_LINE:
4453 case SOUND_MIXER_MIC:
4454 case SOUND_MIXER_CD:
4455 case SOUND_MIXER_RECLEV:
4456 case SOUND_MIXER_IGAIN:
4457 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
4458 (*dev)++;
4459 break;
4460 default:
4461 return (*dev)++;
4462 break;
4463 }
4464 }
4465
4466 return (-1);
4467 }
4468
4469 static int
4470 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4471 {
4472 struct hdac_widget *w;
4473 int i, ret = 0;
4474
4475 if (depth > HDA_PARSE_MAXDEPTH)
4476 return (0);
4477 w = hdac_widget_get(devinfo, nid);
4478 if (w == NULL || w->enable == 0)
4479 return (0);
4480 switch (w->type) {
4481 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4482 w->pflags |= HDA_DAC_PATH;
4483 ret = 1;
4484 break;
4485 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4486 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4487 for (i = 0; i < w->nconns; i++) {
4488 if (hdac_widget_find_dac_path(devinfo,
4489 w->conns[i], depth + 1) != 0) {
4490 if (w->selconn == -1)
4491 w->selconn = i;
4492 ret = 1;
4493 w->pflags |= HDA_DAC_PATH;
4494 }
4495 }
4496 break;
4497 default:
4498 break;
4499 }
4500 return (ret);
4501 }
4502
4503 static int
4504 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4505 {
4506 struct hdac_widget *w;
4507 int i, conndev, ret = 0;
4508
4509 if (depth > HDA_PARSE_MAXDEPTH)
4510 return (0);
4511 w = hdac_widget_get(devinfo, nid);
4512 if (w == NULL || w->enable == 0)
4513 return (0);
4514 switch (w->type) {
4515 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4516 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4517 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4518 for (i = 0; i < w->nconns; i++) {
4519 if (hdac_widget_find_adc_path(devinfo, w->conns[i],
4520 depth + 1) != 0) {
4521 if (w->selconn == -1)
4522 w->selconn = i;
4523 w->pflags |= HDA_ADC_PATH;
4524 ret = 1;
4525 }
4526 }
4527 break;
4528 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4529 conndev = w->wclass.pin.config &
4530 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4531 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4532 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
4533 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
4534 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
4535 w->pflags |= HDA_ADC_PATH;
4536 ret = 1;
4537 }
4538 break;
4539 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4540 if (w->pflags & HDA_DAC_PATH) {
4541 w->pflags |= HDA_ADC_PATH;
4542 ret = 1;
4543 }
4544 break;*/
4545 default:
4546 break;
4547 }
4548 return (ret);
4549 }
4550
4551 static uint32_t
4552 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
4553 nid_t nid, nid_t pnid, int index, int depth)
4554 {
4555 struct hdac_widget *w, *pw;
4556 struct hdac_audio_ctl *ctl;
4557 uint32_t fl = 0;
4558 int i, ossdev, conndev, strategy;
4559
4560 if (depth > HDA_PARSE_MAXDEPTH)
4561 return (0);
4562
4563 w = hdac_widget_get(devinfo, nid);
4564 if (w == NULL || w->enable == 0)
4565 return (0);
4566
4567 pw = hdac_widget_get(devinfo, pnid);
4568 strategy = devinfo->function.audio.parsing_strategy;
4569
4570 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
4571 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
4572 for (i = 0; i < w->nconns; i++) {
4573 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
4574 w->nid, i, depth + 1);
4575 }
4576 w->ctlflags |= fl;
4577 return (fl);
4578 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
4579 (w->pflags & HDA_DAC_PATH)) {
4580 i = 0;
4581 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4582 if (ctl->enable == 0 || ctl->widget == NULL)
4583 continue;
4584 /* XXX This should be compressed! */
4585 if (((ctl->widget->nid == w->nid) ||
4586 (ctl->widget->nid == pnid && ctl->index == index &&
4587 (ctl->dir & HDA_CTL_IN)) ||
4588 (ctl->widget->nid == pnid && pw != NULL &&
4589 pw->type ==
4590 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4591 (pw->nconns < 2 || pw->selconn == index ||
4592 pw->selconn == -1) &&
4593 (ctl->dir & HDA_CTL_OUT)) ||
4594 (strategy == HDA_PARSE_DIRECT &&
4595 ctl->widget->nid == w->nid)) &&
4596 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4597 /*if (pw != NULL && pw->selconn == -1)
4598 pw->selconn = index;
4599 fl |= SOUND_MASK_VOLUME;
4600 fl |= SOUND_MASK_PCM;
4601 ctl->ossmask |= SOUND_MASK_VOLUME;
4602 ctl->ossmask |= SOUND_MASK_PCM;
4603 ctl->ossdev = SOUND_MIXER_PCM;*/
4604 if (!(w->ctlflags & SOUND_MASK_PCM) ||
4605 (pw != NULL &&
4606 !(pw->ctlflags & SOUND_MASK_PCM))) {
4607 fl |= SOUND_MASK_VOLUME;
4608 fl |= SOUND_MASK_PCM;
4609 ctl->ossmask |= SOUND_MASK_VOLUME;
4610 ctl->ossmask |= SOUND_MASK_PCM;
4611 ctl->ossdev = SOUND_MIXER_PCM;
4612 w->ctlflags |= SOUND_MASK_VOLUME;
4613 w->ctlflags |= SOUND_MASK_PCM;
4614 if (pw != NULL) {
4615 if (pw->selconn == -1)
4616 pw->selconn = index;
4617 pw->ctlflags |=
4618 SOUND_MASK_VOLUME;
4619 pw->ctlflags |=
4620 SOUND_MASK_PCM;
4621 }
4622 }
4623 }
4624 }
4625 w->ctlflags |= fl;
4626 return (fl);
4627 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4628 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4629 (w->pflags & HDA_ADC_PATH)) {
4630 conndev = w->wclass.pin.config &
4631 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4632 i = 0;
4633 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4634 if (ctl->enable == 0 || ctl->widget == NULL)
4635 continue;
4636 /* XXX This should be compressed! */
4637 if (((ctl->widget->nid == pnid && ctl->index == index &&
4638 (ctl->dir & HDA_CTL_IN)) ||
4639 (ctl->widget->nid == pnid && pw != NULL &&
4640 pw->type ==
4641 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4642 (pw->nconns < 2 || pw->selconn == index ||
4643 pw->selconn == -1) &&
4644 (ctl->dir & HDA_CTL_OUT)) ||
4645 (strategy == HDA_PARSE_DIRECT &&
4646 ctl->widget->nid == w->nid)) &&
4647 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4648 if (pw != NULL && pw->selconn == -1)
4649 pw->selconn = index;
4650 ossdev = 0;
4651 switch (conndev) {
4652 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
4653 ossdev = SOUND_MIXER_MIC;
4654 break;
4655 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
4656 ossdev = SOUND_MIXER_LINE;
4657 break;
4658 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
4659 ossdev = SOUND_MIXER_CD;
4660 break;
4661 default:
4662 ossdev =
4663 hdac_audio_ctl_ossmixer_getnextdev(
4664 devinfo);
4665 if (ossdev < 0)
4666 ossdev = 0;
4667 break;
4668 }
4669 if (strategy == HDA_PARSE_MIXER) {
4670 fl |= SOUND_MASK_VOLUME;
4671 ctl->ossmask |= SOUND_MASK_VOLUME;
4672 }
4673 fl |= 1 << ossdev;
4674 ctl->ossmask |= 1 << ossdev;
4675 ctl->ossdev = ossdev;
4676 }
4677 }
4678 w->ctlflags |= fl;
4679 return (fl);
4680 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4681 i = 0;
4682 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4683 if (ctl->enable == 0 || ctl->widget == NULL)
4684 continue;
4685 /* XXX This should be compressed! */
4686 if (((ctl->widget->nid == pnid && ctl->index == index &&
4687 (ctl->dir & HDA_CTL_IN)) ||
4688 (ctl->widget->nid == pnid && pw != NULL &&
4689 pw->type ==
4690 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4691 (pw->nconns < 2 || pw->selconn == index ||
4692 pw->selconn == -1) &&
4693 (ctl->dir & HDA_CTL_OUT)) ||
4694 (strategy == HDA_PARSE_DIRECT &&
4695 ctl->widget->nid == w->nid)) &&
4696 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4697 if (pw != NULL && pw->selconn == -1)
4698 pw->selconn = index;
4699 fl |= SOUND_MASK_VOLUME;
4700 fl |= SOUND_MASK_SPEAKER;
4701 ctl->ossmask |= SOUND_MASK_VOLUME;
4702 ctl->ossmask |= SOUND_MASK_SPEAKER;
4703 ctl->ossdev = SOUND_MIXER_SPEAKER;
4704 }
4705 }
4706 w->ctlflags |= fl;
4707 return (fl);
4708 }
4709 return (0);
4710 }
4711
4712 static uint32_t
4713 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4714 {
4715 struct hdac_widget *w, *cw;
4716 struct hdac_audio_ctl *ctl;
4717 uint32_t fl;
4718 int i;
4719
4720 if (depth > HDA_PARSE_MAXDEPTH)
4721 return (0);
4722
4723 w = hdac_widget_get(devinfo, nid);
4724 if (w == NULL || w->enable == 0)
4725 return (0);
4726 /*if (!(w->pflags & HDA_ADC_PATH))
4727 return (0);
4728 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4729 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4730 return (0);*/
4731 i = 0;
4732 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4733 if (ctl->enable == 0 || ctl->widget == NULL)
4734 continue;
4735 if (ctl->widget->nid == nid) {
4736 ctl->ossmask |= SOUND_MASK_RECLEV;
4737 w->ctlflags |= SOUND_MASK_RECLEV;
4738 return (SOUND_MASK_RECLEV);
4739 }
4740 }
4741 for (i = 0; i < w->nconns; i++) {
4742 cw = hdac_widget_get(devinfo, w->conns[i]);
4743 if (cw == NULL || cw->enable == 0)
4744 continue;
4745 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4746 continue;
4747 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
4748 if (fl != 0) {
4749 cw->ctlflags |= fl;
4750 w->ctlflags |= fl;
4751 return (fl);
4752 }
4753 }
4754 return (0);
4755 }
4756
4757 static int
4758 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4759 {
4760 struct hdac_widget *w, *cw;
4761 int i, child = 0;
4762
4763 if (depth > HDA_PARSE_MAXDEPTH)
4764 return (0);
4765
4766 w = hdac_widget_get(devinfo, nid);
4767 if (w == NULL || w->enable == 0)
4768 return (0);
4769 /*if (!(w->pflags & HDA_ADC_PATH))
4770 return (0);
4771 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4772 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4773 return (0);*/
4774 /* XXX weak! */
4775 for (i = 0; i < w->nconns; i++) {
4776 cw = hdac_widget_get(devinfo, w->conns[i]);
4777 if (cw == NULL)
4778 continue;
4779 if (++child > 1) {
4780 w->pflags |= HDA_ADC_RECSEL;
4781 return (1);
4782 }
4783 }
4784 for (i = 0; i < w->nconns; i++) {
4785 if (hdac_audio_ctl_recsel_build(devinfo,
4786 w->conns[i], depth + 1) != 0)
4787 return (1);
4788 }
4789 return (0);
4790 }
4791
4792 static int
4793 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
4794 {
4795 struct hdac_widget *w, *cw;
4796 int i, j, conndev, found_dac = 0;
4797 int strategy;
4798
4799 strategy = devinfo->function.audio.parsing_strategy;
4800
4801 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4802 w = hdac_widget_get(devinfo, i);
4803 if (w == NULL || w->enable == 0)
4804 continue;
4805 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4806 continue;
4807 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
4808 continue;
4809 conndev = w->wclass.pin.config &
4810 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4811 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4812 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4813 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
4814 continue;
4815 for (j = 0; j < w->nconns; j++) {
4816 cw = hdac_widget_get(devinfo, w->conns[j]);
4817 if (cw == NULL || cw->enable == 0)
4818 continue;
4819 if (strategy == HDA_PARSE_MIXER && !(cw->type ==
4820 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4821 cw->type ==
4822 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4823 continue;
4824 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
4825 != 0) {
4826 if (w->selconn == -1)
4827 w->selconn = j;
4828 w->pflags |= HDA_DAC_PATH;
4829 found_dac++;
4830 }
4831 }
4832 }
4833
4834 return (found_dac);
4835 }
4836
4837 static void
4838 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
4839 {
4840 struct hdac_widget *w;
4841 struct hdac_audio_ctl *ctl;
4842 int i, j, dacs, strategy;
4843
4844 /* Construct DAC path */
4845 strategy = HDA_PARSE_MIXER;
4846 devinfo->function.audio.parsing_strategy = strategy;
4847 HDA_BOOTVERBOSE(
4848 device_printf(devinfo->codec->sc->dev,
4849 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
4850 HDA_WIDGET_PARSER_REV);
4851 );
4852 dacs = hdac_audio_build_tree_strategy(devinfo);
4853 if (dacs == 0) {
4854 HDA_BOOTVERBOSE(
4855 device_printf(devinfo->codec->sc->dev,
4856 "HDA_DEBUG: HWiP: 0 DAC path found! "
4857 "Retrying parser "
4858 "using HDA_PARSE_DIRECT strategy.\n");
4859 );
4860 strategy = HDA_PARSE_DIRECT;
4861 devinfo->function.audio.parsing_strategy = strategy;
4862 dacs = hdac_audio_build_tree_strategy(devinfo);
4863 }
4864
4865 HDA_BOOTVERBOSE(
4866 device_printf(devinfo->codec->sc->dev,
4867 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
4868 "strategy.\n",
4869 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
4870 );
4871
4872 /* Construct ADC path */
4873 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4874 w = hdac_widget_get(devinfo, i);
4875 if (w == NULL || w->enable == 0)
4876 continue;
4877 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4878 continue;
4879 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
4880 }
4881
4882 /* Output mixers */
4883 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4884 w = hdac_widget_get(devinfo, i);
4885 if (w == NULL || w->enable == 0)
4886 continue;
4887 if ((strategy == HDA_PARSE_MIXER &&
4888 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4889 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4890 && (w->pflags & HDA_DAC_PATH)) ||
4891 (strategy == HDA_PARSE_DIRECT && (w->pflags &
4892 (HDA_DAC_PATH | HDA_ADC_PATH)))) {
4893 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
4894 w->nid, devinfo->startnode - 1, 0, 0);
4895 } else if (w->type ==
4896 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4897 j = 0;
4898 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
4899 NULL) {
4900 if (ctl->enable == 0 || ctl->widget == NULL)
4901 continue;
4902 if (ctl->widget->nid != w->nid)
4903 continue;
4904 ctl->ossmask |= SOUND_MASK_VOLUME;
4905 ctl->ossmask |= SOUND_MASK_SPEAKER;
4906 ctl->ossdev = SOUND_MIXER_SPEAKER;
4907 w->ctlflags |= SOUND_MASK_VOLUME;
4908 w->ctlflags |= SOUND_MASK_SPEAKER;
4909 }
4910 }
4911 }
4912
4913 /* Input mixers (rec) */
4914 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4915 w = hdac_widget_get(devinfo, i);
4916 if (w == NULL || w->enable == 0)
4917 continue;
4918 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4919 w->pflags & HDA_ADC_PATH))
4920 continue;
4921 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
4922 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
4923 }
4924 }
4925
4926 #define HDA_COMMIT_CONN (1 << 0)
4927 #define HDA_COMMIT_CTRL (1 << 1)
4928 #define HDA_COMMIT_EAPD (1 << 2)
4929 #define HDA_COMMIT_GPIO (1 << 3)
4930 #define HDA_COMMIT_MISC (1 << 4)
4931 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
4932 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC)
4933
4934 static void
4935 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
4936 {
4937 struct hdac_softc *sc = devinfo->codec->sc;
4938 struct hdac_widget *w;
4939 nid_t cad;
4940 int i;
4941
4942 if (!(cfl & HDA_COMMIT_ALL))
4943 return;
4944
4945 cad = devinfo->codec->cad;
4946
4947 if ((cfl & HDA_COMMIT_MISC)) {
4948 if (sc->pci_subvendor == APPLE_INTEL_MAC)
4949 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
4950 0x7e7, 0), cad);
4951 }
4952
4953 if (cfl & HDA_COMMIT_GPIO) {
4954 uint32_t gdata, gmask, gdir;
4955 int commitgpio, numgpio;
4956
4957 gdata = 0;
4958 gmask = 0;
4959 gdir = 0;
4960 commitgpio = 0;
4961
4962 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
4963 devinfo->function.audio.gpio);
4964
4965 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
4966 commitgpio = (numgpio > 0) ? 1 : 0;
4967 else {
4968 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
4969 if (!(devinfo->function.audio.quirks &
4970 (1 << i)))
4971 continue;
4972 if (commitgpio == 0) {
4973 commitgpio = 1;
4974 HDA_BOOTVERBOSE(
4975 gdata = hdac_command(sc,
4976 HDA_CMD_GET_GPIO_DATA(cad,
4977 devinfo->nid), cad);
4978 gmask = hdac_command(sc,
4979 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
4980 devinfo->nid), cad);
4981 gdir = hdac_command(sc,
4982 HDA_CMD_GET_GPIO_DIRECTION(cad,
4983 devinfo->nid), cad);
4984 device_printf(sc->dev,
4985 "GPIO init: data=0x%08x "
4986 "mask=0x%08x dir=0x%08x\n",
4987 gdata, gmask, gdir);
4988 gdata = 0;
4989 gmask = 0;
4990 gdir = 0;
4991 );
4992 }
4993 gdata |= 1 << i;
4994 gmask |= 1 << i;
4995 gdir |= 1 << i;
4996 }
4997 }
4998
4999 if (commitgpio != 0) {
5000 HDA_BOOTVERBOSE(
5001 device_printf(sc->dev,
5002 "GPIO commit: data=0x%08x mask=0x%08x "
5003 "dir=0x%08x\n",
5004 gdata, gmask, gdir);
5005 );
5006 hdac_command(sc,
5007 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
5008 gmask), cad);
5009 hdac_command(sc,
5010 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
5011 gdir), cad);
5012 hdac_command(sc,
5013 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
5014 gdata), cad);
5015 }
5016 }
5017
5018 for (i = 0; i < devinfo->nodecnt; i++) {
5019 w = &devinfo->widget[i];
5020 if (w == NULL || w->enable == 0)
5021 continue;
5022 if (cfl & HDA_COMMIT_CONN) {
5023 if (w->selconn == -1)
5024 w->selconn = 0;
5025 if (w->nconns > 0)
5026 hdac_widget_connection_select(w, w->selconn);
5027 }
5028 if ((cfl & HDA_COMMIT_CTRL) &&
5029 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5030 uint32_t pincap;
5031
5032 pincap = w->wclass.pin.cap;
5033
5034 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
5035 (HDA_DAC_PATH | HDA_ADC_PATH))
5036 device_printf(sc->dev, "WARNING: node %d "
5037 "participate both for DAC/ADC!\n", w->nid);
5038 if (w->pflags & HDA_DAC_PATH) {
5039 w->wclass.pin.ctrl &=
5040 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
5041 if ((w->wclass.pin.config &
5042 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
5043 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
5044 w->wclass.pin.ctrl &=
5045 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
5046 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
5047 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5048 w->wclass.pin.ctrl |=
5049 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5050 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5051 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
5052 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5053 w->wclass.pin.ctrl |=
5054 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5055 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5056 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
5057 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5058 w->wclass.pin.ctrl |=
5059 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5060 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5061 } else if (w->pflags & HDA_ADC_PATH) {
5062 w->wclass.pin.ctrl &=
5063 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5064 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
5065 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
5066 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5067 w->wclass.pin.ctrl |=
5068 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5069 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5070 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
5071 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5072 w->wclass.pin.ctrl |=
5073 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5074 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5075 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
5076 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5077 w->wclass.pin.ctrl |=
5078 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5079 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5080 } else
5081 w->wclass.pin.ctrl &= ~(
5082 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
5083 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5084 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
5085 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
5086 hdac_command(sc,
5087 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
5088 w->wclass.pin.ctrl), cad);
5089 }
5090 if ((cfl & HDA_COMMIT_EAPD) &&
5091 w->param.eapdbtl != HDAC_INVALID) {
5092 uint32_t val;
5093
5094 val = w->param.eapdbtl;
5095 if (devinfo->function.audio.quirks &
5096 HDA_QUIRK_EAPDINV)
5097 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
5098 hdac_command(sc,
5099 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
5100 val), cad);
5101
5102 }
5103 DELAY(1000);
5104 }
5105 }
5106
5107 static void
5108 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
5109 {
5110 struct hdac_softc *sc = devinfo->codec->sc;
5111 struct hdac_audio_ctl *ctl;
5112 int i;
5113
5114 devinfo->function.audio.mvol = 100 | (100 << 8);
5115 i = 0;
5116 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5117 if (ctl->enable == 0 || ctl->widget == NULL) {
5118 HDA_BOOTVERBOSE(
5119 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5120 i, (ctl->widget != NULL) ?
5121 ctl->widget->nid : -1);
5122 if (ctl->childwidget != NULL)
5123 kprintf(" childnid=%d",
5124 ctl->childwidget->nid);
5125 if (ctl->widget == NULL)
5126 kprintf(" NULL WIDGET!");
5127 kprintf(" DISABLED\n");
5128 );
5129 continue;
5130 }
5131 HDA_BOOTVERBOSE(
5132 if (ctl->ossmask == 0) {
5133 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5134 i, ctl->widget->nid);
5135 if (ctl->childwidget != NULL)
5136 kprintf(" childnid=%d",
5137 ctl->childwidget->nid);
5138 kprintf(" Bind to NONE\n");
5139 }
5140 );
5141 if (ctl->step > 0) {
5142 ctl->ossval = (ctl->left * 100) / ctl->step;
5143 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
5144 } else
5145 ctl->ossval = 0;
5146 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
5147 ctl->left, ctl->right);
5148 }
5149 }
5150
5151 static int
5152 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
5153 {
5154 struct hdac_chan *ch;
5155 struct hdac_widget *w;
5156 uint32_t cap, fmtcap, pcmcap, path;
5157 int i, type, ret, max;
5158
5159 if (dir == PCMDIR_PLAY) {
5160 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
5161 ch = &devinfo->codec->sc->play;
5162 path = HDA_DAC_PATH;
5163 } else {
5164 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
5165 ch = &devinfo->codec->sc->rec;
5166 path = HDA_ADC_PATH;
5167 }
5168
5169 ch->caps = hdac_caps;
5170 ch->caps.fmtlist = ch->fmtlist;
5171 ch->bit16 = 1;
5172 ch->bit32 = 0;
5173 ch->pcmrates[0] = 48000;
5174 ch->pcmrates[1] = 0;
5175
5176 ret = 0;
5177 fmtcap = devinfo->function.audio.supp_stream_formats;
5178 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
5179 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
5180
5181 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
5182 w = hdac_widget_get(devinfo, i);
5183 if (w == NULL || w->enable == 0 || w->type != type ||
5184 !(w->pflags & path))
5185 continue;
5186 cap = w->param.widget_cap;
5187 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
5188 continue;*/
5189 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
5190 continue;
5191 cap = w->param.supp_stream_formats;
5192 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
5193 }
5194 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
5195 }*/
5196 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5197 continue;
5198 if (ret == 0) {
5199 fmtcap = w->param.supp_stream_formats;
5200 pcmcap = w->param.supp_pcm_size_rate;
5201 } else {
5202 fmtcap &= w->param.supp_stream_formats;
5203 pcmcap &= w->param.supp_pcm_size_rate;
5204 }
5205 ch->io[ret++] = i;
5206 }
5207 ch->io[ret] = -1;
5208
5209 ch->supp_stream_formats = fmtcap;
5210 ch->supp_pcm_size_rate = pcmcap;
5211
5212 /*
5213 * 8bit = 0
5214 * 16bit = 1
5215 * 20bit = 2
5216 * 24bit = 3
5217 * 32bit = 4
5218 */
5219 if (ret > 0) {
5220 cap = pcmcap;
5221 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5222 ch->bit16 = 1;
5223 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5224 ch->bit16 = 0;
5225 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5226 ch->bit32 = 4;
5227 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5228 ch->bit32 = 3;
5229 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5230 ch->bit32 = 2;
5231 i = 0;
5232 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
5233 ch->fmtlist[i++] = AFMT_S16_LE;
5234 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
5235 if (ch->bit32 > 0) {
5236 if (!(devinfo->function.audio.quirks &
5237 HDA_QUIRK_FORCESTEREO))
5238 ch->fmtlist[i++] = AFMT_S32_LE;
5239 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
5240 }
5241 ch->fmtlist[i] = 0;
5242 i = 0;
5243 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5244 ch->pcmrates[i++] = 8000;
5245 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5246 ch->pcmrates[i++] = 11025;
5247 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5248 ch->pcmrates[i++] = 16000;
5249 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5250 ch->pcmrates[i++] = 22050;
5251 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5252 ch->pcmrates[i++] = 32000;
5253 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5254 ch->pcmrates[i++] = 44100;
5255 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
5256 ch->pcmrates[i++] = 48000;
5257 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5258 ch->pcmrates[i++] = 88200;
5259 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5260 ch->pcmrates[i++] = 96000;
5261 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5262 ch->pcmrates[i++] = 176400;
5263 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5264 ch->pcmrates[i++] = 192000;
5265 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
5266 ch->pcmrates[i] = 0;
5267 if (i > 0) {
5268 ch->caps.minspeed = ch->pcmrates[0];
5269 ch->caps.maxspeed = ch->pcmrates[i - 1];
5270 }
5271 }
5272
5273 return (ret);
5274 }
5275
5276 static void
5277 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
5278 {
5279 struct hdac_audio_ctl *ctl;
5280 struct hdac_softc *sc = devinfo->codec->sc;
5281 int i;
5282 uint32_t fl = 0;
5283
5284
5285 if (flag == 0) {
5286 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
5287 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
5288 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
5289 }
5290
5291 i = 0;
5292 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5293 if (ctl->enable == 0 || ctl->widget == NULL ||
5294 ctl->widget->enable == 0 || (ctl->ossmask &
5295 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)))
5296 continue;
5297 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
5298 (flag != 0 && (ctl->ossmask & flag))) {
5299 if (banner != NULL) {
5300 device_printf(sc->dev, "\n");
5301 device_printf(sc->dev, "%s\n", banner);
5302 }
5303 goto hdac_ctl_dump_it_all;
5304 }
5305 }
5306
5307 return;
5308
5309 hdac_ctl_dump_it_all:
5310 i = 0;
5311 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5312 if (ctl->enable == 0 || ctl->widget == NULL ||
5313 ctl->widget->enable == 0)
5314 continue;
5315 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
5316 (flag != 0 && (ctl->ossmask & flag))))
5317 continue;
5318 if (flag == 0) {
5319 device_printf(sc->dev, "\n");
5320 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
5321 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
5322 }
5323 device_printf(sc->dev, " |\n");
5324 device_printf(sc->dev, " +- nid: %2d index: %2d ",
5325 ctl->widget->nid, ctl->index);
5326 if (ctl->childwidget != NULL)
5327 kprintf("(nid: %2d) ", ctl->childwidget->nid);
5328 else
5329 kprintf(" ");
5330 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
5331 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
5332 ctl->ossmask);
5333 }
5334 }
5335
5336 static void
5337 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
5338 {
5339 uint32_t cap;
5340
5341 cap = fcap;
5342 if (cap != 0) {
5343 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap);
5344 device_printf(sc->dev, " Format:");
5345 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
5346 kprintf(" AC3");
5347 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
5348 kprintf(" FLOAT32");
5349 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5350 kprintf(" PCM");
5351 kprintf("\n");
5352 }
5353 cap = pcmcap;
5354 if (cap != 0) {
5355 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap);
5356 device_printf(sc->dev, " PCM size:");
5357 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5358 kprintf(" 8");
5359 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5360 kprintf(" 16");
5361 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5362 kprintf(" 20");
5363 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5364 kprintf(" 24");
5365 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5366 kprintf(" 32");
5367 kprintf("\n");
5368 device_printf(sc->dev, " PCM rate:");
5369 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5370 kprintf(" 8");
5371 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5372 kprintf(" 11");
5373 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5374 kprintf(" 16");
5375 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5376 kprintf(" 22");
5377 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5378 kprintf(" 32");
5379 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5380 kprintf(" 44");
5381 kprintf(" 48");
5382 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5383 kprintf(" 88");
5384 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5385 kprintf(" 96");
5386 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5387 kprintf(" 176");
5388 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5389 kprintf(" 192");
5390 kprintf("\n");
5391 }
5392 }
5393
5394 static void
5395 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
5396 {
5397 uint32_t pincap, wcap;
5398
5399 pincap = w->wclass.pin.cap;
5400 wcap = w->param.widget_cap;
5401
5402 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
5403 device_printf(sc->dev, " ");
5404 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
5405 kprintf(" ISC");
5406 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
5407 kprintf(" TRQD");
5408 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
5409 kprintf(" PDC");
5410 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
5411 kprintf(" HP");
5412 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
5413 kprintf(" OUT");
5414 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
5415 kprintf(" IN");
5416 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
5417 kprintf(" BAL");
5418 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
5419 kprintf(" VREF[");
5420 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5421 kprintf(" 50");
5422 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5423 kprintf(" 80");
5424 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5425 kprintf(" 100");
5426 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
5427 kprintf(" GROUND");
5428 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
5429 kprintf(" HIZ");
5430 kprintf(" ]");
5431 }
5432 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
5433 kprintf(" EAPD");
5434 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
5435 kprintf(" : UNSOL");
5436 kprintf("\n");
5437 device_printf(sc->dev, " Pin config: 0x%08x\n",
5438 w->wclass.pin.config);
5439 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
5440 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
5441 kprintf(" HP");
5442 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
5443 kprintf(" IN");
5444 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
5445 kprintf(" OUT");
5446 kprintf("\n");
5447 }
5448
5449 static void
5450 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
5451 {
5452 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
5453 device_printf(sc->dev, " "
5454 "mute=%d step=%d size=%d offset=%d\n",
5455 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
5456 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
5457 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
5458 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
5459 }
5460
5461 static void
5462 hdac_dump_nodes(struct hdac_devinfo *devinfo)
5463 {
5464 struct hdac_softc *sc = devinfo->codec->sc;
5465 struct hdac_widget *w, *cw;
5466 int i, j;
5467
5468 device_printf(sc->dev, "\n");
5469 device_printf(sc->dev, "Default Parameter\n");
5470 device_printf(sc->dev, "-----------------\n");
5471 hdac_dump_audio_formats(sc,
5472 devinfo->function.audio.supp_stream_formats,
5473 devinfo->function.audio.supp_pcm_size_rate);
5474 device_printf(sc->dev, " IN amp: 0x%08x\n",
5475 devinfo->function.audio.inamp_cap);
5476 device_printf(sc->dev, " OUT amp: 0x%08x\n",
5477 devinfo->function.audio.outamp_cap);
5478 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5479 w = hdac_widget_get(devinfo, i);
5480 if (w == NULL) {
5481 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
5482 continue;
5483 }
5484 device_printf(sc->dev, "\n");
5485 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid,
5486 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
5487 "DIGITAL" : "ANALOG",
5488 (w->enable == 0) ? " [DISABLED]" : "");
5489 device_printf(sc->dev, " name: %s\n", w->name);
5490 device_printf(sc->dev, " widget_cap: 0x%08x\n",
5491 w->param.widget_cap);
5492 device_printf(sc->dev, " Parse flags: 0x%08x\n",
5493 w->pflags);
5494 device_printf(sc->dev, " Ctl flags: 0x%08x\n",
5495 w->ctlflags);
5496 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
5497 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
5498 hdac_dump_audio_formats(sc,
5499 w->param.supp_stream_formats,
5500 w->param.supp_pcm_size_rate);
5501 } else if (w->type ==
5502 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5503 hdac_dump_pin(sc, w);
5504 if (w->param.eapdbtl != HDAC_INVALID)
5505 device_printf(sc->dev, " EAPD: 0x%08x\n",
5506 w->param.eapdbtl);
5507 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
5508 w->param.outamp_cap != 0)
5509 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
5510 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
5511 w->param.inamp_cap != 0)
5512 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
5513 device_printf(sc->dev, " connections: %d\n", w->nconns);
5514 for (j = 0; j < w->nconns; j++) {
5515 cw = hdac_widget_get(devinfo, w->conns[j]);
5516 device_printf(sc->dev, " |\n");
5517 device_printf(sc->dev, " + <- nid=%d [%s]",
5518 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
5519 if (cw == NULL)
5520 kprintf(" [UNKNOWN]");
5521 else if (cw->enable == 0)
5522 kprintf(" [DISABLED]");
5523 if (w->nconns > 1 && w->selconn == j && w->type !=
5524 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5525 kprintf(" (selected)");
5526 kprintf("\n");
5527 }
5528 }
5529
5530 }
5531
5532 static int
5533 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5534 {
5535 struct hdac_widget *w, *cw;
5536 struct hdac_softc *sc = devinfo->codec->sc;
5537 int i;
5538
5539 if (depth > HDA_PARSE_MAXDEPTH)
5540 return (0);
5541
5542 w = hdac_widget_get(devinfo, nid);
5543 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
5544 return (0);
5545
5546 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5547 device_printf(sc->dev, "\n");
5548 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5549 device_printf(sc->dev, " ^\n");
5550 device_printf(sc->dev, " |\n");
5551 device_printf(sc->dev, " +-----<------+\n");
5552 } else {
5553 device_printf(sc->dev, " ^\n");
5554 device_printf(sc->dev, " |\n");
5555 device_printf(sc->dev, " ");
5556 kprintf(" nid=%d [%s]\n", w->nid, w->name);
5557 }
5558
5559 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
5560 return (1);
5561 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
5562 for (i = 0; i < w->nconns; i++) {
5563 cw = hdac_widget_get(devinfo, w->conns[i]);
5564 if (cw == NULL || cw->enable == 0 || cw->type ==
5565 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5566 continue;
5567 if (hdac_dump_dac_internal(devinfo, cw->nid,
5568 depth + 1) != 0)
5569 return (1);
5570 }
5571 } else if ((w->type ==
5572 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
5573 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5574 w->selconn > -1 && w->selconn < w->nconns) {
5575 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
5576 depth + 1) != 0)
5577 return (1);
5578 }
5579
5580 return (0);
5581 }
5582
5583 static void
5584 hdac_dump_dac(struct hdac_devinfo *devinfo)
5585 {
5586 struct hdac_widget *w;
5587 struct hdac_softc *sc = devinfo->codec->sc;
5588 int i, printed = 0;
5589
5590 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5591 w = hdac_widget_get(devinfo, i);
5592 if (w == NULL || w->enable == 0)
5593 continue;
5594 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
5595 !(w->pflags & HDA_DAC_PATH))
5596 continue;
5597 if (printed == 0) {
5598 printed = 1;
5599 device_printf(sc->dev, "\n");
5600 device_printf(sc->dev, "Playback path:\n");
5601 }
5602 hdac_dump_dac_internal(devinfo, w->nid, 0);
5603 }
5604 }
5605
5606 static void
5607 hdac_dump_adc(struct hdac_devinfo *devinfo)
5608 {
5609 struct hdac_widget *w, *cw;
5610 struct hdac_softc *sc = devinfo->codec->sc;
5611 int i, j;
5612 int printed = 0;
5613 char ossdevs[256];
5614
5615 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5616 w = hdac_widget_get(devinfo, i);
5617 if (w == NULL || w->enable == 0)
5618 continue;
5619 if (!(w->pflags & HDA_ADC_RECSEL))
5620 continue;
5621 if (printed == 0) {
5622 printed = 1;
5623 device_printf(sc->dev, "\n");
5624 device_printf(sc->dev, "Recording sources:\n");
5625 }
5626 device_printf(sc->dev, "\n");
5627 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5628 for (j = 0; j < w->nconns; j++) {
5629 cw = hdac_widget_get(devinfo, w->conns[j]);
5630 if (cw == NULL || cw->enable == 0)
5631 continue;
5632 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
5633 ossdevs, sizeof(ossdevs));
5634 device_printf(sc->dev, " |\n");
5635 device_printf(sc->dev, " + <- nid=%d [%s]",
5636 cw->nid, cw->name);
5637 if (strlen(ossdevs) > 0) {
5638 kprintf(" [recsrc: %s]", ossdevs);
5639 }
5640 kprintf("\n");
5641 }
5642 }
5643 }
5644
5645 static void
5646 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
5647 {
5648 nid_t *nids;
5649
5650 if (pcnt > 0) {
5651 device_printf(sc->dev, "\n");
5652 device_printf(sc->dev, " PCM Playback: %d\n", pcnt);
5653 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5654 sc->play.supp_pcm_size_rate);
5655 device_printf(sc->dev, " DAC:");
5656 for (nids = sc->play.io; *nids != -1; nids++)
5657 kprintf(" %d", *nids);
5658 kprintf("\n");
5659 }
5660
5661 if (rcnt > 0) {
5662 device_printf(sc->dev, "\n");
5663 device_printf(sc->dev, " PCM Record: %d\n", rcnt);
5664 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5665 sc->rec.supp_pcm_size_rate);
5666 device_printf(sc->dev, " ADC:");
5667 for (nids = sc->rec.io; *nids != -1; nids++)
5668 kprintf(" %d", *nids);
5669 kprintf("\n");
5670 }
5671 }
5672
5673 static void
5674 hdac_release_resources(struct hdac_softc *sc)
5675 {
5676 struct hdac_devinfo *devinfo = NULL;
5677 device_t *devlist = NULL;
5678 int i, devcount;
5679
5680 if (sc == NULL)
5681 return;
5682
5683 hdac_lock(sc);
5684 sc->polling = 0;
5685 sc->poll_ival = 0;
5686 callout_stop(&sc->poll_hda);
5687 callout_stop(&sc->poll_hdac);
5688 callout_stop(&sc->poll_jack);
5689 hdac_reset(sc);
5690 hdac_unlock(sc);
5691
5692 hdac_irq_free(sc);
5693
5694 /* give pending interrupts stuck on the lock a chance to clear */
5695 /* bad hack */
5696 tsleep(&sc->irq, 0, "hdaslp", hz / 10);
5697
5698 device_get_children(sc->dev, &devlist, &devcount);
5699 for (i = 0; devlist != NULL && i < devcount; i++) {
5700 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
5701 if (devinfo == NULL)
5702 continue;
5703 if (devinfo->widget != NULL)
5704 kfree(devinfo->widget, M_HDAC);
5705 if (devinfo->node_type ==
5706 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
5707 devinfo->function.audio.ctl != NULL)
5708 kfree(devinfo->function.audio.ctl, M_HDAC);
5709 kfree(devinfo, M_HDAC);
5710 device_delete_child(sc->dev, devlist[i]);
5711 }
5712 if (devlist != NULL)
5713 kfree(devlist, M_TEMP);
5714
5715 for (i = 0; i < HDAC_CODEC_MAX; i++) {
5716 if (sc->codecs[i] != NULL)
5717 kfree(sc->codecs[i], M_HDAC);
5718 sc->codecs[i] = NULL;
5719 }
5720
5721 hdac_dma_free(sc, &sc->pos_dma);
5722 hdac_dma_free(sc, &sc->rirb_dma);
5723 hdac_dma_free(sc, &sc->corb_dma);
5724 if (sc->play.blkcnt > 0)
5725 hdac_dma_free(sc, &sc->play.bdl_dma);
5726 if (sc->rec.blkcnt > 0)
5727 hdac_dma_free(sc, &sc->rec.bdl_dma);
5728 if (sc->chan_dmat != NULL) {
5729 bus_dma_tag_destroy(sc->chan_dmat);
5730 sc->chan_dmat = NULL;
5731 }
5732 hdac_mem_free(sc);
5733 snd_mtxfree(sc->lock);
5734 kfree(sc, M_DEVBUF);
5735 }
5736
5737 /* This function surely going to make its way into upper level someday. */
5738 static void
5739 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
5740 {
5741 char *res = NULL;
5742 int i = 0, j, k, len, inv;
5743
5744 if (on != NULL)
5745 *on = 0;
5746 if (off != NULL)
5747 *off = 0;
5748 if (sc == NULL)
5749 return;
5750 if (resource_string_value(device_get_name(sc->dev),
5751 device_get_unit(sc->dev), "config", &res) != 0)
5752 return;
5753 if (!(res != NULL && strlen(res) > 0))
5754 return;
5755 HDA_BOOTVERBOSE(
5756 device_printf(sc->dev, "HDA_DEBUG: HDA Config:");
5757 );
5758 for (;;) {
5759 while (res[i] != '\0' &&
5760 (res[i] == ',' || isspace(res[i]) != 0))
5761 i++;
5762 if (res[i] == '\0') {
5763 HDA_BOOTVERBOSE(
5764 kprintf("\n");
5765 );
5766 return;
5767 }
5768 j = i;
5769 while (res[j] != '\0' &&
5770 !(res[j] == ',' || isspace(res[j]) != 0))
5771 j++;
5772 len = j - i;
5773 if (len > 2 && strncmp(res + i, "no", 2) == 0)
5774 inv = 2;
5775 else
5776 inv = 0;
5777 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
5778 if (strncmp(res + i + inv,
5779 hdac_quirks_tab[k].key, len - inv) != 0)
5780 continue;
5781 if (len - inv != strlen(hdac_quirks_tab[k].key))
5782 break;
5783 HDA_BOOTVERBOSE(
5784 kprintf(" %s%s", (inv != 0) ? "no" : "",
5785 hdac_quirks_tab[k].key);
5786 );
5787 if (inv == 0 && on != NULL)
5788 *on |= hdac_quirks_tab[k].value;
5789 else if (inv != 0 && off != NULL)
5790 *off |= hdac_quirks_tab[k].value;
5791 break;
5792 }
5793 i = j;
5794 }
5795 }
5796
5797 #ifdef SND_DYNSYSCTL
5798 static int
5799 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
5800 {
5801 struct hdac_softc *sc;
5802 struct hdac_devinfo *devinfo;
5803 device_t dev;
5804 uint32_t ctl;
5805 int err, val;
5806
5807 dev = oidp->oid_arg1;
5808 devinfo = pcm_getdevinfo(dev);
5809 if (devinfo == NULL || devinfo->codec == NULL ||
5810 devinfo->codec->sc == NULL)
5811 return (EINVAL);
5812 sc = devinfo->codec->sc;
5813 hdac_lock(sc);
5814 val = sc->polling;
5815 hdac_unlock(sc);
5816 err = sysctl_handle_int(oidp, &val, 0, req);
5817
5818 if (err != 0 || req->newptr == NULL)
5819 return (err);
5820 if (val < 0 || val > 1)
5821 return (EINVAL);
5822
5823 hdac_lock(sc);
5824 if (val != sc->polling) {
5825 if (hda_chan_active(sc) != 0)
5826 err = EBUSY;
5827 else if (val == 0) {
5828 callout_stop(&sc->poll_hdac);
5829 hdac_unlock(sc);
5830 hdac_lock(sc);
5831 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT,
5832 sc->rirb_size / 2);
5833 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5834 ctl |= HDAC_RIRBCTL_RINTCTL;
5835 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5836 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
5837 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
5838 sc->polling = 0;
5839 DELAY(1000);
5840 } else {
5841 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0);
5842 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0);
5843 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5844 ctl &= ~HDAC_RIRBCTL_RINTCTL;
5845 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5846 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback,
5847 sc);
5848 sc->polling = 1;
5849 DELAY(1000);
5850 }
5851 }
5852 hdac_unlock(sc);
5853
5854 return (err);
5855 }
5856
5857 static int
5858 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
5859 {
5860 struct hdac_softc *sc;
5861 struct hdac_devinfo *devinfo;
5862 device_t dev;
5863 int err, val;
5864
5865 dev = oidp->oid_arg1;
5866 devinfo = pcm_getdevinfo(dev);
5867 if (devinfo == NULL || devinfo->codec == NULL ||
5868 devinfo->codec->sc == NULL)
5869 return (EINVAL);
5870 sc = devinfo->codec->sc;
5871 hdac_lock(sc);
5872 val = ((uint64_t)sc->poll_ival * 1000) / hz;
5873 hdac_unlock(sc);
5874 err = sysctl_handle_int(oidp, &val, 0, req);
5875
5876 if (err != 0 || req->newptr == NULL)
5877 return (err);
5878
5879 if (val < 1)
5880 val = 1;
5881 if (val > 5000)
5882 val = 5000;
5883 val = ((uint64_t)val * hz) / 1000;
5884 if (val < 1)
5885 val = 1;
5886 if (val > (hz * 5))
5887 val = hz * 5;
5888
5889 hdac_lock(sc);
5890 sc->poll_ival = val;
5891 hdac_unlock(sc);
5892
5893 return (err);
5894 }
5895
5896 #ifdef SND_DEBUG
5897 static int
5898 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
5899 {
5900 struct hdac_softc *sc;
5901 struct hdac_devinfo *devinfo;
5902 struct hdac_widget *w;
5903 device_t dev;
5904 uint32_t res, pincap, execres;
5905 int i, err, val;
5906 nid_t cad;
5907
5908 dev = oidp->oid_arg1;
5909 devinfo = pcm_getdevinfo(dev);
5910 if (devinfo == NULL || devinfo->codec == NULL ||
5911 devinfo->codec->sc == NULL)
5912 return (EINVAL);
5913 val = 0;
5914 err = sysctl_handle_int(oidp, &val, 0, req);
5915 if (err != 0 || req->newptr == NULL || val == 0)
5916 return (err);
5917 sc = devinfo->codec->sc;
5918 cad = devinfo->codec->cad;
5919 hdac_lock(sc);
5920 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid);
5921 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5922 w = hdac_widget_get(devinfo, i);
5923 if (w == NULL || w->type !=
5924 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5925 continue;
5926 pincap = w->wclass.pin.cap;
5927 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) ||
5928 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) &&
5929 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) {
5930 timeout = 10000;
5931 hdac_command(sc,
5932 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad);
5933 do {
5934 res = hdac_command(sc,
5935 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
5936 if (res != 0x7fffffff)
5937 break;
5938 DELAY(10);
5939 } while (--timeout != 0);
5940 } else {
5941 timeout = -1;
5942 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad,
5943 w->nid), cad);
5944 }
5945 device_printf(dev,
5946 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n",
5947 w->nid, timeout, res,
5948 (w->enable == 0) ? "DISABLED" : "ENABLED");
5949 }
5950 device_printf(dev,
5951 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
5952 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
5953 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
5954 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
5955 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
5956 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
5957 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
5958 device_printf(dev, " GPI:");
5959 res = hdac_command(sc,
5960 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
5961 kprintf(" data=0x%08x", res);
5962 res = hdac_command(sc,
5963 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
5964 cad);
5965 kprintf(" wake=0x%08x", res);
5966 res = hdac_command(sc,
5967 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
5968 cad);
5969 kprintf(" unsol=0x%08x", res);
5970 res = hdac_command(sc,
5971 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
5972 kprintf(" sticky=0x%08x\n", res);
5973 }
5974 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
5975 device_printf(dev, " GPO:");
5976 res = hdac_command(sc,
5977 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
5978 kprintf(" data=0x%08x\n", res);
5979 }
5980 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
5981 device_printf(dev, "GPI0:");
5982 res = hdac_command(sc,
5983 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
5984 kprintf(" data=0x%08x", res);
5985 res = hdac_command(sc,
5986 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
5987 kprintf(" enable=0x%08x", res);
5988 res = hdac_command(sc,
5989 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
5990 kprintf(" direction=0x%08x\n", res);
5991 res = hdac_command(sc,
5992 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
5993 device_printf(dev, " wake=0x%08x", res);
5994 res = hdac_command(sc,
5995 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
5996 cad);
5997 kprintf(" unsol=0x%08x", res);
5998 res = hdac_command(sc,
5999 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
6000 kprintf(" sticky=0x%08x\n", res);
6001 }
6002 hdac_unlock(sc);
6003 return (0);
6004 }
6005 #endif
6006 #endif
6007
6008 static void
6009 hdac_attach2(void *arg)
6010 {
6011 struct hdac_softc *sc;
6012 struct hdac_widget *w;
6013 struct hdac_audio_ctl *ctl;
6014 uint32_t quirks_on, quirks_off;
6015 int pcnt, rcnt;
6016 int i;
6017 char status[SND_STATUSLEN];
6018 device_t *devlist = NULL;
6019 int devcount;
6020 struct hdac_devinfo *devinfo = NULL;
6021
6022 sc = (struct hdac_softc *)arg;
6023
6024 hdac_config_fetch(sc, &quirks_on, &quirks_off);
6025
6026 HDA_BOOTVERBOSE(
6027 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n",
6028 quirks_on, quirks_off);
6029 );
6030
6031 hdac_lock(sc);
6032
6033 /* Remove ourselves from the config hooks */
6034 if (sc->intrhook.ich_func != NULL) {
6035 config_intrhook_disestablish(&sc->intrhook);
6036 sc->intrhook.ich_func = NULL;
6037 }
6038
6039 /* Start the corb and rirb engines */
6040 HDA_BOOTVERBOSE(
6041 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n");
6042 );
6043 hdac_corb_start(sc);
6044 HDA_BOOTVERBOSE(
6045 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n");
6046 );
6047 hdac_rirb_start(sc);
6048
6049 HDA_BOOTVERBOSE(
6050 device_printf(sc->dev,
6051 "HDA_DEBUG: Enabling controller interrupt...\n");
6052 );
6053 if (sc->polling == 0)
6054 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
6055 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
6056 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
6057 HDAC_GCTL_UNSOL);
6058
6059 DELAY(1000);
6060
6061 HDA_BOOTVERBOSE(
6062 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n");
6063 );
6064 hdac_scan_codecs(sc);
6065
6066 device_get_children(sc->dev, &devlist, &devcount);
6067 for (i = 0; devlist != NULL && i < devcount; i++) {
6068 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
6069 if (devinfo != NULL && devinfo->node_type ==
6070 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
6071 break;
6072 } else
6073 devinfo = NULL;
6074 }
6075 if (devlist != NULL)
6076 kfree(devlist, M_TEMP);
6077
6078 if (devinfo == NULL) {
6079 hdac_unlock(sc);
6080 device_printf(sc->dev, "Audio Function Group not found!\n");
6081 hdac_release_resources(sc);
6082 return;
6083 }
6084
6085 HDA_BOOTVERBOSE(
6086 device_printf(sc->dev,
6087 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n",
6088 devinfo->nid, devinfo->codec->cad);
6089 );
6090 hdac_audio_parse(devinfo);
6091 HDA_BOOTVERBOSE(
6092 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n");
6093 );
6094 hdac_audio_ctl_parse(devinfo);
6095 HDA_BOOTVERBOSE(
6096 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n");
6097 );
6098 hdac_vendor_patch_parse(devinfo);
6099 if (quirks_on != 0)
6100 devinfo->function.audio.quirks |= quirks_on;
6101 if (quirks_off != 0)
6102 devinfo->function.audio.quirks &= ~quirks_off;
6103
6104 /* XXX Disable all DIGITAL path. */
6105 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6106 w = hdac_widget_get(devinfo, i);
6107 if (w == NULL)
6108 continue;
6109 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
6110 w->enable = 0;
6111 continue;
6112 }
6113 /* XXX Disable useless pin ? */
6114 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6115 (w->wclass.pin.config &
6116 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
6117 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
6118 w->enable = 0;
6119 }
6120 i = 0;
6121 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6122 if (ctl->widget == NULL)
6123 continue;
6124 if (ctl->ossmask & SOUND_MASK_DISABLE)
6125 ctl->enable = 0;
6126 w = ctl->widget;
6127 if (w->enable == 0 ||
6128 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6129 ctl->enable = 0;
6130 w = ctl->childwidget;
6131 if (w == NULL)
6132 continue;
6133 if (w->enable == 0 ||
6134 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6135 ctl->enable = 0;
6136 }
6137
6138 HDA_BOOTVERBOSE(
6139 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n");
6140 );
6141 hdac_audio_build_tree(devinfo);
6142
6143 i = 0;
6144 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6145 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))
6146 ctl->ossmask = 0;
6147 }
6148 HDA_BOOTVERBOSE(
6149 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n");
6150 );
6151 hdac_audio_commit(devinfo, HDA_COMMIT_ALL);
6152 HDA_BOOTVERBOSE(
6153 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n");
6154 );
6155 hdac_audio_ctl_commit(devinfo);
6156
6157 HDA_BOOTVERBOSE(
6158 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n");
6159 );
6160 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY);
6161 HDA_BOOTVERBOSE(
6162 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n");
6163 );
6164 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC);
6165
6166 hdac_unlock(sc);
6167 HDA_BOOTVERBOSE(
6168 device_printf(sc->dev,
6169 "HDA_DEBUG: OSS mixer initialization...\n");
6170 );
6171
6172 /*
6173 * There is no point of return after this. If the driver failed,
6174 * so be it. Let the detach procedure do all the cleanup.
6175 */
6176 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0)
6177 device_printf(sc->dev, "Can't register mixer\n");
6178
6179 if (pcnt > 0)
6180 pcnt = 1;
6181 if (rcnt > 0)
6182 rcnt = 1;
6183
6184 HDA_BOOTVERBOSE(
6185 device_printf(sc->dev,
6186 "HDA_DEBUG: Registering PCM channels...\n");
6187 );
6188 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0)
6189 device_printf(sc->dev, "Can't register PCM\n");
6190
6191 sc->registered++;
6192
6193 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
6194 hdac_dma_alloc(sc, &sc->pos_dma,
6195 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
6196 HDA_BOOTVERBOSE(
6197 device_printf(sc->dev,
6198 "Failed to allocate DMA pos buffer (non-fatal)\n");
6199 );
6200 }
6201
6202 for (i = 0; i < pcnt; i++)
6203 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo);
6204 for (i = 0; i < rcnt; i++)
6205 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo);
6206
6207 #ifdef SND_DYNSYSCTL
6208 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6209 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6210 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6211 sysctl_hdac_polling, "I", "Enable polling mode");
6212 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6213 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6214 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
6215 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
6216 "Controller/Jack Sense polling interval (1-1000 ms)");
6217 #ifdef SND_DEBUG
6218 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6219 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6220 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6221 sysctl_hdac_pindump, "I", "Dump pin states/data");
6222 #endif
6223 #endif
6224
6225 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]",
6226 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res),
6227 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV);
6228 pcm_setstatus(sc->dev, status);
6229 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo));
6230 HDA_BOOTVERBOSE(
6231 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n",
6232 hdac_codec_id(devinfo));
6233 );
6234 device_printf(sc->dev, "<HDA Driver Revision: %s>\n",
6235 HDA_DRV_TEST_REV);
6236
6237 HDA_BOOTVERBOSE(
6238 if (devinfo->function.audio.quirks != 0) {
6239 device_printf(sc->dev, "\n");
6240 device_printf(sc->dev, "HDA config/quirks:");
6241 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
6242 if ((devinfo->function.audio.quirks &
6243 hdac_quirks_tab[i].value) ==
6244 hdac_quirks_tab[i].value)
6245 kprintf(" %s", hdac_quirks_tab[i].key);
6246 }
6247 kprintf("\n");
6248 }
6249 device_printf(sc->dev, "\n");
6250 device_printf(sc->dev, "+-------------------+\n");
6251 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
6252 device_printf(sc->dev, "+-------------------+\n");
6253 hdac_dump_nodes(devinfo);
6254 device_printf(sc->dev, "\n");
6255 device_printf(sc->dev, "+------------------------+\n");
6256 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
6257 device_printf(sc->dev, "+------------------------+\n");
6258 device_printf(sc->dev, "\n");
6259 i = 0;
6260 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6261 device_printf(sc->dev, "%3d: nid=%d", i,
6262 (ctl->widget != NULL) ? ctl->widget->nid : -1);
6263 if (ctl->childwidget != NULL)
6264 kprintf(" cnid=%d", ctl->childwidget->nid);
6265 kprintf(" dir=0x%x index=%d "
6266 "ossmask=0x%08x ossdev=%d%s\n",
6267 ctl->dir, ctl->index,
6268 ctl->ossmask, ctl->ossdev,
6269 (ctl->enable == 0) ? " [DISABLED]" : "");
6270 }
6271 device_printf(sc->dev, "\n");
6272 device_printf(sc->dev, "+-----------------------------------+\n");
6273 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n");
6274 device_printf(sc->dev, "+-----------------------------------+\n");
6275 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME);
6276 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM);
6277 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD);
6278 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC);
6279 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE);
6280 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV);
6281 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER);
6282 hdac_dump_ctls(devinfo, NULL, 0);
6283 hdac_dump_dac(devinfo);
6284 hdac_dump_adc(devinfo);
6285 device_printf(sc->dev, "\n");
6286 device_printf(sc->dev, "+--------------------------------------+\n");
6287 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n");
6288 device_printf(sc->dev, "+--------------------------------------+\n");
6289 hdac_dump_pcmchannels(sc, pcnt, rcnt);
6290 );
6291
6292 if (sc->polling != 0) {
6293 hdac_lock(sc);
6294 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
6295 hdac_unlock(sc);
6296 }
6297 }
6298
6299 /****************************************************************************
6300 * int hdac_detach(device_t)
6301 *
6302 * Detach and free up resources utilized by the hdac device.
6303 ****************************************************************************/
6304 static int
6305 hdac_detach(device_t dev)
6306 {
6307 struct hdac_softc *sc = NULL;
6308 struct hdac_devinfo *devinfo = NULL;
6309 int err;
6310
6311 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev);
6312 if (devinfo != NULL && devinfo->codec != NULL)
6313 sc = devinfo->codec->sc;
6314 if (sc == NULL)
6315 return (0);
6316
6317 if (sc->registered > 0) {
6318 err = pcm_unregister(dev);
6319 if (err != 0)
6320 return (err);
6321 }
6322
6323 hdac_release_resources(sc);
6324
6325 return (0);
6326 }
6327
6328 static device_method_t hdac_methods[] = {
6329 /* device interface */
6330 DEVMETHOD(device_probe, hdac_probe),
6331 DEVMETHOD(device_attach, hdac_attach),
6332 DEVMETHOD(device_detach, hdac_detach),
6333 { 0, 0 }
6334 };
6335
6336 static driver_t hdac_driver = {
6337 "pcm",
6338 hdac_methods,
6339 PCM_SOFTC_SIZE,
6340 };
6341
6342 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0);
6343 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
6344 MODULE_VERSION(snd_hda, 1);
DragonFly BSD