2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/ar/if_ar.c,v 1.66 2005/01/06 01:42:28 imp Exp $
29 * $DragonFly: src/sys/dev/netif/ar/if_ar.c,v 1.23 2008/01/06 16:55:50 swildner Exp $
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
48 #include "opt_netgraph.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
59 #include <sys/serialize.h>
61 #include <sys/thread2.h>
65 #include <netgraph/ng_message.h>
66 #include <netgraph/netgraph.h>
67 #include <sys/syslog.h>
68 #include <dev/netif/ar/if_ar.h>
70 #include <net/if_arp.h>
71 #include <net/sppp/if_sppp.h>
75 #include <machine/md_var.h>
77 #include <dev/netif/ic_layer/hd64570.h>
78 #include <dev/netif/ar/if_arregs.h>
88 #define PPP_HEADER_LEN 4
90 devclass_t ar_devclass
;
96 int unit
; /* With regards to all ar devices */
97 int subunit
; /* With regards to this card */
101 u_int txdesc
; /* On card address */
102 u_int txstart
; /* On card address */
103 u_int txend
; /* On card address */
104 u_int txtail
; /* Index of first unused buffer */
105 u_int txmax
; /* number of usable buffers/descriptors */
106 u_int txeda
; /* Error descriptor addresses */
107 }block
[AR_TX_BLOCKS
];
109 char xmit_busy
; /* Transmitter is busy */
110 char txb_inuse
; /* Number of tx blocks currently in use */
111 u_char txb_new
; /* Index to where new buffer will be added */
112 u_char txb_next_tx
; /* Index to next block ready to tx */
114 u_int rxdesc
; /* On card address */
115 u_int rxstart
; /* On card address */
116 u_int rxend
; /* On card address */
117 u_int rxhind
; /* Index to the head of the rx buffers. */
118 u_int rxmax
; /* number of usable buffers/descriptors */
124 int running
; /* something is attached so we are running */
125 int dcd
; /* do we have dcd? */
126 /* ---netgraph bits --- */
127 char nodename
[NG_NODESIZ
]; /* store our node name */
128 int datahooks
; /* number of data hooks attached */
129 node_p node
; /* netgraph node */
130 hook_p hook
; /* data hook */
132 struct ifqueue xmitq_hipri
; /* hi-priority transmit queue */
133 struct ifqueue xmitq
; /* transmit queue */
134 int flags
; /* state */
135 #define SCF_RUNNING 0x01 /* board is active */
136 #define SCF_OACTIVE 0x02 /* output is active */
137 int out_dog
; /* watchdog cycles output count-down */
138 struct callout timer
; /* watchdog timer */
139 u_long inbytes
, outbytes
; /* stats */
140 u_long lastinbytes
, lastoutbytes
; /* a second ago */
141 u_long inrate
, outrate
; /* highest rate seen */
142 u_long inlast
; /* last input N secs ago */
143 u_long out_deficit
; /* output since last input */
144 u_long oerrors
, ierrors
[6];
145 u_long opackets
, ipackets
;
146 #endif /* NETGRAPH */
149 static int next_ar_unit
= 0;
150 static struct lwkt_serialize ar_serializer
;
153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
154 #define QUITE_A_WHILE 300 /* 5 MINUTES */
155 #define LOTS_OF_PACKETS 100
156 #endif /* NETGRAPH */
159 * This translate from irq numbers to
160 * the value that the arnet card needs
161 * in the lower part of the AR_INT_SEL
164 static int irqtable
[16] = {
184 DECLARE_DUMMY_MODULE(if_ar
);
185 MODULE_DEPEND(if_ar
, sppp
, 1, 1, 1);
187 MODULE_DEPEND(ng_sync_ar
, netgraph
, NG_ABI_VERSION
, NG_ABI_VERSION
, NG_ABI_VERSION
);
190 static void arintr(void *arg
);
191 static void ar_xmit(struct ar_softc
*sc
);
193 static void arstart(struct ifnet
*ifp
);
194 static int arioctl(struct ifnet
*ifp
, u_long cmd
, caddr_t data
, struct ucred
*);
195 static void arwatchdog(struct ifnet
*ifp
);
197 static void arstart(struct ar_softc
*sc
);
198 static void arwatchdog(struct ar_softc
*sc
);
199 #endif /* NETGRAPH */
200 static int ar_packet_avail(struct ar_softc
*sc
, int *len
, u_char
*rxstat
);
201 static void ar_copy_rxbuf(struct mbuf
*m
, struct ar_softc
*sc
, int len
);
202 static void ar_eat_packet(struct ar_softc
*sc
, int single
);
203 static void ar_get_packets(struct ar_softc
*sc
);
205 static int ar_read_pim_iface(volatile struct ar_hardc
*hc
, int channel
);
206 static void ar_up(struct ar_softc
*sc
);
207 static void ar_down(struct ar_softc
*sc
);
208 static void arc_init(struct ar_hardc
*hc
);
209 static void ar_init_sca(struct ar_hardc
*hc
, int scano
);
210 static void ar_init_msci(struct ar_softc
*sc
);
211 static void ar_init_rx_dmac(struct ar_softc
*sc
);
212 static void ar_init_tx_dmac(struct ar_softc
*sc
);
213 static void ar_dmac_intr(struct ar_hardc
*hc
, int scano
, u_char isr
);
214 static void ar_msci_intr(struct ar_hardc
*hc
, int scano
, u_char isr
);
215 static void ar_timer_intr(struct ar_hardc
*hc
, int scano
, u_char isr
);
218 static void ngar_watchdog_frame(void * arg
);
219 static void ngar_init(void* ignored
);
221 static ng_constructor_t ngar_constructor
;
222 static ng_rcvmsg_t ngar_rcvmsg
;
223 static ng_shutdown_t ngar_shutdown
;
224 static ng_newhook_t ngar_newhook
;
225 /*static ng_findhook_t ngar_findhook; */
226 static ng_connect_t ngar_connect
;
227 static ng_rcvdata_t ngar_rcvdata
;
228 static ng_disconnect_t ngar_disconnect
;
230 static struct ng_type typestruct
= {
246 static int ngar_done_init
= 0;
247 #endif /* NETGRAPH */
250 ar_attach(device_t device
)
257 #endif /* NETGRAPH */
261 hc
= (struct ar_hardc
*)device_get_softc(device
);
262 lwkt_serialize_init(&ar_serializer
);
264 kprintf("arc%d: %uK RAM, %u ports, rev %u.\n",
272 error
= BUS_SETUP_INTR(device_get_parent(device
), device
, hc
->res_irq
,
274 &hc
->intr_cookie
, &ar_serializer
);
280 for(unit
=0;unit
<hc
->numports
;unit
+=NCHAN
)
281 ar_init_sca(hc
, unit
/ NCHAN
);
284 * Now configure each port on the card.
286 for(unit
=0;unit
<hc
->numports
;sc
++,unit
++) {
289 sc
->unit
= next_ar_unit
;
291 sc
->scano
= unit
/ NCHAN
;
292 sc
->scachan
= unit
%NCHAN
;
299 ifp
= &sc
->ifsppp
.pp_if
;
302 if_initname(ifp
, device_get_name(device
), sc
->unit
);
303 ifp
->if_mtu
= PP_MTU
;
304 ifp
->if_flags
= IFF_POINTOPOINT
| IFF_MULTICAST
;
305 ifp
->if_ioctl
= arioctl
;
306 ifp
->if_start
= arstart
;
307 ifp
->if_watchdog
= arwatchdog
;
309 sc
->ifsppp
.pp_flags
= PP_KEEPALIVE
;
311 switch(hc
->interface
[unit
]) {
312 default: iface
= "UNKNOWN"; break;
313 case AR_IFACE_EIA_232
: iface
= "EIA-232"; break;
314 case AR_IFACE_V_35
: iface
= "EIA-232 or V.35"; break;
315 case AR_IFACE_EIA_530
: iface
= "EIA-530"; break;
316 case AR_IFACE_X_21
: iface
= "X.21"; break;
317 case AR_IFACE_COMBO
: iface
= "COMBO X.21 / EIA-530"; break;
320 kprintf("ar%d: Adapter %d, port %d, interface %s.\n",
326 sppp_attach((struct ifnet
*)&sc
->ifsppp
);
327 if_attach(ifp
, &ar_serializer
);
329 bpfattach(ifp
, DLT_PPP
, PPP_HEADER_LEN
);
332 * we have found a node, make sure our 'type' is availabe.
334 if (ngar_done_init
== 0) ngar_init(NULL
);
335 if (ng_make_node_common(&typestruct
, &sc
->node
) != 0)
337 ksprintf(sc
->nodename
, "%s%d", NG_AR_NODE_TYPE
, sc
->unit
);
338 if (ng_name_node(sc
->node
, sc
->nodename
)) {
339 NG_NODE_UNREF(sc
->node
); /* drop it again */
342 NG_NODE_SET_PRIVATE(sc
->node
, sc
);
343 callout_init(&sc
->timer
);
344 sc
->xmitq
.ifq_maxlen
= IFQ_MAXLEN
;
345 sc
->xmitq_hipri
.ifq_maxlen
= IFQ_MAXLEN
;
347 #endif /* NETGRAPH */
350 if(hc
->bustype
== AR_BUS_ISA
)
357 ar_detach(device_t device
)
359 device_t parent
= device_get_parent(device
);
360 struct ar_hardc
*hc
= device_get_softc(device
);
363 lwkt_serialize_enter(&ar_serializer
);
365 if (hc
->intr_cookie
!= NULL
) {
366 if (BUS_TEARDOWN_INTR(parent
, device
,
367 hc
->res_irq
, hc
->intr_cookie
) != 0) {
368 kprintf("intr teardown failed.. continuing\n");
370 hc
->intr_cookie
= NULL
;
374 * deallocate any system resources we may have
375 * allocated on behalf of this driver.
377 FREE(hc
->sc
, M_DEVBUF
);
379 hc
->mem_start
= NULL
;
380 error
= ar_deallocate_resources(device
);
381 lwkt_serialize_exit(&ar_serializer
);
387 ar_allocate_ioport(device_t device
, int rid
, u_long size
)
389 struct ar_hardc
*hc
= device_get_softc(device
);
391 hc
->rid_ioport
= rid
;
392 hc
->res_ioport
= bus_alloc_resource(device
, SYS_RES_IOPORT
,
393 &hc
->rid_ioport
, 0ul, ~0ul, size
, RF_ACTIVE
);
394 if (hc
->res_ioport
== NULL
) {
397 hc
->bt
= rman_get_bustag(hc
->res_ioport
);
398 hc
->bh
= rman_get_bushandle(hc
->res_ioport
);
403 ar_deallocate_resources(device
);
408 ar_allocate_irq(device_t device
, int rid
, u_long size
)
410 struct ar_hardc
*hc
= device_get_softc(device
);
413 hc
->res_irq
= bus_alloc_resource_any(device
, SYS_RES_IRQ
,
414 &hc
->rid_irq
, RF_SHAREABLE
|RF_ACTIVE
);
415 if (hc
->res_irq
== NULL
) {
421 ar_deallocate_resources(device
);
426 ar_allocate_memory(device_t device
, int rid
, u_long size
)
428 struct ar_hardc
*hc
= device_get_softc(device
);
430 hc
->rid_memory
= rid
;
431 hc
->res_memory
= bus_alloc_resource(device
, SYS_RES_MEMORY
,
432 &hc
->rid_memory
, 0ul, ~0ul, size
, RF_ACTIVE
);
433 if (hc
->res_memory
== NULL
) {
439 ar_deallocate_resources(device
);
444 ar_allocate_plx_memory(device_t device
, int rid
, u_long size
)
446 struct ar_hardc
*hc
= device_get_softc(device
);
448 hc
->rid_plx_memory
= rid
;
449 hc
->res_plx_memory
= bus_alloc_resource(device
, SYS_RES_MEMORY
,
450 &hc
->rid_plx_memory
, 0ul, ~0ul, size
, RF_ACTIVE
);
451 if (hc
->res_plx_memory
== NULL
) {
457 ar_deallocate_resources(device
);
462 ar_deallocate_resources(device_t device
)
464 struct ar_hardc
*hc
= device_get_softc(device
);
466 if (hc
->res_irq
!= 0) {
467 bus_deactivate_resource(device
, SYS_RES_IRQ
,
468 hc
->rid_irq
, hc
->res_irq
);
469 bus_release_resource(device
, SYS_RES_IRQ
,
470 hc
->rid_irq
, hc
->res_irq
);
473 if (hc
->res_ioport
!= 0) {
474 bus_deactivate_resource(device
, SYS_RES_IOPORT
,
475 hc
->rid_ioport
, hc
->res_ioport
);
476 bus_release_resource(device
, SYS_RES_IOPORT
,
477 hc
->rid_ioport
, hc
->res_ioport
);
480 if (hc
->res_memory
!= 0) {
481 bus_deactivate_resource(device
, SYS_RES_MEMORY
,
482 hc
->rid_memory
, hc
->res_memory
);
483 bus_release_resource(device
, SYS_RES_MEMORY
,
484 hc
->rid_memory
, hc
->res_memory
);
487 if (hc
->res_plx_memory
!= 0) {
488 bus_deactivate_resource(device
, SYS_RES_MEMORY
,
489 hc
->rid_plx_memory
, hc
->res_plx_memory
);
490 bus_release_resource(device
, SYS_RES_MEMORY
,
491 hc
->rid_plx_memory
, hc
->res_plx_memory
);
492 hc
->res_plx_memory
= 0;
498 * First figure out which SCA gave the interrupt.
500 * See if there is other interrupts pending.
501 * Repeat until there is no more interrupts.
506 struct ar_hardc
*hc
= (struct ar_hardc
*)arg
;
508 u_char isr0
, isr1
, isr2
, arisr
;
511 /* XXX Use the PCI interrupt score board register later */
512 if(hc
->bustype
== AR_BUS_PCI
)
513 arisr
= hc
->orbase
[AR_ISTAT
* 4];
515 arisr
= ar_inb(hc
, AR_ISTAT
);
517 while(arisr
& AR_BD_INT
) {
518 TRC(kprintf("arisr = %x\n", arisr
));
521 else if(arisr
& AR_INT_1
)
524 /* XXX Oops this shouldn't happen. */
525 kprintf("arc%d: Interrupted with no interrupt.\n",
529 sca
= hc
->sca
[scano
];
531 if(hc
->bustype
== AR_BUS_ISA
)
532 ARC_SET_SCA(hc
, scano
);
538 TRC(kprintf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
544 ar_msci_intr(hc
, scano
, isr0
);
547 ar_dmac_intr(hc
, scano
, isr1
);
550 ar_timer_intr(hc
, scano
, isr2
);
553 * Proccess the second sca's interrupt if available.
554 * Else see if there are any new interrupts.
556 if((arisr
& AR_INT_0
) && (arisr
& AR_INT_1
))
559 if(hc
->bustype
== AR_BUS_PCI
)
560 arisr
= hc
->orbase
[AR_ISTAT
* 4];
562 arisr
= ar_inb(hc
, AR_ISTAT
);
566 if(hc
->bustype
== AR_BUS_ISA
)
572 * This will only start the transmitter. It is assumed that the data
573 * is already there. It is normally called from arstart() or ar_dmac_intr().
577 ar_xmit(struct ar_softc
*sc
)
581 #endif /* NETGRAPH */
585 ifp
= &sc
->ifsppp
.pp_if
;
586 #endif /* NETGRAPH */
587 dmac
= &sc
->sca
->dmac
[DMAC_TXCH(sc
->scachan
)];
589 if(sc
->hc
->bustype
== AR_BUS_ISA
)
590 ARC_SET_SCA(sc
->hc
, sc
->scano
);
591 dmac
->cda
= (u_short
)(sc
->block
[sc
->txb_next_tx
].txdesc
& 0xffff);
593 dmac
->eda
= (u_short
)(sc
->block
[sc
->txb_next_tx
].txeda
& 0xffff);
594 dmac
->dsr
= SCA_DSR_DE
;
599 if(sc
->txb_next_tx
== AR_TX_BLOCKS
)
603 ifp
->if_timer
= 2; /* Value in seconds. */
605 sc
->out_dog
= DOG_HOLDOFF
; /* give ourself some breathing space*/
606 #endif /* NETGRAPH */
607 if(sc
->hc
->bustype
== AR_BUS_ISA
)
612 * This function will be called from the upper level when a user add a
613 * packet to be send, and from the interrupt handler after a finished
616 * This function only place the data in the oncard buffers. It does not
617 * start the transmition. ar_xmit() does that.
619 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
620 * that clears that should ensure that the transmitter and its DMA is
621 * in a "good" idle state.
625 arstart(struct ifnet
*ifp
)
627 struct ar_softc
*sc
= ifp
->if_softc
;
630 arstart(struct ar_softc
*sc
)
632 #endif /* NETGRAPH */
636 sca_descriptor
*txdesc
;
637 struct buf_block
*blkp
;
640 if(!(ifp
->if_flags
& IFF_RUNNING
))
644 #endif /* NETGRAPH */
649 * See if we have space for more packets.
651 if(sc
->txb_inuse
== AR_TX_BLOCKS
) {
653 ifp
->if_flags
|= IFF_OACTIVE
; /* yes, mark active */
655 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
656 #endif /* NETGRAPH */
661 mtx
= sppp_dequeue(ifp
);
663 IF_DEQUEUE(&sc
->xmitq_hipri
, mtx
);
665 IF_DEQUEUE(&sc
->xmitq
, mtx
);
667 #endif /* NETGRAPH */
672 * It is OK to set the memory window outside the loop because
673 * all tx buffers and descriptors are assumed to be in the same
676 if(sc
->hc
->bustype
== AR_BUS_ISA
)
677 ARC_SET_MEM(sc
->hc
, sc
->block
[0].txdesc
);
680 * We stay in this loop until there is nothing in the
681 * TX queue left or the tx buffer is full.
684 blkp
= &sc
->block
[sc
->txb_new
];
685 txdesc
= (sca_descriptor
*)
686 (sc
->hc
->mem_start
+ (blkp
->txdesc
& sc
->hc
->winmsk
));
687 txdata
= (u_char
*)(sc
->hc
->mem_start
+ (blkp
->txstart
& sc
->hc
->winmsk
));
689 len
= mtx
->m_pkthdr
.len
;
691 TRC(kprintf("ar%d: ARstart len %u\n", sc
->unit
, len
));
694 * We can do this because the tx buffers don't wrap.
696 m_copydata(mtx
, 0, len
, txdata
);
698 while(tlen
> AR_BUF_SIZ
) {
700 txdesc
->len
= AR_BUF_SIZ
;
703 txdata
+= AR_BUF_SIZ
;
706 /* XXX Move into the loop? */
707 txdesc
->stat
= SCA_DESC_EOM
;
710 txdata
+= AR_BUF_SIZ
;
716 ++sc
->ifsppp
.pp_if
.if_opackets
;
721 #endif /* NETGRAPH */
724 * Check if we have space for another mbuf.
725 * XXX This is hardcoded. A packet won't be larger
726 * than 3 buffers (3 x 512).
728 if((i
+ 3) >= blkp
->txmax
)
732 mtx
= sppp_dequeue(ifp
);
734 IF_DEQUEUE(&sc
->xmitq_hipri
, mtx
);
736 IF_DEQUEUE(&sc
->xmitq
, mtx
);
738 #endif /* NETGRAPH */
746 * Mark the last descriptor, so that the SCA know where
750 txdesc
->stat
|= SCA_DESC_EOT
;
752 txdesc
= (sca_descriptor
*)blkp
->txdesc
;
753 blkp
->txeda
= (u_short
)((u_int
)&txdesc
[i
]);
756 kprintf("ARstart: %p desc->cp %x\n", &txdesc
->cp
, txdesc
->cp
);
757 kprintf("ARstart: %p desc->bp %x\n", &txdesc
->bp
, txdesc
->bp
);
758 kprintf("ARstart: %p desc->bpb %x\n", &txdesc
->bpb
, txdesc
->bpb
);
759 kprintf("ARstart: %p desc->len %x\n", &txdesc
->len
, txdesc
->len
);
760 kprintf("ARstart: %p desc->stat %x\n", &txdesc
->stat
, txdesc
->stat
);
765 if(sc
->txb_new
== AR_TX_BLOCKS
)
768 if(sc
->xmit_busy
== 0)
771 if(sc
->hc
->bustype
== AR_BUS_ISA
)
779 arioctl(struct ifnet
*ifp
, u_long cmd
, caddr_t data
, struct ucred
*cr
)
782 int was_up
, should_be_up
;
783 struct ar_softc
*sc
= ifp
->if_softc
;
785 TRC(if_printf(ifp
, "arioctl.\n");)
787 was_up
= ifp
->if_flags
& IFF_RUNNING
;
789 error
= sppp_ioctl(ifp
, cmd
, data
);
790 TRC(if_printf(ifp
, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
791 ((struct sppp
*)ifp
)->pp_flags
, ifp
->if_flags
);)
795 if((cmd
!= SIOCSIFFLAGS
) && cmd
!= (SIOCSIFADDR
))
798 TRC(if_printf(ifp
, "arioctl %s.\n",
799 (cmd
== SIOCSIFFLAGS
) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
801 should_be_up
= ifp
->if_flags
& IFF_RUNNING
;
803 if(!was_up
&& should_be_up
) {
804 /* Interface should be up -- start it. */
807 /* XXX Maybe clear the IFF_UP flag so that the link
808 * will only go up after sppp lcp and ipcp negotiation.
810 } else if(was_up
&& !should_be_up
) {
811 /* Interface should be down -- stop it. */
817 #endif /* NETGRAPH */
820 * This is to catch lost tx interrupts.
824 arwatchdog(struct ifnet
*ifp
)
826 struct ar_softc
*sc
= ifp
->if_softc
;
828 arwatchdog(struct ar_softc
*sc
)
830 #endif /* NETGRAPH */
831 msci_channel
*msci
= &sc
->sca
->msci
[sc
->scachan
];
834 if(!(ifp
->if_flags
& IFF_RUNNING
))
836 #endif /* NETGRAPH */
838 if(sc
->hc
->bustype
== AR_BUS_ISA
)
839 ARC_SET_SCA(sc
->hc
, sc
->scano
);
841 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
842 kprintf("ar%d: transmit failed, "
843 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
848 sc
->sca
->dmac
[DMAC_TXCH(sc
->scachan
)].dsr
);
850 if(msci
->st1
& SCA_ST1_UDRN
) {
851 msci
->cmd
= SCA_CMD_TXABORT
;
852 msci
->cmd
= SCA_CMD_TXENABLE
;
853 msci
->st1
= SCA_ST1_UDRN
;
858 ifp
->if_flags
&= ~IFF_OACTIVE
;
860 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
861 #endif /* NETGRAPH */
863 if(sc
->txb_inuse
&& --sc
->txb_inuse
)
870 #endif /* NETGRAPH */
874 ar_up(struct ar_softc
*sc
)
880 msci
= &sca
->msci
[sc
->scachan
];
882 TRC(kprintf("ar%d: sca %p, msci %p, ch %d\n",
883 sc
->unit
, sca
, msci
, sc
->scachan
));
886 * Enable transmitter and receiver.
890 if(sc
->hc
->bustype
== AR_BUS_ISA
)
891 ARC_SET_SCA(sc
->hc
, sc
->scano
);
894 * What about using AUTO mode in msci->md0 ???
895 * And what about CTS/DCD etc... ?
897 if(sc
->hc
->handshake
& AR_SHSK_RTS
)
898 msci
->ctl
&= ~SCA_CTL_RTS
;
899 if(sc
->hc
->handshake
& AR_SHSK_DTR
) {
900 sc
->hc
->txc_dtr
[sc
->scano
] &= sc
->scachan
?
901 ~AR_TXC_DTR_DTR1
: ~AR_TXC_DTR_DTR0
;
902 if(sc
->hc
->bustype
== AR_BUS_PCI
)
903 sc
->hc
->orbase
[sc
->hc
->txc_dtr_off
[sc
->scano
]] =
904 sc
->hc
->txc_dtr
[sc
->scano
];
906 ar_outb(sc
->hc
, sc
->hc
->txc_dtr_off
[sc
->scano
],
907 sc
->hc
->txc_dtr
[sc
->scano
]);
910 if(sc
->scachan
== 0) {
918 msci
->cmd
= SCA_CMD_RXENABLE
;
919 if(sc
->hc
->bustype
== AR_BUS_ISA
)
920 ar_inb(sc
->hc
, AR_ID_5
); /* XXX slow it down a bit. */
921 msci
->cmd
= SCA_CMD_TXENABLE
;
923 if(sc
->hc
->bustype
== AR_BUS_ISA
)
926 callout_reset(&sc
->timer
, hz
, ngar_watchdog_frame
, sc
);
928 #endif /* NETGRAPH */
932 ar_down(struct ar_softc
*sc
)
938 msci
= &sca
->msci
[sc
->scachan
];
941 callout_stop(&sc
->timer
);
943 #endif /* NETGRAPH */
945 * Disable transmitter and receiver.
947 * Disable interrupts.
949 if(sc
->hc
->bustype
== AR_BUS_ISA
)
950 ARC_SET_SCA(sc
->hc
, sc
->scano
);
951 msci
->cmd
= SCA_CMD_RXDISABLE
;
952 if(sc
->hc
->bustype
== AR_BUS_ISA
)
953 ar_inb(sc
->hc
, AR_ID_5
); /* XXX slow it down a bit. */
954 msci
->cmd
= SCA_CMD_TXDISABLE
;
956 if(sc
->hc
->handshake
& AR_SHSK_RTS
)
957 msci
->ctl
|= SCA_CTL_RTS
;
958 if(sc
->hc
->handshake
& AR_SHSK_DTR
) {
959 sc
->hc
->txc_dtr
[sc
->scano
] |= sc
->scachan
?
960 AR_TXC_DTR_DTR1
: AR_TXC_DTR_DTR0
;
961 if(sc
->hc
->bustype
== AR_BUS_PCI
)
962 sc
->hc
->orbase
[sc
->hc
->txc_dtr_off
[sc
->scano
]] =
963 sc
->hc
->txc_dtr
[sc
->scano
];
965 ar_outb(sc
->hc
, sc
->hc
->txc_dtr_off
[sc
->scano
],
966 sc
->hc
->txc_dtr
[sc
->scano
]);
969 if(sc
->scachan
== 0) {
977 if(sc
->hc
->bustype
== AR_BUS_ISA
)
982 ar_read_pim_iface(volatile struct ar_hardc
*hc
, int channel
)
984 int ctype
, i
, val
, x
;
985 volatile u_char
*pimctrl
;
990 pimctrl
= hc
->orbase
+ AR_PIMCTRL
;
994 *pimctrl
= AR_PIM_STROBE
;
996 /* Check if there is a PIM */
998 *pimctrl
= AR_PIM_READ
;
1000 TRC(kprintf("x = %x", x
));
1001 if(x
& AR_PIM_DATA
) {
1002 kprintf("No PIM installed\n");
1003 return (AR_IFACE_UNKNOWN
);
1006 x
= (x
>> 1) & 0x01;
1009 /* Now read the next 15 bits */
1010 for(i
= 1; i
< 16; i
++) {
1011 *pimctrl
= AR_PIM_READ
;
1012 *pimctrl
= AR_PIM_READ
| AR_PIM_STROBE
;
1014 TRC(kprintf(" %x ", x
));
1015 x
= (x
>> 1) & 0x01;
1017 if(i
== 8 && (val
& 0x000f) == 0x0004) {
1021 *pimctrl
= AR_PIM_A2D_DOUT
| AR_PIM_A2D_STROBE
;
1022 *pimctrl
= AR_PIM_A2D_DOUT
;
1025 *pimctrl
= AR_PIM_A2D_DOUT
| AR_PIM_A2D_STROBE
;
1026 *pimctrl
= AR_PIM_A2D_DOUT
;
1029 *pimctrl
= AR_PIM_A2D_DOUT
| AR_PIM_A2D_STROBE
;
1030 *pimctrl
= AR_PIM_A2D_DOUT
;
1032 /* Select channel */
1033 *pimctrl
= AR_PIM_A2D_STROBE
| ((channel
& 2) << 2);
1034 *pimctrl
= ((channel
& 2) << 2);
1035 *pimctrl
= AR_PIM_A2D_STROBE
| ((channel
& 1) << 3);
1036 *pimctrl
= ((channel
& 1) << 3);
1038 *pimctrl
= AR_PIM_A2D_STROBE
;
1042 kprintf("\nOops A2D start bit not zero (%X)\n", x
);
1044 for(ii
= 7; ii
>= 0; ii
--) {
1046 *pimctrl
= AR_PIM_A2D_STROBE
;
1053 TRC(kprintf("\nPIM val %x, ctype %x, %d\n", val
, ctype
, ctype
));
1054 *pimctrl
= AR_PIM_MODEG
;
1055 *pimctrl
= AR_PIM_MODEG
| AR_PIM_AUTO_LED
;
1057 return (AR_IFACE_UNKNOWN
);
1059 return (AR_IFACE_V_35
);
1061 return (AR_IFACE_EIA_232
);
1063 return (AR_IFACE_X_21
);
1065 return (AR_IFACE_EIA_530
);
1067 return (AR_IFACE_UNKNOWN
);
1069 return (AR_IFACE_LOOPBACK
);
1070 return (AR_IFACE_UNKNOWN
);
1074 * Initialize the card, allocate memory for the ar_softc structures
1075 * and fill in the pointers.
1078 arc_init(struct ar_hardc
*hc
)
1080 struct ar_softc
*sc
;
1089 MALLOC(sc
, struct ar_softc
*, hc
->numports
* sizeof(struct ar_softc
),
1090 M_DEVBUF
, M_WAITOK
| M_ZERO
);
1093 hc
->txc_dtr
[0] = AR_TXC_DTR_NOTRESET
|
1094 AR_TXC_DTR_DTR0
| AR_TXC_DTR_DTR1
;
1095 hc
->txc_dtr
[1] = AR_TXC_DTR_DTR0
| AR_TXC_DTR_DTR1
;
1096 hc
->txc_dtr_off
[0] = AR_TXC_DTR0
;
1097 hc
->txc_dtr_off
[1] = AR_TXC_DTR2
;
1098 if(hc
->bustype
== AR_BUS_PCI
) {
1099 hc
->txc_dtr_off
[0] *= 4;
1100 hc
->txc_dtr_off
[1] *= 4;
1104 * reset the card and wait at least 1uS.
1106 if(hc
->bustype
== AR_BUS_PCI
)
1107 hc
->orbase
[AR_TXC_DTR0
* 4] = ~AR_TXC_DTR_NOTRESET
&
1110 ar_outb(hc
, AR_TXC_DTR0
, ~AR_TXC_DTR_NOTRESET
&
1113 if(hc
->bustype
== AR_BUS_PCI
)
1114 hc
->orbase
[AR_TXC_DTR0
* 4] = hc
->txc_dtr
[0];
1116 ar_outb(hc
, AR_TXC_DTR0
, hc
->txc_dtr
[0]);
1118 if(hc
->bustype
== AR_BUS_ISA
) {
1120 * Configure the card.
1123 memst
= rman_get_start(hc
->res_memory
);
1125 isr
= irqtable
[hc
->isa_irq
] << 1;
1127 kprintf("ar%d: Warning illegal interrupt %d\n",
1128 hc
->cunit
, hc
->isa_irq
);
1129 isr
= isr
| ((memst
& 0xc000) >> 10);
1131 hc
->sca
[0] = (sca_regs
*)hc
->mem_start
;
1132 hc
->sca
[1] = (sca_regs
*)hc
->mem_start
;
1134 ar_outb(hc
, AR_MEM_SEL
, mar
);
1135 ar_outb(hc
, AR_INT_SEL
, isr
| AR_INTS_CEN
);
1138 if(hc
->bustype
== AR_BUS_PCI
&& hc
->interface
[0] == AR_IFACE_PIM
)
1139 for(x
= 0; x
< hc
->numports
; x
++)
1140 hc
->interface
[x
] = ar_read_pim_iface(hc
, x
);
1143 * Set the TX clock direction and enable TX.
1145 for(x
=0;x
<hc
->numports
;x
++) {
1146 switch(hc
->interface
[x
]) {
1148 hc
->txc_dtr
[x
/ NCHAN
] |= (x
% NCHAN
== 0) ?
1149 AR_TXC_DTR_TX0
: AR_TXC_DTR_TX1
;
1150 hc
->txc_dtr
[x
/ NCHAN
] |= (x
% NCHAN
== 0) ?
1151 AR_TXC_DTR_TXCS0
: AR_TXC_DTR_TXCS1
;
1153 case AR_IFACE_EIA_530
:
1154 case AR_IFACE_COMBO
:
1156 hc
->txc_dtr
[x
/ NCHAN
] |= (x
% NCHAN
== 0) ?
1157 AR_TXC_DTR_TX0
: AR_TXC_DTR_TX1
;
1162 if(hc
->bustype
== AR_BUS_PCI
)
1163 hc
->orbase
[AR_TXC_DTR0
* 4] = hc
->txc_dtr
[0];
1165 ar_outb(hc
, AR_TXC_DTR0
, hc
->txc_dtr
[0]);
1166 if(hc
->numports
> NCHAN
) {
1167 if(hc
->bustype
== AR_BUS_PCI
)
1168 hc
->orbase
[AR_TXC_DTR2
* 4] = hc
->txc_dtr
[1];
1170 ar_outb(hc
, AR_TXC_DTR2
, hc
->txc_dtr
[1]);
1173 chanmem
= hc
->memsize
/ hc
->numports
;
1176 for(x
=0;x
<hc
->numports
;x
++, sc
++) {
1179 sc
->sca
= hc
->sca
[x
/ NCHAN
];
1181 for(blk
= 0; blk
< AR_TX_BLOCKS
; blk
++) {
1182 sc
->block
[blk
].txdesc
= next
;
1183 bufmem
= (16 * 1024) / AR_TX_BLOCKS
;
1184 descneeded
= bufmem
/ AR_BUF_SIZ
;
1185 sc
->block
[blk
].txstart
= sc
->block
[blk
].txdesc
+
1186 ((((descneeded
* sizeof(sca_descriptor
)) /
1187 AR_BUF_SIZ
) + 1) * AR_BUF_SIZ
);
1188 sc
->block
[blk
].txend
= next
+ bufmem
;
1189 sc
->block
[blk
].txmax
=
1190 (sc
->block
[blk
].txend
- sc
->block
[blk
].txstart
)
1194 TRC(kprintf("ar%d: blk %d: txdesc %x, txstart %x, "
1195 "txend %x, txmax %d\n",
1198 sc
->block
[blk
].txdesc
,
1199 sc
->block
[blk
].txstart
,
1200 sc
->block
[blk
].txend
,
1201 sc
->block
[blk
].txmax
));
1205 bufmem
= chanmem
- (bufmem
* AR_TX_BLOCKS
);
1206 descneeded
= bufmem
/ AR_BUF_SIZ
;
1207 sc
->rxstart
= sc
->rxdesc
+
1208 ((((descneeded
* sizeof(sca_descriptor
)) /
1209 AR_BUF_SIZ
) + 1) * AR_BUF_SIZ
);
1210 sc
->rxend
= next
+ bufmem
;
1211 sc
->rxmax
= (sc
->rxend
- sc
->rxstart
) / AR_BUF_SIZ
;
1213 TRC(kprintf("ar%d: rxdesc %x, rxstart %x, "
1214 "rxend %x, rxmax %d\n",
1215 x
, sc
->rxdesc
, sc
->rxstart
, sc
->rxend
, sc
->rxmax
));
1218 if(hc
->bustype
== AR_BUS_PCI
)
1219 hc
->orbase
[AR_PIMCTRL
] = AR_PIM_MODEG
| AR_PIM_AUTO_LED
;
1224 * The things done here are channel independent.
1226 * Configure the sca waitstates.
1227 * Configure the global interrupt registers.
1228 * Enable master dma enable.
1231 ar_init_sca(struct ar_hardc
*hc
, int scano
)
1235 sca
= hc
->sca
[scano
];
1236 if(hc
->bustype
== AR_BUS_ISA
)
1237 ARC_SET_SCA(hc
, scano
);
1240 * Do the wait registers.
1241 * Set everything to 0 wait states.
1250 * Configure the interrupt registers.
1251 * Most are cleared until the interface is configured.
1253 sca
->ier0
= 0x00; /* MSCI interrupts... Not used with dma. */
1254 sca
->ier1
= 0x00; /* DMAC interrupts */
1255 sca
->ier2
= 0x00; /* TIMER interrupts... Not used yet. */
1256 sca
->itcr
= 0x00; /* Use ivr and no intr ack */
1257 sca
->ivr
= 0x40; /* Fill in the interrupt vector. */
1261 * Configure the timers.
1267 * Set the DMA channel priority to rotate between
1268 * all four channels.
1270 * Enable all dma channels.
1272 if(hc
->bustype
== AR_BUS_PCI
) {
1276 * Stupid problem with the PCI interface chip that break
1281 t
[AR_PCI_SCA_PCR
] = SCA_PCR_PR2
;
1282 t
[AR_PCI_SCA_DMER
] = SCA_DMER_EN
;
1284 sca
->pcr
= SCA_PCR_PR2
;
1285 sca
->dmer
= SCA_DMER_EN
;
1291 * Configure the msci
1293 * NOTE: The serial port configuration is hardcoded at the moment.
1296 ar_init_msci(struct ar_softc
*sc
)
1300 msci
= &sc
->sca
->msci
[sc
->scachan
];
1302 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1303 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1305 msci
->cmd
= SCA_CMD_RESET
;
1307 msci
->md0
= SCA_MD0_CRC_1
|
1309 SCA_MD0_CRC_ENABLE
|
1311 msci
->md1
= SCA_MD1_NOADDRCHK
;
1312 msci
->md2
= SCA_MD2_DUPLEX
| SCA_MD2_NRZ
;
1315 * Acording to the manual I should give a reset after changing the
1318 msci
->cmd
= SCA_CMD_RXRESET
;
1319 msci
->ctl
= SCA_CTL_IDLPAT
| SCA_CTL_UDRNC
| SCA_CTL_RTS
;
1322 * For now all interfaces are programmed to use the RX clock for
1325 switch(sc
->hc
->interface
[sc
->subunit
]) {
1327 msci
->rxs
= SCA_RXS_CLK_RXC0
| SCA_RXS_DIV1
;
1328 msci
->txs
= SCA_TXS_CLK_TXC
| SCA_TXS_DIV1
;
1331 case AR_IFACE_EIA_530
:
1332 case AR_IFACE_COMBO
:
1333 msci
->rxs
= SCA_RXS_CLK_RXC0
| SCA_RXS_DIV1
;
1334 msci
->txs
= SCA_TXS_CLK_RX
| SCA_TXS_DIV1
;
1337 msci
->tmc
= 153; /* This give 64k for loopback */
1340 * Disable all interrupts for now. I think if you are using
1341 * the dmac you don't use these interrupts.
1344 msci
->ie1
= 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1351 msci
->idl
= 0x7E; /* XXX This is what cisco does. */
1354 * This is what the ARNET diags use.
1362 * Configure the rx dma controller.
1365 ar_init_rx_dmac(struct ar_softc
*sc
)
1368 sca_descriptor
*rxd
;
1374 dmac
= &sc
->sca
->dmac
[DMAC_RXCH(sc
->scachan
)];
1376 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1377 ARC_SET_MEM(sc
->hc
, sc
->rxdesc
);
1379 rxd
= (sca_descriptor
*)(sc
->hc
->mem_start
+ (sc
->rxdesc
&sc
->hc
->winmsk
));
1380 rxda_d
= (u_int
)sc
->hc
->mem_start
- (sc
->rxdesc
& ~sc
->hc
->winmsk
);
1382 for(rxbuf
=sc
->rxstart
;rxbuf
<sc
->rxend
;rxbuf
+= AR_BUF_SIZ
, rxd
++) {
1383 rxda
= (u_int
)&rxd
[1] - rxda_d
;
1384 rxd
->cp
= (u_short
)(rxda
& 0xfffful
);
1388 TRC(kprintf("Descrp %p, data pt %x, data %x, ",
1391 rxd
->bp
= (u_short
)(rxbuf
& 0xfffful
);
1392 rxd
->bpb
= (u_char
)((rxbuf
>> 16) & 0xff);
1394 rxd
->stat
= 0xff; /* The sca write here when it is finished. */
1397 TRC(kprintf("bpb %x, bp %x.\n", rxd
->bpb
, rxd
->bp
));
1400 rxd
->cp
= (u_short
)(sc
->rxdesc
& 0xfffful
);
1404 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1405 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1407 dmac
->dsr
= 0; /* Disable DMA transfer */
1408 dmac
->dcr
= SCA_DCR_ABRT
;
1410 /* XXX maybe also SCA_DMR_CNTE */
1411 dmac
->dmr
= SCA_DMR_TMOD
| SCA_DMR_NF
;
1412 dmac
->bfl
= AR_BUF_SIZ
;
1414 dmac
->cda
= (u_short
)(sc
->rxdesc
& 0xffff);
1415 dmac
->sarb
= (u_char
)((sc
->rxdesc
>> 16) & 0xff);
1417 rxd
= (sca_descriptor
*)sc
->rxstart
;
1418 dmac
->eda
= (u_short
)((u_int
)&rxd
[sc
->rxmax
- 1] & 0xffff);
1422 dmac
->dsr
= SCA_DSR_DE
;
1426 * Configure the TX DMA descriptors.
1427 * Initialize the needed values and chain the descriptors.
1430 ar_init_tx_dmac(struct ar_softc
*sc
)
1433 struct buf_block
*blkp
;
1435 sca_descriptor
*txd
;
1440 dmac
= &sc
->sca
->dmac
[DMAC_TXCH(sc
->scachan
)];
1442 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1443 ARC_SET_MEM(sc
->hc
, sc
->block
[0].txdesc
);
1445 for(blk
= 0; blk
< AR_TX_BLOCKS
; blk
++) {
1446 blkp
= &sc
->block
[blk
];
1447 txd
= (sca_descriptor
*)(sc
->hc
->mem_start
+
1448 (blkp
->txdesc
&sc
->hc
->winmsk
));
1449 txda_d
= (u_int
)sc
->hc
->mem_start
-
1450 (blkp
->txdesc
& ~sc
->hc
->winmsk
);
1452 txbuf
=blkp
->txstart
;
1453 for(;txbuf
<blkp
->txend
;txbuf
+= AR_BUF_SIZ
, txd
++) {
1454 txda
= (u_int
)&txd
[1] - txda_d
;
1455 txd
->cp
= (u_short
)(txda
& 0xfffful
);
1457 txd
->bp
= (u_short
)(txbuf
& 0xfffful
);
1458 txd
->bpb
= (u_char
)((txbuf
>> 16) & 0xff);
1459 TRC(kprintf("ar%d: txbuf %x, bpb %x, bp %x\n",
1460 sc
->unit
, txbuf
, txd
->bpb
, txd
->bp
));
1465 txd
->cp
= (u_short
)(blkp
->txdesc
& 0xfffful
);
1467 blkp
->txtail
= (u_int
)txd
- (u_int
)sc
->hc
->mem_start
;
1468 TRC(kprintf("TX Descriptors start %x, end %x.\n",
1473 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1474 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1476 dmac
->dsr
= 0; /* Disable DMA */
1477 dmac
->dcr
= SCA_DCR_ABRT
;
1478 dmac
->dmr
= SCA_DMR_TMOD
| SCA_DMR_NF
;
1479 dmac
->dir
= SCA_DIR_EOT
| SCA_DIR_BOF
| SCA_DIR_COF
;
1481 dmac
->sarb
= (u_char
)((sc
->block
[0].txdesc
>> 16) & 0xff);
1486 * Look through the descriptors to see if there is a complete packet
1487 * available. Stop if we get to where the sca is busy.
1489 * Return the length and status of the packet.
1490 * Return nonzero if there is a packet available.
1493 * It seems that we get the interrupt a bit early. The updateing of
1494 * descriptor values is not always completed when this is called.
1497 ar_packet_avail(struct ar_softc
*sc
,
1502 sca_descriptor
*rxdesc
;
1503 sca_descriptor
*endp
;
1504 sca_descriptor
*cda
;
1506 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1507 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1508 dmac
= &sc
->sca
->dmac
[DMAC_RXCH(sc
->scachan
)];
1509 cda
= (sca_descriptor
*)(sc
->hc
->mem_start
+
1510 ((((u_int
)dmac
->sarb
<< 16) + dmac
->cda
) & sc
->hc
->winmsk
));
1512 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1513 ARC_SET_MEM(sc
->hc
, sc
->rxdesc
);
1514 rxdesc
= (sca_descriptor
*)
1515 (sc
->hc
->mem_start
+ (sc
->rxdesc
& sc
->hc
->winmsk
));
1517 rxdesc
= &rxdesc
[sc
->rxhind
];
1518 endp
= &endp
[sc
->rxmax
];
1522 while(rxdesc
!= cda
) {
1523 *len
+= rxdesc
->len
;
1525 if(rxdesc
->stat
& SCA_DESC_EOM
) {
1526 *rxstat
= rxdesc
->stat
;
1527 TRC(kprintf("ar%d: PKT AVAIL len %d, %x.\n",
1528 sc
->unit
, *len
, *rxstat
));
1534 rxdesc
= (sca_descriptor
*)
1535 (sc
->hc
->mem_start
+ (sc
->rxdesc
& sc
->hc
->winmsk
));
1545 * Copy a packet from the on card memory into a provided mbuf.
1546 * Take into account that buffers wrap and that a packet may
1547 * be larger than a buffer.
1550 ar_copy_rxbuf(struct mbuf
*m
,
1551 struct ar_softc
*sc
,
1554 sca_descriptor
*rxdesc
;
1560 rxdata
= sc
->rxstart
+ (sc
->rxhind
* AR_BUF_SIZ
);
1561 rxmax
= sc
->rxstart
+ (sc
->rxmax
* AR_BUF_SIZ
);
1563 rxdesc
= (sca_descriptor
*)
1564 (sc
->hc
->mem_start
+ (sc
->rxdesc
& sc
->hc
->winmsk
));
1565 rxdesc
= &rxdesc
[sc
->rxhind
];
1568 tlen
= (len
< AR_BUF_SIZ
) ? len
: AR_BUF_SIZ
;
1569 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1570 ARC_SET_MEM(sc
->hc
, rxdata
);
1571 bcopy(sc
->hc
->mem_start
+ (rxdata
& sc
->hc
->winmsk
),
1572 mtod(m
, caddr_t
) + off
,
1578 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1579 ARC_SET_MEM(sc
->hc
, sc
->rxdesc
);
1581 rxdesc
->stat
= 0xff;
1583 rxdata
+= AR_BUF_SIZ
;
1585 if(rxdata
== rxmax
) {
1586 rxdata
= sc
->rxstart
;
1587 rxdesc
= (sca_descriptor
*)
1588 (sc
->hc
->mem_start
+ (sc
->rxdesc
& sc
->hc
->winmsk
));
1594 * If single is set, just eat a packet. Otherwise eat everything up to
1595 * where cda points. Update pointers to point to the next packet.
1598 ar_eat_packet(struct ar_softc
*sc
, int single
)
1601 sca_descriptor
*rxdesc
;
1602 sca_descriptor
*endp
;
1603 sca_descriptor
*cda
;
1607 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1608 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1609 dmac
= &sc
->sca
->dmac
[DMAC_RXCH(sc
->scachan
)];
1610 cda
= (sca_descriptor
*)(sc
->hc
->mem_start
+
1611 ((((u_int
)dmac
->sarb
<< 16) + dmac
->cda
) & sc
->hc
->winmsk
));
1614 * Loop until desc->stat == (0xff || EOM)
1615 * Clear the status and length in the descriptor.
1616 * Increment the descriptor.
1618 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1619 ARC_SET_MEM(sc
->hc
, sc
->rxdesc
);
1620 rxdesc
= (sca_descriptor
*)
1621 (sc
->hc
->mem_start
+ (sc
->rxdesc
& sc
->hc
->winmsk
));
1623 rxdesc
= &rxdesc
[sc
->rxhind
];
1624 endp
= &endp
[sc
->rxmax
];
1626 while(rxdesc
!= cda
) {
1628 if(loopcnt
> sc
->rxmax
) {
1629 kprintf("ar%d: eat pkt %d loop, cda %p, "
1630 "rxdesc %p, stat %x.\n",
1639 stat
= rxdesc
->stat
;
1642 rxdesc
->stat
= 0xff;
1646 if(rxdesc
== endp
) {
1647 rxdesc
= (sca_descriptor
*)
1648 (sc
->hc
->mem_start
+ (sc
->rxdesc
& sc
->hc
->winmsk
));
1652 if(single
&& (stat
== SCA_DESC_EOM
))
1657 * Update the eda to the previous descriptor.
1659 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1660 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1662 rxdesc
= (sca_descriptor
*)sc
->rxdesc
;
1663 rxdesc
= &rxdesc
[(sc
->rxhind
+ sc
->rxmax
- 2 ) % sc
->rxmax
];
1665 sc
->sca
->dmac
[DMAC_RXCH(sc
->scachan
)].eda
=
1666 (u_short
)((u_int
)rxdesc
& 0xffff);
1671 * While there is packets available in the rx buffer, read them out
1672 * into mbufs and ship them off.
1675 ar_get_packets(struct ar_softc
*sc
)
1677 sca_descriptor
*rxdesc
;
1678 struct mbuf
*m
= NULL
;
1686 while(ar_packet_avail(sc
, &len
, &rxstat
)) {
1687 TRC(kprintf("apa: len %d, rxstat %x\n", len
, rxstat
));
1688 if(((rxstat
& SCA_DESC_ERRORS
) == 0) && (len
< MCLBYTES
)) {
1689 m
= m_getl(len
, MB_DONTWAIT
, MT_DATA
, M_PKTHDR
, NULL
);
1691 /* eat packet if get mbuf fail!! */
1692 ar_eat_packet(sc
, 1);
1696 m
->m_pkthdr
.rcvif
= NULL
;
1700 m
->m_pkthdr
.rcvif
= &sc
->ifsppp
.pp_if
;
1702 m
->m_pkthdr
.len
= m
->m_len
= len
;
1703 ar_copy_rxbuf(m
, sc
, len
);
1705 NG_SEND_DATA_ONLY(error
, sc
->hook
, m
);
1708 BPF_MTAP(&sc
->ifsppp
.pp_if
, m
);
1709 sppp_input(&sc
->ifsppp
.pp_if
, m
);
1710 sc
->ifsppp
.pp_if
.if_ipackets
++;
1713 * Update the eda to the previous descriptor.
1715 i
= (len
+ AR_BUF_SIZ
- 1) / AR_BUF_SIZ
;
1716 sc
->rxhind
= (sc
->rxhind
+ i
) % sc
->rxmax
;
1718 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1719 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1721 rxdesc
= (sca_descriptor
*)sc
->rxdesc
;
1723 &rxdesc
[(sc
->rxhind
+ sc
->rxmax
- 2 ) % sc
->rxmax
];
1725 sc
->sca
->dmac
[DMAC_RXCH(sc
->scachan
)].eda
=
1726 (u_short
)((u_int
)rxdesc
& 0xffff);
1730 while((rxstat
== 0xff) && --tries
)
1731 ar_packet_avail(sc
, &len
, &rxstat
);
1734 * It look like we get an interrupt early
1735 * sometimes and then the status is not
1738 if(tries
&& (tries
!= 5))
1741 ar_eat_packet(sc
, 1);
1744 sc
->ifsppp
.pp_if
.if_ierrors
++;
1745 #else /* NETGRAPH */
1747 #endif /* NETGRAPH */
1749 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1750 ARC_SET_SCA(sc
->hc
, sc
->scano
);
1752 TRCL(kprintf("ar%d: Receive error chan %d, "
1753 "stat %x, msci st3 %x,"
1754 "rxhind %d, cda %x, eda %x.\n",
1758 sc
->sca
->msci
[sc
->scachan
].st3
,
1761 DMAC_RXCH(sc
->scachan
)].cda
,
1763 DMAC_RXCH(sc
->scachan
)].eda
));
1770 * All DMA interrupts come here.
1772 * Each channel has two interrupts.
1773 * Interrupt A for errors and Interrupt B for normal stuff like end
1774 * of transmit or receive dmas.
1777 ar_dmac_intr(struct ar_hardc
*hc
, int scano
, u_char isr1
)
1780 u_char dotxstart
= isr1
;
1782 struct ar_softc
*sc
;
1786 sca
= hc
->sca
[scano
];
1789 * Shortcut if there is no interrupts for dma channel 0 or 1
1791 if((isr1
& 0x0F) == 0) {
1797 sc
= &hc
->sc
[mch
+ (NCHAN
* scano
)];
1803 dmac
= &sca
->dmac
[DMAC_TXCH(mch
)];
1805 if(hc
->bustype
== AR_BUS_ISA
)
1806 ARC_SET_SCA(hc
, scano
);
1811 /* Counter overflow */
1812 if(dsr
& SCA_DSR_COF
) {
1813 kprintf("ar%d: TX DMA Counter overflow, "
1814 "txpacket no %lu.\n",
1817 sc
->ifsppp
.pp_if
.if_opackets
);
1818 sc
->ifsppp
.pp_if
.if_oerrors
++;
1819 #else /* NETGRAPH */
1822 #endif /* NETGRAPH */
1825 /* Buffer overflow */
1826 if(dsr
& SCA_DSR_BOF
) {
1827 kprintf("ar%d: TX DMA Buffer overflow, "
1828 "txpacket no %lu, dsr %02x, "
1829 "cda %04x, eda %04x.\n",
1832 sc
->ifsppp
.pp_if
.if_opackets
,
1833 #else /* NETGRAPH */
1835 #endif /* NETGRAPH */
1840 sc
->ifsppp
.pp_if
.if_oerrors
++;
1841 #else /* NETGRAPH */
1843 #endif /* NETGRAPH */
1846 /* End of Transfer */
1847 if(dsr
& SCA_DSR_EOT
) {
1849 * This should be the most common case.
1851 * Clear the IFF_OACTIVE flag.
1853 * Call arstart to start a new transmit if
1854 * there is data to transmit.
1858 sc
->ifsppp
.pp_if
.if_flags
&= ~IFF_OACTIVE
;
1859 sc
->ifsppp
.pp_if
.if_timer
= 0;
1860 #else /* NETGRAPH */
1861 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1862 sc
->out_dog
= 0; /* XXX */
1863 #endif /* NETGRAPH */
1865 if(sc
->txb_inuse
&& --sc
->txb_inuse
)
1874 dmac
= &sca
->dmac
[DMAC_RXCH(mch
)];
1876 if(hc
->bustype
== AR_BUS_ISA
)
1877 ARC_SET_SCA(hc
, scano
);
1882 TRC(kprintf("AR: RX DSR %x\n", dsr
));
1885 if(dsr
& SCA_DSR_EOM
) {
1886 TRC(int tt
= sc
->ifsppp
.pp_if
.if_ipackets
;)
1887 TRC(int ind
= sc
->rxhind
;)
1891 #define IPACKETS sc->ifsppp.pp_if.if_ipackets
1892 #else /* NETGRAPH */
1893 #define IPACKETS sc->ipackets
1894 #endif /* NETGRAPH */
1895 TRC(if(tt
== IPACKETS
) {
1896 sca_descriptor
*rxdesc
;
1899 if(hc
->bustype
== AR_BUS_ISA
)
1900 ARC_SET_SCA(hc
, scano
);
1901 kprintf("AR: RXINTR isr1 %x, dsr %x, "
1902 "no data %d pkts, orxhind %d.\n",
1907 kprintf("AR: rxdesc %x, rxstart %x, "
1908 "rxend %x, rxhind %d, "
1915 kprintf("AR: cda %x, eda %x.\n",
1919 if(sc
->hc
->bustype
== AR_BUS_ISA
)
1922 rxdesc
= (sca_descriptor
*)
1923 (sc
->hc
->mem_start
+
1924 (sc
->rxdesc
& sc
->hc
->winmsk
));
1925 rxdesc
= &rxdesc
[sc
->rxhind
];
1926 for(i
=0;i
<3;i
++,rxdesc
++)
1927 kprintf("AR: rxdesc->stat %x, "
1934 /* Counter overflow */
1935 if(dsr
& SCA_DSR_COF
) {
1936 kprintf("ar%d: RX DMA Counter overflow, "
1940 sc
->ifsppp
.pp_if
.if_ipackets
);
1941 sc
->ifsppp
.pp_if
.if_ierrors
++;
1942 #else /* NETGRAPH */
1945 #endif /* NETGRAPH */
1948 /* Buffer overflow */
1949 if(dsr
& SCA_DSR_BOF
) {
1950 if(hc
->bustype
== AR_BUS_ISA
)
1951 ARC_SET_SCA(hc
, scano
);
1952 kprintf("ar%d: RX DMA Buffer overflow, "
1953 "rxpkts %lu, rxind %d, "
1954 "cda %x, eda %x, dsr %x.\n",
1957 sc
->ifsppp
.pp_if
.if_ipackets
,
1958 #else /* NETGRAPH */
1960 #endif /* NETGRAPH */
1966 * Make sure we eat as many as possible.
1967 * Then get the system running again.
1969 ar_eat_packet(sc
, 0);
1971 sc
->ifsppp
.pp_if
.if_ierrors
++;
1972 #else /* NETGRAPH */
1974 #endif /* NETGRAPH */
1975 if(hc
->bustype
== AR_BUS_ISA
)
1976 ARC_SET_SCA(hc
, scano
);
1977 sca
->msci
[mch
].cmd
= SCA_CMD_RXMSGREJ
;
1978 dmac
->dsr
= SCA_DSR_DE
;
1980 TRC(kprintf("ar%d: RX DMA Buffer overflow, "
1981 "rxpkts %lu, rxind %d, "
1982 "cda %x, eda %x, dsr %x. After\n",
1984 sc
->ifsppp
.pp_if
.if_ipackets
,
1991 /* End of Transfer */
1992 if(dsr
& SCA_DSR_EOT
) {
1994 * If this happen, it means that we are
1995 * receiving faster than what the processor
1998 * XXX We should enable the dma again.
2000 kprintf("ar%d: RX End of transfer, rxpkts %lu.\n",
2003 sc
->ifsppp
.pp_if
.if_ipackets
);
2004 sc
->ifsppp
.pp_if
.if_ierrors
++;
2005 #else /* NETGRAPH */
2008 #endif /* NETGRAPH */
2015 }while((mch
<NCHAN
) && isr1
);
2018 * Now that we have done all the urgent things, see if we
2019 * can fill the transmit buffers.
2021 for(mch
= 0; mch
< NCHAN
; mch
++) {
2022 if(dotxstart
& 0x0C) {
2023 sc
= &hc
->sc
[mch
+ (NCHAN
* scano
)];
2025 arstart(&sc
->ifsppp
.pp_if
);
2026 #else /* NETGRAPH */
2028 #endif /* NETGRAPH */
2035 ar_msci_intr(struct ar_hardc
*hc
, int scano
, u_char isr0
)
2037 kprintf("arc%d: ARINTR: MSCI\n", hc
->cunit
);
2041 ar_timer_intr(struct ar_hardc
*hc
, int scano
, u_char isr2
)
2043 kprintf("arc%d: ARINTR: TIMER\n", hc
->cunit
);
2048 /*****************************************
2049 * Device timeout/watchdog routine.
2050 * called once per second.
2051 * checks to see that if activity was expected, that it hapenned.
2052 * At present we only look to see if expected output was completed.
2055 ngar_watchdog_frame(void * arg
)
2057 struct ar_softc
* sc
= arg
;
2060 if (sc
->running
== 0) {
2061 return; /* if we are not running let timeouts die */
2064 lwkt_serialize_enter(&ar_serializer
);
2067 * calculate the apparent throughputs
2070 speed
= sc
->inbytes
- sc
->lastinbytes
;
2071 sc
->lastinbytes
= sc
->inbytes
;
2072 if ( sc
->inrate
< speed
)
2074 speed
= sc
->outbytes
- sc
->lastoutbytes
;
2075 sc
->lastoutbytes
= sc
->outbytes
;
2076 if ( sc
->outrate
< speed
)
2077 sc
->outrate
= speed
;
2080 if ((sc
->inlast
> QUITE_A_WHILE
)
2081 && (sc
->out_deficit
> LOTS_OF_PACKETS
)) {
2082 log(LOG_ERR
, "ar%d: No response from remote end\n", sc
->unit
);
2086 sc
->inlast
= sc
->out_deficit
= 0;
2087 } else if ( sc
->xmit_busy
) { /* no TX -> no TX timeouts */
2088 if (sc
->out_dog
== 0) {
2089 log(LOG_ERR
, "ar%d: Transmit failure.. no clock?\n",
2097 sc
->inlast
= sc
->out_deficit
= 0;
2102 lwkt_serialize_exit(&ar_serializer
);
2103 callout_reset(&sc
->timer
, hz
, ngar_watchdog_frame
, sc
);
2106 /***********************************************************************
2107 * This section contains the methods for the Netgraph interface
2108 ***********************************************************************/
2110 * It is not possible or allowable to create a node of this type.
2111 * If the hardware exists, it will already have created it.
2114 ngar_constructor(node_p
*nodep
)
2120 * give our ok for a hook to be added...
2121 * If we are not running this should kick the device into life.
2122 * The hook's private info points to our stash of info about that
2126 ngar_newhook(node_p node
, hook_p hook
, const char *name
)
2128 struct ar_softc
* sc
= NG_NODE_PRIVATE(node
);
2131 * check if it's our friend the debug hook
2133 if (strcmp(name
, NG_AR_HOOK_DEBUG
) == 0) {
2134 NG_HOOK_SET_PRIVATE(hook
, NULL
); /* paranoid */
2135 sc
->debug_hook
= hook
;
2140 * Check for raw mode hook.
2142 if (strcmp(name
, NG_AR_HOOK_RAW
) != 0) {
2145 NG_HOOK_SET_PRIVATE(hook
, sc
);
2153 * incoming messages.
2154 * Just respond to the generic TEXT_STATUS message
2157 ngar_rcvmsg(node_p node
, struct ng_mesg
*msg
, const char *retaddr
,
2158 struct ng_mesg
**rptr
)
2160 struct ar_softc
*sc
;
2162 struct ng_mesg
*resp
= NULL
;
2164 sc
= NG_NODE_PRIVATE(node
);
2165 switch (msg
->header
.typecookie
) {
2169 case NGM_GENERIC_COOKIE
:
2170 switch(msg
->header
.cmd
) {
2171 case NGM_TEXT_STATUS
: {
2175 int resplen
= sizeof(struct ng_mesg
) + 512;
2176 NG_MKRESPONSE(resp
, msg
, resplen
, M_INTWAIT
);
2182 pos
= ksprintf(arg
, "%ld bytes in, %ld bytes out\n"
2183 "highest rate seen: %ld B/S in, %ld B/S out\n",
2184 sc
->inbytes
, sc
->outbytes
,
2185 sc
->inrate
, sc
->outrate
);
2186 pos
+= ksprintf(arg
+ pos
,
2187 "%ld output errors\n",
2189 pos
+= ksprintf(arg
+ pos
,
2190 "ierrors = %ld, %ld, %ld, %ld\n",
2196 (resp
)->header
.arglen
= pos
+ 1;
2208 /* Take care of synchronous response, if any */
2209 NG_RESPOND_MSG(error
, node
, retaddr
, resp
, rptr
);
2215 * get data from another node and transmit it to the correct channel
2218 ngar_rcvdata(hook_p hook
, struct mbuf
*m
, meta_p meta
)
2221 struct ar_softc
* sc
= NG_NODE_PRIVATE(NG_HOOK_NODE(hook
));
2222 struct ifqueue
*xmitq_p
;
2225 * data doesn't come in from just anywhere (e.g control hook)
2227 if ( NG_HOOK_PRIVATE(hook
) == NULL
) {
2233 * Now queue the data for when it can be sent
2235 if (meta
&& meta
->priority
> 0)
2236 xmitq_p
= (&sc
->xmitq_hipri
);
2238 xmitq_p
= (&sc
->xmitq
);
2240 if (IF_QFULL(xmitq_p
)) {
2246 IF_ENQUEUE(xmitq_p
, m
);
2253 * It was an error case.
2254 * check if we need to free the mbuf, and then return the error
2256 NG_FREE_DATA(m
, meta
);
2261 * do local shutdown processing..
2262 * this node will refuse to go away, unless the hardware says to..
2263 * don't unref the node, or remove our name. just clear our links up.
2266 ngar_shutdown(node_p node
)
2268 struct ar_softc
* sc
= NG_NODE_PRIVATE(node
);
2271 NG_NODE_UNREF(node
);
2272 /* XXX need to drain the output queues! */
2274 /* The node is dead, long live the node! */
2275 /* stolen from the attach routine */
2276 if (ng_make_node_common(&typestruct
, &sc
->node
) != 0)
2278 ksprintf(sc
->nodename
, "%s%d", NG_AR_NODE_TYPE
, sc
->unit
);
2279 if (ng_name_node(sc
->node
, sc
->nodename
)) {
2281 kprintf("node naming failed\n");
2282 NG_NODE_UNREF(sc
->node
); /* node dissappears */
2285 NG_NODE_SET_PRIVATE(sc
->node
, sc
);
2290 /* already linked */
2292 ngar_connect(hook_p hook
)
2294 /* be really amiable and just say "YUP that's OK by me! " */
2299 * notify on hook disconnection (destruction)
2301 * Invalidate the private data associated with this dlci.
2302 * For this type, removal of the last link resets tries to destroy the node.
2303 * As the device still exists, the shutdown method will not actually
2304 * destroy the node, but reset the device and leave it 'fresh' :)
2306 * The node removal code will remove all references except that owned by the
2310 ngar_disconnect(hook_p hook
)
2312 struct ar_softc
* sc
= NG_NODE_PRIVATE(NG_HOOK_NODE(hook
));
2315 * If it's the data hook, then free resources etc.
2317 if (NG_HOOK_PRIVATE(hook
)) {
2319 if (sc
->datahooks
== 0)
2322 sc
->debug_hook
= NULL
;
2328 * called during bootup
2329 * or LKM loading to put this type into the list of known modules
2332 ngar_init(void *ignored
)
2334 if (ng_newtype(&typestruct
))
2335 kprintf("ngar install failed\n");
2338 #endif /* NETGRAPH */
2341 ********************************* END ************************************