2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
71 #include <sys/param.h>
73 #include <sys/endian.h>
74 #include <sys/interrupt.h>
75 #include <sys/kernel.h>
77 #include <sys/malloc.h>
81 #include <sys/serialize.h>
82 #include <sys/serialize2.h>
83 #include <sys/socket.h>
84 #include <sys/sockio.h>
85 #include <sys/sysctl.h>
86 #include <sys/systm.h>
89 #include <net/ethernet.h>
91 #include <net/if_arp.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 #include <net/ifq_var.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
99 #include <net/if_poll.h>
101 #include <netinet/in_systm.h>
102 #include <netinet/in.h>
103 #include <netinet/ip.h>
104 #include <netinet/tcp.h>
105 #include <netinet/udp.h>
107 #include <bus/pci/pcivar.h>
108 #include <bus/pci/pcireg.h>
110 #include <dev/netif/ig_hal/e1000_api.h>
111 #include <dev/netif/ig_hal/e1000_82571.h>
112 #include <dev/netif/emx/if_emx.h>
115 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
117 if (sc->rss_debug >= lvl) \
118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
120 #else /* !EMX_RSS_DEBUG */
121 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122 #endif /* EMX_RSS_DEBUG */
124 #define EMX_NAME "Intel(R) PRO/1000 "
126 #define EMX_DEVICE(id) \
127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
128 #define EMX_DEVICE_NULL { 0, 0, NULL }
130 static const struct emx_device
{
135 EMX_DEVICE(82571EB_COPPER
),
136 EMX_DEVICE(82571EB_FIBER
),
137 EMX_DEVICE(82571EB_SERDES
),
138 EMX_DEVICE(82571EB_SERDES_DUAL
),
139 EMX_DEVICE(82571EB_SERDES_QUAD
),
140 EMX_DEVICE(82571EB_QUAD_COPPER
),
141 EMX_DEVICE(82571EB_QUAD_COPPER_BP
),
142 EMX_DEVICE(82571EB_QUAD_COPPER_LP
),
143 EMX_DEVICE(82571EB_QUAD_FIBER
),
144 EMX_DEVICE(82571PT_QUAD_COPPER
),
146 EMX_DEVICE(82572EI_COPPER
),
147 EMX_DEVICE(82572EI_FIBER
),
148 EMX_DEVICE(82572EI_SERDES
),
152 EMX_DEVICE(82573E_IAMT
),
155 EMX_DEVICE(80003ES2LAN_COPPER_SPT
),
156 EMX_DEVICE(80003ES2LAN_SERDES_SPT
),
157 EMX_DEVICE(80003ES2LAN_COPPER_DPT
),
158 EMX_DEVICE(80003ES2LAN_SERDES_DPT
),
162 /* required last entry */
166 static int emx_probe(device_t
);
167 static int emx_attach(device_t
);
168 static int emx_detach(device_t
);
169 static int emx_shutdown(device_t
);
170 static int emx_suspend(device_t
);
171 static int emx_resume(device_t
);
173 static void emx_init(void *);
174 static void emx_stop(struct emx_softc
*);
175 static int emx_ioctl(struct ifnet
*, u_long
, caddr_t
, struct ucred
*);
176 static void emx_start(struct ifnet
*);
178 static void emx_qpoll(struct ifnet
*, struct ifpoll_info
*);
180 static void emx_watchdog(struct ifnet
*);
181 static void emx_media_status(struct ifnet
*, struct ifmediareq
*);
182 static int emx_media_change(struct ifnet
*);
183 static void emx_timer(void *);
184 static void emx_serialize(struct ifnet
*, enum ifnet_serialize
);
185 static void emx_deserialize(struct ifnet
*, enum ifnet_serialize
);
186 static int emx_tryserialize(struct ifnet
*, enum ifnet_serialize
);
188 static void emx_serialize_assert(struct ifnet
*, enum ifnet_serialize
,
192 static void emx_intr(void *);
193 static void emx_rxeof(struct emx_softc
*, int, int);
194 static void emx_txeof(struct emx_softc
*);
195 static void emx_tx_collect(struct emx_softc
*);
196 static void emx_tx_purge(struct emx_softc
*);
197 static void emx_enable_intr(struct emx_softc
*);
198 static void emx_disable_intr(struct emx_softc
*);
200 static int emx_dma_alloc(struct emx_softc
*);
201 static void emx_dma_free(struct emx_softc
*);
202 static void emx_init_tx_ring(struct emx_softc
*);
203 static int emx_init_rx_ring(struct emx_softc
*, struct emx_rxdata
*);
204 static void emx_free_rx_ring(struct emx_softc
*, struct emx_rxdata
*);
205 static int emx_create_tx_ring(struct emx_softc
*);
206 static int emx_create_rx_ring(struct emx_softc
*, struct emx_rxdata
*);
207 static void emx_destroy_tx_ring(struct emx_softc
*, int);
208 static void emx_destroy_rx_ring(struct emx_softc
*,
209 struct emx_rxdata
*, int);
210 static int emx_newbuf(struct emx_softc
*, struct emx_rxdata
*, int, int);
211 static int emx_encap(struct emx_softc
*, struct mbuf
**);
212 static int emx_txcsum_pullup(struct emx_softc
*, struct mbuf
**);
213 static int emx_txcsum(struct emx_softc
*, struct mbuf
*,
214 uint32_t *, uint32_t *);
216 static int emx_is_valid_eaddr(const uint8_t *);
217 static int emx_hw_init(struct emx_softc
*);
218 static void emx_setup_ifp(struct emx_softc
*);
219 static void emx_init_tx_unit(struct emx_softc
*);
220 static void emx_init_rx_unit(struct emx_softc
*);
221 static void emx_update_stats(struct emx_softc
*);
222 static void emx_set_promisc(struct emx_softc
*);
223 static void emx_disable_promisc(struct emx_softc
*);
224 static void emx_set_multi(struct emx_softc
*);
225 static void emx_update_link_status(struct emx_softc
*);
226 static void emx_smartspeed(struct emx_softc
*);
228 static void emx_print_debug_info(struct emx_softc
*);
229 static void emx_print_nvm_info(struct emx_softc
*);
230 static void emx_print_hw_stats(struct emx_softc
*);
232 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS
);
233 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS
);
234 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS
);
235 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS
);
236 static void emx_add_sysctl(struct emx_softc
*);
238 static void emx_serialize_skipmain(struct emx_softc
*);
239 static void emx_deserialize_skipmain(struct emx_softc
*);
241 /* Management and WOL Support */
242 static void emx_get_mgmt(struct emx_softc
*);
243 static void emx_rel_mgmt(struct emx_softc
*);
244 static void emx_get_hw_control(struct emx_softc
*);
245 static void emx_rel_hw_control(struct emx_softc
*);
246 static void emx_enable_wol(device_t
);
248 static device_method_t emx_methods
[] = {
249 /* Device interface */
250 DEVMETHOD(device_probe
, emx_probe
),
251 DEVMETHOD(device_attach
, emx_attach
),
252 DEVMETHOD(device_detach
, emx_detach
),
253 DEVMETHOD(device_shutdown
, emx_shutdown
),
254 DEVMETHOD(device_suspend
, emx_suspend
),
255 DEVMETHOD(device_resume
, emx_resume
),
259 static driver_t emx_driver
= {
262 sizeof(struct emx_softc
),
265 static devclass_t emx_devclass
;
267 DECLARE_DUMMY_MODULE(if_emx
);
268 MODULE_DEPEND(emx
, ig_hal
, 1, 1, 1);
269 DRIVER_MODULE(if_emx
, pci
, emx_driver
, emx_devclass
, 0, 0);
274 static int emx_int_throttle_ceil
= EMX_DEFAULT_ITR
;
275 static int emx_rxd
= EMX_DEFAULT_RXD
;
276 static int emx_txd
= EMX_DEFAULT_TXD
;
277 static int emx_smart_pwr_down
= FALSE
;
279 /* Controls whether promiscuous also shows bad packets */
280 static int emx_debug_sbp
= FALSE
;
282 static int emx_82573_workaround
= TRUE
;
284 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil
);
285 TUNABLE_INT("hw.emx.rxd", &emx_rxd
);
286 TUNABLE_INT("hw.emx.txd", &emx_txd
);
287 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down
);
288 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp
);
289 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround
);
291 /* Global used in WOL setup with multiport cards */
292 static int emx_global_quad_port_a
= 0;
294 /* Set this to one to display debug statistics */
295 static int emx_display_debug_stats
= 0;
297 #if !defined(KTR_IF_EMX)
298 #define KTR_IF_EMX KTR_ALL
300 KTR_INFO_MASTER(if_emx
);
301 KTR_INFO(KTR_IF_EMX
, if_emx
, intr_beg
, 0, "intr begin", 0);
302 KTR_INFO(KTR_IF_EMX
, if_emx
, intr_end
, 1, "intr end", 0);
303 KTR_INFO(KTR_IF_EMX
, if_emx
, pkt_receive
, 4, "rx packet", 0);
304 KTR_INFO(KTR_IF_EMX
, if_emx
, pkt_txqueue
, 5, "tx packet", 0);
305 KTR_INFO(KTR_IF_EMX
, if_emx
, pkt_txclean
, 6, "tx clean", 0);
306 #define logif(name) KTR_LOG(if_emx_ ## name)
309 emx_setup_rxdesc(emx_rxdesc_t
*rxd
, const struct emx_rxbuf
*rxbuf
)
311 rxd
->rxd_bufaddr
= htole64(rxbuf
->paddr
);
312 /* DD bit must be cleared */
313 rxd
->rxd_staterr
= 0;
317 emx_rxcsum(uint32_t staterr
, struct mbuf
*mp
)
319 /* Ignore Checksum bit is set */
320 if (staterr
& E1000_RXD_STAT_IXSM
)
323 if ((staterr
& (E1000_RXD_STAT_IPCS
| E1000_RXDEXT_STATERR_IPE
)) ==
325 mp
->m_pkthdr
.csum_flags
|= CSUM_IP_CHECKED
| CSUM_IP_VALID
;
327 if ((staterr
& (E1000_RXD_STAT_TCPCS
| E1000_RXDEXT_STATERR_TCPE
)) ==
328 E1000_RXD_STAT_TCPCS
) {
329 mp
->m_pkthdr
.csum_flags
|= CSUM_DATA_VALID
|
331 CSUM_FRAG_NOT_CHECKED
;
332 mp
->m_pkthdr
.csum_data
= htons(0xffff);
336 static __inline
struct pktinfo
*
337 emx_rssinfo(struct mbuf
*m
, struct pktinfo
*pi
,
338 uint32_t mrq
, uint32_t hash
, uint32_t staterr
)
340 switch (mrq
& EMX_RXDMRQ_RSSTYPE_MASK
) {
341 case EMX_RXDMRQ_IPV4_TCP
:
342 pi
->pi_netisr
= NETISR_IP
;
344 pi
->pi_l3proto
= IPPROTO_TCP
;
347 case EMX_RXDMRQ_IPV6_TCP
:
348 pi
->pi_netisr
= NETISR_IPV6
;
350 pi
->pi_l3proto
= IPPROTO_TCP
;
353 case EMX_RXDMRQ_IPV4
:
354 if (staterr
& E1000_RXD_STAT_IXSM
)
358 (E1000_RXD_STAT_TCPCS
| E1000_RXDEXT_STATERR_TCPE
)) ==
359 E1000_RXD_STAT_TCPCS
) {
360 pi
->pi_netisr
= NETISR_IP
;
362 pi
->pi_l3proto
= IPPROTO_UDP
;
370 m
->m_flags
|= M_HASH
;
371 m
->m_pkthdr
.hash
= toeplitz_hash(hash
);
376 emx_probe(device_t dev
)
378 const struct emx_device
*d
;
381 vid
= pci_get_vendor(dev
);
382 did
= pci_get_device(dev
);
384 for (d
= emx_devices
; d
->desc
!= NULL
; ++d
) {
385 if (vid
== d
->vid
&& did
== d
->did
) {
386 device_set_desc(dev
, d
->desc
);
387 device_set_async_attach(dev
, TRUE
);
395 emx_attach(device_t dev
)
397 struct emx_softc
*sc
= device_get_softc(dev
);
398 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
400 uint16_t eeprom_data
, device_id
;
402 lwkt_serialize_init(&sc
->main_serialize
);
403 lwkt_serialize_init(&sc
->tx_serialize
);
404 for (i
= 0; i
< EMX_NRX_RING
; ++i
)
405 lwkt_serialize_init(&sc
->rx_data
[i
].rx_serialize
);
408 sc
->serializes
[i
++] = &sc
->main_serialize
;
409 sc
->serializes
[i
++] = &sc
->tx_serialize
;
410 sc
->serializes
[i
++] = &sc
->rx_data
[0].rx_serialize
;
411 sc
->serializes
[i
++] = &sc
->rx_data
[1].rx_serialize
;
412 KKASSERT(i
== EMX_NSERIALIZE
);
414 callout_init(&sc
->timer
);
416 sc
->dev
= sc
->osdep
.dev
= dev
;
419 * Determine hardware and mac type
421 sc
->hw
.vendor_id
= pci_get_vendor(dev
);
422 sc
->hw
.device_id
= pci_get_device(dev
);
423 sc
->hw
.revision_id
= pci_get_revid(dev
);
424 sc
->hw
.subsystem_vendor_id
= pci_get_subvendor(dev
);
425 sc
->hw
.subsystem_device_id
= pci_get_subdevice(dev
);
427 if (e1000_set_mac_type(&sc
->hw
))
430 /* Enable bus mastering */
431 pci_enable_busmaster(dev
);
436 sc
->memory_rid
= EMX_BAR_MEM
;
437 sc
->memory
= bus_alloc_resource_any(dev
, SYS_RES_MEMORY
,
438 &sc
->memory_rid
, RF_ACTIVE
);
439 if (sc
->memory
== NULL
) {
440 device_printf(dev
, "Unable to allocate bus resource: memory\n");
444 sc
->osdep
.mem_bus_space_tag
= rman_get_bustag(sc
->memory
);
445 sc
->osdep
.mem_bus_space_handle
= rman_get_bushandle(sc
->memory
);
447 /* XXX This is quite goofy, it is not actually used */
448 sc
->hw
.hw_addr
= (uint8_t *)&sc
->osdep
.mem_bus_space_handle
;
454 sc
->intr_res
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &sc
->intr_rid
,
455 RF_SHAREABLE
| RF_ACTIVE
);
456 if (sc
->intr_res
== NULL
) {
457 device_printf(dev
, "Unable to allocate bus resource: "
463 /* Save PCI command register for Shared Code */
464 sc
->hw
.bus
.pci_cmd_word
= pci_read_config(dev
, PCIR_COMMAND
, 2);
465 sc
->hw
.back
= &sc
->osdep
;
467 /* Do Shared Code initialization */
468 if (e1000_setup_init_funcs(&sc
->hw
, TRUE
)) {
469 device_printf(dev
, "Setup of Shared code failed\n");
473 e1000_get_bus_info(&sc
->hw
);
475 sc
->hw
.mac
.autoneg
= EMX_DO_AUTO_NEG
;
476 sc
->hw
.phy
.autoneg_wait_to_complete
= FALSE
;
477 sc
->hw
.phy
.autoneg_advertised
= EMX_AUTONEG_ADV_DEFAULT
;
480 * Interrupt throttle rate
482 if (emx_int_throttle_ceil
== 0) {
483 sc
->int_throttle_ceil
= 0;
485 int throttle
= emx_int_throttle_ceil
;
488 throttle
= EMX_DEFAULT_ITR
;
490 /* Recalculate the tunable value to get the exact frequency. */
491 throttle
= 1000000000 / 256 / throttle
;
493 /* Upper 16bits of ITR is reserved and should be zero */
494 if (throttle
& 0xffff0000)
495 throttle
= 1000000000 / 256 / EMX_DEFAULT_ITR
;
497 sc
->int_throttle_ceil
= 1000000000 / 256 / throttle
;
500 e1000_init_script_state_82541(&sc
->hw
, TRUE
);
501 e1000_set_tbi_compatibility_82543(&sc
->hw
, TRUE
);
504 if (sc
->hw
.phy
.media_type
== e1000_media_type_copper
) {
505 sc
->hw
.phy
.mdix
= EMX_AUTO_ALL_MODES
;
506 sc
->hw
.phy
.disable_polarity_correction
= FALSE
;
507 sc
->hw
.phy
.ms_type
= EMX_MASTER_SLAVE
;
510 /* Set the frame limits assuming standard ethernet sized frames. */
511 sc
->max_frame_size
= ETHERMTU
+ ETHER_HDR_LEN
+ ETHER_CRC_LEN
;
512 sc
->min_frame_size
= ETHER_MIN_LEN
;
514 /* This controls when hardware reports transmit completion status. */
515 sc
->hw
.mac
.report_tx_early
= 1;
518 /* Calculate # of RX rings */
520 sc
->rx_ring_cnt
= EMX_NRX_RING
;
524 sc
->rx_ring_inuse
= sc
->rx_ring_cnt
;
526 /* Allocate RX/TX rings' busdma(9) stuffs */
527 error
= emx_dma_alloc(sc
);
531 /* Make sure we have a good EEPROM before we read from it */
532 if (e1000_validate_nvm_checksum(&sc
->hw
) < 0) {
534 * Some PCI-E parts fail the first check due to
535 * the link being in sleep state, call it again,
536 * if it fails a second time its a real issue.
538 if (e1000_validate_nvm_checksum(&sc
->hw
) < 0) {
540 "The EEPROM Checksum Is Not Valid\n");
546 /* Initialize the hardware */
547 error
= emx_hw_init(sc
);
549 device_printf(dev
, "Unable to initialize the hardware\n");
553 /* Copy the permanent MAC address out of the EEPROM */
554 if (e1000_read_mac_addr(&sc
->hw
) < 0) {
555 device_printf(dev
, "EEPROM read error while reading MAC"
560 if (!emx_is_valid_eaddr(sc
->hw
.mac
.addr
)) {
561 device_printf(dev
, "Invalid MAC address\n");
566 /* Manually turn off all interrupts */
567 E1000_WRITE_REG(&sc
->hw
, E1000_IMC
, 0xffffffff);
569 /* Setup OS specific network interface */
572 /* Add sysctl tree, must after emx_setup_ifp() */
575 /* Initialize statistics */
576 emx_update_stats(sc
);
578 sc
->hw
.mac
.get_link_status
= 1;
579 emx_update_link_status(sc
);
581 /* Indicate SOL/IDER usage */
582 if (e1000_check_reset_block(&sc
->hw
)) {
584 "PHY reset is blocked due to SOL/IDER session.\n");
587 /* Determine if we have to control management hardware */
588 sc
->has_manage
= e1000_enable_mng_pass_thru(&sc
->hw
);
593 switch (sc
->hw
.mac
.type
) {
595 case e1000_80003es2lan
:
596 if (sc
->hw
.bus
.func
== 1) {
597 e1000_read_nvm(&sc
->hw
,
598 NVM_INIT_CONTROL3_PORT_B
, 1, &eeprom_data
);
600 e1000_read_nvm(&sc
->hw
,
601 NVM_INIT_CONTROL3_PORT_A
, 1, &eeprom_data
);
603 eeprom_data
&= EMX_EEPROM_APME
;
607 /* APME bit in EEPROM is mapped to WUC.APME */
609 E1000_READ_REG(&sc
->hw
, E1000_WUC
) & E1000_WUC_APME
;
613 sc
->wol
= E1000_WUFC_MAG
;
615 * We have the eeprom settings, now apply the special cases
616 * where the eeprom may be wrong or the board won't support
617 * wake on lan on a particular port
619 device_id
= pci_get_device(dev
);
621 case E1000_DEV_ID_82571EB_FIBER
:
623 * Wake events only supported on port A for dual fiber
624 * regardless of eeprom setting
626 if (E1000_READ_REG(&sc
->hw
, E1000_STATUS
) &
631 case E1000_DEV_ID_82571EB_QUAD_COPPER
:
632 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
633 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP
:
634 /* if quad port sc, disable WoL on all but port A */
635 if (emx_global_quad_port_a
!= 0)
637 /* Reset for multiple quad port adapters */
638 if (++emx_global_quad_port_a
== 4)
639 emx_global_quad_port_a
= 0;
643 /* XXX disable wol */
646 sc
->spare_tx_desc
= EMX_TX_SPARE
;
649 * Keep following relationship between spare_tx_desc, oact_tx_desc
651 * (spare_tx_desc + EMX_TX_RESERVED) <=
652 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
654 sc
->oact_tx_desc
= sc
->num_tx_desc
/ 8;
655 if (sc
->oact_tx_desc
> EMX_TX_OACTIVE_MAX
)
656 sc
->oact_tx_desc
= EMX_TX_OACTIVE_MAX
;
657 if (sc
->oact_tx_desc
< sc
->spare_tx_desc
+ EMX_TX_RESERVED
)
658 sc
->oact_tx_desc
= sc
->spare_tx_desc
+ EMX_TX_RESERVED
;
660 sc
->tx_int_nsegs
= sc
->num_tx_desc
/ 16;
661 if (sc
->tx_int_nsegs
< sc
->oact_tx_desc
)
662 sc
->tx_int_nsegs
= sc
->oact_tx_desc
;
664 error
= bus_setup_intr(dev
, sc
->intr_res
, INTR_MPSAFE
, emx_intr
, sc
,
665 &sc
->intr_tag
, &sc
->main_serialize
);
667 device_printf(dev
, "Failed to register interrupt handler");
668 ether_ifdetach(&sc
->arpcom
.ac_if
);
672 ifp
->if_cpuid
= ithread_cpuid(rman_get_start(sc
->intr_res
));
673 KKASSERT(ifp
->if_cpuid
>= 0 && ifp
->if_cpuid
< ncpus
);
681 emx_detach(device_t dev
)
683 struct emx_softc
*sc
= device_get_softc(dev
);
685 if (device_is_attached(dev
)) {
686 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
688 ifnet_serialize_all(ifp
);
692 e1000_phy_hw_reset(&sc
->hw
);
696 if (sc
->hw
.mac
.type
== e1000_82573
&&
697 e1000_check_mng_mode(&sc
->hw
))
698 emx_rel_hw_control(sc
);
701 E1000_WRITE_REG(&sc
->hw
, E1000_WUC
, E1000_WUC_PME_EN
);
702 E1000_WRITE_REG(&sc
->hw
, E1000_WUFC
, sc
->wol
);
706 bus_teardown_intr(dev
, sc
->intr_res
, sc
->intr_tag
);
708 ifnet_deserialize_all(ifp
);
712 bus_generic_detach(dev
);
714 if (sc
->intr_res
!= NULL
) {
715 bus_release_resource(dev
, SYS_RES_IRQ
, sc
->intr_rid
,
719 if (sc
->memory
!= NULL
) {
720 bus_release_resource(dev
, SYS_RES_MEMORY
, sc
->memory_rid
,
726 /* Free sysctl tree */
727 if (sc
->sysctl_tree
!= NULL
)
728 sysctl_ctx_free(&sc
->sysctl_ctx
);
734 emx_shutdown(device_t dev
)
736 return emx_suspend(dev
);
740 emx_suspend(device_t dev
)
742 struct emx_softc
*sc
= device_get_softc(dev
);
743 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
745 ifnet_serialize_all(ifp
);
751 if (sc
->hw
.mac
.type
== e1000_82573
&&
752 e1000_check_mng_mode(&sc
->hw
))
753 emx_rel_hw_control(sc
);
756 E1000_WRITE_REG(&sc
->hw
, E1000_WUC
, E1000_WUC_PME_EN
);
757 E1000_WRITE_REG(&sc
->hw
, E1000_WUFC
, sc
->wol
);
761 ifnet_deserialize_all(ifp
);
763 return bus_generic_suspend(dev
);
767 emx_resume(device_t dev
)
769 struct emx_softc
*sc
= device_get_softc(dev
);
770 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
772 ifnet_serialize_all(ifp
);
778 ifnet_deserialize_all(ifp
);
780 return bus_generic_resume(dev
);
784 emx_start(struct ifnet
*ifp
)
786 struct emx_softc
*sc
= ifp
->if_softc
;
789 ASSERT_SERIALIZED(&sc
->tx_serialize
);
791 if ((ifp
->if_flags
& (IFF_RUNNING
| IFF_OACTIVE
)) != IFF_RUNNING
)
794 if (!sc
->link_active
) {
795 ifq_purge(&ifp
->if_snd
);
799 while (!ifq_is_empty(&ifp
->if_snd
)) {
800 /* Now do we at least have a minimal? */
801 if (EMX_IS_OACTIVE(sc
)) {
803 if (EMX_IS_OACTIVE(sc
)) {
804 ifp
->if_flags
|= IFF_OACTIVE
;
805 sc
->no_tx_desc_avail1
++;
811 m_head
= ifq_dequeue(&ifp
->if_snd
, NULL
);
815 if (emx_encap(sc
, &m_head
)) {
821 /* Send a copy of the frame to the BPF listener */
822 ETHER_BPF_MTAP(ifp
, m_head
);
824 /* Set timeout in case hardware has problems transmitting. */
825 ifp
->if_timer
= EMX_TX_TIMEOUT
;
830 emx_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
832 struct emx_softc
*sc
= ifp
->if_softc
;
833 struct ifreq
*ifr
= (struct ifreq
*)data
;
834 uint16_t eeprom_data
= 0;
835 int max_frame_size
, mask
, reinit
;
838 ASSERT_IFNET_SERIALIZED_ALL(ifp
);
842 switch (sc
->hw
.mac
.type
) {
845 * 82573 only supports jumbo frames
846 * if ASPM is disabled.
848 e1000_read_nvm(&sc
->hw
, NVM_INIT_3GIO_3
, 1,
850 if (eeprom_data
& NVM_WORD1A_ASPM_MASK
) {
851 max_frame_size
= ETHER_MAX_LEN
;
856 /* Limit Jumbo Frame size */
860 case e1000_80003es2lan
:
861 max_frame_size
= 9234;
865 max_frame_size
= MAX_JUMBO_FRAME_SIZE
;
868 if (ifr
->ifr_mtu
> max_frame_size
- ETHER_HDR_LEN
-
874 ifp
->if_mtu
= ifr
->ifr_mtu
;
875 sc
->max_frame_size
= ifp
->if_mtu
+ ETHER_HDR_LEN
+
878 if (ifp
->if_flags
& IFF_RUNNING
)
883 if (ifp
->if_flags
& IFF_UP
) {
884 if ((ifp
->if_flags
& IFF_RUNNING
)) {
885 if ((ifp
->if_flags
^ sc
->if_flags
) &
886 (IFF_PROMISC
| IFF_ALLMULTI
)) {
887 emx_disable_promisc(sc
);
893 } else if (ifp
->if_flags
& IFF_RUNNING
) {
896 sc
->if_flags
= ifp
->if_flags
;
901 if (ifp
->if_flags
& IFF_RUNNING
) {
902 emx_disable_intr(sc
);
905 if (!(ifp
->if_flags
& IFF_NPOLLING
))
912 /* Check SOL/IDER usage */
913 if (e1000_check_reset_block(&sc
->hw
)) {
914 device_printf(sc
->dev
, "Media change is"
915 " blocked due to SOL/IDER session.\n");
921 error
= ifmedia_ioctl(ifp
, ifr
, &sc
->media
, command
);
926 mask
= ifr
->ifr_reqcap
^ ifp
->if_capenable
;
927 if (mask
& IFCAP_HWCSUM
) {
928 ifp
->if_capenable
^= (mask
& IFCAP_HWCSUM
);
931 if (mask
& IFCAP_VLAN_HWTAGGING
) {
932 ifp
->if_capenable
^= IFCAP_VLAN_HWTAGGING
;
935 if (mask
& IFCAP_RSS
) {
936 ifp
->if_capenable
^= IFCAP_RSS
;
939 if (reinit
&& (ifp
->if_flags
& IFF_RUNNING
))
944 error
= ether_ioctl(ifp
, command
, data
);
951 emx_watchdog(struct ifnet
*ifp
)
953 struct emx_softc
*sc
= ifp
->if_softc
;
955 ASSERT_IFNET_SERIALIZED_ALL(ifp
);
958 * The timer is set to 5 every time start queues a packet.
959 * Then txeof keeps resetting it as long as it cleans at
960 * least one descriptor.
961 * Finally, anytime all descriptors are clean the timer is
965 if (E1000_READ_REG(&sc
->hw
, E1000_TDT(0)) ==
966 E1000_READ_REG(&sc
->hw
, E1000_TDH(0))) {
968 * If we reach here, all TX jobs are completed and
969 * the TX engine should have been idled for some time.
970 * We don't need to call if_devstart() here.
972 ifp
->if_flags
&= ~IFF_OACTIVE
;
978 * If we are in this routine because of pause frames, then
979 * don't reset the hardware.
981 if (E1000_READ_REG(&sc
->hw
, E1000_STATUS
) & E1000_STATUS_TXOFF
) {
982 ifp
->if_timer
= EMX_TX_TIMEOUT
;
986 if (e1000_check_for_link(&sc
->hw
) == 0)
987 if_printf(ifp
, "watchdog timeout -- resetting\n");
990 sc
->watchdog_events
++;
994 if (!ifq_is_empty(&ifp
->if_snd
))
1001 struct emx_softc
*sc
= xsc
;
1002 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1003 device_t dev
= sc
->dev
;
1007 ASSERT_IFNET_SERIALIZED_ALL(ifp
);
1012 * Packet Buffer Allocation (PBA)
1013 * Writing PBA sets the receive portion of the buffer
1014 * the remainder is used for the transmit buffer.
1016 switch (sc
->hw
.mac
.type
) {
1017 /* Total Packet Buffer on these is 48K */
1020 case e1000_80003es2lan
:
1021 pba
= E1000_PBA_32K
; /* 32K for Rx, 16K for Tx */
1024 case e1000_82573
: /* 82573: Total Packet Buffer is 32K */
1025 pba
= E1000_PBA_12K
; /* 12K for Rx, 20K for Tx */
1029 pba
= E1000_PBA_20K
; /* 20K for Rx, 20K for Tx */
1033 /* Devices before 82547 had a Packet Buffer of 64K. */
1034 if (sc
->max_frame_size
> 8192)
1035 pba
= E1000_PBA_40K
; /* 40K for Rx, 24K for Tx */
1037 pba
= E1000_PBA_48K
; /* 48K for Rx, 16K for Tx */
1039 E1000_WRITE_REG(&sc
->hw
, E1000_PBA
, pba
);
1041 /* Get the latest mac address, User can use a LAA */
1042 bcopy(IF_LLADDR(ifp
), sc
->hw
.mac
.addr
, ETHER_ADDR_LEN
);
1044 /* Put the address into the Receive Address Array */
1045 e1000_rar_set(&sc
->hw
, sc
->hw
.mac
.addr
, 0);
1048 * With the 82571 sc, RAR[0] may be overwritten
1049 * when the other port is reset, we make a duplicate
1050 * in RAR[14] for that eventuality, this assures
1051 * the interface continues to function.
1053 if (sc
->hw
.mac
.type
== e1000_82571
) {
1054 e1000_set_laa_state_82571(&sc
->hw
, TRUE
);
1055 e1000_rar_set(&sc
->hw
, sc
->hw
.mac
.addr
,
1056 E1000_RAR_ENTRIES
- 1);
1059 /* Initialize the hardware */
1060 if (emx_hw_init(sc
)) {
1061 device_printf(dev
, "Unable to initialize the hardware\n");
1062 /* XXX emx_stop()? */
1065 emx_update_link_status(sc
);
1067 /* Setup VLAN support, basic and offload if available */
1068 E1000_WRITE_REG(&sc
->hw
, E1000_VET
, ETHERTYPE_VLAN
);
1070 if (ifp
->if_capenable
& IFCAP_VLAN_HWTAGGING
) {
1073 ctrl
= E1000_READ_REG(&sc
->hw
, E1000_CTRL
);
1074 ctrl
|= E1000_CTRL_VME
;
1075 E1000_WRITE_REG(&sc
->hw
, E1000_CTRL
, ctrl
);
1078 /* Set hardware offload abilities */
1079 if (ifp
->if_capenable
& IFCAP_TXCSUM
)
1080 ifp
->if_hwassist
= EMX_CSUM_FEATURES
;
1082 ifp
->if_hwassist
= 0;
1084 /* Configure for OS presence */
1087 /* Prepare transmit descriptors and buffers */
1088 emx_init_tx_ring(sc
);
1089 emx_init_tx_unit(sc
);
1091 /* Setup Multicast table */
1095 * Adjust # of RX ring to be used based on IFCAP_RSS
1097 if (ifp
->if_capenable
& IFCAP_RSS
)
1098 sc
->rx_ring_inuse
= sc
->rx_ring_cnt
;
1100 sc
->rx_ring_inuse
= 1;
1102 /* Prepare receive descriptors and buffers */
1103 for (i
= 0; i
< sc
->rx_ring_inuse
; ++i
) {
1104 if (emx_init_rx_ring(sc
, &sc
->rx_data
[i
])) {
1106 "Could not setup receive structures\n");
1111 emx_init_rx_unit(sc
);
1113 /* Don't lose promiscuous settings */
1114 emx_set_promisc(sc
);
1116 ifp
->if_flags
|= IFF_RUNNING
;
1117 ifp
->if_flags
&= ~IFF_OACTIVE
;
1119 callout_reset(&sc
->timer
, hz
, emx_timer
, sc
);
1120 e1000_clear_hw_cntrs_base_generic(&sc
->hw
);
1122 /* MSI/X configuration for 82574 */
1123 if (sc
->hw
.mac
.type
== e1000_82574
) {
1126 tmp
= E1000_READ_REG(&sc
->hw
, E1000_CTRL_EXT
);
1127 tmp
|= E1000_CTRL_EXT_PBA_CLR
;
1128 E1000_WRITE_REG(&sc
->hw
, E1000_CTRL_EXT
, tmp
);
1130 * Set the IVAR - interrupt vector routing.
1131 * Each nibble represents a vector, high bit
1132 * is enable, other 3 bits are the MSIX table
1133 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1134 * Link (other) to 2, hence the magic number.
1136 E1000_WRITE_REG(&sc
->hw
, E1000_IVAR
, 0x800A0908);
1139 #ifdef IFPOLL_ENABLE
1141 * Only enable interrupts if we are not polling, make sure
1142 * they are off otherwise.
1144 if (ifp
->if_flags
& IFF_NPOLLING
)
1145 emx_disable_intr(sc
);
1147 #endif /* IFPOLL_ENABLE */
1148 emx_enable_intr(sc
);
1150 /* Don't reset the phy next time init gets called */
1151 sc
->hw
.phy
.reset_disable
= TRUE
;
1157 struct emx_softc
*sc
= xsc
;
1158 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1162 ASSERT_SERIALIZED(&sc
->main_serialize
);
1164 reg_icr
= E1000_READ_REG(&sc
->hw
, E1000_ICR
);
1166 if ((reg_icr
& E1000_ICR_INT_ASSERTED
) == 0) {
1172 * XXX: some laptops trigger several spurious interrupts
1173 * on emx(4) when in the resume cycle. The ICR register
1174 * reports all-ones value in this case. Processing such
1175 * interrupts would lead to a freeze. I don't know why.
1177 if (reg_icr
== 0xffffffff) {
1182 if (ifp
->if_flags
& IFF_RUNNING
) {
1184 (E1000_ICR_RXT0
| E1000_ICR_RXDMT0
| E1000_ICR_RXO
)) {
1187 for (i
= 0; i
< sc
->rx_ring_inuse
; ++i
) {
1188 lwkt_serialize_enter(
1189 &sc
->rx_data
[i
].rx_serialize
);
1190 emx_rxeof(sc
, i
, -1);
1191 lwkt_serialize_exit(
1192 &sc
->rx_data
[i
].rx_serialize
);
1195 if (reg_icr
& E1000_ICR_TXDW
) {
1196 lwkt_serialize_enter(&sc
->tx_serialize
);
1198 if (!ifq_is_empty(&ifp
->if_snd
))
1200 lwkt_serialize_exit(&sc
->tx_serialize
);
1204 /* Link status change */
1205 if (reg_icr
& (E1000_ICR_RXSEQ
| E1000_ICR_LSC
)) {
1206 emx_serialize_skipmain(sc
);
1208 callout_stop(&sc
->timer
);
1209 sc
->hw
.mac
.get_link_status
= 1;
1210 emx_update_link_status(sc
);
1212 /* Deal with TX cruft when link lost */
1215 callout_reset(&sc
->timer
, hz
, emx_timer
, sc
);
1217 emx_deserialize_skipmain(sc
);
1220 if (reg_icr
& E1000_ICR_RXO
)
1227 emx_media_status(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
1229 struct emx_softc
*sc
= ifp
->if_softc
;
1231 ASSERT_IFNET_SERIALIZED_ALL(ifp
);
1233 emx_update_link_status(sc
);
1235 ifmr
->ifm_status
= IFM_AVALID
;
1236 ifmr
->ifm_active
= IFM_ETHER
;
1238 if (!sc
->link_active
)
1241 ifmr
->ifm_status
|= IFM_ACTIVE
;
1243 if (sc
->hw
.phy
.media_type
== e1000_media_type_fiber
||
1244 sc
->hw
.phy
.media_type
== e1000_media_type_internal_serdes
) {
1245 ifmr
->ifm_active
|= IFM_1000_SX
| IFM_FDX
;
1247 switch (sc
->link_speed
) {
1249 ifmr
->ifm_active
|= IFM_10_T
;
1252 ifmr
->ifm_active
|= IFM_100_TX
;
1256 ifmr
->ifm_active
|= IFM_1000_T
;
1259 if (sc
->link_duplex
== FULL_DUPLEX
)
1260 ifmr
->ifm_active
|= IFM_FDX
;
1262 ifmr
->ifm_active
|= IFM_HDX
;
1267 emx_media_change(struct ifnet
*ifp
)
1269 struct emx_softc
*sc
= ifp
->if_softc
;
1270 struct ifmedia
*ifm
= &sc
->media
;
1272 ASSERT_IFNET_SERIALIZED_ALL(ifp
);
1274 if (IFM_TYPE(ifm
->ifm_media
) != IFM_ETHER
)
1277 switch (IFM_SUBTYPE(ifm
->ifm_media
)) {
1279 sc
->hw
.mac
.autoneg
= EMX_DO_AUTO_NEG
;
1280 sc
->hw
.phy
.autoneg_advertised
= EMX_AUTONEG_ADV_DEFAULT
;
1286 sc
->hw
.mac
.autoneg
= EMX_DO_AUTO_NEG
;
1287 sc
->hw
.phy
.autoneg_advertised
= ADVERTISE_1000_FULL
;
1291 sc
->hw
.mac
.autoneg
= FALSE
;
1292 sc
->hw
.phy
.autoneg_advertised
= 0;
1293 if ((ifm
->ifm_media
& IFM_GMASK
) == IFM_FDX
)
1294 sc
->hw
.mac
.forced_speed_duplex
= ADVERTISE_100_FULL
;
1296 sc
->hw
.mac
.forced_speed_duplex
= ADVERTISE_100_HALF
;
1300 sc
->hw
.mac
.autoneg
= FALSE
;
1301 sc
->hw
.phy
.autoneg_advertised
= 0;
1302 if ((ifm
->ifm_media
& IFM_GMASK
) == IFM_FDX
)
1303 sc
->hw
.mac
.forced_speed_duplex
= ADVERTISE_10_FULL
;
1305 sc
->hw
.mac
.forced_speed_duplex
= ADVERTISE_10_HALF
;
1309 if_printf(ifp
, "Unsupported media type\n");
1314 * As the speed/duplex settings my have changed we need to
1317 sc
->hw
.phy
.reset_disable
= FALSE
;
1325 emx_encap(struct emx_softc
*sc
, struct mbuf
**m_headp
)
1327 bus_dma_segment_t segs
[EMX_MAX_SCATTER
];
1329 struct emx_txbuf
*tx_buffer
, *tx_buffer_mapped
;
1330 struct e1000_tx_desc
*ctxd
= NULL
;
1331 struct mbuf
*m_head
= *m_headp
;
1332 uint32_t txd_upper
, txd_lower
, cmd
= 0;
1333 int maxsegs
, nsegs
, i
, j
, first
, last
= 0, error
;
1335 if (m_head
->m_len
< EMX_TXCSUM_MINHL
&&
1336 (m_head
->m_flags
& EMX_CSUM_FEATURES
)) {
1338 * Make sure that ethernet header and ip.ip_hl are in
1339 * contiguous memory, since if TXCSUM is enabled, later
1340 * TX context descriptor's setup need to access ip.ip_hl.
1342 error
= emx_txcsum_pullup(sc
, m_headp
);
1344 KKASSERT(*m_headp
== NULL
);
1350 txd_upper
= txd_lower
= 0;
1353 * Capture the first descriptor index, this descriptor
1354 * will have the index of the EOP which is the only one
1355 * that now gets a DONE bit writeback.
1357 first
= sc
->next_avail_tx_desc
;
1358 tx_buffer
= &sc
->tx_buf
[first
];
1359 tx_buffer_mapped
= tx_buffer
;
1360 map
= tx_buffer
->map
;
1362 maxsegs
= sc
->num_tx_desc_avail
- EMX_TX_RESERVED
;
1363 KASSERT(maxsegs
>= sc
->spare_tx_desc
, ("not enough spare TX desc\n"));
1364 if (maxsegs
> EMX_MAX_SCATTER
)
1365 maxsegs
= EMX_MAX_SCATTER
;
1367 error
= bus_dmamap_load_mbuf_defrag(sc
->txtag
, map
, m_headp
,
1368 segs
, maxsegs
, &nsegs
, BUS_DMA_NOWAIT
);
1370 if (error
== ENOBUFS
)
1371 sc
->mbuf_alloc_failed
++;
1373 sc
->no_tx_dma_setup
++;
1379 bus_dmamap_sync(sc
->txtag
, map
, BUS_DMASYNC_PREWRITE
);
1382 sc
->tx_nsegs
+= nsegs
;
1384 if (m_head
->m_pkthdr
.csum_flags
& EMX_CSUM_FEATURES
) {
1385 /* TX csum offloading will consume one TX desc */
1386 sc
->tx_nsegs
+= emx_txcsum(sc
, m_head
, &txd_upper
, &txd_lower
);
1388 i
= sc
->next_avail_tx_desc
;
1390 /* Set up our transmit descriptors */
1391 for (j
= 0; j
< nsegs
; j
++) {
1392 tx_buffer
= &sc
->tx_buf
[i
];
1393 ctxd
= &sc
->tx_desc_base
[i
];
1395 ctxd
->buffer_addr
= htole64(segs
[j
].ds_addr
);
1396 ctxd
->lower
.data
= htole32(E1000_TXD_CMD_IFCS
|
1397 txd_lower
| segs
[j
].ds_len
);
1398 ctxd
->upper
.data
= htole32(txd_upper
);
1401 if (++i
== sc
->num_tx_desc
)
1405 sc
->next_avail_tx_desc
= i
;
1407 KKASSERT(sc
->num_tx_desc_avail
> nsegs
);
1408 sc
->num_tx_desc_avail
-= nsegs
;
1410 /* Handle VLAN tag */
1411 if (m_head
->m_flags
& M_VLANTAG
) {
1412 /* Set the vlan id. */
1413 ctxd
->upper
.fields
.special
=
1414 htole16(m_head
->m_pkthdr
.ether_vlantag
);
1416 /* Tell hardware to add tag */
1417 ctxd
->lower
.data
|= htole32(E1000_TXD_CMD_VLE
);
1420 tx_buffer
->m_head
= m_head
;
1421 tx_buffer_mapped
->map
= tx_buffer
->map
;
1422 tx_buffer
->map
= map
;
1424 if (sc
->tx_nsegs
>= sc
->tx_int_nsegs
) {
1428 * Report Status (RS) is turned on
1429 * every tx_int_nsegs descriptors.
1431 cmd
= E1000_TXD_CMD_RS
;
1434 * Keep track of the descriptor, which will
1435 * be written back by hardware.
1437 sc
->tx_dd
[sc
->tx_dd_tail
] = last
;
1438 EMX_INC_TXDD_IDX(sc
->tx_dd_tail
);
1439 KKASSERT(sc
->tx_dd_tail
!= sc
->tx_dd_head
);
1443 * Last Descriptor of Packet needs End Of Packet (EOP)
1445 ctxd
->lower
.data
|= htole32(E1000_TXD_CMD_EOP
| cmd
);
1448 * Advance the Transmit Descriptor Tail (TDT), this tells
1449 * the E1000 that this frame is available to transmit.
1451 E1000_WRITE_REG(&sc
->hw
, E1000_TDT(0), i
);
1457 emx_set_promisc(struct emx_softc
*sc
)
1459 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1462 reg_rctl
= E1000_READ_REG(&sc
->hw
, E1000_RCTL
);
1464 if (ifp
->if_flags
& IFF_PROMISC
) {
1465 reg_rctl
|= (E1000_RCTL_UPE
| E1000_RCTL_MPE
);
1466 /* Turn this on if you want to see bad packets */
1468 reg_rctl
|= E1000_RCTL_SBP
;
1469 E1000_WRITE_REG(&sc
->hw
, E1000_RCTL
, reg_rctl
);
1470 } else if (ifp
->if_flags
& IFF_ALLMULTI
) {
1471 reg_rctl
|= E1000_RCTL_MPE
;
1472 reg_rctl
&= ~E1000_RCTL_UPE
;
1473 E1000_WRITE_REG(&sc
->hw
, E1000_RCTL
, reg_rctl
);
1478 emx_disable_promisc(struct emx_softc
*sc
)
1482 reg_rctl
= E1000_READ_REG(&sc
->hw
, E1000_RCTL
);
1484 reg_rctl
&= ~E1000_RCTL_UPE
;
1485 reg_rctl
&= ~E1000_RCTL_MPE
;
1486 reg_rctl
&= ~E1000_RCTL_SBP
;
1487 E1000_WRITE_REG(&sc
->hw
, E1000_RCTL
, reg_rctl
);
1491 emx_set_multi(struct emx_softc
*sc
)
1493 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1494 struct ifmultiaddr
*ifma
;
1495 uint32_t reg_rctl
= 0;
1496 uint8_t mta
[512]; /* Largest MTS is 4096 bits */
1499 LIST_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
) {
1500 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
1503 if (mcnt
== EMX_MCAST_ADDR_MAX
)
1506 bcopy(LLADDR((struct sockaddr_dl
*)ifma
->ifma_addr
),
1507 &mta
[mcnt
* ETHER_ADDR_LEN
], ETHER_ADDR_LEN
);
1511 if (mcnt
>= EMX_MCAST_ADDR_MAX
) {
1512 reg_rctl
= E1000_READ_REG(&sc
->hw
, E1000_RCTL
);
1513 reg_rctl
|= E1000_RCTL_MPE
;
1514 E1000_WRITE_REG(&sc
->hw
, E1000_RCTL
, reg_rctl
);
1516 e1000_update_mc_addr_list(&sc
->hw
, mta
,
1517 mcnt
, 1, sc
->hw
.mac
.rar_entry_count
);
1522 * This routine checks for link status and updates statistics.
1525 emx_timer(void *xsc
)
1527 struct emx_softc
*sc
= xsc
;
1528 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1530 ifnet_serialize_all(ifp
);
1532 emx_update_link_status(sc
);
1533 emx_update_stats(sc
);
1535 /* Reset LAA into RAR[0] on 82571 */
1536 if (e1000_get_laa_state_82571(&sc
->hw
) == TRUE
)
1537 e1000_rar_set(&sc
->hw
, sc
->hw
.mac
.addr
, 0);
1539 if (emx_display_debug_stats
&& (ifp
->if_flags
& IFF_RUNNING
))
1540 emx_print_hw_stats(sc
);
1544 callout_reset(&sc
->timer
, hz
, emx_timer
, sc
);
1546 ifnet_deserialize_all(ifp
);
1550 emx_update_link_status(struct emx_softc
*sc
)
1552 struct e1000_hw
*hw
= &sc
->hw
;
1553 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1554 device_t dev
= sc
->dev
;
1555 uint32_t link_check
= 0;
1557 /* Get the cached link value or read phy for real */
1558 switch (hw
->phy
.media_type
) {
1559 case e1000_media_type_copper
:
1560 if (hw
->mac
.get_link_status
) {
1561 /* Do the work to read phy */
1562 e1000_check_for_link(hw
);
1563 link_check
= !hw
->mac
.get_link_status
;
1564 if (link_check
) /* ESB2 fix */
1565 e1000_cfg_on_link_up(hw
);
1571 case e1000_media_type_fiber
:
1572 e1000_check_for_link(hw
);
1573 link_check
= E1000_READ_REG(hw
, E1000_STATUS
) & E1000_STATUS_LU
;
1576 case e1000_media_type_internal_serdes
:
1577 e1000_check_for_link(hw
);
1578 link_check
= sc
->hw
.mac
.serdes_has_link
;
1581 case e1000_media_type_unknown
:
1586 /* Now check for a transition */
1587 if (link_check
&& sc
->link_active
== 0) {
1588 e1000_get_speed_and_duplex(hw
, &sc
->link_speed
,
1592 * Check if we should enable/disable SPEED_MODE bit on
1595 if (hw
->mac
.type
== e1000_82571
||
1596 hw
->mac
.type
== e1000_82572
) {
1599 tarc0
= E1000_READ_REG(hw
, E1000_TARC(0));
1600 if (sc
->link_speed
!= SPEED_1000
)
1601 tarc0
&= ~EMX_TARC_SPEED_MODE
;
1603 tarc0
|= EMX_TARC_SPEED_MODE
;
1604 E1000_WRITE_REG(hw
, E1000_TARC(0), tarc0
);
1607 device_printf(dev
, "Link is up %d Mbps %s\n",
1609 ((sc
->link_duplex
== FULL_DUPLEX
) ?
1610 "Full Duplex" : "Half Duplex"));
1612 sc
->link_active
= 1;
1614 ifp
->if_baudrate
= sc
->link_speed
* 1000000;
1615 ifp
->if_link_state
= LINK_STATE_UP
;
1616 if_link_state_change(ifp
);
1617 } else if (!link_check
&& sc
->link_active
== 1) {
1618 ifp
->if_baudrate
= sc
->link_speed
= 0;
1619 sc
->link_duplex
= 0;
1621 device_printf(dev
, "Link is Down\n");
1622 sc
->link_active
= 0;
1624 /* Link down, disable watchdog */
1627 ifp
->if_link_state
= LINK_STATE_DOWN
;
1628 if_link_state_change(ifp
);
1633 emx_stop(struct emx_softc
*sc
)
1635 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1638 ASSERT_IFNET_SERIALIZED_ALL(ifp
);
1640 emx_disable_intr(sc
);
1642 callout_stop(&sc
->timer
);
1644 ifp
->if_flags
&= ~(IFF_RUNNING
| IFF_OACTIVE
);
1648 * Disable multiple receive queues.
1651 * We should disable multiple receive queues before
1652 * resetting the hardware.
1654 E1000_WRITE_REG(&sc
->hw
, E1000_MRQC
, 0);
1656 e1000_reset_hw(&sc
->hw
);
1657 E1000_WRITE_REG(&sc
->hw
, E1000_WUC
, 0);
1659 for (i
= 0; i
< sc
->num_tx_desc
; i
++) {
1660 struct emx_txbuf
*tx_buffer
= &sc
->tx_buf
[i
];
1662 if (tx_buffer
->m_head
!= NULL
) {
1663 bus_dmamap_unload(sc
->txtag
, tx_buffer
->map
);
1664 m_freem(tx_buffer
->m_head
);
1665 tx_buffer
->m_head
= NULL
;
1669 for (i
= 0; i
< sc
->rx_ring_inuse
; ++i
)
1670 emx_free_rx_ring(sc
, &sc
->rx_data
[i
]);
1674 sc
->csum_iphlen
= 0;
1682 emx_hw_init(struct emx_softc
*sc
)
1684 device_t dev
= sc
->dev
;
1685 uint16_t rx_buffer_size
;
1687 /* Issue a global reset */
1688 e1000_reset_hw(&sc
->hw
);
1690 /* Get control from any management/hw control */
1691 if (sc
->hw
.mac
.type
== e1000_82573
&&
1692 e1000_check_mng_mode(&sc
->hw
))
1693 emx_get_hw_control(sc
);
1695 /* Set up smart power down as default off on newer adapters. */
1696 if (!emx_smart_pwr_down
&&
1697 (sc
->hw
.mac
.type
== e1000_82571
||
1698 sc
->hw
.mac
.type
== e1000_82572
)) {
1699 uint16_t phy_tmp
= 0;
1701 /* Speed up time to link by disabling smart power down. */
1702 e1000_read_phy_reg(&sc
->hw
,
1703 IGP02E1000_PHY_POWER_MGMT
, &phy_tmp
);
1704 phy_tmp
&= ~IGP02E1000_PM_SPD
;
1705 e1000_write_phy_reg(&sc
->hw
,
1706 IGP02E1000_PHY_POWER_MGMT
, phy_tmp
);
1710 * These parameters control the automatic generation (Tx) and
1711 * response (Rx) to Ethernet PAUSE frames.
1712 * - High water mark should allow for at least two frames to be
1713 * received after sending an XOFF.
1714 * - Low water mark works best when it is very near the high water mark.
1715 * This allows the receiver to restart by sending XON when it has
1716 * drained a bit. Here we use an arbitary value of 1500 which will
1717 * restart after one full frame is pulled from the buffer. There
1718 * could be several smaller frames in the buffer and if so they will
1719 * not trigger the XON until their total number reduces the buffer
1721 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1723 rx_buffer_size
= (E1000_READ_REG(&sc
->hw
, E1000_PBA
) & 0xffff) << 10;
1725 sc
->hw
.fc
.high_water
= rx_buffer_size
-
1726 roundup2(sc
->max_frame_size
, 1024);
1727 sc
->hw
.fc
.low_water
= sc
->hw
.fc
.high_water
- 1500;
1729 if (sc
->hw
.mac
.type
== e1000_80003es2lan
)
1730 sc
->hw
.fc
.pause_time
= 0xFFFF;
1732 sc
->hw
.fc
.pause_time
= EMX_FC_PAUSE_TIME
;
1733 sc
->hw
.fc
.send_xon
= TRUE
;
1734 sc
->hw
.fc
.requested_mode
= e1000_fc_full
;
1736 if (e1000_init_hw(&sc
->hw
) < 0) {
1737 device_printf(dev
, "Hardware Initialization Failed\n");
1741 e1000_check_for_link(&sc
->hw
);
1747 emx_setup_ifp(struct emx_softc
*sc
)
1749 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1751 if_initname(ifp
, device_get_name(sc
->dev
),
1752 device_get_unit(sc
->dev
));
1754 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
1755 ifp
->if_init
= emx_init
;
1756 ifp
->if_ioctl
= emx_ioctl
;
1757 ifp
->if_start
= emx_start
;
1758 #ifdef IFPOLL_ENABLE
1759 ifp
->if_qpoll
= emx_qpoll
;
1761 ifp
->if_watchdog
= emx_watchdog
;
1762 ifp
->if_serialize
= emx_serialize
;
1763 ifp
->if_deserialize
= emx_deserialize
;
1764 ifp
->if_tryserialize
= emx_tryserialize
;
1766 ifp
->if_serialize_assert
= emx_serialize_assert
;
1768 ifq_set_maxlen(&ifp
->if_snd
, sc
->num_tx_desc
- 1);
1769 ifq_set_ready(&ifp
->if_snd
);
1771 ether_ifattach(ifp
, sc
->hw
.mac
.addr
, NULL
);
1773 ifp
->if_capabilities
= IFCAP_HWCSUM
|
1774 IFCAP_VLAN_HWTAGGING
|
1776 if (sc
->rx_ring_cnt
> 1)
1777 ifp
->if_capabilities
|= IFCAP_RSS
;
1778 ifp
->if_capenable
= ifp
->if_capabilities
;
1779 ifp
->if_hwassist
= EMX_CSUM_FEATURES
;
1782 * Tell the upper layer(s) we support long frames.
1784 ifp
->if_data
.ifi_hdrlen
= sizeof(struct ether_vlan_header
);
1787 * Specify the media types supported by this sc and register
1788 * callbacks to update media and link information
1790 ifmedia_init(&sc
->media
, IFM_IMASK
,
1791 emx_media_change
, emx_media_status
);
1792 if (sc
->hw
.phy
.media_type
== e1000_media_type_fiber
||
1793 sc
->hw
.phy
.media_type
== e1000_media_type_internal_serdes
) {
1794 ifmedia_add(&sc
->media
, IFM_ETHER
| IFM_1000_SX
| IFM_FDX
,
1796 ifmedia_add(&sc
->media
, IFM_ETHER
| IFM_1000_SX
, 0, NULL
);
1798 ifmedia_add(&sc
->media
, IFM_ETHER
| IFM_10_T
, 0, NULL
);
1799 ifmedia_add(&sc
->media
, IFM_ETHER
| IFM_10_T
| IFM_FDX
,
1801 ifmedia_add(&sc
->media
, IFM_ETHER
| IFM_100_TX
, 0, NULL
);
1802 ifmedia_add(&sc
->media
, IFM_ETHER
| IFM_100_TX
| IFM_FDX
,
1804 if (sc
->hw
.phy
.type
!= e1000_phy_ife
) {
1805 ifmedia_add(&sc
->media
,
1806 IFM_ETHER
| IFM_1000_T
| IFM_FDX
, 0, NULL
);
1807 ifmedia_add(&sc
->media
,
1808 IFM_ETHER
| IFM_1000_T
, 0, NULL
);
1811 ifmedia_add(&sc
->media
, IFM_ETHER
| IFM_AUTO
, 0, NULL
);
1812 ifmedia_set(&sc
->media
, IFM_ETHER
| IFM_AUTO
);
1816 * Workaround for SmartSpeed on 82541 and 82547 controllers
1819 emx_smartspeed(struct emx_softc
*sc
)
1823 if (sc
->link_active
|| sc
->hw
.phy
.type
!= e1000_phy_igp
||
1824 sc
->hw
.mac
.autoneg
== 0 ||
1825 (sc
->hw
.phy
.autoneg_advertised
& ADVERTISE_1000_FULL
) == 0)
1828 if (sc
->smartspeed
== 0) {
1830 * If Master/Slave config fault is asserted twice,
1831 * we assume back-to-back
1833 e1000_read_phy_reg(&sc
->hw
, PHY_1000T_STATUS
, &phy_tmp
);
1834 if (!(phy_tmp
& SR_1000T_MS_CONFIG_FAULT
))
1836 e1000_read_phy_reg(&sc
->hw
, PHY_1000T_STATUS
, &phy_tmp
);
1837 if (phy_tmp
& SR_1000T_MS_CONFIG_FAULT
) {
1838 e1000_read_phy_reg(&sc
->hw
,
1839 PHY_1000T_CTRL
, &phy_tmp
);
1840 if (phy_tmp
& CR_1000T_MS_ENABLE
) {
1841 phy_tmp
&= ~CR_1000T_MS_ENABLE
;
1842 e1000_write_phy_reg(&sc
->hw
,
1843 PHY_1000T_CTRL
, phy_tmp
);
1845 if (sc
->hw
.mac
.autoneg
&&
1846 !e1000_phy_setup_autoneg(&sc
->hw
) &&
1847 !e1000_read_phy_reg(&sc
->hw
,
1848 PHY_CONTROL
, &phy_tmp
)) {
1849 phy_tmp
|= MII_CR_AUTO_NEG_EN
|
1850 MII_CR_RESTART_AUTO_NEG
;
1851 e1000_write_phy_reg(&sc
->hw
,
1852 PHY_CONTROL
, phy_tmp
);
1857 } else if (sc
->smartspeed
== EMX_SMARTSPEED_DOWNSHIFT
) {
1858 /* If still no link, perhaps using 2/3 pair cable */
1859 e1000_read_phy_reg(&sc
->hw
, PHY_1000T_CTRL
, &phy_tmp
);
1860 phy_tmp
|= CR_1000T_MS_ENABLE
;
1861 e1000_write_phy_reg(&sc
->hw
, PHY_1000T_CTRL
, phy_tmp
);
1862 if (sc
->hw
.mac
.autoneg
&&
1863 !e1000_phy_setup_autoneg(&sc
->hw
) &&
1864 !e1000_read_phy_reg(&sc
->hw
, PHY_CONTROL
, &phy_tmp
)) {
1865 phy_tmp
|= MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
;
1866 e1000_write_phy_reg(&sc
->hw
, PHY_CONTROL
, phy_tmp
);
1870 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1871 if (sc
->smartspeed
++ == EMX_SMARTSPEED_MAX
)
1876 emx_create_tx_ring(struct emx_softc
*sc
)
1878 device_t dev
= sc
->dev
;
1879 struct emx_txbuf
*tx_buffer
;
1880 int error
, i
, tsize
;
1883 * Validate number of transmit descriptors. It must not exceed
1884 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1886 if ((emx_txd
* sizeof(struct e1000_tx_desc
)) % EMX_DBA_ALIGN
!= 0 ||
1887 emx_txd
> EMX_MAX_TXD
|| emx_txd
< EMX_MIN_TXD
) {
1888 device_printf(dev
, "Using %d TX descriptors instead of %d!\n",
1889 EMX_DEFAULT_TXD
, emx_txd
);
1890 sc
->num_tx_desc
= EMX_DEFAULT_TXD
;
1892 sc
->num_tx_desc
= emx_txd
;
1896 * Allocate Transmit Descriptor ring
1898 tsize
= roundup2(sc
->num_tx_desc
* sizeof(struct e1000_tx_desc
),
1900 sc
->tx_desc_base
= bus_dmamem_coherent_any(sc
->parent_dtag
,
1901 EMX_DBA_ALIGN
, tsize
, BUS_DMA_WAITOK
,
1902 &sc
->tx_desc_dtag
, &sc
->tx_desc_dmap
,
1903 &sc
->tx_desc_paddr
);
1904 if (sc
->tx_desc_base
== NULL
) {
1905 device_printf(dev
, "Unable to allocate tx_desc memory\n");
1909 sc
->tx_buf
= kmalloc(sizeof(struct emx_txbuf
) * sc
->num_tx_desc
,
1910 M_DEVBUF
, M_WAITOK
| M_ZERO
);
1913 * Create DMA tags for tx buffers
1915 error
= bus_dma_tag_create(sc
->parent_dtag
, /* parent */
1916 1, 0, /* alignment, bounds */
1917 BUS_SPACE_MAXADDR
, /* lowaddr */
1918 BUS_SPACE_MAXADDR
, /* highaddr */
1919 NULL
, NULL
, /* filter, filterarg */
1920 EMX_TSO_SIZE
, /* maxsize */
1921 EMX_MAX_SCATTER
, /* nsegments */
1922 EMX_MAX_SEGSIZE
, /* maxsegsize */
1923 BUS_DMA_WAITOK
| BUS_DMA_ALLOCNOW
|
1924 BUS_DMA_ONEBPAGE
, /* flags */
1927 device_printf(dev
, "Unable to allocate TX DMA tag\n");
1928 kfree(sc
->tx_buf
, M_DEVBUF
);
1934 * Create DMA maps for tx buffers
1936 for (i
= 0; i
< sc
->num_tx_desc
; i
++) {
1937 tx_buffer
= &sc
->tx_buf
[i
];
1939 error
= bus_dmamap_create(sc
->txtag
,
1940 BUS_DMA_WAITOK
| BUS_DMA_ONEBPAGE
,
1943 device_printf(dev
, "Unable to create TX DMA map\n");
1944 emx_destroy_tx_ring(sc
, i
);
1952 emx_init_tx_ring(struct emx_softc
*sc
)
1954 /* Clear the old ring contents */
1955 bzero(sc
->tx_desc_base
,
1956 sizeof(struct e1000_tx_desc
) * sc
->num_tx_desc
);
1959 sc
->next_avail_tx_desc
= 0;
1960 sc
->next_tx_to_clean
= 0;
1961 sc
->num_tx_desc_avail
= sc
->num_tx_desc
;
1965 emx_init_tx_unit(struct emx_softc
*sc
)
1967 uint32_t tctl
, tarc
, tipg
= 0;
1970 /* Setup the Base and Length of the Tx Descriptor Ring */
1971 bus_addr
= sc
->tx_desc_paddr
;
1972 E1000_WRITE_REG(&sc
->hw
, E1000_TDLEN(0),
1973 sc
->num_tx_desc
* sizeof(struct e1000_tx_desc
));
1974 E1000_WRITE_REG(&sc
->hw
, E1000_TDBAH(0),
1975 (uint32_t)(bus_addr
>> 32));
1976 E1000_WRITE_REG(&sc
->hw
, E1000_TDBAL(0),
1977 (uint32_t)bus_addr
);
1978 /* Setup the HW Tx Head and Tail descriptor pointers */
1979 E1000_WRITE_REG(&sc
->hw
, E1000_TDT(0), 0);
1980 E1000_WRITE_REG(&sc
->hw
, E1000_TDH(0), 0);
1982 /* Set the default values for the Tx Inter Packet Gap timer */
1983 switch (sc
->hw
.mac
.type
) {
1984 case e1000_80003es2lan
:
1985 tipg
= DEFAULT_82543_TIPG_IPGR1
;
1986 tipg
|= DEFAULT_80003ES2LAN_TIPG_IPGR2
<<
1987 E1000_TIPG_IPGR2_SHIFT
;
1991 if (sc
->hw
.phy
.media_type
== e1000_media_type_fiber
||
1992 sc
->hw
.phy
.media_type
== e1000_media_type_internal_serdes
)
1993 tipg
= DEFAULT_82543_TIPG_IPGT_FIBER
;
1995 tipg
= DEFAULT_82543_TIPG_IPGT_COPPER
;
1996 tipg
|= DEFAULT_82543_TIPG_IPGR1
<< E1000_TIPG_IPGR1_SHIFT
;
1997 tipg
|= DEFAULT_82543_TIPG_IPGR2
<< E1000_TIPG_IPGR2_SHIFT
;
2001 E1000_WRITE_REG(&sc
->hw
, E1000_TIPG
, tipg
);
2003 /* NOTE: 0 is not allowed for TIDV */
2004 E1000_WRITE_REG(&sc
->hw
, E1000_TIDV
, 1);
2005 E1000_WRITE_REG(&sc
->hw
, E1000_TADV
, 0);
2007 if (sc
->hw
.mac
.type
== e1000_82571
||
2008 sc
->hw
.mac
.type
== e1000_82572
) {
2009 tarc
= E1000_READ_REG(&sc
->hw
, E1000_TARC(0));
2010 tarc
|= EMX_TARC_SPEED_MODE
;
2011 E1000_WRITE_REG(&sc
->hw
, E1000_TARC(0), tarc
);
2012 } else if (sc
->hw
.mac
.type
== e1000_80003es2lan
) {
2013 tarc
= E1000_READ_REG(&sc
->hw
, E1000_TARC(0));
2015 E1000_WRITE_REG(&sc
->hw
, E1000_TARC(0), tarc
);
2016 tarc
= E1000_READ_REG(&sc
->hw
, E1000_TARC(1));
2018 E1000_WRITE_REG(&sc
->hw
, E1000_TARC(1), tarc
);
2021 /* Program the Transmit Control Register */
2022 tctl
= E1000_READ_REG(&sc
->hw
, E1000_TCTL
);
2023 tctl
&= ~E1000_TCTL_CT
;
2024 tctl
|= E1000_TCTL_PSP
| E1000_TCTL_RTLC
| E1000_TCTL_EN
|
2025 (E1000_COLLISION_THRESHOLD
<< E1000_CT_SHIFT
);
2026 tctl
|= E1000_TCTL_MULR
;
2028 /* This write will effectively turn on the transmit unit. */
2029 E1000_WRITE_REG(&sc
->hw
, E1000_TCTL
, tctl
);
2033 emx_destroy_tx_ring(struct emx_softc
*sc
, int ndesc
)
2035 struct emx_txbuf
*tx_buffer
;
2038 /* Free Transmit Descriptor ring */
2039 if (sc
->tx_desc_base
) {
2040 bus_dmamap_unload(sc
->tx_desc_dtag
, sc
->tx_desc_dmap
);
2041 bus_dmamem_free(sc
->tx_desc_dtag
, sc
->tx_desc_base
,
2043 bus_dma_tag_destroy(sc
->tx_desc_dtag
);
2045 sc
->tx_desc_base
= NULL
;
2048 if (sc
->tx_buf
== NULL
)
2051 for (i
= 0; i
< ndesc
; i
++) {
2052 tx_buffer
= &sc
->tx_buf
[i
];
2054 KKASSERT(tx_buffer
->m_head
== NULL
);
2055 bus_dmamap_destroy(sc
->txtag
, tx_buffer
->map
);
2057 bus_dma_tag_destroy(sc
->txtag
);
2059 kfree(sc
->tx_buf
, M_DEVBUF
);
2064 * The offload context needs to be set when we transfer the first
2065 * packet of a particular protocol (TCP/UDP). This routine has been
2066 * enhanced to deal with inserted VLAN headers.
2068 * If the new packet's ether header length, ip header length and
2069 * csum offloading type are same as the previous packet, we should
2070 * avoid allocating a new csum context descriptor; mainly to take
2071 * advantage of the pipeline effect of the TX data read request.
2073 * This function returns number of TX descrptors allocated for
2077 emx_txcsum(struct emx_softc
*sc
, struct mbuf
*mp
,
2078 uint32_t *txd_upper
, uint32_t *txd_lower
)
2080 struct e1000_context_desc
*TXD
;
2081 struct emx_txbuf
*tx_buffer
;
2082 struct ether_vlan_header
*eh
;
2084 int curr_txd
, ehdrlen
, csum_flags
;
2085 uint32_t cmd
, hdr_len
, ip_hlen
;
2089 * Determine where frame payload starts.
2090 * Jump over vlan headers if already present,
2091 * helpful for QinQ too.
2093 KASSERT(mp
->m_len
>= ETHER_HDR_LEN
,
2094 ("emx_txcsum_pullup is not called (eh)?\n"));
2095 eh
= mtod(mp
, struct ether_vlan_header
*);
2096 if (eh
->evl_encap_proto
== htons(ETHERTYPE_VLAN
)) {
2097 KASSERT(mp
->m_len
>= ETHER_HDR_LEN
+ EVL_ENCAPLEN
,
2098 ("emx_txcsum_pullup is not called (evh)?\n"));
2099 etype
= ntohs(eh
->evl_proto
);
2100 ehdrlen
= ETHER_HDR_LEN
+ EVL_ENCAPLEN
;
2102 etype
= ntohs(eh
->evl_encap_proto
);
2103 ehdrlen
= ETHER_HDR_LEN
;
2107 * We only support TCP/UDP for IPv4 for the moment.
2108 * TODO: Support SCTP too when it hits the tree.
2110 if (etype
!= ETHERTYPE_IP
)
2113 KASSERT(mp
->m_len
>= ehdrlen
+ EMX_IPVHL_SIZE
,
2114 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2116 /* NOTE: We could only safely access ip.ip_vhl part */
2117 ip
= (struct ip
*)(mp
->m_data
+ ehdrlen
);
2118 ip_hlen
= ip
->ip_hl
<< 2;
2120 csum_flags
= mp
->m_pkthdr
.csum_flags
& EMX_CSUM_FEATURES
;
2122 if (sc
->csum_ehlen
== ehdrlen
&& sc
->csum_iphlen
== ip_hlen
&&
2123 sc
->csum_flags
== csum_flags
) {
2125 * Same csum offload context as the previous packets;
2128 *txd_upper
= sc
->csum_txd_upper
;
2129 *txd_lower
= sc
->csum_txd_lower
;
2134 * Setup a new csum offload context.
2137 curr_txd
= sc
->next_avail_tx_desc
;
2138 tx_buffer
= &sc
->tx_buf
[curr_txd
];
2139 TXD
= (struct e1000_context_desc
*)&sc
->tx_desc_base
[curr_txd
];
2143 /* Setup of IP header checksum. */
2144 if (csum_flags
& CSUM_IP
) {
2146 * Start offset for header checksum calculation.
2147 * End offset for header checksum calculation.
2148 * Offset of place to put the checksum.
2150 TXD
->lower_setup
.ip_fields
.ipcss
= ehdrlen
;
2151 TXD
->lower_setup
.ip_fields
.ipcse
=
2152 htole16(ehdrlen
+ ip_hlen
- 1);
2153 TXD
->lower_setup
.ip_fields
.ipcso
=
2154 ehdrlen
+ offsetof(struct ip
, ip_sum
);
2155 cmd
|= E1000_TXD_CMD_IP
;
2156 *txd_upper
|= E1000_TXD_POPTS_IXSM
<< 8;
2158 hdr_len
= ehdrlen
+ ip_hlen
;
2160 if (csum_flags
& CSUM_TCP
) {
2162 * Start offset for payload checksum calculation.
2163 * End offset for payload checksum calculation.
2164 * Offset of place to put the checksum.
2166 TXD
->upper_setup
.tcp_fields
.tucss
= hdr_len
;
2167 TXD
->upper_setup
.tcp_fields
.tucse
= htole16(0);
2168 TXD
->upper_setup
.tcp_fields
.tucso
=
2169 hdr_len
+ offsetof(struct tcphdr
, th_sum
);
2170 cmd
|= E1000_TXD_CMD_TCP
;
2171 *txd_upper
|= E1000_TXD_POPTS_TXSM
<< 8;
2172 } else if (csum_flags
& CSUM_UDP
) {
2174 * Start offset for header checksum calculation.
2175 * End offset for header checksum calculation.
2176 * Offset of place to put the checksum.
2178 TXD
->upper_setup
.tcp_fields
.tucss
= hdr_len
;
2179 TXD
->upper_setup
.tcp_fields
.tucse
= htole16(0);
2180 TXD
->upper_setup
.tcp_fields
.tucso
=
2181 hdr_len
+ offsetof(struct udphdr
, uh_sum
);
2182 *txd_upper
|= E1000_TXD_POPTS_TXSM
<< 8;
2185 *txd_lower
= E1000_TXD_CMD_DEXT
| /* Extended descr type */
2186 E1000_TXD_DTYP_D
; /* Data descr */
2188 /* Save the information for this csum offloading context */
2189 sc
->csum_ehlen
= ehdrlen
;
2190 sc
->csum_iphlen
= ip_hlen
;
2191 sc
->csum_flags
= csum_flags
;
2192 sc
->csum_txd_upper
= *txd_upper
;
2193 sc
->csum_txd_lower
= *txd_lower
;
2195 TXD
->tcp_seg_setup
.data
= htole32(0);
2196 TXD
->cmd_and_length
=
2197 htole32(E1000_TXD_CMD_IFCS
| E1000_TXD_CMD_DEXT
| cmd
);
2199 if (++curr_txd
== sc
->num_tx_desc
)
2202 KKASSERT(sc
->num_tx_desc_avail
> 0);
2203 sc
->num_tx_desc_avail
--;
2205 sc
->next_avail_tx_desc
= curr_txd
;
2210 emx_txcsum_pullup(struct emx_softc
*sc
, struct mbuf
**m0
)
2212 struct mbuf
*m
= *m0
;
2213 struct ether_header
*eh
;
2216 sc
->tx_csum_try_pullup
++;
2218 len
= ETHER_HDR_LEN
+ EMX_IPVHL_SIZE
;
2220 if (__predict_false(!M_WRITABLE(m
))) {
2221 if (__predict_false(m
->m_len
< ETHER_HDR_LEN
)) {
2222 sc
->tx_csum_drop1
++;
2227 eh
= mtod(m
, struct ether_header
*);
2229 if (eh
->ether_type
== htons(ETHERTYPE_VLAN
))
2230 len
+= EVL_ENCAPLEN
;
2232 if (m
->m_len
< len
) {
2233 sc
->tx_csum_drop2
++;
2241 if (__predict_false(m
->m_len
< ETHER_HDR_LEN
)) {
2242 sc
->tx_csum_pullup1
++;
2243 m
= m_pullup(m
, ETHER_HDR_LEN
);
2245 sc
->tx_csum_pullup1_failed
++;
2251 eh
= mtod(m
, struct ether_header
*);
2253 if (eh
->ether_type
== htons(ETHERTYPE_VLAN
))
2254 len
+= EVL_ENCAPLEN
;
2256 if (m
->m_len
< len
) {
2257 sc
->tx_csum_pullup2
++;
2258 m
= m_pullup(m
, len
);
2260 sc
->tx_csum_pullup2_failed
++;
2270 emx_txeof(struct emx_softc
*sc
)
2272 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2273 struct emx_txbuf
*tx_buffer
;
2274 int first
, num_avail
;
2276 if (sc
->tx_dd_head
== sc
->tx_dd_tail
)
2279 if (sc
->num_tx_desc_avail
== sc
->num_tx_desc
)
2282 num_avail
= sc
->num_tx_desc_avail
;
2283 first
= sc
->next_tx_to_clean
;
2285 while (sc
->tx_dd_head
!= sc
->tx_dd_tail
) {
2286 int dd_idx
= sc
->tx_dd
[sc
->tx_dd_head
];
2287 struct e1000_tx_desc
*tx_desc
;
2289 tx_desc
= &sc
->tx_desc_base
[dd_idx
];
2290 if (tx_desc
->upper
.fields
.status
& E1000_TXD_STAT_DD
) {
2291 EMX_INC_TXDD_IDX(sc
->tx_dd_head
);
2293 if (++dd_idx
== sc
->num_tx_desc
)
2296 while (first
!= dd_idx
) {
2301 tx_buffer
= &sc
->tx_buf
[first
];
2302 if (tx_buffer
->m_head
) {
2304 bus_dmamap_unload(sc
->txtag
,
2306 m_freem(tx_buffer
->m_head
);
2307 tx_buffer
->m_head
= NULL
;
2310 if (++first
== sc
->num_tx_desc
)
2317 sc
->next_tx_to_clean
= first
;
2318 sc
->num_tx_desc_avail
= num_avail
;
2320 if (sc
->tx_dd_head
== sc
->tx_dd_tail
) {
2325 if (!EMX_IS_OACTIVE(sc
)) {
2326 ifp
->if_flags
&= ~IFF_OACTIVE
;
2328 /* All clean, turn off the timer */
2329 if (sc
->num_tx_desc_avail
== sc
->num_tx_desc
)
2335 emx_tx_collect(struct emx_softc
*sc
)
2337 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2338 struct emx_txbuf
*tx_buffer
;
2339 int tdh
, first
, num_avail
, dd_idx
= -1;
2341 if (sc
->num_tx_desc_avail
== sc
->num_tx_desc
)
2344 tdh
= E1000_READ_REG(&sc
->hw
, E1000_TDH(0));
2345 if (tdh
== sc
->next_tx_to_clean
)
2348 if (sc
->tx_dd_head
!= sc
->tx_dd_tail
)
2349 dd_idx
= sc
->tx_dd
[sc
->tx_dd_head
];
2351 num_avail
= sc
->num_tx_desc_avail
;
2352 first
= sc
->next_tx_to_clean
;
2354 while (first
!= tdh
) {
2359 tx_buffer
= &sc
->tx_buf
[first
];
2360 if (tx_buffer
->m_head
) {
2362 bus_dmamap_unload(sc
->txtag
,
2364 m_freem(tx_buffer
->m_head
);
2365 tx_buffer
->m_head
= NULL
;
2368 if (first
== dd_idx
) {
2369 EMX_INC_TXDD_IDX(sc
->tx_dd_head
);
2370 if (sc
->tx_dd_head
== sc
->tx_dd_tail
) {
2375 dd_idx
= sc
->tx_dd
[sc
->tx_dd_head
];
2379 if (++first
== sc
->num_tx_desc
)
2382 sc
->next_tx_to_clean
= first
;
2383 sc
->num_tx_desc_avail
= num_avail
;
2385 if (!EMX_IS_OACTIVE(sc
)) {
2386 ifp
->if_flags
&= ~IFF_OACTIVE
;
2388 /* All clean, turn off the timer */
2389 if (sc
->num_tx_desc_avail
== sc
->num_tx_desc
)
2395 * When Link is lost sometimes there is work still in the TX ring
2396 * which will result in a watchdog, rather than allow that do an
2397 * attempted cleanup and then reinit here. Note that this has been
2398 * seens mostly with fiber adapters.
2401 emx_tx_purge(struct emx_softc
*sc
)
2403 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2405 if (!sc
->link_active
&& ifp
->if_timer
) {
2407 if (ifp
->if_timer
) {
2408 if_printf(ifp
, "Link lost, TX pending, reinit\n");
2416 emx_newbuf(struct emx_softc
*sc
, struct emx_rxdata
*rdata
, int i
, int init
)
2419 bus_dma_segment_t seg
;
2421 struct emx_rxbuf
*rx_buffer
;
2424 m
= m_getcl(init
? MB_WAIT
: MB_DONTWAIT
, MT_DATA
, M_PKTHDR
);
2426 rdata
->mbuf_cluster_failed
++;
2428 if_printf(&sc
->arpcom
.ac_if
,
2429 "Unable to allocate RX mbuf\n");
2433 m
->m_len
= m
->m_pkthdr
.len
= MCLBYTES
;
2435 if (sc
->max_frame_size
<= MCLBYTES
- ETHER_ALIGN
)
2436 m_adj(m
, ETHER_ALIGN
);
2438 error
= bus_dmamap_load_mbuf_segment(rdata
->rxtag
,
2439 rdata
->rx_sparemap
, m
,
2440 &seg
, 1, &nseg
, BUS_DMA_NOWAIT
);
2444 if_printf(&sc
->arpcom
.ac_if
,
2445 "Unable to load RX mbuf\n");
2450 rx_buffer
= &rdata
->rx_buf
[i
];
2451 if (rx_buffer
->m_head
!= NULL
)
2452 bus_dmamap_unload(rdata
->rxtag
, rx_buffer
->map
);
2454 map
= rx_buffer
->map
;
2455 rx_buffer
->map
= rdata
->rx_sparemap
;
2456 rdata
->rx_sparemap
= map
;
2458 rx_buffer
->m_head
= m
;
2459 rx_buffer
->paddr
= seg
.ds_addr
;
2461 emx_setup_rxdesc(&rdata
->rx_desc
[i
], rx_buffer
);
2466 emx_create_rx_ring(struct emx_softc
*sc
, struct emx_rxdata
*rdata
)
2468 device_t dev
= sc
->dev
;
2469 struct emx_rxbuf
*rx_buffer
;
2470 int i
, error
, rsize
;
2473 * Validate number of receive descriptors. It must not exceed
2474 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2476 if ((emx_rxd
* sizeof(emx_rxdesc_t
)) % EMX_DBA_ALIGN
!= 0 ||
2477 emx_rxd
> EMX_MAX_RXD
|| emx_rxd
< EMX_MIN_RXD
) {
2478 device_printf(dev
, "Using %d RX descriptors instead of %d!\n",
2479 EMX_DEFAULT_RXD
, emx_rxd
);
2480 rdata
->num_rx_desc
= EMX_DEFAULT_RXD
;
2482 rdata
->num_rx_desc
= emx_rxd
;
2486 * Allocate Receive Descriptor ring
2488 rsize
= roundup2(rdata
->num_rx_desc
* sizeof(emx_rxdesc_t
),
2490 rdata
->rx_desc
= bus_dmamem_coherent_any(sc
->parent_dtag
,
2491 EMX_DBA_ALIGN
, rsize
, BUS_DMA_WAITOK
,
2492 &rdata
->rx_desc_dtag
, &rdata
->rx_desc_dmap
,
2493 &rdata
->rx_desc_paddr
);
2494 if (rdata
->rx_desc
== NULL
) {
2495 device_printf(dev
, "Unable to allocate rx_desc memory\n");
2499 rdata
->rx_buf
= kmalloc(sizeof(struct emx_rxbuf
) * rdata
->num_rx_desc
,
2500 M_DEVBUF
, M_WAITOK
| M_ZERO
);
2503 * Create DMA tag for rx buffers
2505 error
= bus_dma_tag_create(sc
->parent_dtag
, /* parent */
2506 1, 0, /* alignment, bounds */
2507 BUS_SPACE_MAXADDR
, /* lowaddr */
2508 BUS_SPACE_MAXADDR
, /* highaddr */
2509 NULL
, NULL
, /* filter, filterarg */
2510 MCLBYTES
, /* maxsize */
2512 MCLBYTES
, /* maxsegsize */
2513 BUS_DMA_WAITOK
| BUS_DMA_ALLOCNOW
, /* flags */
2516 device_printf(dev
, "Unable to allocate RX DMA tag\n");
2517 kfree(rdata
->rx_buf
, M_DEVBUF
);
2518 rdata
->rx_buf
= NULL
;
2523 * Create spare DMA map for rx buffers
2525 error
= bus_dmamap_create(rdata
->rxtag
, BUS_DMA_WAITOK
,
2526 &rdata
->rx_sparemap
);
2528 device_printf(dev
, "Unable to create spare RX DMA map\n");
2529 bus_dma_tag_destroy(rdata
->rxtag
);
2530 kfree(rdata
->rx_buf
, M_DEVBUF
);
2531 rdata
->rx_buf
= NULL
;
2536 * Create DMA maps for rx buffers
2538 for (i
= 0; i
< rdata
->num_rx_desc
; i
++) {
2539 rx_buffer
= &rdata
->rx_buf
[i
];
2541 error
= bus_dmamap_create(rdata
->rxtag
, BUS_DMA_WAITOK
,
2544 device_printf(dev
, "Unable to create RX DMA map\n");
2545 emx_destroy_rx_ring(sc
, rdata
, i
);
2553 emx_free_rx_ring(struct emx_softc
*sc
, struct emx_rxdata
*rdata
)
2557 for (i
= 0; i
< rdata
->num_rx_desc
; i
++) {
2558 struct emx_rxbuf
*rx_buffer
= &rdata
->rx_buf
[i
];
2560 if (rx_buffer
->m_head
!= NULL
) {
2561 bus_dmamap_unload(rdata
->rxtag
, rx_buffer
->map
);
2562 m_freem(rx_buffer
->m_head
);
2563 rx_buffer
->m_head
= NULL
;
2567 if (rdata
->fmp
!= NULL
)
2568 m_freem(rdata
->fmp
);
2574 emx_init_rx_ring(struct emx_softc
*sc
, struct emx_rxdata
*rdata
)
2578 /* Reset descriptor ring */
2579 bzero(rdata
->rx_desc
, sizeof(emx_rxdesc_t
) * rdata
->num_rx_desc
);
2581 /* Allocate new ones. */
2582 for (i
= 0; i
< rdata
->num_rx_desc
; i
++) {
2583 error
= emx_newbuf(sc
, rdata
, i
, 1);
2588 /* Setup our descriptor pointers */
2589 rdata
->next_rx_desc_to_check
= 0;
2595 emx_init_rx_unit(struct emx_softc
*sc
)
2597 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2599 uint32_t rctl
, rxcsum
, rfctl
;
2603 * Make sure receives are disabled while setting
2604 * up the descriptor ring
2606 rctl
= E1000_READ_REG(&sc
->hw
, E1000_RCTL
);
2607 E1000_WRITE_REG(&sc
->hw
, E1000_RCTL
, rctl
& ~E1000_RCTL_EN
);
2610 * Set the interrupt throttling rate. Value is calculated
2611 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2613 if (sc
->int_throttle_ceil
) {
2614 E1000_WRITE_REG(&sc
->hw
, E1000_ITR
,
2615 1000000000 / 256 / sc
->int_throttle_ceil
);
2617 E1000_WRITE_REG(&sc
->hw
, E1000_ITR
, 0);
2620 /* Use extended RX descriptor */
2621 rfctl
= E1000_RFCTL_EXTEN
;
2623 /* Disable accelerated ackknowledge */
2624 if (sc
->hw
.mac
.type
== e1000_82574
)
2625 rfctl
|= E1000_RFCTL_ACK_DIS
;
2627 E1000_WRITE_REG(&sc
->hw
, E1000_RFCTL
, rfctl
);
2629 /* Setup the Base and Length of the Rx Descriptor Ring */
2630 for (i
= 0; i
< sc
->rx_ring_inuse
; ++i
) {
2631 struct emx_rxdata
*rdata
= &sc
->rx_data
[i
];
2633 bus_addr
= rdata
->rx_desc_paddr
;
2634 E1000_WRITE_REG(&sc
->hw
, E1000_RDLEN(i
),
2635 rdata
->num_rx_desc
* sizeof(emx_rxdesc_t
));
2636 E1000_WRITE_REG(&sc
->hw
, E1000_RDBAH(i
),
2637 (uint32_t)(bus_addr
>> 32));
2638 E1000_WRITE_REG(&sc
->hw
, E1000_RDBAL(i
),
2639 (uint32_t)bus_addr
);
2642 /* Setup the Receive Control Register */
2643 rctl
&= ~(3 << E1000_RCTL_MO_SHIFT
);
2644 rctl
|= E1000_RCTL_EN
| E1000_RCTL_BAM
| E1000_RCTL_LBM_NO
|
2645 E1000_RCTL_RDMTS_HALF
| E1000_RCTL_SECRC
|
2646 (sc
->hw
.mac
.mc_filter_type
<< E1000_RCTL_MO_SHIFT
);
2648 /* Make sure VLAN Filters are off */
2649 rctl
&= ~E1000_RCTL_VFE
;
2651 /* Don't store bad paket */
2652 rctl
&= ~E1000_RCTL_SBP
;
2655 rctl
|= E1000_RCTL_SZ_2048
;
2657 if (ifp
->if_mtu
> ETHERMTU
)
2658 rctl
|= E1000_RCTL_LPE
;
2660 rctl
&= ~E1000_RCTL_LPE
;
2663 * Receive Checksum Offload for TCP and UDP
2665 * Checksum offloading is also enabled if multiple receive
2666 * queue is to be supported, since we need it to figure out
2669 if (ifp
->if_capenable
& (IFCAP_RSS
| IFCAP_RXCSUM
)) {
2670 rxcsum
= E1000_READ_REG(&sc
->hw
, E1000_RXCSUM
);
2674 * PCSD must be enabled to enable multiple
2677 rxcsum
|= E1000_RXCSUM_IPOFL
| E1000_RXCSUM_TUOFL
|
2679 E1000_WRITE_REG(&sc
->hw
, E1000_RXCSUM
, rxcsum
);
2683 * Configure multiple receive queue (RSS)
2685 if (ifp
->if_capenable
& IFCAP_RSS
) {
2686 uint8_t key
[EMX_NRSSRK
* EMX_RSSRK_SIZE
];
2689 KASSERT(sc
->rx_ring_inuse
== EMX_NRX_RING
,
2690 ("invalid number of RX ring (%d)",
2691 sc
->rx_ring_inuse
));
2695 * When we reach here, RSS has already been disabled
2696 * in emx_stop(), so we could safely configure RSS key
2697 * and redirect table.
2703 toeplitz_get_key(key
, sizeof(key
));
2704 for (i
= 0; i
< EMX_NRSSRK
; ++i
) {
2707 rssrk
= EMX_RSSRK_VAL(key
, i
);
2708 EMX_RSS_DPRINTF(sc
, 1, "rssrk%d 0x%08x\n", i
, rssrk
);
2710 E1000_WRITE_REG(&sc
->hw
, E1000_RSSRK(i
), rssrk
);
2714 * Configure RSS redirect table in following fashion:
2715 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2718 for (i
= 0; i
< EMX_RETA_SIZE
; ++i
) {
2721 q
= (i
% sc
->rx_ring_inuse
) << EMX_RETA_RINGIDX_SHIFT
;
2722 reta
|= q
<< (8 * i
);
2724 EMX_RSS_DPRINTF(sc
, 1, "reta 0x%08x\n", reta
);
2726 for (i
= 0; i
< EMX_NRETA
; ++i
)
2727 E1000_WRITE_REG(&sc
->hw
, E1000_RETA(i
), reta
);
2730 * Enable multiple receive queues.
2731 * Enable IPv4 RSS standard hash functions.
2732 * Disable RSS interrupt.
2734 E1000_WRITE_REG(&sc
->hw
, E1000_MRQC
,
2735 E1000_MRQC_ENABLE_RSS_2Q
|
2736 E1000_MRQC_RSS_FIELD_IPV4_TCP
|
2737 E1000_MRQC_RSS_FIELD_IPV4
);
2741 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2742 * long latencies are observed, like Lenovo X60. This
2743 * change eliminates the problem, but since having positive
2744 * values in RDTR is a known source of problems on other
2745 * platforms another solution is being sought.
2747 if (emx_82573_workaround
&& sc
->hw
.mac
.type
== e1000_82573
) {
2748 E1000_WRITE_REG(&sc
->hw
, E1000_RADV
, EMX_RADV_82573
);
2749 E1000_WRITE_REG(&sc
->hw
, E1000_RDTR
, EMX_RDTR_82573
);
2753 * Setup the HW Rx Head and Tail Descriptor Pointers
2755 for (i
= 0; i
< sc
->rx_ring_inuse
; ++i
) {
2756 E1000_WRITE_REG(&sc
->hw
, E1000_RDH(i
), 0);
2757 E1000_WRITE_REG(&sc
->hw
, E1000_RDT(i
),
2758 sc
->rx_data
[i
].num_rx_desc
- 1);
2761 /* Enable Receives */
2762 E1000_WRITE_REG(&sc
->hw
, E1000_RCTL
, rctl
);
2766 emx_destroy_rx_ring(struct emx_softc
*sc
, struct emx_rxdata
*rdata
, int ndesc
)
2768 struct emx_rxbuf
*rx_buffer
;
2771 /* Free Receive Descriptor ring */
2772 if (rdata
->rx_desc
) {
2773 bus_dmamap_unload(rdata
->rx_desc_dtag
, rdata
->rx_desc_dmap
);
2774 bus_dmamem_free(rdata
->rx_desc_dtag
, rdata
->rx_desc
,
2775 rdata
->rx_desc_dmap
);
2776 bus_dma_tag_destroy(rdata
->rx_desc_dtag
);
2778 rdata
->rx_desc
= NULL
;
2781 if (rdata
->rx_buf
== NULL
)
2784 for (i
= 0; i
< ndesc
; i
++) {
2785 rx_buffer
= &rdata
->rx_buf
[i
];
2787 KKASSERT(rx_buffer
->m_head
== NULL
);
2788 bus_dmamap_destroy(rdata
->rxtag
, rx_buffer
->map
);
2790 bus_dmamap_destroy(rdata
->rxtag
, rdata
->rx_sparemap
);
2791 bus_dma_tag_destroy(rdata
->rxtag
);
2793 kfree(rdata
->rx_buf
, M_DEVBUF
);
2794 rdata
->rx_buf
= NULL
;
2798 emx_rxeof(struct emx_softc
*sc
, int ring_idx
, int count
)
2800 struct emx_rxdata
*rdata
= &sc
->rx_data
[ring_idx
];
2801 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2803 emx_rxdesc_t
*current_desc
;
2806 struct mbuf_chain chain
[MAXCPU
];
2808 i
= rdata
->next_rx_desc_to_check
;
2809 current_desc
= &rdata
->rx_desc
[i
];
2810 staterr
= le32toh(current_desc
->rxd_staterr
);
2812 if (!(staterr
& E1000_RXD_STAT_DD
))
2815 ether_input_chain_init(chain
);
2817 while ((staterr
& E1000_RXD_STAT_DD
) && count
!= 0) {
2818 struct pktinfo
*pi
= NULL
, pi0
;
2819 struct emx_rxbuf
*rx_buf
= &rdata
->rx_buf
[i
];
2820 struct mbuf
*m
= NULL
;
2825 mp
= rx_buf
->m_head
;
2828 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2829 * needs to access the last received byte in the mbuf.
2831 bus_dmamap_sync(rdata
->rxtag
, rx_buf
->map
,
2832 BUS_DMASYNC_POSTREAD
);
2834 len
= le16toh(current_desc
->rxd_length
);
2835 if (staterr
& E1000_RXD_STAT_EOP
) {
2842 if (!(staterr
& E1000_RXDEXT_ERR_FRAME_ERR_MASK
)) {
2844 uint32_t mrq
, rss_hash
;
2847 * Save several necessary information,
2848 * before emx_newbuf() destroy it.
2850 if ((staterr
& E1000_RXD_STAT_VP
) && eop
)
2851 vlan
= le16toh(current_desc
->rxd_vlan
);
2853 mrq
= le32toh(current_desc
->rxd_mrq
);
2854 rss_hash
= le32toh(current_desc
->rxd_rss
);
2856 EMX_RSS_DPRINTF(sc
, 10,
2857 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2858 ring_idx
, mrq
, rss_hash
);
2860 if (emx_newbuf(sc
, rdata
, i
, 0) != 0) {
2865 /* Assign correct length to the current fragment */
2868 if (rdata
->fmp
== NULL
) {
2869 mp
->m_pkthdr
.len
= len
;
2870 rdata
->fmp
= mp
; /* Store the first mbuf */
2874 * Chain mbuf's together
2876 rdata
->lmp
->m_next
= mp
;
2877 rdata
->lmp
= rdata
->lmp
->m_next
;
2878 rdata
->fmp
->m_pkthdr
.len
+= len
;
2882 rdata
->fmp
->m_pkthdr
.rcvif
= ifp
;
2885 if (ifp
->if_capenable
& IFCAP_RXCSUM
)
2886 emx_rxcsum(staterr
, rdata
->fmp
);
2888 if (staterr
& E1000_RXD_STAT_VP
) {
2889 rdata
->fmp
->m_pkthdr
.ether_vlantag
=
2891 rdata
->fmp
->m_flags
|= M_VLANTAG
;
2897 if (ifp
->if_capenable
& IFCAP_RSS
) {
2898 pi
= emx_rssinfo(m
, &pi0
, mrq
,
2901 #ifdef EMX_RSS_DEBUG
2908 emx_setup_rxdesc(current_desc
, rx_buf
);
2909 if (rdata
->fmp
!= NULL
) {
2910 m_freem(rdata
->fmp
);
2918 ether_input_chain(ifp
, m
, pi
, chain
);
2920 /* Advance our pointers to the next descriptor. */
2921 if (++i
== rdata
->num_rx_desc
)
2924 current_desc
= &rdata
->rx_desc
[i
];
2925 staterr
= le32toh(current_desc
->rxd_staterr
);
2927 rdata
->next_rx_desc_to_check
= i
;
2929 ether_input_dispatch(chain
);
2931 /* Advance the E1000's Receive Queue "Tail Pointer". */
2933 i
= rdata
->num_rx_desc
- 1;
2934 E1000_WRITE_REG(&sc
->hw
, E1000_RDT(ring_idx
), i
);
2938 emx_enable_intr(struct emx_softc
*sc
)
2940 lwkt_serialize_handler_enable(&sc
->main_serialize
);
2941 E1000_WRITE_REG(&sc
->hw
, E1000_IMS
, IMS_ENABLE_MASK
);
2945 emx_disable_intr(struct emx_softc
*sc
)
2947 E1000_WRITE_REG(&sc
->hw
, E1000_IMC
, 0xffffffff);
2948 lwkt_serialize_handler_disable(&sc
->main_serialize
);
2952 * Bit of a misnomer, what this really means is
2953 * to enable OS management of the system... aka
2954 * to disable special hardware management features
2957 emx_get_mgmt(struct emx_softc
*sc
)
2959 /* A shared code workaround */
2960 if (sc
->has_manage
) {
2961 int manc2h
= E1000_READ_REG(&sc
->hw
, E1000_MANC2H
);
2962 int manc
= E1000_READ_REG(&sc
->hw
, E1000_MANC
);
2964 /* disable hardware interception of ARP */
2965 manc
&= ~(E1000_MANC_ARP_EN
);
2967 /* enable receiving management packets to the host */
2968 manc
|= E1000_MANC_EN_MNG2HOST
;
2969 #define E1000_MNG2HOST_PORT_623 (1 << 5)
2970 #define E1000_MNG2HOST_PORT_664 (1 << 6)
2971 manc2h
|= E1000_MNG2HOST_PORT_623
;
2972 manc2h
|= E1000_MNG2HOST_PORT_664
;
2973 E1000_WRITE_REG(&sc
->hw
, E1000_MANC2H
, manc2h
);
2975 E1000_WRITE_REG(&sc
->hw
, E1000_MANC
, manc
);
2980 * Give control back to hardware management
2981 * controller if there is one.
2984 emx_rel_mgmt(struct emx_softc
*sc
)
2986 if (sc
->has_manage
) {
2987 int manc
= E1000_READ_REG(&sc
->hw
, E1000_MANC
);
2989 /* re-enable hardware interception of ARP */
2990 manc
|= E1000_MANC_ARP_EN
;
2991 manc
&= ~E1000_MANC_EN_MNG2HOST
;
2993 E1000_WRITE_REG(&sc
->hw
, E1000_MANC
, manc
);
2998 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
2999 * For ASF and Pass Through versions of f/w this means that
3000 * the driver is loaded. For AMT version (only with 82573)
3001 * of the f/w this means that the network i/f is open.
3004 emx_get_hw_control(struct emx_softc
*sc
)
3006 uint32_t ctrl_ext
, swsm
;
3008 /* Let firmware know the driver has taken over */
3009 switch (sc
->hw
.mac
.type
) {
3011 swsm
= E1000_READ_REG(&sc
->hw
, E1000_SWSM
);
3012 E1000_WRITE_REG(&sc
->hw
, E1000_SWSM
,
3013 swsm
| E1000_SWSM_DRV_LOAD
);
3018 case e1000_80003es2lan
:
3019 ctrl_ext
= E1000_READ_REG(&sc
->hw
, E1000_CTRL_EXT
);
3020 E1000_WRITE_REG(&sc
->hw
, E1000_CTRL_EXT
,
3021 ctrl_ext
| E1000_CTRL_EXT_DRV_LOAD
);
3030 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3031 * For ASF and Pass Through versions of f/w this means that the
3032 * driver is no longer loaded. For AMT version (only with 82573)
3033 * of the f/w this means that the network i/f is closed.
3036 emx_rel_hw_control(struct emx_softc
*sc
)
3038 uint32_t ctrl_ext
, swsm
;
3040 /* Let firmware taken over control of h/w */
3041 switch (sc
->hw
.mac
.type
) {
3043 swsm
= E1000_READ_REG(&sc
->hw
, E1000_SWSM
);
3044 E1000_WRITE_REG(&sc
->hw
, E1000_SWSM
,
3045 swsm
& ~E1000_SWSM_DRV_LOAD
);
3050 case e1000_80003es2lan
:
3051 ctrl_ext
= E1000_READ_REG(&sc
->hw
, E1000_CTRL_EXT
);
3052 E1000_WRITE_REG(&sc
->hw
, E1000_CTRL_EXT
,
3053 ctrl_ext
& ~E1000_CTRL_EXT_DRV_LOAD
);
3062 emx_is_valid_eaddr(const uint8_t *addr
)
3064 char zero_addr
[ETHER_ADDR_LEN
] = { 0, 0, 0, 0, 0, 0 };
3066 if ((addr
[0] & 1) || !bcmp(addr
, zero_addr
, ETHER_ADDR_LEN
))
3073 * Enable PCI Wake On Lan capability
3076 emx_enable_wol(device_t dev
)
3078 uint16_t cap
, status
;
3081 /* First find the capabilities pointer*/
3082 cap
= pci_read_config(dev
, PCIR_CAP_PTR
, 2);
3084 /* Read the PM Capabilities */
3085 id
= pci_read_config(dev
, cap
, 1);
3086 if (id
!= PCIY_PMG
) /* Something wrong */
3090 * OK, we have the power capabilities,
3091 * so now get the status register
3093 cap
+= PCIR_POWER_STATUS
;
3094 status
= pci_read_config(dev
, cap
, 2);
3095 status
|= PCIM_PSTAT_PME
| PCIM_PSTAT_PMEENABLE
;
3096 pci_write_config(dev
, cap
, status
, 2);
3100 emx_update_stats(struct emx_softc
*sc
)
3102 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3104 if (sc
->hw
.phy
.media_type
== e1000_media_type_copper
||
3105 (E1000_READ_REG(&sc
->hw
, E1000_STATUS
) & E1000_STATUS_LU
)) {
3106 sc
->stats
.symerrs
+= E1000_READ_REG(&sc
->hw
, E1000_SYMERRS
);
3107 sc
->stats
.sec
+= E1000_READ_REG(&sc
->hw
, E1000_SEC
);
3109 sc
->stats
.crcerrs
+= E1000_READ_REG(&sc
->hw
, E1000_CRCERRS
);
3110 sc
->stats
.mpc
+= E1000_READ_REG(&sc
->hw
, E1000_MPC
);
3111 sc
->stats
.scc
+= E1000_READ_REG(&sc
->hw
, E1000_SCC
);
3112 sc
->stats
.ecol
+= E1000_READ_REG(&sc
->hw
, E1000_ECOL
);
3114 sc
->stats
.mcc
+= E1000_READ_REG(&sc
->hw
, E1000_MCC
);
3115 sc
->stats
.latecol
+= E1000_READ_REG(&sc
->hw
, E1000_LATECOL
);
3116 sc
->stats
.colc
+= E1000_READ_REG(&sc
->hw
, E1000_COLC
);
3117 sc
->stats
.dc
+= E1000_READ_REG(&sc
->hw
, E1000_DC
);
3118 sc
->stats
.rlec
+= E1000_READ_REG(&sc
->hw
, E1000_RLEC
);
3119 sc
->stats
.xonrxc
+= E1000_READ_REG(&sc
->hw
, E1000_XONRXC
);
3120 sc
->stats
.xontxc
+= E1000_READ_REG(&sc
->hw
, E1000_XONTXC
);
3121 sc
->stats
.xoffrxc
+= E1000_READ_REG(&sc
->hw
, E1000_XOFFRXC
);
3122 sc
->stats
.xofftxc
+= E1000_READ_REG(&sc
->hw
, E1000_XOFFTXC
);
3123 sc
->stats
.fcruc
+= E1000_READ_REG(&sc
->hw
, E1000_FCRUC
);
3124 sc
->stats
.prc64
+= E1000_READ_REG(&sc
->hw
, E1000_PRC64
);
3125 sc
->stats
.prc127
+= E1000_READ_REG(&sc
->hw
, E1000_PRC127
);
3126 sc
->stats
.prc255
+= E1000_READ_REG(&sc
->hw
, E1000_PRC255
);
3127 sc
->stats
.prc511
+= E1000_READ_REG(&sc
->hw
, E1000_PRC511
);
3128 sc
->stats
.prc1023
+= E1000_READ_REG(&sc
->hw
, E1000_PRC1023
);
3129 sc
->stats
.prc1522
+= E1000_READ_REG(&sc
->hw
, E1000_PRC1522
);
3130 sc
->stats
.gprc
+= E1000_READ_REG(&sc
->hw
, E1000_GPRC
);
3131 sc
->stats
.bprc
+= E1000_READ_REG(&sc
->hw
, E1000_BPRC
);
3132 sc
->stats
.mprc
+= E1000_READ_REG(&sc
->hw
, E1000_MPRC
);
3133 sc
->stats
.gptc
+= E1000_READ_REG(&sc
->hw
, E1000_GPTC
);
3135 /* For the 64-bit byte counters the low dword must be read first. */
3136 /* Both registers clear on the read of the high dword */
3138 sc
->stats
.gorc
+= E1000_READ_REG(&sc
->hw
, E1000_GORCH
);
3139 sc
->stats
.gotc
+= E1000_READ_REG(&sc
->hw
, E1000_GOTCH
);
3141 sc
->stats
.rnbc
+= E1000_READ_REG(&sc
->hw
, E1000_RNBC
);
3142 sc
->stats
.ruc
+= E1000_READ_REG(&sc
->hw
, E1000_RUC
);
3143 sc
->stats
.rfc
+= E1000_READ_REG(&sc
->hw
, E1000_RFC
);
3144 sc
->stats
.roc
+= E1000_READ_REG(&sc
->hw
, E1000_ROC
);
3145 sc
->stats
.rjc
+= E1000_READ_REG(&sc
->hw
, E1000_RJC
);
3147 sc
->stats
.tor
+= E1000_READ_REG(&sc
->hw
, E1000_TORH
);
3148 sc
->stats
.tot
+= E1000_READ_REG(&sc
->hw
, E1000_TOTH
);
3150 sc
->stats
.tpr
+= E1000_READ_REG(&sc
->hw
, E1000_TPR
);
3151 sc
->stats
.tpt
+= E1000_READ_REG(&sc
->hw
, E1000_TPT
);
3152 sc
->stats
.ptc64
+= E1000_READ_REG(&sc
->hw
, E1000_PTC64
);
3153 sc
->stats
.ptc127
+= E1000_READ_REG(&sc
->hw
, E1000_PTC127
);
3154 sc
->stats
.ptc255
+= E1000_READ_REG(&sc
->hw
, E1000_PTC255
);
3155 sc
->stats
.ptc511
+= E1000_READ_REG(&sc
->hw
, E1000_PTC511
);
3156 sc
->stats
.ptc1023
+= E1000_READ_REG(&sc
->hw
, E1000_PTC1023
);
3157 sc
->stats
.ptc1522
+= E1000_READ_REG(&sc
->hw
, E1000_PTC1522
);
3158 sc
->stats
.mptc
+= E1000_READ_REG(&sc
->hw
, E1000_MPTC
);
3159 sc
->stats
.bptc
+= E1000_READ_REG(&sc
->hw
, E1000_BPTC
);
3161 sc
->stats
.algnerrc
+= E1000_READ_REG(&sc
->hw
, E1000_ALGNERRC
);
3162 sc
->stats
.rxerrc
+= E1000_READ_REG(&sc
->hw
, E1000_RXERRC
);
3163 sc
->stats
.tncrs
+= E1000_READ_REG(&sc
->hw
, E1000_TNCRS
);
3164 sc
->stats
.cexterr
+= E1000_READ_REG(&sc
->hw
, E1000_CEXTERR
);
3165 sc
->stats
.tsctc
+= E1000_READ_REG(&sc
->hw
, E1000_TSCTC
);
3166 sc
->stats
.tsctfc
+= E1000_READ_REG(&sc
->hw
, E1000_TSCTFC
);
3168 ifp
->if_collisions
= sc
->stats
.colc
;
3171 ifp
->if_ierrors
= sc
->dropped_pkts
+ sc
->stats
.rxerrc
+
3172 sc
->stats
.crcerrs
+ sc
->stats
.algnerrc
+
3173 sc
->stats
.ruc
+ sc
->stats
.roc
+
3174 sc
->stats
.mpc
+ sc
->stats
.cexterr
;
3177 ifp
->if_oerrors
= sc
->stats
.ecol
+ sc
->stats
.latecol
+
3178 sc
->watchdog_events
;
3182 emx_print_debug_info(struct emx_softc
*sc
)
3184 device_t dev
= sc
->dev
;
3185 uint8_t *hw_addr
= sc
->hw
.hw_addr
;
3187 device_printf(dev
, "Adapter hardware address = %p \n", hw_addr
);
3188 device_printf(dev
, "CTRL = 0x%x RCTL = 0x%x \n",
3189 E1000_READ_REG(&sc
->hw
, E1000_CTRL
),
3190 E1000_READ_REG(&sc
->hw
, E1000_RCTL
));
3191 device_printf(dev
, "Packet buffer = Tx=%dk Rx=%dk \n",
3192 ((E1000_READ_REG(&sc
->hw
, E1000_PBA
) & 0xffff0000) >> 16),\
3193 (E1000_READ_REG(&sc
->hw
, E1000_PBA
) & 0xffff) );
3194 device_printf(dev
, "Flow control watermarks high = %d low = %d\n",
3195 sc
->hw
.fc
.high_water
, sc
->hw
.fc
.low_water
);
3196 device_printf(dev
, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3197 E1000_READ_REG(&sc
->hw
, E1000_TIDV
),
3198 E1000_READ_REG(&sc
->hw
, E1000_TADV
));
3199 device_printf(dev
, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3200 E1000_READ_REG(&sc
->hw
, E1000_RDTR
),
3201 E1000_READ_REG(&sc
->hw
, E1000_RADV
));
3202 device_printf(dev
, "hw tdh = %d, hw tdt = %d\n",
3203 E1000_READ_REG(&sc
->hw
, E1000_TDH(0)),
3204 E1000_READ_REG(&sc
->hw
, E1000_TDT(0)));
3205 device_printf(dev
, "hw rdh = %d, hw rdt = %d\n",
3206 E1000_READ_REG(&sc
->hw
, E1000_RDH(0)),
3207 E1000_READ_REG(&sc
->hw
, E1000_RDT(0)));
3208 device_printf(dev
, "Num Tx descriptors avail = %d\n",
3209 sc
->num_tx_desc_avail
);
3210 device_printf(dev
, "Tx Descriptors not avail1 = %ld\n",
3211 sc
->no_tx_desc_avail1
);
3212 device_printf(dev
, "Tx Descriptors not avail2 = %ld\n",
3213 sc
->no_tx_desc_avail2
);
3214 device_printf(dev
, "Std mbuf failed = %ld\n",
3215 sc
->mbuf_alloc_failed
);
3216 device_printf(dev
, "Std mbuf cluster failed = %ld\n",
3217 sc
->rx_data
[0].mbuf_cluster_failed
);
3218 device_printf(dev
, "Driver dropped packets = %ld\n",
3220 device_printf(dev
, "Driver tx dma failure in encap = %ld\n",
3221 sc
->no_tx_dma_setup
);
3223 device_printf(dev
, "TXCSUM try pullup = %lu\n",
3224 sc
->tx_csum_try_pullup
);
3225 device_printf(dev
, "TXCSUM m_pullup(eh) called = %lu\n",
3226 sc
->tx_csum_pullup1
);
3227 device_printf(dev
, "TXCSUM m_pullup(eh) failed = %lu\n",
3228 sc
->tx_csum_pullup1_failed
);
3229 device_printf(dev
, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3230 sc
->tx_csum_pullup2
);
3231 device_printf(dev
, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3232 sc
->tx_csum_pullup2_failed
);
3233 device_printf(dev
, "TXCSUM non-writable(eh) droped = %lu\n",
3235 device_printf(dev
, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3240 emx_print_hw_stats(struct emx_softc
*sc
)
3242 device_t dev
= sc
->dev
;
3244 device_printf(dev
, "Excessive collisions = %lld\n",
3245 (long long)sc
->stats
.ecol
);
3246 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3247 device_printf(dev
, "Symbol errors = %lld\n",
3248 (long long)sc
->stats
.symerrs
);
3250 device_printf(dev
, "Sequence errors = %lld\n",
3251 (long long)sc
->stats
.sec
);
3252 device_printf(dev
, "Defer count = %lld\n",
3253 (long long)sc
->stats
.dc
);
3254 device_printf(dev
, "Missed Packets = %lld\n",
3255 (long long)sc
->stats
.mpc
);
3256 device_printf(dev
, "Receive No Buffers = %lld\n",
3257 (long long)sc
->stats
.rnbc
);
3258 /* RLEC is inaccurate on some hardware, calculate our own. */
3259 device_printf(dev
, "Receive Length Errors = %lld\n",
3260 ((long long)sc
->stats
.roc
+ (long long)sc
->stats
.ruc
));
3261 device_printf(dev
, "Receive errors = %lld\n",
3262 (long long)sc
->stats
.rxerrc
);
3263 device_printf(dev
, "Crc errors = %lld\n",
3264 (long long)sc
->stats
.crcerrs
);
3265 device_printf(dev
, "Alignment errors = %lld\n",
3266 (long long)sc
->stats
.algnerrc
);
3267 device_printf(dev
, "Collision/Carrier extension errors = %lld\n",
3268 (long long)sc
->stats
.cexterr
);
3269 device_printf(dev
, "RX overruns = %ld\n", sc
->rx_overruns
);
3270 device_printf(dev
, "watchdog timeouts = %ld\n",
3271 sc
->watchdog_events
);
3272 device_printf(dev
, "XON Rcvd = %lld\n",
3273 (long long)sc
->stats
.xonrxc
);
3274 device_printf(dev
, "XON Xmtd = %lld\n",
3275 (long long)sc
->stats
.xontxc
);
3276 device_printf(dev
, "XOFF Rcvd = %lld\n",
3277 (long long)sc
->stats
.xoffrxc
);
3278 device_printf(dev
, "XOFF Xmtd = %lld\n",
3279 (long long)sc
->stats
.xofftxc
);
3280 device_printf(dev
, "Good Packets Rcvd = %lld\n",
3281 (long long)sc
->stats
.gprc
);
3282 device_printf(dev
, "Good Packets Xmtd = %lld\n",
3283 (long long)sc
->stats
.gptc
);
3287 emx_print_nvm_info(struct emx_softc
*sc
)
3289 uint16_t eeprom_data
;
3292 /* Its a bit crude, but it gets the job done */
3293 kprintf("\nInterface EEPROM Dump:\n");
3294 kprintf("Offset\n0x0000 ");
3295 for (i
= 0, j
= 0; i
< 32; i
++, j
++) {
3296 if (j
== 8) { /* Make the offset block */
3298 kprintf("\n0x00%x0 ",row
);
3300 e1000_read_nvm(&sc
->hw
, i
, 1, &eeprom_data
);
3301 kprintf("%04x ", eeprom_data
);
3307 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS
)
3309 struct emx_softc
*sc
;
3314 error
= sysctl_handle_int(oidp
, &result
, 0, req
);
3315 if (error
|| !req
->newptr
)
3318 sc
= (struct emx_softc
*)arg1
;
3319 ifp
= &sc
->arpcom
.ac_if
;
3321 ifnet_serialize_all(ifp
);
3324 emx_print_debug_info(sc
);
3327 * This value will cause a hex dump of the
3328 * first 32 16-bit words of the EEPROM to
3332 emx_print_nvm_info(sc
);
3334 ifnet_deserialize_all(ifp
);
3340 emx_sysctl_stats(SYSCTL_HANDLER_ARGS
)
3345 error
= sysctl_handle_int(oidp
, &result
, 0, req
);
3346 if (error
|| !req
->newptr
)
3350 struct emx_softc
*sc
= (struct emx_softc
*)arg1
;
3351 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3353 ifnet_serialize_all(ifp
);
3354 emx_print_hw_stats(sc
);
3355 ifnet_deserialize_all(ifp
);
3361 emx_add_sysctl(struct emx_softc
*sc
)
3363 #ifdef EMX_RSS_DEBUG
3368 sysctl_ctx_init(&sc
->sysctl_ctx
);
3369 sc
->sysctl_tree
= SYSCTL_ADD_NODE(&sc
->sysctl_ctx
,
3370 SYSCTL_STATIC_CHILDREN(_hw
), OID_AUTO
,
3371 device_get_nameunit(sc
->dev
),
3373 if (sc
->sysctl_tree
== NULL
) {
3374 device_printf(sc
->dev
, "can't add sysctl node\n");
3378 SYSCTL_ADD_PROC(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3379 OID_AUTO
, "debug", CTLTYPE_INT
|CTLFLAG_RW
, sc
, 0,
3380 emx_sysctl_debug_info
, "I", "Debug Information");
3382 SYSCTL_ADD_PROC(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3383 OID_AUTO
, "stats", CTLTYPE_INT
|CTLFLAG_RW
, sc
, 0,
3384 emx_sysctl_stats
, "I", "Statistics");
3386 SYSCTL_ADD_INT(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3387 OID_AUTO
, "rxd", CTLFLAG_RD
,
3388 &sc
->rx_data
[0].num_rx_desc
, 0, NULL
);
3389 SYSCTL_ADD_INT(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3390 OID_AUTO
, "txd", CTLFLAG_RD
, &sc
->num_tx_desc
, 0, NULL
);
3392 SYSCTL_ADD_PROC(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3393 OID_AUTO
, "int_throttle_ceil", CTLTYPE_INT
|CTLFLAG_RW
,
3394 sc
, 0, emx_sysctl_int_throttle
, "I",
3395 "interrupt throttling rate");
3396 SYSCTL_ADD_PROC(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3397 OID_AUTO
, "int_tx_nsegs", CTLTYPE_INT
|CTLFLAG_RW
,
3398 sc
, 0, emx_sysctl_int_tx_nsegs
, "I",
3399 "# segments per TX interrupt");
3401 SYSCTL_ADD_INT(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3402 OID_AUTO
, "rx_ring_inuse", CTLFLAG_RD
,
3403 &sc
->rx_ring_inuse
, 0, "RX ring in use");
3405 #ifdef EMX_RSS_DEBUG
3406 SYSCTL_ADD_INT(&sc
->sysctl_ctx
, SYSCTL_CHILDREN(sc
->sysctl_tree
),
3407 OID_AUTO
, "rss_debug", CTLFLAG_RW
, &sc
->rss_debug
,
3408 0, "RSS debug level");
3409 for (i
= 0; i
< sc
->rx_ring_cnt
; ++i
) {
3410 ksnprintf(rx_pkt
, sizeof(rx_pkt
), "rx%d_pkt", i
);
3411 SYSCTL_ADD_UINT(&sc
->sysctl_ctx
,
3412 SYSCTL_CHILDREN(sc
->sysctl_tree
), OID_AUTO
,
3414 &sc
->rx_data
[i
].rx_pkts
, 0, "RXed packets");
3420 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS
)
3422 struct emx_softc
*sc
= (void *)arg1
;
3423 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3424 int error
, throttle
;
3426 throttle
= sc
->int_throttle_ceil
;
3427 error
= sysctl_handle_int(oidp
, &throttle
, 0, req
);
3428 if (error
|| req
->newptr
== NULL
)
3430 if (throttle
< 0 || throttle
> 1000000000 / 256)
3435 * Set the interrupt throttling rate in 256ns increments,
3436 * recalculate sysctl value assignment to get exact frequency.
3438 throttle
= 1000000000 / 256 / throttle
;
3440 /* Upper 16bits of ITR is reserved and should be zero */
3441 if (throttle
& 0xffff0000)
3445 ifnet_serialize_all(ifp
);
3448 sc
->int_throttle_ceil
= 1000000000 / 256 / throttle
;
3450 sc
->int_throttle_ceil
= 0;
3452 if (ifp
->if_flags
& IFF_RUNNING
)
3453 E1000_WRITE_REG(&sc
->hw
, E1000_ITR
, throttle
);
3455 ifnet_deserialize_all(ifp
);
3458 if_printf(ifp
, "Interrupt moderation set to %d/sec\n",
3459 sc
->int_throttle_ceil
);
3465 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS
)
3467 struct emx_softc
*sc
= (void *)arg1
;
3468 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
3471 segs
= sc
->tx_int_nsegs
;
3472 error
= sysctl_handle_int(oidp
, &segs
, 0, req
);
3473 if (error
|| req
->newptr
== NULL
)
3478 ifnet_serialize_all(ifp
);
3481 * Don't allow int_tx_nsegs to become:
3482 * o Less the oact_tx_desc
3483 * o Too large that no TX desc will cause TX interrupt to
3484 * be generated (OACTIVE will never recover)
3485 * o Too small that will cause tx_dd[] overflow
3487 if (segs
< sc
->oact_tx_desc
||
3488 segs
>= sc
->num_tx_desc
- sc
->oact_tx_desc
||
3489 segs
< sc
->num_tx_desc
/ EMX_TXDD_SAFE
) {
3493 sc
->tx_int_nsegs
= segs
;
3496 ifnet_deserialize_all(ifp
);
3502 emx_dma_alloc(struct emx_softc
*sc
)
3507 * Create top level busdma tag
3509 error
= bus_dma_tag_create(NULL
, 1, 0,
3510 BUS_SPACE_MAXADDR
, BUS_SPACE_MAXADDR
,
3512 BUS_SPACE_MAXSIZE_32BIT
, 0, BUS_SPACE_MAXSIZE_32BIT
,
3513 0, &sc
->parent_dtag
);
3515 device_printf(sc
->dev
, "could not create top level DMA tag\n");
3520 * Allocate transmit descriptors ring and buffers
3522 error
= emx_create_tx_ring(sc
);
3524 device_printf(sc
->dev
, "Could not setup transmit structures\n");
3529 * Allocate receive descriptors ring and buffers
3531 for (i
= 0; i
< sc
->rx_ring_cnt
; ++i
) {
3532 error
= emx_create_rx_ring(sc
, &sc
->rx_data
[i
]);
3534 device_printf(sc
->dev
,
3535 "Could not setup receive structures\n");
3543 emx_dma_free(struct emx_softc
*sc
)
3547 emx_destroy_tx_ring(sc
, sc
->num_tx_desc
);
3549 for (i
= 0; i
< sc
->rx_ring_cnt
; ++i
) {
3550 emx_destroy_rx_ring(sc
, &sc
->rx_data
[i
],
3551 sc
->rx_data
[i
].num_rx_desc
);
3554 /* Free top level busdma tag */
3555 if (sc
->parent_dtag
!= NULL
)
3556 bus_dma_tag_destroy(sc
->parent_dtag
);
3560 emx_serialize(struct ifnet
*ifp
, enum ifnet_serialize slz
)
3562 struct emx_softc
*sc
= ifp
->if_softc
;
3565 case IFNET_SERIALIZE_ALL
:
3566 lwkt_serialize_array_enter(sc
->serializes
, EMX_NSERIALIZE
, 0);
3569 case IFNET_SERIALIZE_MAIN
:
3570 lwkt_serialize_enter(&sc
->main_serialize
);
3573 case IFNET_SERIALIZE_TX
:
3574 lwkt_serialize_enter(&sc
->tx_serialize
);
3577 case IFNET_SERIALIZE_RX(0):
3578 lwkt_serialize_enter(&sc
->rx_data
[0].rx_serialize
);
3581 case IFNET_SERIALIZE_RX(1):
3582 lwkt_serialize_enter(&sc
->rx_data
[1].rx_serialize
);
3586 panic("%s unsupported serialize type\n", ifp
->if_xname
);
3591 emx_deserialize(struct ifnet
*ifp
, enum ifnet_serialize slz
)
3593 struct emx_softc
*sc
= ifp
->if_softc
;
3596 case IFNET_SERIALIZE_ALL
:
3597 lwkt_serialize_array_exit(sc
->serializes
, EMX_NSERIALIZE
, 0);
3600 case IFNET_SERIALIZE_MAIN
:
3601 lwkt_serialize_exit(&sc
->main_serialize
);
3604 case IFNET_SERIALIZE_TX
:
3605 lwkt_serialize_exit(&sc
->tx_serialize
);
3608 case IFNET_SERIALIZE_RX(0):
3609 lwkt_serialize_exit(&sc
->rx_data
[0].rx_serialize
);
3612 case IFNET_SERIALIZE_RX(1):
3613 lwkt_serialize_exit(&sc
->rx_data
[1].rx_serialize
);
3617 panic("%s unsupported serialize type\n", ifp
->if_xname
);
3622 emx_tryserialize(struct ifnet
*ifp
, enum ifnet_serialize slz
)
3624 struct emx_softc
*sc
= ifp
->if_softc
;
3627 case IFNET_SERIALIZE_ALL
:
3628 return lwkt_serialize_array_try(sc
->serializes
,
3631 case IFNET_SERIALIZE_MAIN
:
3632 return lwkt_serialize_try(&sc
->main_serialize
);
3634 case IFNET_SERIALIZE_TX
:
3635 return lwkt_serialize_try(&sc
->tx_serialize
);
3637 case IFNET_SERIALIZE_RX(0):
3638 return lwkt_serialize_try(&sc
->rx_data
[0].rx_serialize
);
3640 case IFNET_SERIALIZE_RX(1):
3641 return lwkt_serialize_try(&sc
->rx_data
[1].rx_serialize
);
3644 panic("%s unsupported serialize type\n", ifp
->if_xname
);
3649 emx_serialize_skipmain(struct emx_softc
*sc
)
3651 lwkt_serialize_array_enter(sc
->serializes
, EMX_NSERIALIZE
, 1);
3655 emx_deserialize_skipmain(struct emx_softc
*sc
)
3657 lwkt_serialize_array_exit(sc
->serializes
, EMX_NSERIALIZE
, 1);
3663 emx_serialize_assert(struct ifnet
*ifp
, enum ifnet_serialize slz
,
3664 boolean_t serialized
)
3666 struct emx_softc
*sc
= ifp
->if_softc
;
3670 case IFNET_SERIALIZE_ALL
:
3672 for (i
= 0; i
< EMX_NSERIALIZE
; ++i
)
3673 ASSERT_SERIALIZED(sc
->serializes
[i
]);
3675 for (i
= 0; i
< EMX_NSERIALIZE
; ++i
)
3676 ASSERT_NOT_SERIALIZED(sc
->serializes
[i
]);
3680 case IFNET_SERIALIZE_MAIN
:
3682 ASSERT_SERIALIZED(&sc
->main_serialize
);
3684 ASSERT_NOT_SERIALIZED(&sc
->main_serialize
);
3687 case IFNET_SERIALIZE_TX
:
3689 ASSERT_SERIALIZED(&sc
->tx_serialize
);
3691 ASSERT_NOT_SERIALIZED(&sc
->tx_serialize
);
3694 case IFNET_SERIALIZE_RX(0):
3696 ASSERT_SERIALIZED(&sc
->rx_data
[0].rx_serialize
);
3698 ASSERT_NOT_SERIALIZED(&sc
->rx_data
[0].rx_serialize
);
3701 case IFNET_SERIALIZE_RX(1):
3703 ASSERT_SERIALIZED(&sc
->rx_data
[1].rx_serialize
);
3705 ASSERT_NOT_SERIALIZED(&sc
->rx_data
[1].rx_serialize
);
3709 panic("%s unsupported serialize type\n", ifp
->if_xname
);
3713 #endif /* INVARIANTS */
3715 #ifdef IFPOLL_ENABLE
3718 emx_qpoll_status(struct ifnet
*ifp
, int pollhz __unused
)
3720 struct emx_softc
*sc
= ifp
->if_softc
;
3723 ASSERT_SERIALIZED(&sc
->main_serialize
);
3725 reg_icr
= E1000_READ_REG(&sc
->hw
, E1000_ICR
);
3726 if (reg_icr
& (E1000_ICR_RXSEQ
| E1000_ICR_LSC
)) {
3727 emx_serialize_skipmain(sc
);
3729 callout_stop(&sc
->timer
);
3730 sc
->hw
.mac
.get_link_status
= 1;
3731 emx_update_link_status(sc
);
3732 callout_reset(&sc
->timer
, hz
, emx_timer
, sc
);
3734 emx_deserialize_skipmain(sc
);
3739 emx_qpoll_tx(struct ifnet
*ifp
, void *arg __unused
, int cycle __unused
)
3741 struct emx_softc
*sc
= ifp
->if_softc
;
3743 ASSERT_SERIALIZED(&sc
->tx_serialize
);
3746 if (!ifq_is_empty(&ifp
->if_snd
))
3751 emx_qpoll_rx(struct ifnet
*ifp
, void *arg
, int cycle
)
3753 struct emx_softc
*sc
= ifp
->if_softc
;
3754 struct emx_rxdata
*rdata
= arg
;
3756 ASSERT_SERIALIZED(&rdata
->rx_serialize
);
3758 emx_rxeof(sc
, rdata
- sc
->rx_data
, cycle
);
3762 emx_qpoll(struct ifnet
*ifp
, struct ifpoll_info
*info
)
3764 struct emx_softc
*sc
= ifp
->if_softc
;
3766 ASSERT_IFNET_SERIALIZED_ALL(ifp
);
3771 info
->ifpi_status
.status_func
= emx_qpoll_status
;
3772 info
->ifpi_status
.serializer
= &sc
->main_serialize
;
3774 info
->ifpi_tx
[0].poll_func
= emx_qpoll_tx
;
3775 info
->ifpi_tx
[0].arg
= NULL
;
3776 info
->ifpi_tx
[0].serializer
= &sc
->tx_serialize
;
3778 for (i
= 0; i
< sc
->rx_ring_cnt
; ++i
) {
3779 info
->ifpi_rx
[i
].poll_func
= emx_qpoll_rx
;
3780 info
->ifpi_rx
[i
].arg
= &sc
->rx_data
[i
];
3781 info
->ifpi_rx
[i
].serializer
=
3782 &sc
->rx_data
[i
].rx_serialize
;
3785 if (ifp
->if_flags
& IFF_RUNNING
)
3786 emx_disable_intr(sc
);
3787 } else if (ifp
->if_flags
& IFF_RUNNING
) {
3788 emx_enable_intr(sc
);
3792 #endif /* IFPOLL_ENABLE */