drivers/scsi/esp.h

   1 /* esp.h:  Defines and structures for the Sparc ESP (Enhanced SCSI
   2  *         Processor) driver under Linux.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_ESP_H
   8 #define _SPARC_ESP_H
   9
  10 /* For dvma controller register definitions. */
  11 #include <asm/dma.h>
  12
  13 /* The ESP SCSI controllers have their register sets in three
  14  * "classes":
  15  *
  16  * 1) Registers which are both read and write.
  17  * 2) Registers which are read only.
  18  * 3) Registers which are write only.
  19  *
  20  * Yet, they all live within the same IO space.
  21  */
  22
  23 /* All the ESP registers are one byte each and are accessed longwords
  24  * apart with a big-endian ordering to the bytes.
  25  */
  26
  27 struct Sparc_ESP_regs {
  28                                 /* Access    Description              Offset */
  29     volatile unchar esp_tclow;  /* rw  Low bits of the transfer count 0x00   */
  30                                 unchar tlpad1[3];
  31     volatile unchar esp_tcmed;  /* rw  Mid bits of the transfer count 0x04   */
  32                                 unchar fdpad[3];
  33     volatile unchar esp_fdata;  /* rw  FIFO data bits                 0x08   */
  34                                 unchar cbpad[3];
  35     volatile unchar esp_cmd;    /* rw  SCSI command bits              0x0c   */
  36                                 unchar stpad[3];
  37     volatile unchar esp_status; /* ro  ESP status register            0x10   */
  38 #define esp_busid   esp_status  /* wo  Bus ID for select/reselect     0x10   */
  39                                 unchar irqpd[3];
  40     volatile unchar esp_intrpt; /* ro  Kind of interrupt              0x14   */
  41 #define esp_timeo   esp_intrpt  /* wo  Timeout value for select/resel 0x14   */
  42                                 unchar sspad[3];
  43     volatile unchar esp_sstep;  /* ro  Sequence step register         0x18   */
  44 #define esp_stp     esp_sstep   /* wo  Transfer period per sync       0x18   */
  45                                 unchar ffpad[3];
  46     volatile unchar esp_fflags; /* ro  Bits of current FIFO info      0x1c   */
  47 #define esp_soff    esp_fflags  /* wo  Sync offset                    0x1c   */
  48                                 unchar cf1pd[3];
  49     volatile unchar esp_cfg1;   /* rw  First configuration register   0x20   */
  50                                 unchar cfpad[3];
  51     volatile unchar esp_cfact;  /* wo  Clock conversion factor        0x24   */
  52 #define esp_status2 esp_cfact   /* ro  HME status2 register           0x24   */
  53                                 unchar ctpad[3];
  54     volatile unchar esp_ctest;  /* wo  Chip test register             0x28   */
  55                                 unchar cf2pd[3];
  56     volatile unchar esp_cfg2;   /* rw  Second configuration register  0x2c   */
  57                                 unchar cf3pd[3];
  58
  59     /* The following is only found on the 53C9X series SCSI chips */
  60     volatile unchar esp_cfg3;   /* rw  Third configuration register   0x30  */
  61                                 unchar thpd[7];
  62
  63     /* The following is found on all chips except the NCR53C90 (ESP100) */
  64     volatile unchar esp_tchi;   /* rw  High bits of transfer count    0x38  */
  65 #define esp_uid     esp_tchi    /* ro  Unique ID code                 0x38  */
  66 #define fas_rlo     esp_tchi    /* rw  HME extended counter           0x38  */
  67                                 unchar fgpad[3];
  68     volatile unchar esp_fgrnd;  /* rw  Data base for fifo             0x3c  */
  69 #define fas_rhi     esp_fgrnd   /* rw  HME extended counter           0x3c  */
  70 };
  71
  72 /* Various revisions of the ESP board. */
  73 enum esp_rev {
  74   esp100     = 0x00,  /* NCR53C90 - very broken */
  75   esp100a    = 0x01,  /* NCR53C90A */
  76   esp236     = 0x02,
  77   fas236     = 0x03,
  78   fas100a    = 0x04,
  79   fast       = 0x05,
  80   fashme     = 0x06,
  81   espunknown = 0x07
  82 };
  83
  84 /* We get one of these for each ESP probed. */
  85 struct Sparc_ESP {
  86   struct Sparc_ESP *next;                 /* Next ESP on probed or NULL */
  87   struct Sparc_ESP_regs *eregs;           /* All esp registers */
  88   struct Linux_SBus_DMA *dma;             /* Who I do transfers with. */
  89   struct sparc_dma_registers *dregs;      /* And his registers. */
  90   struct Scsi_Host *ehost;                /* Backpointer to SCSI Host */
  91
  92   struct linux_sbus_device *edev;         /* Pointer to SBus entry */
  93   char prom_name[64];                     /* Name of ESP device from prom */
  94   int prom_node;                          /* Prom node where ESP found */
  95   int esp_id;                             /* Unique per-ESP ID number */
  96
  97   /* ESP Configuration Registers */
  98   unsigned char config1;                  /* Copy of the 1st config register */
  99   unsigned char config2;                  /* Copy of the 2nd config register */
 100   unsigned char config3[16];              /* Copy of the 3rd config register */
 101
 102   /* The current command we are sending to the ESP chip.  This esp_command
 103    * ptr needs to be mapped in DVMA area so we can send commands and read
 104    * from the ESP fifo without burning precious CPU cycles.  Programmed I/O
 105    * sucks when we have the DVMA to do it for us.  The ESP is stupid and will
 106    * only send out 6, 10, and 12 byte SCSI commands, others we need to send
 107    * one byte at a time.  esp_slowcmd being set says that we are doing one
 108    * of the command types ESP doesn't understand, esp_scmdp keeps track of
 109    * which byte we are sending, esp_scmdleft says how many bytes to go.
 110    */
 111   volatile unchar *esp_command;           /* Location of command (CPU view)  */
 112   __u32            esp_command_dvma;      /* Location of command (DVMA view) */
 113   unsigned char esp_clen;                 /* Length of this command */
 114   unsigned char esp_slowcmd;
 115   unsigned char *esp_scmdp;
 116   unsigned char esp_scmdleft;
 117
 118   /* The following are used to determine the cause of an IRQ. Upon every
 119    * IRQ entry we synchronize these with the hardware registers.
 120    */
 121   unchar ireg;                            /* Copy of ESP interrupt register */
 122   unchar sreg;                            /* Same for ESP status register */
 123   unchar seqreg;                          /* The ESP sequence register */
 124   unchar sreg2;                           /* Copy of HME status2 register */
 125
 126   /* The HME is the biggest piece of shit I have ever seen. */
 127   unchar hme_fifo_workaround_buffer[16 * 2]; /* 16-bit/entry fifo for wide scsi */
 128   unchar hme_fifo_workaround_count;
 129
 130   /* Clock periods, frequencies, synchronization, etc. */
 131   unsigned int cfreq;                    /* Clock frequency in HZ */
 132   unsigned int cfact;                    /* Clock conversion factor */
 133   unsigned int ccycle;                   /* One ESP clock cycle */
 134   unsigned int ctick;                    /* One ESP clock time */
 135   unsigned int radelay;                  /* FAST chip req/ack delay */
 136   unsigned int neg_defp;                 /* Default negotiation period */
 137   unsigned int sync_defp;                /* Default sync transfer period */
 138   unsigned int max_period;               /* longest our period can be */
 139   unsigned int min_period;               /* shortest period we can withstand */
 140   /* For slow to medium speed input clock rates we shoot for 5mb/s,
 141    * but for high input clock rates we try to do 10mb/s although I
 142    * don't think a transfer can even run that fast with an ESP even
 143    * with DMA2 scatter gather pipelining.
 144    */
 145 #define SYNC_DEFP_SLOW            0x32   /* 5mb/s  */
 146 #define SYNC_DEFP_FAST            0x19   /* 10mb/s */
 147
 148   unsigned int snip;                      /* Sync. negotiation in progress */
 149   unsigned int wnip;                      /* WIDE negotiation in progress */
 150   unsigned int targets_present;           /* targets spoken to before */
 151
 152   int current_transfer_size;              /* Set at beginning of data dma */
 153
 154   unchar espcmdlog[32];                   /* Log of current esp cmds sent. */
 155   unchar espcmdent;                       /* Current entry in esp cmd log. */
 156
 157   /* Misc. info about this ESP */
 158   enum esp_rev erev;                      /* ESP revision */
 159   int irq;                                /* SBus IRQ for this ESP */
 160   int scsi_id;                            /* Who am I as initiator? */
 161   int scsi_id_mask;                       /* Bitmask of 'me'. */
 162   int diff;                               /* Differential SCSI bus? */
 163   int bursts;                             /* Burst sizes our DVMA supports */
 164
 165   /* Our command queues, only one cmd lives in the current_SC queue. */
 166   Scsi_Cmnd *issue_SC;           /* Commands to be issued */
 167   Scsi_Cmnd *current_SC;         /* Who is currently working the bus */
 168   Scsi_Cmnd *disconnected_SC;    /* Commands disconnected from the bus */
 169
 170   /* Message goo */
 171   unchar cur_msgout[16];
 172   unchar cur_msgin[16];
 173   unchar prevmsgout, prevmsgin;
 174   unchar msgout_len, msgin_len;
 175   unchar msgout_ctr, msgin_ctr;
 176
 177   /* States that we cannot keep in the per cmd structure because they
 178    * cannot be assosciated with any specific command.
 179    */
 180   unchar resetting_bus;
 181 };
 182
 183 /* Bitfield meanings for the above registers. */
 184
 185 /* ESP config reg 1, read-write, found on all ESP chips */
 186 #define ESP_CONFIG1_ID        0x07             /* My BUS ID bits */
 187 #define ESP_CONFIG1_CHTEST    0x08             /* Enable ESP chip tests */
 188 #define ESP_CONFIG1_PENABLE   0x10             /* Enable parity checks */
 189 #define ESP_CONFIG1_PARTEST   0x20             /* Parity test mode enabled? */
 190 #define ESP_CONFIG1_SRRDISAB  0x40             /* Disable SCSI reset reports */
 191 #define ESP_CONFIG1_SLCABLE   0x80             /* Enable slow cable mode */
 192
 193 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
 194 #define ESP_CONFIG2_DMAPARITY 0x01             /* enable DMA Parity (200,236) */
 195 #define ESP_CONFIG2_REGPARITY 0x02             /* enable reg Parity (200,236) */
 196 #define ESP_CONFIG2_BADPARITY 0x04             /* Bad parity target abort  */
 197 #define ESP_CONFIG2_SCSI2ENAB 0x08             /* Enable SCSI-2 features (tmode only) */
 198 #define ESP_CONFIG2_HI        0x10             /* High Impedance DREQ ???  */
 199 #define ESP_CONFIG2_HMEFENAB  0x10             /* HME features enable */
 200 #define ESP_CONFIG2_BCM       0x20             /* Enable byte-ctrl (236)   */
 201 #define ESP_CONFIG2_DISPINT   0x20             /* Disable pause irq (hme) */
 202 #define ESP_CONFIG2_FENAB     0x40             /* Enable features (fas100,esp216)      */
 203 #define ESP_CONFIG2_SPL       0x40             /* Enable status-phase latch (esp236)   */
 204 #define ESP_CONFIG2_MKDONE    0x40             /* HME magic feature */
 205 #define ESP_CONFIG2_HME32     0x80             /* HME 32 extended */
 206 #define ESP_CONFIG2_MAGIC     0xe0             /* Invalid bits... */
 207
 208 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
 209 #define ESP_CONFIG3_FCLOCK    0x01             /* FAST SCSI clock rate (esp100a/hme) */
 210 #define ESP_CONFIG3_TEM       0x01             /* Enable thresh-8 mode (esp/fas236)  */
 211 #define ESP_CONFIG3_FAST      0x02             /* Enable FAST SCSI     (esp100a/hme) */
 212 #define ESP_CONFIG3_ADMA      0x02             /* Enable alternate-dma (esp/fas236)  */
 213 #define ESP_CONFIG3_TENB      0x04             /* group2 SCSI2 support (esp100a/hme) */
 214 #define ESP_CONFIG3_SRB       0x04             /* Save residual byte   (esp/fas236)  */
 215 #define ESP_CONFIG3_TMS       0x08             /* Three-byte msg's ok  (esp100a/hme) */
 216 #define ESP_CONFIG3_FCLK      0x08             /* Fast SCSI clock rate (esp/fas236)  */
 217 #define ESP_CONFIG3_IDMSG     0x10             /* ID message checking  (esp100a/hme) */
 218 #define ESP_CONFIG3_FSCSI     0x10             /* Enable FAST SCSI     (esp/fas236)  */
 219 #define ESP_CONFIG3_GTM       0x20             /* group2 SCSI2 support (esp/fas236)  */
 220 #define ESP_CONFIG3_BIGID     0x20             /* SCSI-ID's are 4bits  (hme)         */
 221 #define ESP_CONFIG3_TBMS      0x40             /* Three-byte msg's ok  (esp/fas236)  */
 222 #define ESP_CONFIG3_EWIDE     0x40             /* Enable Wide-SCSI     (hme)         */
 223 #define ESP_CONFIG3_IMS       0x80             /* ID msg chk'ng        (esp/fas236)  */
 224 #define ESP_CONFIG3_OBPUSH    0x80             /* Push odd-byte to dma (hme)         */
 225
 226 /* ESP command register read-write */
 227 /* Group 1 commands:  These may be sent at any point in time to the ESP
 228  *                    chip.  None of them can generate interrupts 'cept
 229  *                    the "SCSI bus reset" command if you have not disabled
 230  *                    SCSI reset interrupts in the config1 ESP register.
 231  */
 232 #define ESP_CMD_NULL          0x00             /* Null command, ie. a nop */
 233 #define ESP_CMD_FLUSH         0x01             /* FIFO Flush */
 234 #define ESP_CMD_RC            0x02             /* Chip reset */
 235 #define ESP_CMD_RS            0x03             /* SCSI bus reset */
 236
 237 /* Group 2 commands:  ESP must be an initiator and connected to a target
 238  *                    for these commands to work.
 239  */
 240 #define ESP_CMD_TI            0x10             /* Transfer Information */
 241 #define ESP_CMD_ICCSEQ        0x11             /* Initiator cmd complete sequence */
 242 #define ESP_CMD_MOK           0x12             /* Message okie-dokie */
 243 #define ESP_CMD_TPAD          0x18             /* Transfer Pad */
 244 #define ESP_CMD_SATN          0x1a             /* Set ATN */
 245 #define ESP_CMD_RATN          0x1b             /* De-assert ATN */
 246
 247 /* Group 3 commands:  ESP must be in the MSGOUT or MSGIN state and be connected
 248  *                    to a target as the initiator for these commands to work.
 249  */
 250 #define ESP_CMD_SMSG          0x20             /* Send message */
 251 #define ESP_CMD_SSTAT         0x21             /* Send status */
 252 #define ESP_CMD_SDATA         0x22             /* Send data */
 253 #define ESP_CMD_DSEQ          0x23             /* Discontinue Sequence */
 254 #define ESP_CMD_TSEQ          0x24             /* Terminate Sequence */
 255 #define ESP_CMD_TCCSEQ        0x25             /* Target cmd cmplt sequence */
 256 #define ESP_CMD_DCNCT         0x27             /* Disconnect */
 257 #define ESP_CMD_RMSG          0x28             /* Receive Message */
 258 #define ESP_CMD_RCMD          0x29             /* Receive Command */
 259 #define ESP_CMD_RDATA         0x2a             /* Receive Data */
 260 #define ESP_CMD_RCSEQ         0x2b             /* Receive cmd sequence */
 261
 262 /* Group 4 commands:  The ESP must be in the disconnected state and must
 263  *                    not be connected to any targets as initiator for
 264  *                    these commands to work.
 265  */
 266 #define ESP_CMD_RSEL          0x40             /* Reselect */
 267 #define ESP_CMD_SEL           0x41             /* Select w/o ATN */
 268 #define ESP_CMD_SELA          0x42             /* Select w/ATN */
 269 #define ESP_CMD_SELAS         0x43             /* Select w/ATN & STOP */
 270 #define ESP_CMD_ESEL          0x44             /* Enable selection */
 271 #define ESP_CMD_DSEL          0x45             /* Disable selections */
 272 #define ESP_CMD_SA3           0x46             /* Select w/ATN3 */
 273 #define ESP_CMD_RSEL3         0x47             /* Reselect3 */
 274
 275 /* This bit enables the ESP's DMA on the SBus */
 276 #define ESP_CMD_DMA           0x80             /* Do DMA? */
 277
 278
 279 /* ESP status register read-only */
 280 #define ESP_STAT_PIO          0x01             /* IO phase bit */
 281 #define ESP_STAT_PCD          0x02             /* CD phase bit */
 282 #define ESP_STAT_PMSG         0x04             /* MSG phase bit */
 283 #define ESP_STAT_PMASK        0x07             /* Mask of phase bits */
 284 #define ESP_STAT_TDONE        0x08             /* Transfer Completed */
 285 #define ESP_STAT_TCNT         0x10             /* Transfer Counter Is Zero */
 286 #define ESP_STAT_PERR         0x20             /* Parity error */
 287 #define ESP_STAT_SPAM         0x40             /* Real bad error */
 288 /* This indicates the 'interrupt pending' condition on esp236, it is a reserved
 289  * bit on other revs of the ESP.
 290  */
 291 #define ESP_STAT_INTR         0x80             /* Interrupt */
 292
 293 /* HME only: status 2 register */
 294 #define ESP_STAT2_SCHBIT      0x01 /* Upper bits 3-7 of sstep enabled */
 295 #define ESP_STAT2_FFLAGS      0x02 /* The fifo flags are now latched */
 296 #define ESP_STAT2_XCNT        0x04 /* The transfer counter is latched */
 297 #define ESP_STAT2_CREGA       0x08 /* The command reg is active now */
 298 #define ESP_STAT2_WIDE        0x10 /* Interface on this adapter is wide */
 299 #define ESP_STAT2_F1BYTE      0x20 /* There is one byte at top of fifo */
 300 #define ESP_STAT2_FMSB        0x40 /* Next byte in fifo is most significant */
 301 #define ESP_STAT2_FEMPTY      0x80 /* FIFO is empty */
 302
 303 /* The status register can be masked with ESP_STAT_PMASK and compared
 304  * with the following values to determine the current phase the ESP
 305  * (at least thinks it) is in.  For our purposes we also add our own
 306  * software 'done' bit for our phase management engine.
 307  */
 308 #define ESP_DOP   (0)                                       /* Data Out  */
 309 #define ESP_DIP   (ESP_STAT_PIO)                            /* Data In   */
 310 #define ESP_CMDP  (ESP_STAT_PCD)                            /* Command   */
 311 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO)               /* Status    */
 312 #define ESP_MOP   (ESP_STAT_PMSG|ESP_STAT_PCD)              /* Message Out */
 313 #define ESP_MIP   (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
 314
 315 /* ESP interrupt register read-only */
 316 #define ESP_INTR_S            0x01             /* Select w/o ATN */
 317 #define ESP_INTR_SATN         0x02             /* Select w/ATN */
 318 #define ESP_INTR_RSEL         0x04             /* Reselected */
 319 #define ESP_INTR_FDONE        0x08             /* Function done */
 320 #define ESP_INTR_BSERV        0x10             /* Bus service */
 321 #define ESP_INTR_DC           0x20             /* Disconnect */
 322 #define ESP_INTR_IC           0x40             /* Illegal command given */
 323 #define ESP_INTR_SR           0x80             /* SCSI bus reset detected */
 324
 325 /* Interrupt status macros */
 326 #define ESP_SRESET_IRQ(esp)  ((esp)->intreg & (ESP_INTR_SR))
 327 #define ESP_ILLCMD_IRQ(esp)  ((esp)->intreg & (ESP_INTR_IC))
 328 #define ESP_SELECT_WITH_ATN_IRQ(esp)     ((esp)->intreg & (ESP_INTR_SATN))
 329 #define ESP_SELECT_WITHOUT_ATN_IRQ(esp)  ((esp)->intreg & (ESP_INTR_S))
 330 #define ESP_SELECTION_IRQ(esp)  ((ESP_SELECT_WITH_ATN_IRQ(esp)) ||         \
 331                                  (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
 332 #define ESP_RESELECTION_IRQ(esp)         ((esp)->intreg & (ESP_INTR_RSEL))
 333
 334 /* ESP sequence step register read-only */
 335 #define ESP_STEP_VBITS        0x07             /* Valid bits */
 336 #define ESP_STEP_ASEL         0x00             /* Selection&Arbitrate cmplt */
 337 #define ESP_STEP_SID          0x01             /* One msg byte sent */
 338 #define ESP_STEP_NCMD         0x02             /* Was not in command phase */
 339 #define ESP_STEP_PPC          0x03             /* Early phase chg caused cmnd
 340                                                 * bytes to be lost
 341                                                 */
 342 #define ESP_STEP_FINI4        0x04             /* Command was sent ok */
 343
 344 /* Ho hum, some ESP's set the step register to this as well... */
 345 #define ESP_STEP_FINI5        0x05
 346 #define ESP_STEP_FINI6        0x06
 347 #define ESP_STEP_FINI7        0x07
 348
 349 /* ESP chip-test register read-write */
 350 #define ESP_TEST_TARG         0x01             /* Target test mode */
 351 #define ESP_TEST_INI          0x02             /* Initiator test mode */
 352 #define ESP_TEST_TS           0x04             /* Tristate test mode */
 353
 354 /* ESP unique ID register read-only, found on fas236+fas100a only */
 355 #define ESP_UID_F100A         0x00             /* ESP FAS100A  */
 356 #define ESP_UID_F236          0x02             /* ESP FAS236   */
 357 #define ESP_UID_REV           0x07             /* ESP revision */
 358 #define ESP_UID_FAM           0xf8             /* ESP family   */
 359
 360 /* ESP fifo flags register read-only */
 361 /* Note that the following implies a 16 byte FIFO on the ESP. */
 362 #define ESP_FF_FBYTES         0x1f             /* Num bytes in FIFO */
 363 #define ESP_FF_ONOTZERO       0x20             /* offset ctr not zero (esp100) */
 364 #define ESP_FF_SSTEP          0xe0             /* Sequence step */
 365
 366 /* ESP clock conversion factor register write-only */
 367 #define ESP_CCF_F0            0x00             /* 35.01MHz - 40MHz */
 368 #define ESP_CCF_NEVER         0x01             /* Set it to this and die */
 369 #define ESP_CCF_F2            0x02             /* 10MHz */
 370 #define ESP_CCF_F3            0x03             /* 10.01MHz - 15MHz */
 371 #define ESP_CCF_F4            0x04             /* 15.01MHz - 20MHz */
 372 #define ESP_CCF_F5            0x05             /* 20.01MHz - 25MHz */
 373 #define ESP_CCF_F6            0x06             /* 25.01MHz - 30MHz */
 374 #define ESP_CCF_F7            0x07             /* 30.01MHz - 35MHz */
 375
 376 /* HME only... */
 377 #define ESP_BUSID_RESELID     0x10
 378 #define ESP_BUSID_CTR32BIT    0x40
 379
 380 #define ESP_BUS_TIMEOUT        275             /* In milli-seconds */
 381 #define ESP_TIMEO_CONST       8192
 382 #define ESP_NEG_DEFP(mhz, cfact) \
 383         ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
 384 #define ESP_MHZ_TO_CYCLE(mhertz)  ((1000000000) / ((mhertz) / 1000))
 385 #define ESP_TICK(ccf, cycle)  ((7682 * (ccf) * (cycle) / 1000))
 386
 387 extern int esp_detect(struct SHT *);
 388 extern const char *esp_info(struct Scsi_Host *);
 389 extern int esp_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
 390 extern int esp_command(Scsi_Cmnd *);
 391 extern int esp_abort(Scsi_Cmnd *);
 392 extern int esp_reset(Scsi_Cmnd *, unsigned int);
 393 extern int esp_proc_info(char *buffer, char **start, off_t offset, int length,
 394                          int hostno, int inout);
 395
 396 extern struct proc_dir_entry proc_scsi_esp;
 397
 398 #define SCSI_SPARC_ESP {                                        \
 399                 proc_dir:       &proc_scsi_esp,                 \
 400                 proc_info:      &esp_proc_info,                 \
 401                 name:           "Sun ESP 100/100a/200",         \
 402                 detect:         esp_detect,                     \
 403                 info:           esp_info,                       \
 404                 command:        esp_command,                    \
 405                 queuecommand:   esp_queue,                      \
 406                 abort:          esp_abort,                      \
 407                 reset:          esp_reset,                      \
 408                 can_queue:      7,                              \
 409                 this_id:        7,                              \
 410                 sg_tablesize:   SG_ALL,                         \
 411                 cmd_per_lun:    1,                              \
 412                 use_clustering: DISABLE_CLUSTERING,             \
 413                 use_new_eh_code: 0                              \
 414 }
 415
 416 /* For our interrupt engine. */
 417 #define for_each_esp(esp) \
 418         for((esp) = espchain; (esp); (esp) = (esp)->next)
 419
 420 #endif /* !(_SPARC_ESP_H) */